1 /* gdb.c --- sim interface to GDB.
3 Copyright (C) 2005, 2007-2012 Free Software Foundation, Inc.
4 Contributed by Red Hat, Inc.
6 This file is part of the GNU simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "gdb/callback.h"
30 #include "gdb/remote-sim.h"
31 #include "gdb/signals.h"
32 #include "gdb/sim-m32c.h"
42 /* I don't want to wrap up all the minisim's data structures in an
43 object and pass that around. That'd be a big change, and neither
44 GDB nor run needs that ability.
46 So we just have one instance, that lives in global variables, and
47 each time we open it, we re-initialize it. */
53 static struct sim_state the_minisim
= {
54 "This is the sole m32c minisim instance. See libsim.a's global variables."
60 sim_open (SIM_OPEN_KIND kind
,
61 struct host_callback_struct
*callback
,
62 struct bfd
*abfd
, char **argv
)
66 fprintf (stderr
, "m32c minisim: re-opened sim\n");
68 /* The 'run' interface doesn't use this function, so we don't care
69 about KIND; it's always SIM_OPEN_DEBUG. */
70 if (kind
!= SIM_OPEN_DEBUG
)
71 fprintf (stderr
, "m32c minisim: sim_open KIND != SIM_OPEN_DEBUG: %d\n",
75 m32c_set_mach (bfd_get_mach (abfd
));
77 /* We can use ABFD, if non-NULL to select the appropriate
78 architecture. But we only support the r8c right now. */
80 set_callbacks (callback
);
82 /* We don't expect any command-line arguments. */
92 check_desc (SIM_DESC sd
)
94 if (sd
!= &the_minisim
)
95 fprintf (stderr
, "m32c minisim: desc != &the_minisim\n");
99 sim_close (SIM_DESC sd
, int quitting
)
103 /* Not much to do. At least free up our memory. */
110 open_objfile (const char *filename
)
112 bfd
*prog
= bfd_openr (filename
, 0);
116 fprintf (stderr
, "Can't read %s\n", filename
);
120 if (!bfd_check_format (prog
, bfd_object
))
122 fprintf (stderr
, "%s not a m32c program\n", filename
);
131 sim_load (SIM_DESC sd
, char *prog
, struct bfd
* abfd
, int from_tty
)
136 abfd
= open_objfile (prog
);
146 sim_create_inferior (SIM_DESC sd
, struct bfd
* abfd
, char **argv
, char **env
)
157 sim_read (SIM_DESC sd
, SIM_ADDR mem
, unsigned char *buf
, int length
)
164 mem_get_blk ((int) mem
, buf
, length
);
170 sim_write (SIM_DESC sd
, SIM_ADDR mem
, const unsigned char *buf
, int length
)
174 mem_put_blk ((int) mem
, buf
, length
);
180 /* Read the LENGTH bytes at BUF as an little-endian value. */
182 get_le (unsigned char *buf
, int length
)
185 while (--length
>= 0)
186 acc
= (acc
<< 8) + buf
[length
];
191 /* Store VAL as a little-endian value in the LENGTH bytes at BUF. */
193 put_le (unsigned char *buf
, int length
, DI val
)
197 for (i
= 0; i
< length
; i
++)
205 check_regno (enum m32c_sim_reg regno
)
207 return 0 <= regno
&& regno
< m32c_sim_reg_num_regs
;
211 mask_size (int addr_mask
)
222 "m32c minisim: addr_mask_size: unexpected mask 0x%x\n",
224 return sizeof (addr_mask
);
229 reg_size (enum m32c_sim_reg regno
)
233 case m32c_sim_reg_r0_bank0
:
234 case m32c_sim_reg_r1_bank0
:
235 case m32c_sim_reg_r2_bank0
:
236 case m32c_sim_reg_r3_bank0
:
237 case m32c_sim_reg_r0_bank1
:
238 case m32c_sim_reg_r1_bank1
:
239 case m32c_sim_reg_r2_bank1
:
240 case m32c_sim_reg_r3_bank1
:
241 case m32c_sim_reg_flg
:
242 case m32c_sim_reg_svf
:
245 case m32c_sim_reg_a0_bank0
:
246 case m32c_sim_reg_a1_bank0
:
247 case m32c_sim_reg_fb_bank0
:
248 case m32c_sim_reg_sb_bank0
:
249 case m32c_sim_reg_a0_bank1
:
250 case m32c_sim_reg_a1_bank1
:
251 case m32c_sim_reg_fb_bank1
:
252 case m32c_sim_reg_sb_bank1
:
253 case m32c_sim_reg_usp
:
254 case m32c_sim_reg_isp
:
255 return mask_size (addr_mask
);
257 case m32c_sim_reg_pc
:
258 case m32c_sim_reg_intb
:
259 case m32c_sim_reg_svp
:
260 case m32c_sim_reg_vct
:
261 return mask_size (membus_mask
);
263 case m32c_sim_reg_dmd0
:
264 case m32c_sim_reg_dmd1
:
267 case m32c_sim_reg_dct0
:
268 case m32c_sim_reg_dct1
:
269 case m32c_sim_reg_drc0
:
270 case m32c_sim_reg_drc1
:
273 case m32c_sim_reg_dma0
:
274 case m32c_sim_reg_dma1
:
275 case m32c_sim_reg_dsa0
:
276 case m32c_sim_reg_dsa1
:
277 case m32c_sim_reg_dra0
:
278 case m32c_sim_reg_dra1
:
282 fprintf (stderr
, "m32c minisim: unrecognized register number: %d\n",
289 sim_fetch_register (SIM_DESC sd
, int regno
, unsigned char *buf
, int length
)
295 if (!check_regno (regno
))
298 size
= reg_size (regno
);
305 case m32c_sim_reg_r0_bank0
:
306 val
= regs
.r
[0].r_r0
;
308 case m32c_sim_reg_r1_bank0
:
309 val
= regs
.r
[0].r_r1
;
311 case m32c_sim_reg_r2_bank0
:
312 val
= regs
.r
[0].r_r2
;
314 case m32c_sim_reg_r3_bank0
:
315 val
= regs
.r
[0].r_r3
;
317 case m32c_sim_reg_a0_bank0
:
318 val
= regs
.r
[0].r_a0
;
320 case m32c_sim_reg_a1_bank0
:
321 val
= regs
.r
[0].r_a1
;
323 case m32c_sim_reg_fb_bank0
:
324 val
= regs
.r
[0].r_fb
;
326 case m32c_sim_reg_sb_bank0
:
327 val
= regs
.r
[0].r_sb
;
329 case m32c_sim_reg_r0_bank1
:
330 val
= regs
.r
[1].r_r0
;
332 case m32c_sim_reg_r1_bank1
:
333 val
= regs
.r
[1].r_r1
;
335 case m32c_sim_reg_r2_bank1
:
336 val
= regs
.r
[1].r_r2
;
338 case m32c_sim_reg_r3_bank1
:
339 val
= regs
.r
[1].r_r3
;
341 case m32c_sim_reg_a0_bank1
:
342 val
= regs
.r
[1].r_a0
;
344 case m32c_sim_reg_a1_bank1
:
345 val
= regs
.r
[1].r_a1
;
347 case m32c_sim_reg_fb_bank1
:
348 val
= regs
.r
[1].r_fb
;
350 case m32c_sim_reg_sb_bank1
:
351 val
= regs
.r
[1].r_sb
;
354 case m32c_sim_reg_usp
:
357 case m32c_sim_reg_isp
:
360 case m32c_sim_reg_pc
:
363 case m32c_sim_reg_intb
:
364 val
= regs
.r_intbl
* 65536 + regs
.r_intbl
;
366 case m32c_sim_reg_flg
:
370 /* These registers aren't implemented by the minisim. */
371 case m32c_sim_reg_svf
:
372 case m32c_sim_reg_svp
:
373 case m32c_sim_reg_vct
:
374 case m32c_sim_reg_dmd0
:
375 case m32c_sim_reg_dmd1
:
376 case m32c_sim_reg_dct0
:
377 case m32c_sim_reg_dct1
:
378 case m32c_sim_reg_drc0
:
379 case m32c_sim_reg_drc1
:
380 case m32c_sim_reg_dma0
:
381 case m32c_sim_reg_dma1
:
382 case m32c_sim_reg_dsa0
:
383 case m32c_sim_reg_dsa1
:
384 case m32c_sim_reg_dra0
:
385 case m32c_sim_reg_dra1
:
389 fprintf (stderr
, "m32c minisim: unrecognized register number: %d\n",
394 put_le (buf
, length
, val
);
401 sim_store_register (SIM_DESC sd
, int regno
, unsigned char *buf
, int length
)
407 if (!check_regno (regno
))
410 size
= reg_size (regno
);
414 DI val
= get_le (buf
, length
);
418 case m32c_sim_reg_r0_bank0
:
419 regs
.r
[0].r_r0
= val
& 0xffff;
421 case m32c_sim_reg_r1_bank0
:
422 regs
.r
[0].r_r1
= val
& 0xffff;
424 case m32c_sim_reg_r2_bank0
:
425 regs
.r
[0].r_r2
= val
& 0xffff;
427 case m32c_sim_reg_r3_bank0
:
428 regs
.r
[0].r_r3
= val
& 0xffff;
430 case m32c_sim_reg_a0_bank0
:
431 regs
.r
[0].r_a0
= val
& addr_mask
;
433 case m32c_sim_reg_a1_bank0
:
434 regs
.r
[0].r_a1
= val
& addr_mask
;
436 case m32c_sim_reg_fb_bank0
:
437 regs
.r
[0].r_fb
= val
& addr_mask
;
439 case m32c_sim_reg_sb_bank0
:
440 regs
.r
[0].r_sb
= val
& addr_mask
;
442 case m32c_sim_reg_r0_bank1
:
443 regs
.r
[1].r_r0
= val
& 0xffff;
445 case m32c_sim_reg_r1_bank1
:
446 regs
.r
[1].r_r1
= val
& 0xffff;
448 case m32c_sim_reg_r2_bank1
:
449 regs
.r
[1].r_r2
= val
& 0xffff;
451 case m32c_sim_reg_r3_bank1
:
452 regs
.r
[1].r_r3
= val
& 0xffff;
454 case m32c_sim_reg_a0_bank1
:
455 regs
.r
[1].r_a0
= val
& addr_mask
;
457 case m32c_sim_reg_a1_bank1
:
458 regs
.r
[1].r_a1
= val
& addr_mask
;
460 case m32c_sim_reg_fb_bank1
:
461 regs
.r
[1].r_fb
= val
& addr_mask
;
463 case m32c_sim_reg_sb_bank1
:
464 regs
.r
[1].r_sb
= val
& addr_mask
;
467 case m32c_sim_reg_usp
:
468 regs
.r_usp
= val
& addr_mask
;
470 case m32c_sim_reg_isp
:
471 regs
.r_isp
= val
& addr_mask
;
473 case m32c_sim_reg_pc
:
474 regs
.r_pc
= val
& membus_mask
;
476 case m32c_sim_reg_intb
:
477 regs
.r_intbl
= (val
& membus_mask
) & 0xffff;
478 regs
.r_intbh
= (val
& membus_mask
) >> 16;
480 case m32c_sim_reg_flg
:
481 regs
.r_flags
= val
& 0xffff;
484 /* These registers aren't implemented by the minisim. */
485 case m32c_sim_reg_svf
:
486 case m32c_sim_reg_svp
:
487 case m32c_sim_reg_vct
:
488 case m32c_sim_reg_dmd0
:
489 case m32c_sim_reg_dmd1
:
490 case m32c_sim_reg_dct0
:
491 case m32c_sim_reg_dct1
:
492 case m32c_sim_reg_drc0
:
493 case m32c_sim_reg_drc1
:
494 case m32c_sim_reg_dma0
:
495 case m32c_sim_reg_dma1
:
496 case m32c_sim_reg_dsa0
:
497 case m32c_sim_reg_dsa1
:
498 case m32c_sim_reg_dra0
:
499 case m32c_sim_reg_dra1
:
503 fprintf (stderr
, "m32c minisim: unrecognized register number: %d\n",
513 sim_info (SIM_DESC sd
, int verbose
)
517 printf ("The m32c minisim doesn't collect any statistics.\n");
520 static volatile int stop
;
521 static enum sim_stop reason
;
525 /* Given a signal number used by the M32C bsp (that is, newlib),
526 return a target signal number used by GDB. */
528 m32c_signal_to_target (int m32c
)
533 return TARGET_SIGNAL_ILL
;
536 return TARGET_SIGNAL_TRAP
;
539 return TARGET_SIGNAL_BUS
;
542 return TARGET_SIGNAL_SEGV
;
545 return TARGET_SIGNAL_XCPU
;
548 return TARGET_SIGNAL_INT
;
551 return TARGET_SIGNAL_FPE
;
554 return TARGET_SIGNAL_ABRT
;
561 /* Take a step return code RC and set up the variables consulted by
562 sim_stop_reason appropriately. */
566 if (M32C_STEPPED (rc
) || M32C_HIT_BREAK (rc
))
568 reason
= sim_stopped
;
569 siggnal
= TARGET_SIGNAL_TRAP
;
571 else if (M32C_STOPPED (rc
))
573 reason
= sim_stopped
;
574 siggnal
= m32c_signal_to_target (M32C_STOP_SIG (rc
));
578 assert (M32C_EXITED (rc
));
580 siggnal
= M32C_EXIT_STATUS (rc
);
586 sim_resume (SIM_DESC sd
, int step
, int sig_to_deliver
)
590 if (sig_to_deliver
!= 0)
593 "Warning: the m32c minisim does not implement "
594 "signal delivery yet.\n" "Resuming with no signal.\n");
599 handle_step (decode_opcode ());
606 /* We don't clear 'stop' here, because then we would miss
607 interrupts that arrived on the way here. Instead, we clear
608 the flag in sim_stop_reason, after GDB has disabled the
609 interrupt signal handler. */
615 reason
= sim_stopped
;
616 siggnal
= TARGET_SIGNAL_INT
;
620 int rc
= decode_opcode ();
625 if (!M32C_STEPPED (rc
))
632 m32c_sim_restore_console ();
636 sim_stop (SIM_DESC sd
)
644 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason_p
, int *sigrc_p
)
653 sim_do_command (SIM_DESC sd
, char *cmd
)
659 /* Skip leading whitespace. */
663 /* Find the extent of the command word. */
664 for (p
= cmd
; *p
; p
++)
668 /* Null-terminate the command word, and record the start of any
669 further arguments. */
675 while (isspace (*args
))
681 if (strcmp (cmd
, "trace") == 0)
683 if (strcmp (args
, "on") == 0)
685 else if (strcmp (args
, "off") == 0)
688 printf ("The 'sim trace' command expects 'on' or 'off' "
689 "as an argument.\n");
691 else if (strcmp (cmd
, "verbose") == 0)
693 if (strcmp (args
, "on") == 0)
695 else if (strcmp (args
, "off") == 0)
698 printf ("The 'sim verbose' command expects 'on' or 'off'"
699 " as an argument.\n");
702 printf ("The 'sim' command expects either 'trace' or 'verbose'"
703 " as a subcommand.\n");
707 sim_complete_command (SIM_DESC sd
, char *text
, char *word
)
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