sim/m32r/cpu.h

   1 /* CPU family header for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RBF_H
  26 #define CPU_M32RBF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[16];
  49 #define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index)
  50 #define SET_H_CR(index, x) \
  51 do { \
  52 m32rbf_h_cr_set_handler (current_cpu, (index), (x));\
  53 } while (0)
  54   /* accumulator */
  55   DI h_accum;
  56 #define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu)
  57 #define SET_H_ACCUM(x) \
  58 do { \
  59 m32rbf_h_accum_set_handler (current_cpu, (x));\
  60 } while (0)
  61   /* condition bit */
  62   BI h_cond;
  63 #define GET_H_COND() CPU (h_cond)
  64 #define SET_H_COND(x) (CPU (h_cond) = (x))
  65   /* psw part of psw */
  66   UQI h_psw;
  67 #define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu)
  68 #define SET_H_PSW(x) \
  69 do { \
  70 m32rbf_h_psw_set_handler (current_cpu, (x));\
  71 } while (0)
  72   /* backup psw */
  73   UQI h_bpsw;
  74 #define GET_H_BPSW() CPU (h_bpsw)
  75 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
  76   /* backup bpsw */
  77   UQI h_bbpsw;
  78 #define GET_H_BBPSW() CPU (h_bbpsw)
  79 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
  80   /* lock */
  81   BI h_lock;
  82 #define GET_H_LOCK() CPU (h_lock)
  83 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  84   } hardware;
  85 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  86 } M32RBF_CPU_DATA;
  87
  88 /* Cover fns for register access.  */
  89 USI m32rbf_h_pc_get (SIM_CPU *);
  90 void m32rbf_h_pc_set (SIM_CPU *, USI);
  91 SI m32rbf_h_gr_get (SIM_CPU *, UINT);
  92 void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
  93 USI m32rbf_h_cr_get (SIM_CPU *, UINT);
  94 void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
  95 DI m32rbf_h_accum_get (SIM_CPU *);
  96 void m32rbf_h_accum_set (SIM_CPU *, DI);
  97 BI m32rbf_h_cond_get (SIM_CPU *);
  98 void m32rbf_h_cond_set (SIM_CPU *, BI);
  99 UQI m32rbf_h_psw_get (SIM_CPU *);
 100 void m32rbf_h_psw_set (SIM_CPU *, UQI);
 101 UQI m32rbf_h_bpsw_get (SIM_CPU *);
 102 void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
 103 UQI m32rbf_h_bbpsw_get (SIM_CPU *);
 104 void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
 105 BI m32rbf_h_lock_get (SIM_CPU *);
 106 void m32rbf_h_lock_set (SIM_CPU *, BI);
 107
 108 /* These must be hand-written.  */
 109 extern CPUREG_FETCH_FN m32rbf_fetch_register;
 110 extern CPUREG_STORE_FN m32rbf_store_register;
 111
 112 typedef struct {
 113   UINT h_gr;
 114 } MODEL_M32R_D_DATA;
 115
 116 typedef struct {
 117   int empty;
 118 } MODEL_TEST_DATA;
 119
 120 union sem_fields {
 121     struct { /* empty sformat for unspecified field list */
 122       int empty;
 123     } fmt_empty;
 124     struct { /* e.g. add $dr,$sr */
 125       SI * i_dr;
 126       SI * i_sr;
 127       unsigned char in_dr;
 128       unsigned char in_sr;
 129       unsigned char out_dr;
 130     } fmt_add;
 131     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
 132       INT f_simm16;
 133       SI * i_sr;
 134       SI * i_dr;
 135       unsigned char in_sr;
 136       unsigned char out_dr;
 137     } fmt_add3;
 138     struct { /* e.g. and3 $dr,$sr,$uimm16 */
 139       UINT f_uimm16;
 140       SI * i_sr;
 141       SI * i_dr;
 142       unsigned char in_sr;
 143       unsigned char out_dr;
 144     } fmt_and3;
 145     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
 146       UINT f_uimm16;
 147       SI * i_sr;
 148       SI * i_dr;
 149       unsigned char in_sr;
 150       unsigned char out_dr;
 151     } fmt_or3;
 152     struct { /* e.g. addi $dr,$simm8 */
 153       INT f_simm8;
 154       SI * i_dr;
 155       unsigned char in_dr;
 156       unsigned char out_dr;
 157     } fmt_addi;
 158     struct { /* e.g. addv $dr,$sr */
 159       SI * i_dr;
 160       SI * i_sr;
 161       unsigned char in_dr;
 162       unsigned char in_sr;
 163       unsigned char out_dr;
 164     } fmt_addv;
 165     struct { /* e.g. addv3 $dr,$sr,$simm16 */
 166       INT f_simm16;
 167       SI * i_sr;
 168       SI * i_dr;
 169       unsigned char in_sr;
 170       unsigned char out_dr;
 171     } fmt_addv3;
 172     struct { /* e.g. addx $dr,$sr */
 173       SI * i_dr;
 174       SI * i_sr;
 175       unsigned char in_dr;
 176       unsigned char in_sr;
 177       unsigned char out_dr;
 178     } fmt_addx;
 179     struct { /* e.g. cmp $src1,$src2 */
 180       SI * i_src1;
 181       SI * i_src2;
 182       unsigned char in_src1;
 183       unsigned char in_src2;
 184     } fmt_cmp;
 185     struct { /* e.g. cmpi $src2,$simm16 */
 186       INT f_simm16;
 187       SI * i_src2;
 188       unsigned char in_src2;
 189     } fmt_cmpi;
 190     struct { /* e.g. div $dr,$sr */
 191       SI * i_dr;
 192       SI * i_sr;
 193       unsigned char in_dr;
 194       unsigned char in_sr;
 195       unsigned char out_dr;
 196     } fmt_div;
 197     struct { /* e.g. ld $dr,@$sr */
 198       SI * i_sr;
 199       SI * i_dr;
 200       unsigned char in_sr;
 201       unsigned char out_dr;
 202     } fmt_ld;
 203     struct { /* e.g. ld $dr,@($slo16,$sr) */
 204       INT f_simm16;
 205       SI * i_sr;
 206       SI * i_dr;
 207       unsigned char in_sr;
 208       unsigned char out_dr;
 209     } fmt_ld_d;
 210     struct { /* e.g. ldb $dr,@$sr */
 211       SI * i_sr;
 212       SI * i_dr;
 213       unsigned char in_sr;
 214       unsigned char out_dr;
 215     } fmt_ldb;
 216     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 217       INT f_simm16;
 218       SI * i_sr;
 219       SI * i_dr;
 220       unsigned char in_sr;
 221       unsigned char out_dr;
 222     } fmt_ldb_d;
 223     struct { /* e.g. ldh $dr,@$sr */
 224       SI * i_sr;
 225       SI * i_dr;
 226       unsigned char in_sr;
 227       unsigned char out_dr;
 228     } fmt_ldh;
 229     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 230       INT f_simm16;
 231       SI * i_sr;
 232       SI * i_dr;
 233       unsigned char in_sr;
 234       unsigned char out_dr;
 235     } fmt_ldh_d;
 236     struct { /* e.g. ld $dr,@$sr+ */
 237       SI * i_sr;
 238       SI * i_dr;
 239       unsigned char in_sr;
 240       unsigned char out_dr;
 241       unsigned char out_sr;
 242     } fmt_ld_plus;
 243     struct { /* e.g. ld24 $dr,$uimm24 */
 244       ADDR i_uimm24;
 245       SI * i_dr;
 246       unsigned char out_dr;
 247     } fmt_ld24;
 248     struct { /* e.g. ldi8 $dr,$simm8 */
 249       INT f_simm8;
 250       SI * i_dr;
 251       unsigned char out_dr;
 252     } fmt_ldi8;
 253     struct { /* e.g. ldi16 $dr,$hash$slo16 */
 254       INT f_simm16;
 255       SI * i_dr;
 256       unsigned char out_dr;
 257     } fmt_ldi16;
 258     struct { /* e.g. lock $dr,@$sr */
 259       SI * i_sr;
 260       SI * i_dr;
 261       unsigned char in_sr;
 262       unsigned char out_dr;
 263     } fmt_lock;
 264     struct { /* e.g. machi $src1,$src2 */
 265       SI * i_src1;
 266       SI * i_src2;
 267       unsigned char in_src1;
 268       unsigned char in_src2;
 269     } fmt_machi;
 270     struct { /* e.g. mulhi $src1,$src2 */
 271       SI * i_src1;
 272       SI * i_src2;
 273       unsigned char in_src1;
 274       unsigned char in_src2;
 275     } fmt_mulhi;
 276     struct { /* e.g. mv $dr,$sr */
 277       SI * i_sr;
 278       SI * i_dr;
 279       unsigned char in_sr;
 280       unsigned char out_dr;
 281     } fmt_mv;
 282     struct { /* e.g. mvfachi $dr */
 283       SI * i_dr;
 284       unsigned char out_dr;
 285     } fmt_mvfachi;
 286     struct { /* e.g. mvfc $dr,$scr */
 287       UINT f_r2;
 288       SI * i_dr;
 289       unsigned char out_dr;
 290     } fmt_mvfc;
 291     struct { /* e.g. mvtachi $src1 */
 292       SI * i_src1;
 293       unsigned char in_src1;
 294     } fmt_mvtachi;
 295     struct { /* e.g. mvtc $sr,$dcr */
 296       UINT f_r1;
 297       SI * i_sr;
 298       unsigned char in_sr;
 299     } fmt_mvtc;
 300     struct { /* e.g. nop */
 301       int empty;
 302     } fmt_nop;
 303     struct { /* e.g. rac */
 304       int empty;
 305     } fmt_rac;
 306     struct { /* e.g. seth $dr,$hash$hi16 */
 307       UINT f_hi16;
 308       SI * i_dr;
 309       unsigned char out_dr;
 310     } fmt_seth;
 311     struct { /* e.g. sll3 $dr,$sr,$simm16 */
 312       INT f_simm16;
 313       SI * i_sr;
 314       SI * i_dr;
 315       unsigned char in_sr;
 316       unsigned char out_dr;
 317     } fmt_sll3;
 318     struct { /* e.g. slli $dr,$uimm5 */
 319       UINT f_uimm5;
 320       SI * i_dr;
 321       unsigned char in_dr;
 322       unsigned char out_dr;
 323     } fmt_slli;
 324     struct { /* e.g. st $src1,@$src2 */
 325       SI * i_src1;
 326       SI * i_src2;
 327       unsigned char in_src1;
 328       unsigned char in_src2;
 329     } fmt_st;
 330     struct { /* e.g. st $src1,@($slo16,$src2) */
 331       INT f_simm16;
 332       SI * i_src1;
 333       SI * i_src2;
 334       unsigned char in_src1;
 335       unsigned char in_src2;
 336     } fmt_st_d;
 337     struct { /* e.g. stb $src1,@$src2 */
 338       SI * i_src1;
 339       SI * i_src2;
 340       unsigned char in_src1;
 341       unsigned char in_src2;
 342     } fmt_stb;
 343     struct { /* e.g. stb $src1,@($slo16,$src2) */
 344       INT f_simm16;
 345       SI * i_src1;
 346       SI * i_src2;
 347       unsigned char in_src1;
 348       unsigned char in_src2;
 349     } fmt_stb_d;
 350     struct { /* e.g. sth $src1,@$src2 */
 351       SI * i_src1;
 352       SI * i_src2;
 353       unsigned char in_src1;
 354       unsigned char in_src2;
 355     } fmt_sth;
 356     struct { /* e.g. sth $src1,@($slo16,$src2) */
 357       INT f_simm16;
 358       SI * i_src1;
 359       SI * i_src2;
 360       unsigned char in_src1;
 361       unsigned char in_src2;
 362     } fmt_sth_d;
 363     struct { /* e.g. st $src1,@+$src2 */
 364       SI * i_src1;
 365       SI * i_src2;
 366       unsigned char in_src1;
 367       unsigned char in_src2;
 368       unsigned char out_src2;
 369     } fmt_st_plus;
 370     struct { /* e.g. unlock $src1,@$src2 */
 371       SI * i_src1;
 372       SI * i_src2;
 373       unsigned char in_src1;
 374       unsigned char in_src2;
 375     } fmt_unlock;
 376   /* cti insns, kept separately so addr_cache is in fixed place */
 377   struct {
 378     union {
 379     struct { /* e.g. bc.s $disp8 */
 380       IADDR i_disp8;
 381     } fmt_bc8;
 382     struct { /* e.g. bc.l $disp24 */
 383       IADDR i_disp24;
 384     } fmt_bc24;
 385     struct { /* e.g. beq $src1,$src2,$disp16 */
 386       IADDR i_disp16;
 387       SI * i_src1;
 388       SI * i_src2;
 389       unsigned char in_src1;
 390       unsigned char in_src2;
 391     } fmt_beq;
 392     struct { /* e.g. beqz $src2,$disp16 */
 393       IADDR i_disp16;
 394       SI * i_src2;
 395       unsigned char in_src2;
 396     } fmt_beqz;
 397     struct { /* e.g. bl.s $disp8 */
 398       IADDR i_disp8;
 399       unsigned char out_h_gr_14;
 400     } fmt_bl8;
 401     struct { /* e.g. bl.l $disp24 */
 402       IADDR i_disp24;
 403       unsigned char out_h_gr_14;
 404     } fmt_bl24;
 405     struct { /* e.g. bra.s $disp8 */
 406       IADDR i_disp8;
 407     } fmt_bra8;
 408     struct { /* e.g. bra.l $disp24 */
 409       IADDR i_disp24;
 410     } fmt_bra24;
 411     struct { /* e.g. jl $sr */
 412       SI * i_sr;
 413       unsigned char in_sr;
 414       unsigned char out_h_gr_14;
 415     } fmt_jl;
 416     struct { /* e.g. jmp $sr */
 417       SI * i_sr;
 418       unsigned char in_sr;
 419     } fmt_jmp;
 420     struct { /* e.g. rte */
 421       int empty;
 422     } fmt_rte;
 423     struct { /* e.g. trap $uimm4 */
 424       UINT f_uimm4;
 425     } fmt_trap;
 426     } fields;
 427 #if WITH_SCACHE_PBB
 428     SEM_PC addr_cache;
 429 #endif
 430   } cti;
 431 #if WITH_SCACHE_PBB
 432   /* Writeback handler.  */
 433   struct {
 434     /* Pointer to argbuf entry for insn whose results need writing back.  */
 435     const struct argbuf *abuf;
 436   } write;
 437   /* x-before handler */
 438   struct {
 439     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 440     int first_p;
 441   } before;
 442   /* x-after handler */
 443   struct {
 444     int empty;
 445   } after;
 446   /* This entry is used to terminate each pbb.  */
 447   struct {
 448     /* Number of insns in pbb.  */
 449     int insn_count;
 450     /* Next pbb to execute.  */
 451     SCACHE *next;
 452   } chain;
 453 #endif
 454 };
 455
 456 /* The ARGBUF struct.  */
 457 struct argbuf {
 458   /* These are the baseclass definitions.  */
 459   IADDR addr;
 460   const IDESC *idesc;
 461   char trace_p;
 462   char profile_p;
 463   /* cpu specific data follows */
 464   union sem semantic;
 465   int written;
 466   union sem_fields fields;
 467 };
 468
 469 /* A cached insn.
 470
 471    ??? SCACHE used to contain more than just argbuf.  We could delete the
 472    type entirely and always just use ARGBUF, but for future concerns and as
 473    a level of abstraction it is left in.  */
 474
 475 struct scache {
 476   struct argbuf argbuf;
 477 };
 478
 479 /* Macros to simplify extraction, reading and semantic code.
 480    These define and assign the local vars that contain the insn's fields.  */
 481
 482 #define EXTRACT_IFMT_EMPTY_VARS \
 483   /* Instruction fields.  */ \
 484   unsigned int length;
 485 #define EXTRACT_IFMT_EMPTY_CODE \
 486   length = 0; \
 487
 488 #define EXTRACT_IFMT_ADD_VARS \
 489   /* Instruction fields.  */ \
 490   UINT f_op1; \
 491   UINT f_r1; \
 492   UINT f_op2; \
 493   UINT f_r2; \
 494   unsigned int length;
 495 #define EXTRACT_IFMT_ADD_CODE \
 496   length = 2; \
 497   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 498   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 499   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 500   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 501
 502 #define EXTRACT_IFMT_ADD3_VARS \
 503   /* Instruction fields.  */ \
 504   UINT f_op1; \
 505   UINT f_r1; \
 506   UINT f_op2; \
 507   UINT f_r2; \
 508   INT f_simm16; \
 509   unsigned int length;
 510 #define EXTRACT_IFMT_ADD3_CODE \
 511   length = 4; \
 512   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 513   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 514   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 515   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 516   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 517
 518 #define EXTRACT_IFMT_AND3_VARS \
 519   /* Instruction fields.  */ \
 520   UINT f_op1; \
 521   UINT f_r1; \
 522   UINT f_op2; \
 523   UINT f_r2; \
 524   UINT f_uimm16; \
 525   unsigned int length;
 526 #define EXTRACT_IFMT_AND3_CODE \
 527   length = 4; \
 528   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 529   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 530   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 531   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 532   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 533
 534 #define EXTRACT_IFMT_OR3_VARS \
 535   /* Instruction fields.  */ \
 536   UINT f_op1; \
 537   UINT f_r1; \
 538   UINT f_op2; \
 539   UINT f_r2; \
 540   UINT f_uimm16; \
 541   unsigned int length;
 542 #define EXTRACT_IFMT_OR3_CODE \
 543   length = 4; \
 544   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 545   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 546   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 547   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 548   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 549
 550 #define EXTRACT_IFMT_ADDI_VARS \
 551   /* Instruction fields.  */ \
 552   UINT f_op1; \
 553   UINT f_r1; \
 554   INT f_simm8; \
 555   unsigned int length;
 556 #define EXTRACT_IFMT_ADDI_CODE \
 557   length = 2; \
 558   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 559   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 560   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 561
 562 #define EXTRACT_IFMT_ADDV3_VARS \
 563   /* Instruction fields.  */ \
 564   UINT f_op1; \
 565   UINT f_r1; \
 566   UINT f_op2; \
 567   UINT f_r2; \
 568   INT f_simm16; \
 569   unsigned int length;
 570 #define EXTRACT_IFMT_ADDV3_CODE \
 571   length = 4; \
 572   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 573   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 574   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 575   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 576   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 577
 578 #define EXTRACT_IFMT_BC8_VARS \
 579   /* Instruction fields.  */ \
 580   UINT f_op1; \
 581   UINT f_r1; \
 582   SI f_disp8; \
 583   unsigned int length;
 584 #define EXTRACT_IFMT_BC8_CODE \
 585   length = 2; \
 586   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 587   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 588   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 589
 590 #define EXTRACT_IFMT_BC24_VARS \
 591   /* Instruction fields.  */ \
 592   UINT f_op1; \
 593   UINT f_r1; \
 594   SI f_disp24; \
 595   unsigned int length;
 596 #define EXTRACT_IFMT_BC24_CODE \
 597   length = 4; \
 598   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 599   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 600   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 601
 602 #define EXTRACT_IFMT_BEQ_VARS \
 603   /* Instruction fields.  */ \
 604   UINT f_op1; \
 605   UINT f_r1; \
 606   UINT f_op2; \
 607   UINT f_r2; \
 608   SI f_disp16; \
 609   unsigned int length;
 610 #define EXTRACT_IFMT_BEQ_CODE \
 611   length = 4; \
 612   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 613   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 614   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 615   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 616   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 617
 618 #define EXTRACT_IFMT_BEQZ_VARS \
 619   /* Instruction fields.  */ \
 620   UINT f_op1; \
 621   UINT f_r1; \
 622   UINT f_op2; \
 623   UINT f_r2; \
 624   SI f_disp16; \
 625   unsigned int length;
 626 #define EXTRACT_IFMT_BEQZ_CODE \
 627   length = 4; \
 628   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 629   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 630   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 631   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 632   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 633
 634 #define EXTRACT_IFMT_CMP_VARS \
 635   /* Instruction fields.  */ \
 636   UINT f_op1; \
 637   UINT f_r1; \
 638   UINT f_op2; \
 639   UINT f_r2; \
 640   unsigned int length;
 641 #define EXTRACT_IFMT_CMP_CODE \
 642   length = 2; \
 643   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 644   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 645   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 646   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 647
 648 #define EXTRACT_IFMT_CMPI_VARS \
 649   /* Instruction fields.  */ \
 650   UINT f_op1; \
 651   UINT f_r1; \
 652   UINT f_op2; \
 653   UINT f_r2; \
 654   INT f_simm16; \
 655   unsigned int length;
 656 #define EXTRACT_IFMT_CMPI_CODE \
 657   length = 4; \
 658   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 659   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 660   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 661   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 662   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 663
 664 #define EXTRACT_IFMT_DIV_VARS \
 665   /* Instruction fields.  */ \
 666   UINT f_op1; \
 667   UINT f_r1; \
 668   UINT f_op2; \
 669   UINT f_r2; \
 670   INT f_simm16; \
 671   unsigned int length;
 672 #define EXTRACT_IFMT_DIV_CODE \
 673   length = 4; \
 674   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 675   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 676   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 677   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 678   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 679
 680 #define EXTRACT_IFMT_JL_VARS \
 681   /* Instruction fields.  */ \
 682   UINT f_op1; \
 683   UINT f_r1; \
 684   UINT f_op2; \
 685   UINT f_r2; \
 686   unsigned int length;
 687 #define EXTRACT_IFMT_JL_CODE \
 688   length = 2; \
 689   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 690   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 691   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 692   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 693
 694 #define EXTRACT_IFMT_LD24_VARS \
 695   /* Instruction fields.  */ \
 696   UINT f_op1; \
 697   UINT f_r1; \
 698   UINT f_uimm24; \
 699   unsigned int length;
 700 #define EXTRACT_IFMT_LD24_CODE \
 701   length = 4; \
 702   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 703   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 704   f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
 705
 706 #define EXTRACT_IFMT_LDI16_VARS \
 707   /* Instruction fields.  */ \
 708   UINT f_op1; \
 709   UINT f_r1; \
 710   UINT f_op2; \
 711   UINT f_r2; \
 712   INT f_simm16; \
 713   unsigned int length;
 714 #define EXTRACT_IFMT_LDI16_CODE \
 715   length = 4; \
 716   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 717   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 718   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 719   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 720   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 721
 722 #define EXTRACT_IFMT_MVFACHI_VARS \
 723   /* Instruction fields.  */ \
 724   UINT f_op1; \
 725   UINT f_r1; \
 726   UINT f_op2; \
 727   UINT f_r2; \
 728   unsigned int length;
 729 #define EXTRACT_IFMT_MVFACHI_CODE \
 730   length = 2; \
 731   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 732   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 733   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 734   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 735
 736 #define EXTRACT_IFMT_MVFC_VARS \
 737   /* Instruction fields.  */ \
 738   UINT f_op1; \
 739   UINT f_r1; \
 740   UINT f_op2; \
 741   UINT f_r2; \
 742   unsigned int length;
 743 #define EXTRACT_IFMT_MVFC_CODE \
 744   length = 2; \
 745   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 746   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 747   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 748   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 749
 750 #define EXTRACT_IFMT_MVTACHI_VARS \
 751   /* Instruction fields.  */ \
 752   UINT f_op1; \
 753   UINT f_r1; \
 754   UINT f_op2; \
 755   UINT f_r2; \
 756   unsigned int length;
 757 #define EXTRACT_IFMT_MVTACHI_CODE \
 758   length = 2; \
 759   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 760   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 761   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 762   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 763
 764 #define EXTRACT_IFMT_MVTC_VARS \
 765   /* Instruction fields.  */ \
 766   UINT f_op1; \
 767   UINT f_r1; \
 768   UINT f_op2; \
 769   UINT f_r2; \
 770   unsigned int length;
 771 #define EXTRACT_IFMT_MVTC_CODE \
 772   length = 2; \
 773   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 774   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 775   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 776   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 777
 778 #define EXTRACT_IFMT_NOP_VARS \
 779   /* Instruction fields.  */ \
 780   UINT f_op1; \
 781   UINT f_r1; \
 782   UINT f_op2; \
 783   UINT f_r2; \
 784   unsigned int length;
 785 #define EXTRACT_IFMT_NOP_CODE \
 786   length = 2; \
 787   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 788   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 789   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 790   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 791
 792 #define EXTRACT_IFMT_SETH_VARS \
 793   /* Instruction fields.  */ \
 794   UINT f_op1; \
 795   UINT f_r1; \
 796   UINT f_op2; \
 797   UINT f_r2; \
 798   UINT f_hi16; \
 799   unsigned int length;
 800 #define EXTRACT_IFMT_SETH_CODE \
 801   length = 4; \
 802   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 803   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 804   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 805   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 806   f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
 807
 808 #define EXTRACT_IFMT_SLLI_VARS \
 809   /* Instruction fields.  */ \
 810   UINT f_op1; \
 811   UINT f_r1; \
 812   UINT f_shift_op2; \
 813   UINT f_uimm5; \
 814   unsigned int length;
 815 #define EXTRACT_IFMT_SLLI_CODE \
 816   length = 2; \
 817   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 818   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 819   f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
 820   f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
 821
 822 #define EXTRACT_IFMT_ST_D_VARS \
 823   /* Instruction fields.  */ \
 824   UINT f_op1; \
 825   UINT f_r1; \
 826   UINT f_op2; \
 827   UINT f_r2; \
 828   INT f_simm16; \
 829   unsigned int length;
 830 #define EXTRACT_IFMT_ST_D_CODE \
 831   length = 4; \
 832   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 833   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 834   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 835   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 836   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 837
 838 #define EXTRACT_IFMT_TRAP_VARS \
 839   /* Instruction fields.  */ \
 840   UINT f_op1; \
 841   UINT f_r1; \
 842   UINT f_op2; \
 843   UINT f_uimm4; \
 844   unsigned int length;
 845 #define EXTRACT_IFMT_TRAP_CODE \
 846   length = 2; \
 847   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 848   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 849   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 850   f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
 851
 852 /* Collection of various things for the trace handler to use.  */
 853
 854 typedef struct trace_record {
 855   IADDR pc;
 856   /* FIXME:wip */
 857 } TRACE_RECORD;
 858
 859 #endif /* CPU_M32RBF_H */