1 /* CPU family header for m32rbf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
7 This file is part of the GNU simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>.
27 /* Maximum number of instructions that are fetched at a time.
28 This is for LIW type instructions sets (e.g. m32r). */
29 #define MAX_LIW_INSNS 2
31 /* Maximum number of instructions that can be executed in parallel. */
32 #define MAX_PARALLEL_INSNS 1
34 /* CPU state information. */
36 /* Hardware elements. */
40 #define GET_H_PC() CPU (h_pc)
41 #define SET_H_PC(x) (CPU (h_pc) = (x))
42 /* general registers */
44 #define GET_H_GR(a1) CPU (h_gr)[a1]
45 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
46 /* control registers */
48 #define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index)
49 #define SET_H_CR(index, x) \
51 m32rbf_h_cr_set_handler (current_cpu, (index), (x));\
55 #define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu)
56 #define SET_H_ACCUM(x) \
58 m32rbf_h_accum_set_handler (current_cpu, (x));\
62 #define GET_H_COND() CPU (h_cond)
63 #define SET_H_COND(x) (CPU (h_cond) = (x))
66 #define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu)
67 #define SET_H_PSW(x) \
69 m32rbf_h_psw_set_handler (current_cpu, (x));\
73 #define GET_H_BPSW() CPU (h_bpsw)
74 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
77 #define GET_H_BBPSW() CPU (h_bbpsw)
78 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
81 #define GET_H_LOCK() CPU (h_lock)
82 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
84 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
87 /* Cover fns for register access. */
88 USI
m32rbf_h_pc_get (SIM_CPU
*);
89 void m32rbf_h_pc_set (SIM_CPU
*, USI
);
90 SI
m32rbf_h_gr_get (SIM_CPU
*, UINT
);
91 void m32rbf_h_gr_set (SIM_CPU
*, UINT
, SI
);
92 USI
m32rbf_h_cr_get (SIM_CPU
*, UINT
);
93 void m32rbf_h_cr_set (SIM_CPU
*, UINT
, USI
);
94 DI
m32rbf_h_accum_get (SIM_CPU
*);
95 void m32rbf_h_accum_set (SIM_CPU
*, DI
);
96 BI
m32rbf_h_cond_get (SIM_CPU
*);
97 void m32rbf_h_cond_set (SIM_CPU
*, BI
);
98 UQI
m32rbf_h_psw_get (SIM_CPU
*);
99 void m32rbf_h_psw_set (SIM_CPU
*, UQI
);
100 UQI
m32rbf_h_bpsw_get (SIM_CPU
*);
101 void m32rbf_h_bpsw_set (SIM_CPU
*, UQI
);
102 UQI
m32rbf_h_bbpsw_get (SIM_CPU
*);
103 void m32rbf_h_bbpsw_set (SIM_CPU
*, UQI
);
104 BI
m32rbf_h_lock_get (SIM_CPU
*);
105 void m32rbf_h_lock_set (SIM_CPU
*, BI
);
107 /* These must be hand-written. */
108 extern CPUREG_FETCH_FN m32rbf_fetch_register
;
109 extern CPUREG_STORE_FN m32rbf_store_register
;
119 /* Instruction argument buffer. */
122 struct { /* no operands */
133 unsigned char out_h_gr_SI_14
;
137 unsigned char out_h_gr_SI_14
;
143 unsigned char out_dr
;
149 unsigned char out_dr
;
155 unsigned char out_h_gr_SI_14
;
169 unsigned char out_dr
;
176 unsigned char out_dr
;
183 unsigned char in_src1
;
184 unsigned char in_src2
;
185 unsigned char out_src2
;
193 unsigned char in_src1
;
194 unsigned char in_src2
;
202 unsigned char out_dr
;
203 unsigned char out_sr
;
211 unsigned char in_src1
;
212 unsigned char in_src2
;
221 unsigned char out_dr
;
230 unsigned char out_dr
;
239 unsigned char out_dr
;
242 /* Writeback handler. */
244 /* Pointer to argbuf entry for insn whose results need writing back. */
245 const struct argbuf
*abuf
;
247 /* x-before handler */
249 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
252 /* x-after handler */
256 /* This entry is used to terminate each pbb. */
258 /* Number of insns in pbb. */
260 /* Next pbb to execute. */
262 SCACHE
*branch_target
;
267 /* The ARGBUF struct. */
269 /* These are the baseclass definitions. */
274 /* ??? Temporary hack for skip insns. */
277 /* cpu specific data follows */
280 union sem_fields fields
;
285 ??? SCACHE used to contain more than just argbuf. We could delete the
286 type entirely and always just use ARGBUF, but for future concerns and as
287 a level of abstraction it is left in. */
290 struct argbuf argbuf
;
293 /* Macros to simplify extraction, reading and semantic code.
294 These define and assign the local vars that contain the insn's fields. */
296 #define EXTRACT_IFMT_EMPTY_VARS \
298 #define EXTRACT_IFMT_EMPTY_CODE \
301 #define EXTRACT_IFMT_ADD_VARS \
307 #define EXTRACT_IFMT_ADD_CODE \
309 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
310 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
311 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
312 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
314 #define EXTRACT_IFMT_ADD3_VARS \
321 #define EXTRACT_IFMT_ADD3_CODE \
323 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
324 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
325 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
326 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
327 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
329 #define EXTRACT_IFMT_AND3_VARS \
336 #define EXTRACT_IFMT_AND3_CODE \
338 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
339 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
340 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
341 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
342 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
344 #define EXTRACT_IFMT_OR3_VARS \
351 #define EXTRACT_IFMT_OR3_CODE \
353 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
354 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
355 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
356 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
357 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
359 #define EXTRACT_IFMT_ADDI_VARS \
364 #define EXTRACT_IFMT_ADDI_CODE \
366 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
367 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
368 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
370 #define EXTRACT_IFMT_ADDV3_VARS \
377 #define EXTRACT_IFMT_ADDV3_CODE \
379 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
380 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
381 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
382 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
383 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
385 #define EXTRACT_IFMT_BC8_VARS \
390 #define EXTRACT_IFMT_BC8_CODE \
392 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
393 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
394 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
396 #define EXTRACT_IFMT_BC24_VARS \
401 #define EXTRACT_IFMT_BC24_CODE \
403 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
404 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
405 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
407 #define EXTRACT_IFMT_BEQ_VARS \
414 #define EXTRACT_IFMT_BEQ_CODE \
416 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
417 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
418 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
419 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
420 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
422 #define EXTRACT_IFMT_BEQZ_VARS \
429 #define EXTRACT_IFMT_BEQZ_CODE \
431 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
432 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
433 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
434 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
435 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
437 #define EXTRACT_IFMT_CMP_VARS \
443 #define EXTRACT_IFMT_CMP_CODE \
445 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
446 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
447 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
448 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
450 #define EXTRACT_IFMT_CMPI_VARS \
457 #define EXTRACT_IFMT_CMPI_CODE \
459 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
460 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
461 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
462 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
463 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
465 #define EXTRACT_IFMT_DIV_VARS \
472 #define EXTRACT_IFMT_DIV_CODE \
474 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
475 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
476 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
477 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
478 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
480 #define EXTRACT_IFMT_JL_VARS \
486 #define EXTRACT_IFMT_JL_CODE \
488 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
489 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
490 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
491 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
493 #define EXTRACT_IFMT_LD24_VARS \
498 #define EXTRACT_IFMT_LD24_CODE \
500 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
501 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
502 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
504 #define EXTRACT_IFMT_LDI16_VARS \
511 #define EXTRACT_IFMT_LDI16_CODE \
513 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
514 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
515 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
516 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
517 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
519 #define EXTRACT_IFMT_MVFACHI_VARS \
525 #define EXTRACT_IFMT_MVFACHI_CODE \
527 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
528 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
529 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
530 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
532 #define EXTRACT_IFMT_MVFC_VARS \
538 #define EXTRACT_IFMT_MVFC_CODE \
540 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
541 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
542 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
543 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
545 #define EXTRACT_IFMT_MVTACHI_VARS \
551 #define EXTRACT_IFMT_MVTACHI_CODE \
553 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
554 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
555 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
556 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
558 #define EXTRACT_IFMT_MVTC_VARS \
564 #define EXTRACT_IFMT_MVTC_CODE \
566 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
567 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
568 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
569 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
571 #define EXTRACT_IFMT_NOP_VARS \
577 #define EXTRACT_IFMT_NOP_CODE \
579 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
580 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
581 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
582 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
584 #define EXTRACT_IFMT_SETH_VARS \
591 #define EXTRACT_IFMT_SETH_CODE \
593 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
594 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
595 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
596 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
597 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
599 #define EXTRACT_IFMT_SLLI_VARS \
605 #define EXTRACT_IFMT_SLLI_CODE \
607 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
608 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
609 f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
610 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
612 #define EXTRACT_IFMT_ST_D_VARS \
619 #define EXTRACT_IFMT_ST_D_CODE \
621 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
622 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
623 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
624 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
625 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
627 #define EXTRACT_IFMT_TRAP_VARS \
633 #define EXTRACT_IFMT_TRAP_CODE \
635 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
636 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
637 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
638 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
640 #define EXTRACT_IFMT_CLRPSW_VARS \
645 #define EXTRACT_IFMT_CLRPSW_CODE \
647 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
648 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
649 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
651 #define EXTRACT_IFMT_BSET_VARS \
659 #define EXTRACT_IFMT_BSET_CODE \
661 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
662 f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
663 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
664 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
665 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
666 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
668 #define EXTRACT_IFMT_BTST_VARS \
675 #define EXTRACT_IFMT_BTST_CODE \
677 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
678 f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
679 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
680 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
681 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
683 /* Collection of various things for the trace handler to use. */
685 typedef struct trace_record
{
690 #endif /* CPU_M32RBF_H */