1 /* CPU family header for m32rxf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 2
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 2
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
49 /* GET_H_CR macro user-written */
50 /* SET_H_CR macro user-written */
53 /* GET_H_ACCUM macro user-written */
54 /* SET_H_ACCUM macro user-written */
55 /* start-sanitize-m32rx */
58 /* end-sanitize-m32rx */
59 /* start-sanitize-m32rx */
60 /* GET_H_ACCUMS macro user-written */
61 /* SET_H_ACCUMS macro user-written */
62 /* end-sanitize-m32rx */
65 #define GET_H_COND() CPU (h_cond)
66 #define SET_H_COND(x) (CPU (h_cond) = (x))
69 /* GET_H_PSW macro user-written */
70 /* SET_H_PSW macro user-written */
73 #define GET_H_BPSW() CPU (h_bpsw)
74 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
77 #define GET_H_BBPSW() CPU (h_bbpsw)
78 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
81 #define GET_H_LOCK() CPU (h_lock)
82 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
84 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
87 /* Cover fns for register access. */
88 USI
m32rxf_h_pc_get (SIM_CPU
*);
89 void m32rxf_h_pc_set (SIM_CPU
*, USI
);
90 SI
m32rxf_h_gr_get (SIM_CPU
*, UINT
);
91 void m32rxf_h_gr_set (SIM_CPU
*, UINT
, SI
);
92 USI
m32rxf_h_cr_get (SIM_CPU
*, UINT
);
93 void m32rxf_h_cr_set (SIM_CPU
*, UINT
, USI
);
94 DI
m32rxf_h_accum_get (SIM_CPU
*);
95 void m32rxf_h_accum_set (SIM_CPU
*, DI
);
96 DI
m32rxf_h_accums_get (SIM_CPU
*, UINT
);
97 void m32rxf_h_accums_set (SIM_CPU
*, UINT
, DI
);
98 BI
m32rxf_h_cond_get (SIM_CPU
*);
99 void m32rxf_h_cond_set (SIM_CPU
*, BI
);
100 UQI
m32rxf_h_psw_get (SIM_CPU
*);
101 void m32rxf_h_psw_set (SIM_CPU
*, UQI
);
102 UQI
m32rxf_h_bpsw_get (SIM_CPU
*);
103 void m32rxf_h_bpsw_set (SIM_CPU
*, UQI
);
104 UQI
m32rxf_h_bbpsw_get (SIM_CPU
*);
105 void m32rxf_h_bbpsw_set (SIM_CPU
*, UQI
);
106 BI
m32rxf_h_lock_get (SIM_CPU
*);
107 void m32rxf_h_lock_set (SIM_CPU
*, BI
);
109 /* These must be hand-written. */
110 extern CPUREG_FETCH_FN m32rxf_fetch_register
;
111 extern CPUREG_STORE_FN m32rxf_store_register
;
118 struct { /* empty sformat for unspecified field list */
121 struct { /* e.g. add $dr,$sr */
126 unsigned char out_dr
;
128 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
133 unsigned char out_dr
;
135 struct { /* e.g. and3 $dr,$sr,$uimm16 */
140 unsigned char out_dr
;
142 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
147 unsigned char out_dr
;
149 struct { /* e.g. addi $dr,$simm8 */
153 unsigned char out_dr
;
155 struct { /* e.g. addv $dr,$sr */
160 unsigned char out_dr
;
162 struct { /* e.g. addv3 $dr,$sr,$simm16 */
167 unsigned char out_dr
;
169 struct { /* e.g. addx $dr,$sr */
174 unsigned char out_dr
;
176 struct { /* e.g. cmp $src1,$src2 */
179 unsigned char in_src1
;
180 unsigned char in_src2
;
182 struct { /* e.g. cmpi $src2,$simm16 */
185 unsigned char in_src2
;
187 struct { /* e.g. cmpz $src2 */
189 unsigned char in_src2
;
191 struct { /* e.g. div $dr,$sr */
196 unsigned char out_dr
;
198 struct { /* e.g. ld $dr,@$sr */
202 unsigned char out_dr
;
204 struct { /* e.g. ld $dr,@($slo16,$sr) */
209 unsigned char out_dr
;
211 struct { /* e.g. ldb $dr,@$sr */
215 unsigned char out_dr
;
217 struct { /* e.g. ldb $dr,@($slo16,$sr) */
222 unsigned char out_dr
;
224 struct { /* e.g. ldh $dr,@$sr */
228 unsigned char out_dr
;
230 struct { /* e.g. ldh $dr,@($slo16,$sr) */
235 unsigned char out_dr
;
237 struct { /* e.g. ld $dr,@$sr+ */
241 unsigned char out_dr
;
242 unsigned char out_sr
;
244 struct { /* e.g. ld24 $dr,$uimm24 */
247 unsigned char out_dr
;
249 struct { /* e.g. ldi8 $dr,$simm8 */
252 unsigned char out_dr
;
254 struct { /* e.g. ldi16 $dr,$hash$slo16 */
257 unsigned char out_dr
;
259 struct { /* e.g. lock $dr,@$sr */
263 unsigned char out_dr
;
265 struct { /* e.g. machi $src1,$src2,$acc */
269 unsigned char in_src1
;
270 unsigned char in_src2
;
272 struct { /* e.g. mulhi $src1,$src2,$acc */
276 unsigned char in_src1
;
277 unsigned char in_src2
;
279 struct { /* e.g. mv $dr,$sr */
283 unsigned char out_dr
;
285 struct { /* e.g. mvfachi $dr,$accs */
288 unsigned char out_dr
;
290 struct { /* e.g. mvfc $dr,$scr */
293 unsigned char out_dr
;
295 struct { /* e.g. mvtachi $src1,$accs */
298 unsigned char in_src1
;
300 struct { /* e.g. mvtc $sr,$dcr */
305 struct { /* e.g. nop */
308 struct { /* e.g. rac $accd,$accs,$imm1 */
313 struct { /* e.g. seth $dr,$hash$hi16 */
316 unsigned char out_dr
;
318 struct { /* e.g. sll3 $dr,$sr,$simm16 */
323 unsigned char out_dr
;
325 struct { /* e.g. slli $dr,$uimm5 */
329 unsigned char out_dr
;
331 struct { /* e.g. st $src1,@$src2 */
334 unsigned char in_src1
;
335 unsigned char in_src2
;
337 struct { /* e.g. st $src1,@($slo16,$src2) */
341 unsigned char in_src1
;
342 unsigned char in_src2
;
344 struct { /* e.g. stb $src1,@$src2 */
347 unsigned char in_src1
;
348 unsigned char in_src2
;
350 struct { /* e.g. stb $src1,@($slo16,$src2) */
354 unsigned char in_src1
;
355 unsigned char in_src2
;
357 struct { /* e.g. sth $src1,@$src2 */
360 unsigned char in_src1
;
361 unsigned char in_src2
;
363 struct { /* e.g. sth $src1,@($slo16,$src2) */
367 unsigned char in_src1
;
368 unsigned char in_src2
;
370 struct { /* e.g. st $src1,@+$src2 */
373 unsigned char in_src1
;
374 unsigned char in_src2
;
375 unsigned char out_src2
;
377 struct { /* e.g. unlock $src1,@$src2 */
380 unsigned char in_src1
;
381 unsigned char in_src2
;
383 struct { /* e.g. satb $dr,$sr */
387 unsigned char out_dr
;
389 struct { /* e.g. sat $dr,$sr */
393 unsigned char out_dr
;
395 struct { /* e.g. sadd */
398 struct { /* e.g. macwu1 $src1,$src2 */
401 unsigned char in_src1
;
402 unsigned char in_src2
;
404 struct { /* e.g. msblo $src1,$src2 */
407 unsigned char in_src1
;
408 unsigned char in_src2
;
410 struct { /* e.g. mulwu1 $src1,$src2 */
413 unsigned char in_src1
;
414 unsigned char in_src2
;
416 /* cti insns, kept separately so addr_cache is in fixed place */
419 struct { /* e.g. bc.s $disp8 */
422 struct { /* e.g. bc.l $disp24 */
425 struct { /* e.g. beq $src1,$src2,$disp16 */
429 unsigned char in_src1
;
430 unsigned char in_src2
;
432 struct { /* e.g. beqz $src2,$disp16 */
435 unsigned char in_src2
;
437 struct { /* e.g. bl.s $disp8 */
439 unsigned char out_h_gr_14
;
441 struct { /* e.g. bl.l $disp24 */
443 unsigned char out_h_gr_14
;
445 struct { /* e.g. bcl.s $disp8 */
447 unsigned char out_h_gr_14
;
449 struct { /* e.g. bcl.l $disp24 */
451 unsigned char out_h_gr_14
;
453 struct { /* e.g. bra.s $disp8 */
456 struct { /* e.g. bra.l $disp24 */
459 struct { /* e.g. jc $sr */
463 struct { /* e.g. jl $sr */
466 unsigned char out_h_gr_14
;
468 struct { /* e.g. jmp $sr */
472 struct { /* e.g. rte */
475 struct { /* e.g. trap $uimm4 */
478 struct { /* e.g. sc */
487 /* Writeback handler. */
489 /* Pointer to argbuf entry for insn whose results need writing back. */
490 const struct argbuf
*abuf
;
492 /* x-before handler */
494 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
497 /* x-after handler */
501 /* This entry is used to terminate each pbb. */
503 /* Number of insns in pbb. */
505 /* Next pbb to execute. */
511 /* The ARGBUF struct. */
513 /* These are the baseclass definitions. */
518 /* cpu specific data follows */
521 union sem_fields fields
;
526 ??? SCACHE used to contain more than just argbuf. We could delete the
527 type entirely and always just use ARGBUF, but for future concerns and as
528 a level of abstraction it is left in. */
531 struct argbuf argbuf
;
534 /* Macros to simplify extraction, reading and semantic code.
535 These define and assign the local vars that contain the insn's fields. */
537 #define EXTRACT_IFMT_EMPTY_VARS \
538 /* Instruction fields. */ \
540 #define EXTRACT_IFMT_EMPTY_CODE \
543 #define EXTRACT_IFMT_ADD_VARS \
544 /* Instruction fields. */ \
550 #define EXTRACT_IFMT_ADD_CODE \
552 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
553 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
554 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
555 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
557 #define EXTRACT_IFMT_ADD3_VARS \
558 /* Instruction fields. */ \
565 #define EXTRACT_IFMT_ADD3_CODE \
567 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
568 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
569 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
570 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
571 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
573 #define EXTRACT_IFMT_AND3_VARS \
574 /* Instruction fields. */ \
581 #define EXTRACT_IFMT_AND3_CODE \
583 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
584 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
585 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
586 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
587 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
589 #define EXTRACT_IFMT_OR3_VARS \
590 /* Instruction fields. */ \
597 #define EXTRACT_IFMT_OR3_CODE \
599 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
600 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
601 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
602 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
603 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
605 #define EXTRACT_IFMT_ADDI_VARS \
606 /* Instruction fields. */ \
611 #define EXTRACT_IFMT_ADDI_CODE \
613 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
614 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
615 f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
617 #define EXTRACT_IFMT_ADDV3_VARS \
618 /* Instruction fields. */ \
625 #define EXTRACT_IFMT_ADDV3_CODE \
627 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
628 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
629 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
630 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
631 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
633 #define EXTRACT_IFMT_BC8_VARS \
634 /* Instruction fields. */ \
639 #define EXTRACT_IFMT_BC8_CODE \
641 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
642 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
643 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
645 #define EXTRACT_IFMT_BC24_VARS \
646 /* Instruction fields. */ \
651 #define EXTRACT_IFMT_BC24_CODE \
653 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
654 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
655 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
657 #define EXTRACT_IFMT_BEQ_VARS \
658 /* Instruction fields. */ \
665 #define EXTRACT_IFMT_BEQ_CODE \
667 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
668 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
669 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
670 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
671 f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
673 #define EXTRACT_IFMT_BEQZ_VARS \
674 /* Instruction fields. */ \
681 #define EXTRACT_IFMT_BEQZ_CODE \
683 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
684 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
685 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
686 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
687 f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
689 #define EXTRACT_IFMT_CMP_VARS \
690 /* Instruction fields. */ \
696 #define EXTRACT_IFMT_CMP_CODE \
698 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
699 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
700 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
701 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
703 #define EXTRACT_IFMT_CMPI_VARS \
704 /* Instruction fields. */ \
711 #define EXTRACT_IFMT_CMPI_CODE \
713 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
714 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
715 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
716 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
717 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
719 #define EXTRACT_IFMT_CMPZ_VARS \
720 /* Instruction fields. */ \
726 #define EXTRACT_IFMT_CMPZ_CODE \
728 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
729 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
730 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
731 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
733 #define EXTRACT_IFMT_DIV_VARS \
734 /* Instruction fields. */ \
741 #define EXTRACT_IFMT_DIV_CODE \
743 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
744 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
745 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
746 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
747 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
749 #define EXTRACT_IFMT_JC_VARS \
750 /* Instruction fields. */ \
756 #define EXTRACT_IFMT_JC_CODE \
758 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
759 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
760 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
761 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
763 #define EXTRACT_IFMT_LD24_VARS \
764 /* Instruction fields. */ \
769 #define EXTRACT_IFMT_LD24_CODE \
771 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
772 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
773 f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
775 #define EXTRACT_IFMT_LDI16_VARS \
776 /* Instruction fields. */ \
783 #define EXTRACT_IFMT_LDI16_CODE \
785 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
786 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
787 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
788 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
789 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
791 #define EXTRACT_IFMT_MACHI_A_VARS \
792 /* Instruction fields. */ \
799 #define EXTRACT_IFMT_MACHI_A_CODE \
801 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
802 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
803 f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
804 f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
805 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
807 #define EXTRACT_IFMT_MVFACHI_A_VARS \
808 /* Instruction fields. */ \
815 #define EXTRACT_IFMT_MVFACHI_A_CODE \
817 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
818 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
819 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
820 f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
821 f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
823 #define EXTRACT_IFMT_MVFC_VARS \
824 /* Instruction fields. */ \
830 #define EXTRACT_IFMT_MVFC_CODE \
832 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
833 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
834 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
835 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
837 #define EXTRACT_IFMT_MVTACHI_A_VARS \
838 /* Instruction fields. */ \
845 #define EXTRACT_IFMT_MVTACHI_A_CODE \
847 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
848 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
849 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
850 f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
851 f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
853 #define EXTRACT_IFMT_MVTC_VARS \
854 /* Instruction fields. */ \
860 #define EXTRACT_IFMT_MVTC_CODE \
862 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
863 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
864 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
865 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
867 #define EXTRACT_IFMT_NOP_VARS \
868 /* Instruction fields. */ \
874 #define EXTRACT_IFMT_NOP_CODE \
876 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
877 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
878 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
879 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
881 #define EXTRACT_IFMT_RAC_DSI_VARS \
882 /* Instruction fields. */ \
891 #define EXTRACT_IFMT_RAC_DSI_CODE \
893 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
894 f_accd = EXTRACT_UINT (insn, 16, 4, 2); \
895 f_bits67 = EXTRACT_UINT (insn, 16, 6, 2); \
896 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
897 f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
898 f_bit14 = EXTRACT_UINT (insn, 16, 14, 1); \
899 f_imm1 = ((EXTRACT_UINT (insn, 16, 15, 1)) + (1)); \
901 #define EXTRACT_IFMT_SETH_VARS \
902 /* Instruction fields. */ \
909 #define EXTRACT_IFMT_SETH_CODE \
911 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
912 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
913 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
914 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
915 f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
917 #define EXTRACT_IFMT_SLLI_VARS \
918 /* Instruction fields. */ \
924 #define EXTRACT_IFMT_SLLI_CODE \
926 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
927 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
928 f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
929 f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
931 #define EXTRACT_IFMT_ST_D_VARS \
932 /* Instruction fields. */ \
939 #define EXTRACT_IFMT_ST_D_CODE \
941 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
942 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
943 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
944 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
945 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
947 #define EXTRACT_IFMT_TRAP_VARS \
948 /* Instruction fields. */ \
954 #define EXTRACT_IFMT_TRAP_CODE \
956 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
957 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
958 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
959 f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
961 #define EXTRACT_IFMT_SATB_VARS \
962 /* Instruction fields. */ \
969 #define EXTRACT_IFMT_SATB_CODE \
971 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
972 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
973 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
974 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
975 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
977 /* Queued output values of an instruction. */
981 struct { /* empty sformat for unspecified field list */
984 struct { /* e.g. add $dr,$sr */
987 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
990 struct { /* e.g. and3 $dr,$sr,$uimm16 */
993 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
996 struct { /* e.g. addi $dr,$simm8 */
999 struct { /* e.g. addv $dr,$sr */
1003 struct { /* e.g. addv3 $dr,$sr,$simm16 */
1007 struct { /* e.g. addx $dr,$sr */
1011 struct { /* e.g. bc.s $disp8 */
1014 struct { /* e.g. bc.l $disp24 */
1017 struct { /* e.g. beq $src1,$src2,$disp16 */
1020 struct { /* e.g. beqz $src2,$disp16 */
1023 struct { /* e.g. bl.s $disp8 */
1027 struct { /* e.g. bl.l $disp24 */
1031 struct { /* e.g. bcl.s $disp8 */
1035 struct { /* e.g. bcl.l $disp24 */
1039 struct { /* e.g. bra.s $disp8 */
1042 struct { /* e.g. bra.l $disp24 */
1045 struct { /* e.g. cmp $src1,$src2 */
1048 struct { /* e.g. cmpi $src2,$simm16 */
1051 struct { /* e.g. cmpz $src2 */
1054 struct { /* e.g. div $dr,$sr */
1057 struct { /* e.g. jc $sr */
1060 struct { /* e.g. jl $sr */
1064 struct { /* e.g. jmp $sr */
1067 struct { /* e.g. ld $dr,@$sr */
1070 struct { /* e.g. ld $dr,@($slo16,$sr) */
1073 struct { /* e.g. ldb $dr,@$sr */
1076 struct { /* e.g. ldb $dr,@($slo16,$sr) */
1079 struct { /* e.g. ldh $dr,@$sr */
1082 struct { /* e.g. ldh $dr,@($slo16,$sr) */
1085 struct { /* e.g. ld $dr,@$sr+ */
1089 struct { /* e.g. ld24 $dr,$uimm24 */
1092 struct { /* e.g. ldi8 $dr,$simm8 */
1095 struct { /* e.g. ldi16 $dr,$hash$slo16 */
1098 struct { /* e.g. lock $dr,@$sr */
1102 struct { /* e.g. machi $src1,$src2,$acc */
1105 struct { /* e.g. mulhi $src1,$src2,$acc */
1108 struct { /* e.g. mv $dr,$sr */
1111 struct { /* e.g. mvfachi $dr,$accs */
1114 struct { /* e.g. mvfc $dr,$scr */
1117 struct { /* e.g. mvtachi $src1,$accs */
1120 struct { /* e.g. mvtc $sr,$dcr */
1123 struct { /* e.g. nop */
1126 struct { /* e.g. rac $accd,$accs,$imm1 */
1129 struct { /* e.g. rte */
1135 struct { /* e.g. seth $dr,$hash$hi16 */
1138 struct { /* e.g. sll3 $dr,$sr,$simm16 */
1141 struct { /* e.g. slli $dr,$uimm5 */
1144 struct { /* e.g. st $src1,@$src2 */
1146 USI h_memory_src2_idx
;
1148 struct { /* e.g. st $src1,@($slo16,$src2) */
1149 SI h_memory_add__VM_src2_slo16
;
1150 USI h_memory_add__VM_src2_slo16_idx
;
1152 struct { /* e.g. stb $src1,@$src2 */
1154 USI h_memory_src2_idx
;
1156 struct { /* e.g. stb $src1,@($slo16,$src2) */
1157 QI h_memory_add__VM_src2_slo16
;
1158 USI h_memory_add__VM_src2_slo16_idx
;
1160 struct { /* e.g. sth $src1,@$src2 */
1162 USI h_memory_src2_idx
;
1164 struct { /* e.g. sth $src1,@($slo16,$src2) */
1165 HI h_memory_add__VM_src2_slo16
;
1166 USI h_memory_add__VM_src2_slo16_idx
;
1168 struct { /* e.g. st $src1,@+$src2 */
1169 SI h_memory_new_src2
;
1170 USI h_memory_new_src2_idx
;
1173 struct { /* e.g. trap $uimm4 */
1181 struct { /* e.g. unlock $src1,@$src2 */
1184 USI h_memory_src2_idx
;
1186 struct { /* e.g. satb $dr,$sr */
1189 struct { /* e.g. sat $dr,$sr */
1192 struct { /* e.g. sadd */
1195 struct { /* e.g. macwu1 $src1,$src2 */
1198 struct { /* e.g. msblo $src1,$src2 */
1201 struct { /* e.g. mulwu1 $src1,$src2 */
1204 struct { /* e.g. sc */
1208 /* For conditionally written operands, bitmask of which ones were. */
1212 /* Collection of various things for the trace handler to use. */
1214 typedef struct trace_record
{
1219 #endif /* CPU_M32RXF_H */