1 /* Simulator instruction decoder for m32rxf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 #define WANT_CPU m32rxf
26 #define WANT_CPU_M32RXF
29 #include "sim-assert.h"
31 /* Insn can't be executed in parallel.
32 Or is that "do NOt Pass to Air defense Radar"? :-) */
35 /* The instruction descriptor array.
36 This is computed at runtime. Space for it is not malloc'd to save a
37 teensy bit of cpu in the decoder. Moving it to malloc space is trivial
38 but won't be done until necessary (we don't currently support the runtime
39 addition of instructions nor an SMP machine with different cpus). */
40 static IDESC m32rxf_insn_data
[M32RXF_INSN_MAX
];
42 /* Commas between elements are contained in the macros.
43 Some of these are conditionally compiled out. */
45 static const struct insn_sem m32rxf_insn_sem
[] =
47 { VIRTUAL_INSN_X_INVALID
, M32RXF_INSN_X_INVALID
, M32RXF_SFMT_EMPTY
, NOPAR
, NOPAR
},
48 { VIRTUAL_INSN_X_AFTER
, M32RXF_INSN_X_AFTER
, M32RXF_SFMT_EMPTY
, NOPAR
, NOPAR
},
49 { VIRTUAL_INSN_X_BEFORE
, M32RXF_INSN_X_BEFORE
, M32RXF_SFMT_EMPTY
, NOPAR
, NOPAR
},
50 { VIRTUAL_INSN_X_CTI_CHAIN
, M32RXF_INSN_X_CTI_CHAIN
, M32RXF_SFMT_EMPTY
, NOPAR
, NOPAR
},
51 { VIRTUAL_INSN_X_CHAIN
, M32RXF_INSN_X_CHAIN
, M32RXF_SFMT_EMPTY
, NOPAR
, NOPAR
},
52 { VIRTUAL_INSN_X_BEGIN
, M32RXF_INSN_X_BEGIN
, M32RXF_SFMT_EMPTY
, NOPAR
, NOPAR
},
53 { M32R_INSN_ADD
, M32RXF_INSN_ADD
, M32RXF_SFMT_ADD
, M32RXF_INSN_PAR_ADD
, M32RXF_INSN_WRITE_ADD
},
54 { M32R_INSN_ADD3
, M32RXF_INSN_ADD3
, M32RXF_SFMT_ADD3
, NOPAR
, NOPAR
},
55 { M32R_INSN_AND
, M32RXF_INSN_AND
, M32RXF_SFMT_ADD
, M32RXF_INSN_PAR_AND
, M32RXF_INSN_WRITE_AND
},
56 { M32R_INSN_AND3
, M32RXF_INSN_AND3
, M32RXF_SFMT_AND3
, NOPAR
, NOPAR
},
57 { M32R_INSN_OR
, M32RXF_INSN_OR
, M32RXF_SFMT_ADD
, M32RXF_INSN_PAR_OR
, M32RXF_INSN_WRITE_OR
},
58 { M32R_INSN_OR3
, M32RXF_INSN_OR3
, M32RXF_SFMT_OR3
, NOPAR
, NOPAR
},
59 { M32R_INSN_XOR
, M32RXF_INSN_XOR
, M32RXF_SFMT_ADD
, M32RXF_INSN_PAR_XOR
, M32RXF_INSN_WRITE_XOR
},
60 { M32R_INSN_XOR3
, M32RXF_INSN_XOR3
, M32RXF_SFMT_AND3
, NOPAR
, NOPAR
},
61 { M32R_INSN_ADDI
, M32RXF_INSN_ADDI
, M32RXF_SFMT_ADDI
, M32RXF_INSN_PAR_ADDI
, M32RXF_INSN_WRITE_ADDI
},
62 { M32R_INSN_ADDV
, M32RXF_INSN_ADDV
, M32RXF_SFMT_ADDV
, M32RXF_INSN_PAR_ADDV
, M32RXF_INSN_WRITE_ADDV
},
63 { M32R_INSN_ADDV3
, M32RXF_INSN_ADDV3
, M32RXF_SFMT_ADDV3
, NOPAR
, NOPAR
},
64 { M32R_INSN_ADDX
, M32RXF_INSN_ADDX
, M32RXF_SFMT_ADDX
, M32RXF_INSN_PAR_ADDX
, M32RXF_INSN_WRITE_ADDX
},
65 { M32R_INSN_BC8
, M32RXF_INSN_BC8
, M32RXF_SFMT_BC8
, M32RXF_INSN_PAR_BC8
, M32RXF_INSN_WRITE_BC8
},
66 { M32R_INSN_BC24
, M32RXF_INSN_BC24
, M32RXF_SFMT_BC24
, NOPAR
, NOPAR
},
67 { M32R_INSN_BEQ
, M32RXF_INSN_BEQ
, M32RXF_SFMT_BEQ
, NOPAR
, NOPAR
},
68 { M32R_INSN_BEQZ
, M32RXF_INSN_BEQZ
, M32RXF_SFMT_BEQZ
, NOPAR
, NOPAR
},
69 { M32R_INSN_BGEZ
, M32RXF_INSN_BGEZ
, M32RXF_SFMT_BEQZ
, NOPAR
, NOPAR
},
70 { M32R_INSN_BGTZ
, M32RXF_INSN_BGTZ
, M32RXF_SFMT_BEQZ
, NOPAR
, NOPAR
},
71 { M32R_INSN_BLEZ
, M32RXF_INSN_BLEZ
, M32RXF_SFMT_BEQZ
, NOPAR
, NOPAR
},
72 { M32R_INSN_BLTZ
, M32RXF_INSN_BLTZ
, M32RXF_SFMT_BEQZ
, NOPAR
, NOPAR
},
73 { M32R_INSN_BNEZ
, M32RXF_INSN_BNEZ
, M32RXF_SFMT_BEQZ
, NOPAR
, NOPAR
},
74 { M32R_INSN_BL8
, M32RXF_INSN_BL8
, M32RXF_SFMT_BL8
, M32RXF_INSN_PAR_BL8
, M32RXF_INSN_WRITE_BL8
},
75 { M32R_INSN_BL24
, M32RXF_INSN_BL24
, M32RXF_SFMT_BL24
, NOPAR
, NOPAR
},
76 { M32R_INSN_BCL8
, M32RXF_INSN_BCL8
, M32RXF_SFMT_BCL8
, M32RXF_INSN_PAR_BCL8
, M32RXF_INSN_WRITE_BCL8
},
77 { M32R_INSN_BCL24
, M32RXF_INSN_BCL24
, M32RXF_SFMT_BCL24
, NOPAR
, NOPAR
},
78 { M32R_INSN_BNC8
, M32RXF_INSN_BNC8
, M32RXF_SFMT_BC8
, M32RXF_INSN_PAR_BNC8
, M32RXF_INSN_WRITE_BNC8
},
79 { M32R_INSN_BNC24
, M32RXF_INSN_BNC24
, M32RXF_SFMT_BC24
, NOPAR
, NOPAR
},
80 { M32R_INSN_BNE
, M32RXF_INSN_BNE
, M32RXF_SFMT_BEQ
, NOPAR
, NOPAR
},
81 { M32R_INSN_BRA8
, M32RXF_INSN_BRA8
, M32RXF_SFMT_BRA8
, M32RXF_INSN_PAR_BRA8
, M32RXF_INSN_WRITE_BRA8
},
82 { M32R_INSN_BRA24
, M32RXF_INSN_BRA24
, M32RXF_SFMT_BRA24
, NOPAR
, NOPAR
},
83 { M32R_INSN_BNCL8
, M32RXF_INSN_BNCL8
, M32RXF_SFMT_BCL8
, M32RXF_INSN_PAR_BNCL8
, M32RXF_INSN_WRITE_BNCL8
},
84 { M32R_INSN_BNCL24
, M32RXF_INSN_BNCL24
, M32RXF_SFMT_BCL24
, NOPAR
, NOPAR
},
85 { M32R_INSN_CMP
, M32RXF_INSN_CMP
, M32RXF_SFMT_CMP
, M32RXF_INSN_PAR_CMP
, M32RXF_INSN_WRITE_CMP
},
86 { M32R_INSN_CMPI
, M32RXF_INSN_CMPI
, M32RXF_SFMT_CMPI
, NOPAR
, NOPAR
},
87 { M32R_INSN_CMPU
, M32RXF_INSN_CMPU
, M32RXF_SFMT_CMP
, M32RXF_INSN_PAR_CMPU
, M32RXF_INSN_WRITE_CMPU
},
88 { M32R_INSN_CMPUI
, M32RXF_INSN_CMPUI
, M32RXF_SFMT_CMPI
, NOPAR
, NOPAR
},
89 { M32R_INSN_CMPEQ
, M32RXF_INSN_CMPEQ
, M32RXF_SFMT_CMP
, M32RXF_INSN_PAR_CMPEQ
, M32RXF_INSN_WRITE_CMPEQ
},
90 { M32R_INSN_CMPZ
, M32RXF_INSN_CMPZ
, M32RXF_SFMT_CMPZ
, M32RXF_INSN_PAR_CMPZ
, M32RXF_INSN_WRITE_CMPZ
},
91 { M32R_INSN_DIV
, M32RXF_INSN_DIV
, M32RXF_SFMT_DIV
, NOPAR
, NOPAR
},
92 { M32R_INSN_DIVU
, M32RXF_INSN_DIVU
, M32RXF_SFMT_DIV
, NOPAR
, NOPAR
},
93 { M32R_INSN_REM
, M32RXF_INSN_REM
, M32RXF_SFMT_DIV
, NOPAR
, NOPAR
},
94 { M32R_INSN_REMU
, M32RXF_INSN_REMU
, M32RXF_SFMT_DIV
, NOPAR
, NOPAR
},
95 { M32R_INSN_DIVH
, M32RXF_INSN_DIVH
, M32RXF_SFMT_DIV
, NOPAR
, NOPAR
},
96 { M32R_INSN_JC
, M32RXF_INSN_JC
, M32RXF_SFMT_JC
, M32RXF_INSN_PAR_JC
, M32RXF_INSN_WRITE_JC
},
97 { M32R_INSN_JNC
, M32RXF_INSN_JNC
, M32RXF_SFMT_JC
, M32RXF_INSN_PAR_JNC
, M32RXF_INSN_WRITE_JNC
},
98 { M32R_INSN_JL
, M32RXF_INSN_JL
, M32RXF_SFMT_JL
, M32RXF_INSN_PAR_JL
, M32RXF_INSN_WRITE_JL
},
99 { M32R_INSN_JMP
, M32RXF_INSN_JMP
, M32RXF_SFMT_JMP
, M32RXF_INSN_PAR_JMP
, M32RXF_INSN_WRITE_JMP
},
100 { M32R_INSN_LD
, M32RXF_INSN_LD
, M32RXF_SFMT_LD
, M32RXF_INSN_PAR_LD
, M32RXF_INSN_WRITE_LD
},
101 { M32R_INSN_LD_D
, M32RXF_INSN_LD_D
, M32RXF_SFMT_LD_D
, NOPAR
, NOPAR
},
102 { M32R_INSN_LDB
, M32RXF_INSN_LDB
, M32RXF_SFMT_LD
, M32RXF_INSN_PAR_LDB
, M32RXF_INSN_WRITE_LDB
},
103 { M32R_INSN_LDB_D
, M32RXF_INSN_LDB_D
, M32RXF_SFMT_LD_D
, NOPAR
, NOPAR
},
104 { M32R_INSN_LDH
, M32RXF_INSN_LDH
, M32RXF_SFMT_LD
, M32RXF_INSN_PAR_LDH
, M32RXF_INSN_WRITE_LDH
},
105 { M32R_INSN_LDH_D
, M32RXF_INSN_LDH_D
, M32RXF_SFMT_LD_D
, NOPAR
, NOPAR
},
106 { M32R_INSN_LDUB
, M32RXF_INSN_LDUB
, M32RXF_SFMT_LD
, M32RXF_INSN_PAR_LDUB
, M32RXF_INSN_WRITE_LDUB
},
107 { M32R_INSN_LDUB_D
, M32RXF_INSN_LDUB_D
, M32RXF_SFMT_LD_D
, NOPAR
, NOPAR
},
108 { M32R_INSN_LDUH
, M32RXF_INSN_LDUH
, M32RXF_SFMT_LD
, M32RXF_INSN_PAR_LDUH
, M32RXF_INSN_WRITE_LDUH
},
109 { M32R_INSN_LDUH_D
, M32RXF_INSN_LDUH_D
, M32RXF_SFMT_LD_D
, NOPAR
, NOPAR
},
110 { M32R_INSN_LD_PLUS
, M32RXF_INSN_LD_PLUS
, M32RXF_SFMT_LD_PLUS
, M32RXF_INSN_PAR_LD_PLUS
, M32RXF_INSN_WRITE_LD_PLUS
},
111 { M32R_INSN_LD24
, M32RXF_INSN_LD24
, M32RXF_SFMT_LD24
, NOPAR
, NOPAR
},
112 { M32R_INSN_LDI8
, M32RXF_INSN_LDI8
, M32RXF_SFMT_LDI8
, M32RXF_INSN_PAR_LDI8
, M32RXF_INSN_WRITE_LDI8
},
113 { M32R_INSN_LDI16
, M32RXF_INSN_LDI16
, M32RXF_SFMT_LDI16
, NOPAR
, NOPAR
},
114 { M32R_INSN_LOCK
, M32RXF_INSN_LOCK
, M32RXF_SFMT_LOCK
, M32RXF_INSN_PAR_LOCK
, M32RXF_INSN_WRITE_LOCK
},
115 { M32R_INSN_MACHI_A
, M32RXF_INSN_MACHI_A
, M32RXF_SFMT_MACHI_A
, M32RXF_INSN_PAR_MACHI_A
, M32RXF_INSN_WRITE_MACHI_A
},
116 { M32R_INSN_MACLO_A
, M32RXF_INSN_MACLO_A
, M32RXF_SFMT_MACHI_A
, M32RXF_INSN_PAR_MACLO_A
, M32RXF_INSN_WRITE_MACLO_A
},
117 { M32R_INSN_MACWHI_A
, M32RXF_INSN_MACWHI_A
, M32RXF_SFMT_MACHI_A
, M32RXF_INSN_PAR_MACWHI_A
, M32RXF_INSN_WRITE_MACWHI_A
},
118 { M32R_INSN_MACWLO_A
, M32RXF_INSN_MACWLO_A
, M32RXF_SFMT_MACHI_A
, M32RXF_INSN_PAR_MACWLO_A
, M32RXF_INSN_WRITE_MACWLO_A
},
119 { M32R_INSN_MUL
, M32RXF_INSN_MUL
, M32RXF_SFMT_ADD
, M32RXF_INSN_PAR_MUL
, M32RXF_INSN_WRITE_MUL
},
120 { M32R_INSN_MULHI_A
, M32RXF_INSN_MULHI_A
, M32RXF_SFMT_MULHI_A
, M32RXF_INSN_PAR_MULHI_A
, M32RXF_INSN_WRITE_MULHI_A
},
121 { M32R_INSN_MULLO_A
, M32RXF_INSN_MULLO_A
, M32RXF_SFMT_MULHI_A
, M32RXF_INSN_PAR_MULLO_A
, M32RXF_INSN_WRITE_MULLO_A
},
122 { M32R_INSN_MULWHI_A
, M32RXF_INSN_MULWHI_A
, M32RXF_SFMT_MULHI_A
, M32RXF_INSN_PAR_MULWHI_A
, M32RXF_INSN_WRITE_MULWHI_A
},
123 { M32R_INSN_MULWLO_A
, M32RXF_INSN_MULWLO_A
, M32RXF_SFMT_MULHI_A
, M32RXF_INSN_PAR_MULWLO_A
, M32RXF_INSN_WRITE_MULWLO_A
},
124 { M32R_INSN_MV
, M32RXF_INSN_MV
, M32RXF_SFMT_MV
, M32RXF_INSN_PAR_MV
, M32RXF_INSN_WRITE_MV
},
125 { M32R_INSN_MVFACHI_A
, M32RXF_INSN_MVFACHI_A
, M32RXF_SFMT_MVFACHI_A
, M32RXF_INSN_PAR_MVFACHI_A
, M32RXF_INSN_WRITE_MVFACHI_A
},
126 { M32R_INSN_MVFACLO_A
, M32RXF_INSN_MVFACLO_A
, M32RXF_SFMT_MVFACHI_A
, M32RXF_INSN_PAR_MVFACLO_A
, M32RXF_INSN_WRITE_MVFACLO_A
},
127 { M32R_INSN_MVFACMI_A
, M32RXF_INSN_MVFACMI_A
, M32RXF_SFMT_MVFACHI_A
, M32RXF_INSN_PAR_MVFACMI_A
, M32RXF_INSN_WRITE_MVFACMI_A
},
128 { M32R_INSN_MVFC
, M32RXF_INSN_MVFC
, M32RXF_SFMT_MVFC
, M32RXF_INSN_PAR_MVFC
, M32RXF_INSN_WRITE_MVFC
},
129 { M32R_INSN_MVTACHI_A
, M32RXF_INSN_MVTACHI_A
, M32RXF_SFMT_MVTACHI_A
, M32RXF_INSN_PAR_MVTACHI_A
, M32RXF_INSN_WRITE_MVTACHI_A
},
130 { M32R_INSN_MVTACLO_A
, M32RXF_INSN_MVTACLO_A
, M32RXF_SFMT_MVTACHI_A
, M32RXF_INSN_PAR_MVTACLO_A
, M32RXF_INSN_WRITE_MVTACLO_A
},
131 { M32R_INSN_MVTC
, M32RXF_INSN_MVTC
, M32RXF_SFMT_MVTC
, M32RXF_INSN_PAR_MVTC
, M32RXF_INSN_WRITE_MVTC
},
132 { M32R_INSN_NEG
, M32RXF_INSN_NEG
, M32RXF_SFMT_MV
, M32RXF_INSN_PAR_NEG
, M32RXF_INSN_WRITE_NEG
},
133 { M32R_INSN_NOP
, M32RXF_INSN_NOP
, M32RXF_SFMT_NOP
, M32RXF_INSN_PAR_NOP
, M32RXF_INSN_WRITE_NOP
},
134 { M32R_INSN_NOT
, M32RXF_INSN_NOT
, M32RXF_SFMT_MV
, M32RXF_INSN_PAR_NOT
, M32RXF_INSN_WRITE_NOT
},
135 { M32R_INSN_RAC_DSI
, M32RXF_INSN_RAC_DSI
, M32RXF_SFMT_RAC_DSI
, M32RXF_INSN_PAR_RAC_DSI
, M32RXF_INSN_WRITE_RAC_DSI
},
136 { M32R_INSN_RACH_DSI
, M32RXF_INSN_RACH_DSI
, M32RXF_SFMT_RAC_DSI
, M32RXF_INSN_PAR_RACH_DSI
, M32RXF_INSN_WRITE_RACH_DSI
},
137 { M32R_INSN_RTE
, M32RXF_INSN_RTE
, M32RXF_SFMT_RTE
, M32RXF_INSN_PAR_RTE
, M32RXF_INSN_WRITE_RTE
},
138 { M32R_INSN_SETH
, M32RXF_INSN_SETH
, M32RXF_SFMT_SETH
, NOPAR
, NOPAR
},
139 { M32R_INSN_SLL
, M32RXF_INSN_SLL
, M32RXF_SFMT_ADD
, M32RXF_INSN_PAR_SLL
, M32RXF_INSN_WRITE_SLL
},
140 { M32R_INSN_SLL3
, M32RXF_INSN_SLL3
, M32RXF_SFMT_SLL3
, NOPAR
, NOPAR
},
141 { M32R_INSN_SLLI
, M32RXF_INSN_SLLI
, M32RXF_SFMT_SLLI
, M32RXF_INSN_PAR_SLLI
, M32RXF_INSN_WRITE_SLLI
},
142 { M32R_INSN_SRA
, M32RXF_INSN_SRA
, M32RXF_SFMT_ADD
, M32RXF_INSN_PAR_SRA
, M32RXF_INSN_WRITE_SRA
},
143 { M32R_INSN_SRA3
, M32RXF_INSN_SRA3
, M32RXF_SFMT_SLL3
, NOPAR
, NOPAR
},
144 { M32R_INSN_SRAI
, M32RXF_INSN_SRAI
, M32RXF_SFMT_SLLI
, M32RXF_INSN_PAR_SRAI
, M32RXF_INSN_WRITE_SRAI
},
145 { M32R_INSN_SRL
, M32RXF_INSN_SRL
, M32RXF_SFMT_ADD
, M32RXF_INSN_PAR_SRL
, M32RXF_INSN_WRITE_SRL
},
146 { M32R_INSN_SRL3
, M32RXF_INSN_SRL3
, M32RXF_SFMT_SLL3
, NOPAR
, NOPAR
},
147 { M32R_INSN_SRLI
, M32RXF_INSN_SRLI
, M32RXF_SFMT_SLLI
, M32RXF_INSN_PAR_SRLI
, M32RXF_INSN_WRITE_SRLI
},
148 { M32R_INSN_ST
, M32RXF_INSN_ST
, M32RXF_SFMT_ST
, M32RXF_INSN_PAR_ST
, M32RXF_INSN_WRITE_ST
},
149 { M32R_INSN_ST_D
, M32RXF_INSN_ST_D
, M32RXF_SFMT_ST_D
, NOPAR
, NOPAR
},
150 { M32R_INSN_STB
, M32RXF_INSN_STB
, M32RXF_SFMT_STB
, M32RXF_INSN_PAR_STB
, M32RXF_INSN_WRITE_STB
},
151 { M32R_INSN_STB_D
, M32RXF_INSN_STB_D
, M32RXF_SFMT_STB_D
, NOPAR
, NOPAR
},
152 { M32R_INSN_STH
, M32RXF_INSN_STH
, M32RXF_SFMT_STH
, M32RXF_INSN_PAR_STH
, M32RXF_INSN_WRITE_STH
},
153 { M32R_INSN_STH_D
, M32RXF_INSN_STH_D
, M32RXF_SFMT_STH_D
, NOPAR
, NOPAR
},
154 { M32R_INSN_ST_PLUS
, M32RXF_INSN_ST_PLUS
, M32RXF_SFMT_ST_PLUS
, M32RXF_INSN_PAR_ST_PLUS
, M32RXF_INSN_WRITE_ST_PLUS
},
155 { M32R_INSN_ST_MINUS
, M32RXF_INSN_ST_MINUS
, M32RXF_SFMT_ST_PLUS
, M32RXF_INSN_PAR_ST_MINUS
, M32RXF_INSN_WRITE_ST_MINUS
},
156 { M32R_INSN_SUB
, M32RXF_INSN_SUB
, M32RXF_SFMT_ADD
, M32RXF_INSN_PAR_SUB
, M32RXF_INSN_WRITE_SUB
},
157 { M32R_INSN_SUBV
, M32RXF_INSN_SUBV
, M32RXF_SFMT_ADDV
, M32RXF_INSN_PAR_SUBV
, M32RXF_INSN_WRITE_SUBV
},
158 { M32R_INSN_SUBX
, M32RXF_INSN_SUBX
, M32RXF_SFMT_ADDX
, M32RXF_INSN_PAR_SUBX
, M32RXF_INSN_WRITE_SUBX
},
159 { M32R_INSN_TRAP
, M32RXF_INSN_TRAP
, M32RXF_SFMT_TRAP
, M32RXF_INSN_PAR_TRAP
, M32RXF_INSN_WRITE_TRAP
},
160 { M32R_INSN_UNLOCK
, M32RXF_INSN_UNLOCK
, M32RXF_SFMT_UNLOCK
, M32RXF_INSN_PAR_UNLOCK
, M32RXF_INSN_WRITE_UNLOCK
},
161 { M32R_INSN_SATB
, M32RXF_INSN_SATB
, M32RXF_SFMT_SATB
, NOPAR
, NOPAR
},
162 { M32R_INSN_SATH
, M32RXF_INSN_SATH
, M32RXF_SFMT_SATB
, NOPAR
, NOPAR
},
163 { M32R_INSN_SAT
, M32RXF_INSN_SAT
, M32RXF_SFMT_SAT
, NOPAR
, NOPAR
},
164 { M32R_INSN_PCMPBZ
, M32RXF_INSN_PCMPBZ
, M32RXF_SFMT_CMPZ
, M32RXF_INSN_PAR_PCMPBZ
, M32RXF_INSN_WRITE_PCMPBZ
},
165 { M32R_INSN_SADD
, M32RXF_INSN_SADD
, M32RXF_SFMT_SADD
, M32RXF_INSN_PAR_SADD
, M32RXF_INSN_WRITE_SADD
},
166 { M32R_INSN_MACWU1
, M32RXF_INSN_MACWU1
, M32RXF_SFMT_MACWU1
, M32RXF_INSN_PAR_MACWU1
, M32RXF_INSN_WRITE_MACWU1
},
167 { M32R_INSN_MSBLO
, M32RXF_INSN_MSBLO
, M32RXF_SFMT_MSBLO
, M32RXF_INSN_PAR_MSBLO
, M32RXF_INSN_WRITE_MSBLO
},
168 { M32R_INSN_MULWU1
, M32RXF_INSN_MULWU1
, M32RXF_SFMT_MULWU1
, M32RXF_INSN_PAR_MULWU1
, M32RXF_INSN_WRITE_MULWU1
},
169 { M32R_INSN_MACLH1
, M32RXF_INSN_MACLH1
, M32RXF_SFMT_MACWU1
, M32RXF_INSN_PAR_MACLH1
, M32RXF_INSN_WRITE_MACLH1
},
170 { M32R_INSN_SC
, M32RXF_INSN_SC
, M32RXF_SFMT_SC
, M32RXF_INSN_PAR_SC
, M32RXF_INSN_WRITE_SC
},
171 { M32R_INSN_SNC
, M32RXF_INSN_SNC
, M32RXF_SFMT_SC
, M32RXF_INSN_PAR_SNC
, M32RXF_INSN_WRITE_SNC
},
174 static const struct insn_sem m32rxf_insn_sem_invalid
= {
175 VIRTUAL_INSN_X_INVALID
, M32RXF_INSN_X_INVALID
, M32RXF_SFMT_EMPTY
, NOPAR
, NOPAR
178 /* Initialize an IDESC from the compile-time computable parts. */
181 init_idesc (SIM_CPU
*cpu
, IDESC
*id
, const struct insn_sem
*t
)
183 const CGEN_INSN
*insn_table
= CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu
))->init_entries
;
187 if ((int) t
->type
<= 0)
188 id
->idata
= & cgen_virtual_insn_table
[- (int) t
->type
];
190 id
->idata
= & insn_table
[t
->type
];
191 id
->attrs
= CGEN_INSN_ATTRS (id
->idata
);
192 /* Oh my god, a magic number. */
193 id
->length
= CGEN_INSN_BITSIZE (id
->idata
) / 8;
195 #if WITH_PROFILE_MODEL_P
196 id
->timing
= & MODEL_TIMING (CPU_MODEL (cpu
)) [t
->index
];
198 SIM_DESC sd
= CPU_STATE (cpu
);
199 SIM_ASSERT (t
->index
== id
->timing
->num
);
203 /* Semantic pointers are initialized elsewhere. */
206 /* Initialize the instruction descriptor table. */
209 m32rxf_init_idesc_table (SIM_CPU
*cpu
)
212 const struct insn_sem
*t
,*tend
;
213 int tabsize
= M32RXF_INSN_MAX
;
214 IDESC
*table
= m32rxf_insn_data
;
216 memset (table
, 0, tabsize
* sizeof (IDESC
));
218 /* First set all entries to the `invalid insn'. */
219 t
= & m32rxf_insn_sem_invalid
;
220 for (id
= table
, tabend
= table
+ tabsize
; id
< tabend
; ++id
)
221 init_idesc (cpu
, id
, t
);
223 /* Now fill in the values for the chosen cpu. */
224 for (t
= m32rxf_insn_sem
, tend
= t
+ sizeof (m32rxf_insn_sem
) / sizeof (*t
);
227 init_idesc (cpu
, & table
[t
->index
], t
);
228 if (t
->par_index
!= NOPAR
)
230 init_idesc (cpu
, &table
[t
->par_index
], t
);
231 table
[t
->index
].par_idesc
= &table
[t
->par_index
];
233 if (t
->par_index
!= NOPAR
)
235 init_idesc (cpu
, &table
[t
->write_index
], t
);
236 table
[t
->par_index
].par_idesc
= &table
[t
->write_index
];
240 /* Link the IDESC table into the cpu. */
241 CPU_IDESC (cpu
) = table
;
244 /* Given an instruction, return a pointer to its IDESC entry. */
247 m32rxf_decode (SIM_CPU
*current_cpu
, IADDR pc
,
248 CGEN_INSN_INT base_insn
, CGEN_INSN_INT entire_insn
,
251 /* Result of decoder. */
252 M32RXF_INSN_TYPE itype
;
255 CGEN_INSN_INT insn
= base_insn
;
258 unsigned int val
= (((insn
>> 8) & (15 << 4)) | ((insn
>> 4) & (15 << 0)));
261 case 0 : itype
= M32RXF_INSN_SUBV
; goto extract_sfmt_addv
;
262 case 1 : itype
= M32RXF_INSN_SUBX
; goto extract_sfmt_addx
;
263 case 2 : itype
= M32RXF_INSN_SUB
; goto extract_sfmt_add
;
264 case 3 : itype
= M32RXF_INSN_NEG
; goto extract_sfmt_mv
;
265 case 4 : itype
= M32RXF_INSN_CMP
; goto extract_sfmt_cmp
;
266 case 5 : itype
= M32RXF_INSN_CMPU
; goto extract_sfmt_cmp
;
267 case 6 : itype
= M32RXF_INSN_CMPEQ
; goto extract_sfmt_cmp
;
270 unsigned int val
= (((insn
>> 8) & (15 << 0)));
273 case 0 : itype
= M32RXF_INSN_CMPZ
; goto extract_sfmt_cmpz
;
274 case 3 : itype
= M32RXF_INSN_PCMPBZ
; goto extract_sfmt_cmpz
;
275 default : itype
= M32RXF_INSN_X_INVALID
; goto extract_sfmt_empty
;
278 case 8 : itype
= M32RXF_INSN_ADDV
; goto extract_sfmt_addv
;
279 case 9 : itype
= M32RXF_INSN_ADDX
; goto extract_sfmt_addx
;
280 case 10 : itype
= M32RXF_INSN_ADD
; goto extract_sfmt_add
;
281 case 11 : itype
= M32RXF_INSN_NOT
; goto extract_sfmt_mv
;
282 case 12 : itype
= M32RXF_INSN_AND
; goto extract_sfmt_add
;
283 case 13 : itype
= M32RXF_INSN_XOR
; goto extract_sfmt_add
;
284 case 14 : itype
= M32RXF_INSN_OR
; goto extract_sfmt_add
;
285 case 16 : itype
= M32RXF_INSN_SRL
; goto extract_sfmt_add
;
286 case 18 : itype
= M32RXF_INSN_SRA
; goto extract_sfmt_add
;
287 case 20 : itype
= M32RXF_INSN_SLL
; goto extract_sfmt_add
;
288 case 22 : itype
= M32RXF_INSN_MUL
; goto extract_sfmt_add
;
289 case 24 : itype
= M32RXF_INSN_MV
; goto extract_sfmt_mv
;
290 case 25 : itype
= M32RXF_INSN_MVFC
; goto extract_sfmt_mvfc
;
291 case 26 : itype
= M32RXF_INSN_MVTC
; goto extract_sfmt_mvtc
;
294 unsigned int val
= (((insn
>> 8) & (15 << 0)));
297 case 12 : itype
= M32RXF_INSN_JC
; goto extract_sfmt_jc
;
298 case 13 : itype
= M32RXF_INSN_JNC
; goto extract_sfmt_jc
;
299 case 14 : itype
= M32RXF_INSN_JL
; goto extract_sfmt_jl
;
300 case 15 : itype
= M32RXF_INSN_JMP
; goto extract_sfmt_jmp
;
301 default : itype
= M32RXF_INSN_X_INVALID
; goto extract_sfmt_empty
;
304 case 29 : itype
= M32RXF_INSN_RTE
; goto extract_sfmt_rte
;
305 case 31 : itype
= M32RXF_INSN_TRAP
; goto extract_sfmt_trap
;
306 case 32 : itype
= M32RXF_INSN_STB
; goto extract_sfmt_stb
;
307 case 34 : itype
= M32RXF_INSN_STH
; goto extract_sfmt_sth
;
308 case 36 : itype
= M32RXF_INSN_ST
; goto extract_sfmt_st
;
309 case 37 : itype
= M32RXF_INSN_UNLOCK
; goto extract_sfmt_unlock
;
310 case 38 : itype
= M32RXF_INSN_ST_PLUS
; goto extract_sfmt_st_plus
;
311 case 39 : itype
= M32RXF_INSN_ST_MINUS
; goto extract_sfmt_st_plus
;
312 case 40 : itype
= M32RXF_INSN_LDB
; goto extract_sfmt_ld
;
313 case 41 : itype
= M32RXF_INSN_LDUB
; goto extract_sfmt_ld
;
314 case 42 : itype
= M32RXF_INSN_LDH
; goto extract_sfmt_ld
;
315 case 43 : itype
= M32RXF_INSN_LDUH
; goto extract_sfmt_ld
;
316 case 44 : itype
= M32RXF_INSN_LD
; goto extract_sfmt_ld
;
317 case 45 : itype
= M32RXF_INSN_LOCK
; goto extract_sfmt_lock
;
318 case 46 : itype
= M32RXF_INSN_LD_PLUS
; goto extract_sfmt_ld_plus
;
319 case 48 : /* fall through */
320 case 56 : itype
= M32RXF_INSN_MULHI_A
; goto extract_sfmt_mulhi_a
;
321 case 49 : /* fall through */
322 case 57 : itype
= M32RXF_INSN_MULLO_A
; goto extract_sfmt_mulhi_a
;
323 case 50 : /* fall through */
324 case 58 : itype
= M32RXF_INSN_MULWHI_A
; goto extract_sfmt_mulhi_a
;
325 case 51 : /* fall through */
326 case 59 : itype
= M32RXF_INSN_MULWLO_A
; goto extract_sfmt_mulhi_a
;
327 case 52 : /* fall through */
328 case 60 : itype
= M32RXF_INSN_MACHI_A
; goto extract_sfmt_machi_a
;
329 case 53 : /* fall through */
330 case 61 : itype
= M32RXF_INSN_MACLO_A
; goto extract_sfmt_machi_a
;
331 case 54 : /* fall through */
332 case 62 : itype
= M32RXF_INSN_MACWHI_A
; goto extract_sfmt_machi_a
;
333 case 55 : /* fall through */
334 case 63 : itype
= M32RXF_INSN_MACWLO_A
; goto extract_sfmt_machi_a
;
335 case 64 : /* fall through */
336 case 65 : /* fall through */
337 case 66 : /* fall through */
338 case 67 : /* fall through */
339 case 68 : /* fall through */
340 case 69 : /* fall through */
341 case 70 : /* fall through */
342 case 71 : /* fall through */
343 case 72 : /* fall through */
344 case 73 : /* fall through */
345 case 74 : /* fall through */
346 case 75 : /* fall through */
347 case 76 : /* fall through */
348 case 77 : /* fall through */
349 case 78 : /* fall through */
350 case 79 : itype
= M32RXF_INSN_ADDI
; goto extract_sfmt_addi
;
351 case 80 : /* fall through */
352 case 81 : itype
= M32RXF_INSN_SRLI
; goto extract_sfmt_slli
;
353 case 82 : /* fall through */
354 case 83 : itype
= M32RXF_INSN_SRAI
; goto extract_sfmt_slli
;
355 case 84 : /* fall through */
356 case 85 : itype
= M32RXF_INSN_SLLI
; goto extract_sfmt_slli
;
359 unsigned int val
= (((insn
>> 0) & (3 << 0)));
362 case 0 : itype
= M32RXF_INSN_MVTACHI_A
; goto extract_sfmt_mvtachi_a
;
363 case 1 : itype
= M32RXF_INSN_MVTACLO_A
; goto extract_sfmt_mvtachi_a
;
364 default : itype
= M32RXF_INSN_X_INVALID
; goto extract_sfmt_empty
;
367 case 88 : itype
= M32RXF_INSN_RACH_DSI
; goto extract_sfmt_rac_dsi
;
368 case 89 : itype
= M32RXF_INSN_RAC_DSI
; goto extract_sfmt_rac_dsi
;
369 case 90 : itype
= M32RXF_INSN_MULWU1
; goto extract_sfmt_mulwu1
;
370 case 91 : itype
= M32RXF_INSN_MACWU1
; goto extract_sfmt_macwu1
;
371 case 92 : itype
= M32RXF_INSN_MACLH1
; goto extract_sfmt_macwu1
;
372 case 93 : itype
= M32RXF_INSN_MSBLO
; goto extract_sfmt_msblo
;
373 case 94 : itype
= M32RXF_INSN_SADD
; goto extract_sfmt_sadd
;
376 unsigned int val
= (((insn
>> 0) & (3 << 0)));
379 case 0 : itype
= M32RXF_INSN_MVFACHI_A
; goto extract_sfmt_mvfachi_a
;
380 case 1 : itype
= M32RXF_INSN_MVFACLO_A
; goto extract_sfmt_mvfachi_a
;
381 case 2 : itype
= M32RXF_INSN_MVFACMI_A
; goto extract_sfmt_mvfachi_a
;
382 default : itype
= M32RXF_INSN_X_INVALID
; goto extract_sfmt_empty
;
385 case 96 : /* fall through */
386 case 97 : /* fall through */
387 case 98 : /* fall through */
388 case 99 : /* fall through */
389 case 100 : /* fall through */
390 case 101 : /* fall through */
391 case 102 : /* fall through */
392 case 103 : /* fall through */
393 case 104 : /* fall through */
394 case 105 : /* fall through */
395 case 106 : /* fall through */
396 case 107 : /* fall through */
397 case 108 : /* fall through */
398 case 109 : /* fall through */
399 case 110 : /* fall through */
400 case 111 : itype
= M32RXF_INSN_LDI8
; goto extract_sfmt_ldi8
;
403 unsigned int val
= (((insn
>> 8) & (15 << 0)));
406 case 0 : itype
= M32RXF_INSN_NOP
; goto extract_sfmt_nop
;
407 case 4 : itype
= M32RXF_INSN_SC
; goto extract_sfmt_sc
;
408 case 5 : itype
= M32RXF_INSN_SNC
; goto extract_sfmt_sc
;
409 case 8 : itype
= M32RXF_INSN_BCL8
; goto extract_sfmt_bcl8
;
410 case 9 : itype
= M32RXF_INSN_BNCL8
; goto extract_sfmt_bcl8
;
411 case 12 : itype
= M32RXF_INSN_BC8
; goto extract_sfmt_bc8
;
412 case 13 : itype
= M32RXF_INSN_BNC8
; goto extract_sfmt_bc8
;
413 case 14 : itype
= M32RXF_INSN_BL8
; goto extract_sfmt_bl8
;
414 case 15 : itype
= M32RXF_INSN_BRA8
; goto extract_sfmt_bra8
;
415 default : itype
= M32RXF_INSN_X_INVALID
; goto extract_sfmt_empty
;
418 case 113 : /* fall through */
419 case 114 : /* fall through */
420 case 115 : /* fall through */
421 case 116 : /* fall through */
422 case 117 : /* fall through */
423 case 118 : /* fall through */
424 case 119 : /* fall through */
425 case 120 : /* fall through */
426 case 121 : /* fall through */
427 case 122 : /* fall through */
428 case 123 : /* fall through */
429 case 124 : /* fall through */
430 case 125 : /* fall through */
431 case 126 : /* fall through */
434 unsigned int val
= (((insn
>> 8) & (15 << 0)));
437 case 8 : itype
= M32RXF_INSN_BCL8
; goto extract_sfmt_bcl8
;
438 case 9 : itype
= M32RXF_INSN_BNCL8
; goto extract_sfmt_bcl8
;
439 case 12 : itype
= M32RXF_INSN_BC8
; goto extract_sfmt_bc8
;
440 case 13 : itype
= M32RXF_INSN_BNC8
; goto extract_sfmt_bc8
;
441 case 14 : itype
= M32RXF_INSN_BL8
; goto extract_sfmt_bl8
;
442 case 15 : itype
= M32RXF_INSN_BRA8
; goto extract_sfmt_bra8
;
443 default : itype
= M32RXF_INSN_X_INVALID
; goto extract_sfmt_empty
;
446 case 132 : itype
= M32RXF_INSN_CMPI
; goto extract_sfmt_cmpi
;
447 case 133 : itype
= M32RXF_INSN_CMPUI
; goto extract_sfmt_cmpi
;
450 unsigned int val
= (((insn
>> -6) & (63 << 0)));
455 unsigned int val
= (((insn
>> -12) & (63 << 0)));
458 case 0 : itype
= M32RXF_INSN_SAT
; goto extract_sfmt_sat
;
459 case 32 : itype
= M32RXF_INSN_SATH
; goto extract_sfmt_satb
;
460 case 48 : itype
= M32RXF_INSN_SATB
; goto extract_sfmt_satb
;
461 default : itype
= M32RXF_INSN_X_INVALID
; goto extract_sfmt_empty
;
464 default : itype
= M32RXF_INSN_X_INVALID
; goto extract_sfmt_empty
;
467 case 136 : itype
= M32RXF_INSN_ADDV3
; goto extract_sfmt_addv3
;
468 case 138 : itype
= M32RXF_INSN_ADD3
; goto extract_sfmt_add3
;
469 case 140 : itype
= M32RXF_INSN_AND3
; goto extract_sfmt_and3
;
470 case 141 : itype
= M32RXF_INSN_XOR3
; goto extract_sfmt_and3
;
471 case 142 : itype
= M32RXF_INSN_OR3
; goto extract_sfmt_or3
;
474 unsigned int val
= (((insn
>> -6) & (63 << 0)));
479 unsigned int val
= (((insn
>> -12) & (63 << 0)));
482 case 0 : itype
= M32RXF_INSN_DIV
; goto extract_sfmt_div
;
483 case 1 : itype
= M32RXF_INSN_DIVH
; goto extract_sfmt_div
;
484 default : itype
= M32RXF_INSN_X_INVALID
; goto extract_sfmt_empty
;
487 default : itype
= M32RXF_INSN_X_INVALID
; goto extract_sfmt_empty
;
490 case 145 : itype
= M32RXF_INSN_DIVU
; goto extract_sfmt_div
;
491 case 146 : itype
= M32RXF_INSN_REM
; goto extract_sfmt_div
;
492 case 147 : itype
= M32RXF_INSN_REMU
; goto extract_sfmt_div
;
493 case 152 : itype
= M32RXF_INSN_SRL3
; goto extract_sfmt_sll3
;
494 case 154 : itype
= M32RXF_INSN_SRA3
; goto extract_sfmt_sll3
;
495 case 156 : itype
= M32RXF_INSN_SLL3
; goto extract_sfmt_sll3
;
496 case 159 : itype
= M32RXF_INSN_LDI16
; goto extract_sfmt_ldi16
;
497 case 160 : itype
= M32RXF_INSN_STB_D
; goto extract_sfmt_stb_d
;
498 case 162 : itype
= M32RXF_INSN_STH_D
; goto extract_sfmt_sth_d
;
499 case 164 : itype
= M32RXF_INSN_ST_D
; goto extract_sfmt_st_d
;
500 case 168 : itype
= M32RXF_INSN_LDB_D
; goto extract_sfmt_ld_d
;
501 case 169 : itype
= M32RXF_INSN_LDUB_D
; goto extract_sfmt_ld_d
;
502 case 170 : itype
= M32RXF_INSN_LDH_D
; goto extract_sfmt_ld_d
;
503 case 171 : itype
= M32RXF_INSN_LDUH_D
; goto extract_sfmt_ld_d
;
504 case 172 : itype
= M32RXF_INSN_LD_D
; goto extract_sfmt_ld_d
;
505 case 176 : itype
= M32RXF_INSN_BEQ
; goto extract_sfmt_beq
;
506 case 177 : itype
= M32RXF_INSN_BNE
; goto extract_sfmt_beq
;
507 case 184 : itype
= M32RXF_INSN_BEQZ
; goto extract_sfmt_beqz
;
508 case 185 : itype
= M32RXF_INSN_BNEZ
; goto extract_sfmt_beqz
;
509 case 186 : itype
= M32RXF_INSN_BLTZ
; goto extract_sfmt_beqz
;
510 case 187 : itype
= M32RXF_INSN_BGEZ
; goto extract_sfmt_beqz
;
511 case 188 : itype
= M32RXF_INSN_BLEZ
; goto extract_sfmt_beqz
;
512 case 189 : itype
= M32RXF_INSN_BGTZ
; goto extract_sfmt_beqz
;
513 case 220 : itype
= M32RXF_INSN_SETH
; goto extract_sfmt_seth
;
514 case 224 : /* fall through */
515 case 225 : /* fall through */
516 case 226 : /* fall through */
517 case 227 : /* fall through */
518 case 228 : /* fall through */
519 case 229 : /* fall through */
520 case 230 : /* fall through */
521 case 231 : /* fall through */
522 case 232 : /* fall through */
523 case 233 : /* fall through */
524 case 234 : /* fall through */
525 case 235 : /* fall through */
526 case 236 : /* fall through */
527 case 237 : /* fall through */
528 case 238 : /* fall through */
529 case 239 : itype
= M32RXF_INSN_LD24
; goto extract_sfmt_ld24
;
530 case 240 : /* fall through */
531 case 241 : /* fall through */
532 case 242 : /* fall through */
533 case 243 : /* fall through */
534 case 244 : /* fall through */
535 case 245 : /* fall through */
536 case 246 : /* fall through */
537 case 247 : /* fall through */
538 case 248 : /* fall through */
539 case 249 : /* fall through */
540 case 250 : /* fall through */
541 case 251 : /* fall through */
542 case 252 : /* fall through */
543 case 253 : /* fall through */
544 case 254 : /* fall through */
547 unsigned int val
= (((insn
>> 8) & (15 << 0)));
550 case 8 : itype
= M32RXF_INSN_BCL24
; goto extract_sfmt_bcl24
;
551 case 9 : itype
= M32RXF_INSN_BNCL24
; goto extract_sfmt_bcl24
;
552 case 12 : itype
= M32RXF_INSN_BC24
; goto extract_sfmt_bc24
;
553 case 13 : itype
= M32RXF_INSN_BNC24
; goto extract_sfmt_bc24
;
554 case 14 : itype
= M32RXF_INSN_BL24
; goto extract_sfmt_bl24
;
555 case 15 : itype
= M32RXF_INSN_BRA24
; goto extract_sfmt_bra24
;
556 default : itype
= M32RXF_INSN_X_INVALID
; goto extract_sfmt_empty
;
559 default : itype
= M32RXF_INSN_X_INVALID
; goto extract_sfmt_empty
;
564 /* The instruction has been decoded, now extract the fields. */
568 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
569 CGEN_INSN_INT insn
= entire_insn
;
570 #define FLD(f) abuf->fields.fmt_empty.f
573 /* Record the fields for the semantic handler. */
574 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_empty", (char *) 0));
582 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
583 CGEN_INSN_INT insn
= entire_insn
;
584 #define FLD(f) abuf->fields.sfmt_add.f
588 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
589 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
591 /* Record the fields for the semantic handler. */
594 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
595 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
596 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_add", "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
598 #if WITH_PROFILE_MODEL_P
599 /* Record the fields for profiling. */
600 if (PROFILE_MODEL_P (current_cpu
))
613 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
614 CGEN_INSN_INT insn
= entire_insn
;
615 #define FLD(f) abuf->fields.sfmt_add3.f
620 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
621 f_r2
= EXTRACT_MSB0_UINT (insn
, 32, 12, 4);
622 f_simm16
= EXTRACT_MSB0_INT (insn
, 32, 16, 16);
624 /* Record the fields for the semantic handler. */
625 FLD (f_simm16
) = f_simm16
;
628 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
629 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
630 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16
, "f_r2 0x%x", 'x', f_r2
, "f_r1 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
632 #if WITH_PROFILE_MODEL_P
633 /* Record the fields for profiling. */
634 if (PROFILE_MODEL_P (current_cpu
))
646 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
647 CGEN_INSN_INT insn
= entire_insn
;
648 #define FLD(f) abuf->fields.sfmt_and3.f
653 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
654 f_r2
= EXTRACT_MSB0_UINT (insn
, 32, 12, 4);
655 f_uimm16
= EXTRACT_MSB0_UINT (insn
, 32, 16, 16);
657 /* Record the fields for the semantic handler. */
659 FLD (f_uimm16
) = f_uimm16
;
661 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
662 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
663 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_and3", "f_r2 0x%x", 'x', f_r2
, "f_uimm16 0x%x", 'x', f_uimm16
, "f_r1 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
665 #if WITH_PROFILE_MODEL_P
666 /* Record the fields for profiling. */
667 if (PROFILE_MODEL_P (current_cpu
))
679 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
680 CGEN_INSN_INT insn
= entire_insn
;
681 #define FLD(f) abuf->fields.sfmt_and3.f
686 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
687 f_r2
= EXTRACT_MSB0_UINT (insn
, 32, 12, 4);
688 f_uimm16
= EXTRACT_MSB0_UINT (insn
, 32, 16, 16);
690 /* Record the fields for the semantic handler. */
692 FLD (f_uimm16
) = f_uimm16
;
694 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
695 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
696 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_or3", "f_r2 0x%x", 'x', f_r2
, "f_uimm16 0x%x", 'x', f_uimm16
, "f_r1 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
698 #if WITH_PROFILE_MODEL_P
699 /* Record the fields for profiling. */
700 if (PROFILE_MODEL_P (current_cpu
))
712 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
713 CGEN_INSN_INT insn
= entire_insn
;
714 #define FLD(f) abuf->fields.sfmt_addi.f
718 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
719 f_simm8
= EXTRACT_MSB0_INT (insn
, 16, 8, 8);
721 /* Record the fields for the semantic handler. */
723 FLD (f_simm8
) = f_simm8
;
724 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
725 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_addi", "f_r1 0x%x", 'x', f_r1
, "f_simm8 0x%x", 'x', f_simm8
, "dr 0x%x", 'x', f_r1
, (char *) 0));
727 #if WITH_PROFILE_MODEL_P
728 /* Record the fields for profiling. */
729 if (PROFILE_MODEL_P (current_cpu
))
741 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
742 CGEN_INSN_INT insn
= entire_insn
;
743 #define FLD(f) abuf->fields.sfmt_add.f
747 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
748 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
750 /* Record the fields for the semantic handler. */
753 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
754 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
755 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_addv", "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
757 #if WITH_PROFILE_MODEL_P
758 /* Record the fields for profiling. */
759 if (PROFILE_MODEL_P (current_cpu
))
772 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
773 CGEN_INSN_INT insn
= entire_insn
;
774 #define FLD(f) abuf->fields.sfmt_add3.f
779 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
780 f_r2
= EXTRACT_MSB0_UINT (insn
, 32, 12, 4);
781 f_simm16
= EXTRACT_MSB0_INT (insn
, 32, 16, 16);
783 /* Record the fields for the semantic handler. */
784 FLD (f_simm16
) = f_simm16
;
787 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
788 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
789 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16
, "f_r2 0x%x", 'x', f_r2
, "f_r1 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
791 #if WITH_PROFILE_MODEL_P
792 /* Record the fields for profiling. */
793 if (PROFILE_MODEL_P (current_cpu
))
805 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
806 CGEN_INSN_INT insn
= entire_insn
;
807 #define FLD(f) abuf->fields.sfmt_add.f
811 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
812 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
814 /* Record the fields for the semantic handler. */
817 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
818 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
819 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_addx", "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
821 #if WITH_PROFILE_MODEL_P
822 /* Record the fields for profiling. */
823 if (PROFILE_MODEL_P (current_cpu
))
836 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
837 CGEN_INSN_INT insn
= entire_insn
;
838 #define FLD(f) abuf->fields.sfmt_bl8.f
841 f_disp8
= ((((EXTRACT_MSB0_INT (insn
, 16, 8, 8)) << (2))) + (((pc
) & (-4))));
843 /* Record the fields for the semantic handler. */
844 FLD (i_disp8
) = f_disp8
;
845 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8
, (char *) 0));
847 #if WITH_PROFILE_MODEL_P
848 /* Record the fields for profiling. */
849 if (PROFILE_MODEL_P (current_cpu
))
859 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
860 CGEN_INSN_INT insn
= entire_insn
;
861 #define FLD(f) abuf->fields.sfmt_bl24.f
864 f_disp24
= ((((EXTRACT_MSB0_INT (insn
, 32, 8, 24)) << (2))) + (pc
));
866 /* Record the fields for the semantic handler. */
867 FLD (i_disp24
) = f_disp24
;
868 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24
, (char *) 0));
870 #if WITH_PROFILE_MODEL_P
871 /* Record the fields for profiling. */
872 if (PROFILE_MODEL_P (current_cpu
))
882 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
883 CGEN_INSN_INT insn
= entire_insn
;
884 #define FLD(f) abuf->fields.sfmt_beq.f
889 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
890 f_r2
= EXTRACT_MSB0_UINT (insn
, 32, 12, 4);
891 f_disp16
= ((((EXTRACT_MSB0_INT (insn
, 32, 16, 16)) << (2))) + (pc
));
893 /* Record the fields for the semantic handler. */
896 FLD (i_disp16
) = f_disp16
;
897 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
898 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
899 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_beq", "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "disp16 0x%x", 'x', f_disp16
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
901 #if WITH_PROFILE_MODEL_P
902 /* Record the fields for profiling. */
903 if (PROFILE_MODEL_P (current_cpu
))
905 FLD (in_src1
) = f_r1
;
906 FLD (in_src2
) = f_r2
;
915 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
916 CGEN_INSN_INT insn
= entire_insn
;
917 #define FLD(f) abuf->fields.sfmt_beq.f
921 f_r2
= EXTRACT_MSB0_UINT (insn
, 32, 12, 4);
922 f_disp16
= ((((EXTRACT_MSB0_INT (insn
, 32, 16, 16)) << (2))) + (pc
));
924 /* Record the fields for the semantic handler. */
926 FLD (i_disp16
) = f_disp16
;
927 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
928 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2
, "disp16 0x%x", 'x', f_disp16
, "src2 0x%x", 'x', f_r2
, (char *) 0));
930 #if WITH_PROFILE_MODEL_P
931 /* Record the fields for profiling. */
932 if (PROFILE_MODEL_P (current_cpu
))
934 FLD (in_src2
) = f_r2
;
943 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
944 CGEN_INSN_INT insn
= entire_insn
;
945 #define FLD(f) abuf->fields.sfmt_bl8.f
948 f_disp8
= ((((EXTRACT_MSB0_INT (insn
, 16, 8, 8)) << (2))) + (((pc
) & (-4))));
950 /* Record the fields for the semantic handler. */
951 FLD (i_disp8
) = f_disp8
;
952 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8
, (char *) 0));
954 #if WITH_PROFILE_MODEL_P
955 /* Record the fields for profiling. */
956 if (PROFILE_MODEL_P (current_cpu
))
958 FLD (out_h_gr_14
) = 14;
967 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
968 CGEN_INSN_INT insn
= entire_insn
;
969 #define FLD(f) abuf->fields.sfmt_bl24.f
972 f_disp24
= ((((EXTRACT_MSB0_INT (insn
, 32, 8, 24)) << (2))) + (pc
));
974 /* Record the fields for the semantic handler. */
975 FLD (i_disp24
) = f_disp24
;
976 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24
, (char *) 0));
978 #if WITH_PROFILE_MODEL_P
979 /* Record the fields for profiling. */
980 if (PROFILE_MODEL_P (current_cpu
))
982 FLD (out_h_gr_14
) = 14;
991 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
992 CGEN_INSN_INT insn
= entire_insn
;
993 #define FLD(f) abuf->fields.sfmt_bl8.f
996 f_disp8
= ((((EXTRACT_MSB0_INT (insn
, 16, 8, 8)) << (2))) + (((pc
) & (-4))));
998 /* Record the fields for the semantic handler. */
999 FLD (i_disp8
) = f_disp8
;
1000 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8
, (char *) 0));
1002 #if WITH_PROFILE_MODEL_P
1003 /* Record the fields for profiling. */
1004 if (PROFILE_MODEL_P (current_cpu
))
1006 FLD (out_h_gr_14
) = 14;
1015 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1016 CGEN_INSN_INT insn
= entire_insn
;
1017 #define FLD(f) abuf->fields.sfmt_bl24.f
1020 f_disp24
= ((((EXTRACT_MSB0_INT (insn
, 32, 8, 24)) << (2))) + (pc
));
1022 /* Record the fields for the semantic handler. */
1023 FLD (i_disp24
) = f_disp24
;
1024 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24
, (char *) 0));
1026 #if WITH_PROFILE_MODEL_P
1027 /* Record the fields for profiling. */
1028 if (PROFILE_MODEL_P (current_cpu
))
1030 FLD (out_h_gr_14
) = 14;
1039 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1040 CGEN_INSN_INT insn
= entire_insn
;
1041 #define FLD(f) abuf->fields.sfmt_bl8.f
1044 f_disp8
= ((((EXTRACT_MSB0_INT (insn
, 16, 8, 8)) << (2))) + (((pc
) & (-4))));
1046 /* Record the fields for the semantic handler. */
1047 FLD (i_disp8
) = f_disp8
;
1048 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8
, (char *) 0));
1050 #if WITH_PROFILE_MODEL_P
1051 /* Record the fields for profiling. */
1052 if (PROFILE_MODEL_P (current_cpu
))
1062 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1063 CGEN_INSN_INT insn
= entire_insn
;
1064 #define FLD(f) abuf->fields.sfmt_bl24.f
1067 f_disp24
= ((((EXTRACT_MSB0_INT (insn
, 32, 8, 24)) << (2))) + (pc
));
1069 /* Record the fields for the semantic handler. */
1070 FLD (i_disp24
) = f_disp24
;
1071 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24
, (char *) 0));
1073 #if WITH_PROFILE_MODEL_P
1074 /* Record the fields for profiling. */
1075 if (PROFILE_MODEL_P (current_cpu
))
1085 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1086 CGEN_INSN_INT insn
= entire_insn
;
1087 #define FLD(f) abuf->fields.sfmt_st_plus.f
1091 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1092 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1094 /* Record the fields for the semantic handler. */
1097 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1098 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1099 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1101 #if WITH_PROFILE_MODEL_P
1102 /* Record the fields for profiling. */
1103 if (PROFILE_MODEL_P (current_cpu
))
1105 FLD (in_src1
) = f_r1
;
1106 FLD (in_src2
) = f_r2
;
1115 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1116 CGEN_INSN_INT insn
= entire_insn
;
1117 #define FLD(f) abuf->fields.sfmt_st_d.f
1121 f_r2
= EXTRACT_MSB0_UINT (insn
, 32, 12, 4);
1122 f_simm16
= EXTRACT_MSB0_INT (insn
, 32, 16, 16);
1124 /* Record the fields for the semantic handler. */
1125 FLD (f_simm16
) = f_simm16
;
1127 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1128 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16
, "f_r2 0x%x", 'x', f_r2
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1130 #if WITH_PROFILE_MODEL_P
1131 /* Record the fields for profiling. */
1132 if (PROFILE_MODEL_P (current_cpu
))
1134 FLD (in_src2
) = f_r2
;
1143 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1144 CGEN_INSN_INT insn
= entire_insn
;
1145 #define FLD(f) abuf->fields.sfmt_st_plus.f
1148 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1150 /* Record the fields for the semantic handler. */
1152 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1153 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1155 #if WITH_PROFILE_MODEL_P
1156 /* Record the fields for profiling. */
1157 if (PROFILE_MODEL_P (current_cpu
))
1159 FLD (in_src2
) = f_r2
;
1168 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1169 CGEN_INSN_INT insn
= entire_insn
;
1170 #define FLD(f) abuf->fields.sfmt_add.f
1174 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
1175 f_r2
= EXTRACT_MSB0_UINT (insn
, 32, 12, 4);
1177 /* Record the fields for the semantic handler. */
1180 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1181 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1182 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_div", "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
1184 #if WITH_PROFILE_MODEL_P
1185 /* Record the fields for profiling. */
1186 if (PROFILE_MODEL_P (current_cpu
))
1190 FLD (out_dr
) = f_r1
;
1199 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1200 CGEN_INSN_INT insn
= entire_insn
;
1201 #define FLD(f) abuf->fields.sfmt_jl.f
1204 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1206 /* Record the fields for the semantic handler. */
1208 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1209 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_jc", "f_r2 0x%x", 'x', f_r2
, "sr 0x%x", 'x', f_r2
, (char *) 0));
1211 #if WITH_PROFILE_MODEL_P
1212 /* Record the fields for profiling. */
1213 if (PROFILE_MODEL_P (current_cpu
))
1224 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1225 CGEN_INSN_INT insn
= entire_insn
;
1226 #define FLD(f) abuf->fields.sfmt_jl.f
1229 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1231 /* Record the fields for the semantic handler. */
1233 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1234 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_jl", "f_r2 0x%x", 'x', f_r2
, "sr 0x%x", 'x', f_r2
, (char *) 0));
1236 #if WITH_PROFILE_MODEL_P
1237 /* Record the fields for profiling. */
1238 if (PROFILE_MODEL_P (current_cpu
))
1241 FLD (out_h_gr_14
) = 14;
1250 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1251 CGEN_INSN_INT insn
= entire_insn
;
1252 #define FLD(f) abuf->fields.sfmt_jl.f
1255 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1257 /* Record the fields for the semantic handler. */
1259 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1260 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2
, "sr 0x%x", 'x', f_r2
, (char *) 0));
1262 #if WITH_PROFILE_MODEL_P
1263 /* Record the fields for profiling. */
1264 if (PROFILE_MODEL_P (current_cpu
))
1275 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1276 CGEN_INSN_INT insn
= entire_insn
;
1277 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1281 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1282 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1284 /* Record the fields for the semantic handler. */
1287 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1288 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1289 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_ld", "f_r2 0x%x", 'x', f_r2
, "f_r1 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1291 #if WITH_PROFILE_MODEL_P
1292 /* Record the fields for profiling. */
1293 if (PROFILE_MODEL_P (current_cpu
))
1296 FLD (out_dr
) = f_r1
;
1305 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1306 CGEN_INSN_INT insn
= entire_insn
;
1307 #define FLD(f) abuf->fields.sfmt_add3.f
1312 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
1313 f_r2
= EXTRACT_MSB0_UINT (insn
, 32, 12, 4);
1314 f_simm16
= EXTRACT_MSB0_INT (insn
, 32, 16, 16);
1316 /* Record the fields for the semantic handler. */
1317 FLD (f_simm16
) = f_simm16
;
1320 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1321 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1322 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16
, "f_r2 0x%x", 'x', f_r2
, "f_r1 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1324 #if WITH_PROFILE_MODEL_P
1325 /* Record the fields for profiling. */
1326 if (PROFILE_MODEL_P (current_cpu
))
1329 FLD (out_dr
) = f_r1
;
1336 extract_sfmt_ld_plus
:
1338 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1339 CGEN_INSN_INT insn
= entire_insn
;
1340 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1344 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1345 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1347 /* Record the fields for the semantic handler. */
1350 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1351 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1352 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2
, "f_r1 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1354 #if WITH_PROFILE_MODEL_P
1355 /* Record the fields for profiling. */
1356 if (PROFILE_MODEL_P (current_cpu
))
1359 FLD (out_dr
) = f_r1
;
1360 FLD (out_sr
) = f_r2
;
1369 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1370 CGEN_INSN_INT insn
= entire_insn
;
1371 #define FLD(f) abuf->fields.sfmt_ld24.f
1375 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
1376 f_uimm24
= EXTRACT_MSB0_UINT (insn
, 32, 8, 24);
1378 /* Record the fields for the semantic handler. */
1380 FLD (i_uimm24
) = f_uimm24
;
1381 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1382 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1
, "uimm24 0x%x", 'x', f_uimm24
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1384 #if WITH_PROFILE_MODEL_P
1385 /* Record the fields for profiling. */
1386 if (PROFILE_MODEL_P (current_cpu
))
1388 FLD (out_dr
) = f_r1
;
1397 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1398 CGEN_INSN_INT insn
= entire_insn
;
1399 #define FLD(f) abuf->fields.sfmt_addi.f
1403 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1404 f_simm8
= EXTRACT_MSB0_INT (insn
, 16, 8, 8);
1406 /* Record the fields for the semantic handler. */
1407 FLD (f_simm8
) = f_simm8
;
1409 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1410 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8
, "f_r1 0x%x", 'x', f_r1
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1412 #if WITH_PROFILE_MODEL_P
1413 /* Record the fields for profiling. */
1414 if (PROFILE_MODEL_P (current_cpu
))
1416 FLD (out_dr
) = f_r1
;
1425 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1426 CGEN_INSN_INT insn
= entire_insn
;
1427 #define FLD(f) abuf->fields.sfmt_add3.f
1431 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
1432 f_simm16
= EXTRACT_MSB0_INT (insn
, 32, 16, 16);
1434 /* Record the fields for the semantic handler. */
1435 FLD (f_simm16
) = f_simm16
;
1437 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1438 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16
, "f_r1 0x%x", 'x', f_r1
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1440 #if WITH_PROFILE_MODEL_P
1441 /* Record the fields for profiling. */
1442 if (PROFILE_MODEL_P (current_cpu
))
1444 FLD (out_dr
) = f_r1
;
1453 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1454 CGEN_INSN_INT insn
= entire_insn
;
1455 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1459 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1460 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1462 /* Record the fields for the semantic handler. */
1465 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1466 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1467 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_lock", "f_r2 0x%x", 'x', f_r2
, "f_r1 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1469 #if WITH_PROFILE_MODEL_P
1470 /* Record the fields for profiling. */
1471 if (PROFILE_MODEL_P (current_cpu
))
1474 FLD (out_dr
) = f_r1
;
1481 extract_sfmt_machi_a
:
1483 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1484 CGEN_INSN_INT insn
= entire_insn
;
1485 #define FLD(f) abuf->fields.sfmt_machi_a.f
1490 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1491 f_acc
= EXTRACT_MSB0_UINT (insn
, 16, 8, 1);
1492 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1494 /* Record the fields for the semantic handler. */
1495 FLD (f_acc
) = f_acc
;
1498 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1499 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1500 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc
, "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1502 #if WITH_PROFILE_MODEL_P
1503 /* Record the fields for profiling. */
1504 if (PROFILE_MODEL_P (current_cpu
))
1506 FLD (in_src1
) = f_r1
;
1507 FLD (in_src2
) = f_r2
;
1514 extract_sfmt_mulhi_a
:
1516 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1517 CGEN_INSN_INT insn
= entire_insn
;
1518 #define FLD(f) abuf->fields.sfmt_machi_a.f
1523 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1524 f_acc
= EXTRACT_MSB0_UINT (insn
, 16, 8, 1);
1525 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1527 /* Record the fields for the semantic handler. */
1530 FLD (f_acc
) = f_acc
;
1531 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1532 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1533 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "f_acc 0x%x", 'x', f_acc
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1535 #if WITH_PROFILE_MODEL_P
1536 /* Record the fields for profiling. */
1537 if (PROFILE_MODEL_P (current_cpu
))
1539 FLD (in_src1
) = f_r1
;
1540 FLD (in_src2
) = f_r2
;
1549 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1550 CGEN_INSN_INT insn
= entire_insn
;
1551 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1555 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1556 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1558 /* Record the fields for the semantic handler. */
1561 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1562 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1563 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_mv", "f_r2 0x%x", 'x', f_r2
, "f_r1 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1565 #if WITH_PROFILE_MODEL_P
1566 /* Record the fields for profiling. */
1567 if (PROFILE_MODEL_P (current_cpu
))
1570 FLD (out_dr
) = f_r1
;
1577 extract_sfmt_mvfachi_a
:
1579 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1580 CGEN_INSN_INT insn
= entire_insn
;
1581 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f
1585 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1586 f_accs
= EXTRACT_MSB0_UINT (insn
, 16, 12, 2);
1588 /* Record the fields for the semantic handler. */
1589 FLD (f_accs
) = f_accs
;
1591 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1592 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs
, "f_r1 0x%x", 'x', f_r1
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1594 #if WITH_PROFILE_MODEL_P
1595 /* Record the fields for profiling. */
1596 if (PROFILE_MODEL_P (current_cpu
))
1598 FLD (out_dr
) = f_r1
;
1607 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1608 CGEN_INSN_INT insn
= entire_insn
;
1609 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1613 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1614 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1616 /* Record the fields for the semantic handler. */
1619 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1620 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2
, "f_r1 0x%x", 'x', f_r1
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1622 #if WITH_PROFILE_MODEL_P
1623 /* Record the fields for profiling. */
1624 if (PROFILE_MODEL_P (current_cpu
))
1626 FLD (out_dr
) = f_r1
;
1633 extract_sfmt_mvtachi_a
:
1635 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1636 CGEN_INSN_INT insn
= entire_insn
;
1637 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f
1641 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1642 f_accs
= EXTRACT_MSB0_UINT (insn
, 16, 12, 2);
1644 /* Record the fields for the semantic handler. */
1645 FLD (f_accs
) = f_accs
;
1647 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1648 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs
, "f_r1 0x%x", 'x', f_r1
, "src1 0x%x", 'x', f_r1
, (char *) 0));
1650 #if WITH_PROFILE_MODEL_P
1651 /* Record the fields for profiling. */
1652 if (PROFILE_MODEL_P (current_cpu
))
1654 FLD (in_src1
) = f_r1
;
1663 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1664 CGEN_INSN_INT insn
= entire_insn
;
1665 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1669 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1670 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1672 /* Record the fields for the semantic handler. */
1675 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1676 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2
, "f_r1 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
1678 #if WITH_PROFILE_MODEL_P
1679 /* Record the fields for profiling. */
1680 if (PROFILE_MODEL_P (current_cpu
))
1691 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1692 CGEN_INSN_INT insn
= entire_insn
;
1693 #define FLD(f) abuf->fields.fmt_empty.f
1696 /* Record the fields for the semantic handler. */
1697 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_nop", (char *) 0));
1703 extract_sfmt_rac_dsi
:
1705 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1706 CGEN_INSN_INT insn
= entire_insn
;
1707 #define FLD(f) abuf->fields.sfmt_rac_dsi.f
1712 f_accd
= EXTRACT_MSB0_UINT (insn
, 16, 4, 2);
1713 f_accs
= EXTRACT_MSB0_UINT (insn
, 16, 12, 2);
1714 f_imm1
= ((EXTRACT_MSB0_UINT (insn
, 16, 15, 1)) + (1));
1716 /* Record the fields for the semantic handler. */
1717 FLD (f_accs
) = f_accs
;
1718 FLD (f_imm1
) = f_imm1
;
1719 FLD (f_accd
) = f_accd
;
1720 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs
, "f_imm1 0x%x", 'x', f_imm1
, "f_accd 0x%x", 'x', f_accd
, (char *) 0));
1728 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1729 CGEN_INSN_INT insn
= entire_insn
;
1730 #define FLD(f) abuf->fields.fmt_empty.f
1733 /* Record the fields for the semantic handler. */
1734 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_rte", (char *) 0));
1736 #if WITH_PROFILE_MODEL_P
1737 /* Record the fields for profiling. */
1738 if (PROFILE_MODEL_P (current_cpu
))
1748 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1749 CGEN_INSN_INT insn
= entire_insn
;
1750 #define FLD(f) abuf->fields.sfmt_seth.f
1754 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
1755 f_hi16
= EXTRACT_MSB0_UINT (insn
, 32, 16, 16);
1757 /* Record the fields for the semantic handler. */
1758 FLD (f_hi16
) = f_hi16
;
1760 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1761 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16
, "f_r1 0x%x", 'x', f_r1
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1763 #if WITH_PROFILE_MODEL_P
1764 /* Record the fields for profiling. */
1765 if (PROFILE_MODEL_P (current_cpu
))
1767 FLD (out_dr
) = f_r1
;
1776 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1777 CGEN_INSN_INT insn
= entire_insn
;
1778 #define FLD(f) abuf->fields.sfmt_add3.f
1783 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
1784 f_r2
= EXTRACT_MSB0_UINT (insn
, 32, 12, 4);
1785 f_simm16
= EXTRACT_MSB0_INT (insn
, 32, 16, 16);
1787 /* Record the fields for the semantic handler. */
1788 FLD (f_simm16
) = f_simm16
;
1791 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1792 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1793 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16
, "f_r2 0x%x", 'x', f_r2
, "f_r1 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1795 #if WITH_PROFILE_MODEL_P
1796 /* Record the fields for profiling. */
1797 if (PROFILE_MODEL_P (current_cpu
))
1800 FLD (out_dr
) = f_r1
;
1809 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1810 CGEN_INSN_INT insn
= entire_insn
;
1811 #define FLD(f) abuf->fields.sfmt_slli.f
1815 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1816 f_uimm5
= EXTRACT_MSB0_UINT (insn
, 16, 11, 5);
1818 /* Record the fields for the semantic handler. */
1820 FLD (f_uimm5
) = f_uimm5
;
1821 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1822 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_slli", "f_r1 0x%x", 'x', f_r1
, "f_uimm5 0x%x", 'x', f_uimm5
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1824 #if WITH_PROFILE_MODEL_P
1825 /* Record the fields for profiling. */
1826 if (PROFILE_MODEL_P (current_cpu
))
1829 FLD (out_dr
) = f_r1
;
1838 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1839 CGEN_INSN_INT insn
= entire_insn
;
1840 #define FLD(f) abuf->fields.sfmt_st_plus.f
1844 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1845 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1847 /* Record the fields for the semantic handler. */
1850 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1851 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1852 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_st", "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1854 #if WITH_PROFILE_MODEL_P
1855 /* Record the fields for profiling. */
1856 if (PROFILE_MODEL_P (current_cpu
))
1858 FLD (in_src1
) = f_r1
;
1859 FLD (in_src2
) = f_r2
;
1868 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1869 CGEN_INSN_INT insn
= entire_insn
;
1870 #define FLD(f) abuf->fields.sfmt_st_d.f
1875 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
1876 f_r2
= EXTRACT_MSB0_UINT (insn
, 32, 12, 4);
1877 f_simm16
= EXTRACT_MSB0_INT (insn
, 32, 16, 16);
1879 /* Record the fields for the semantic handler. */
1880 FLD (f_simm16
) = f_simm16
;
1883 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1884 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1885 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16
, "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1887 #if WITH_PROFILE_MODEL_P
1888 /* Record the fields for profiling. */
1889 if (PROFILE_MODEL_P (current_cpu
))
1891 FLD (in_src1
) = f_r1
;
1892 FLD (in_src2
) = f_r2
;
1901 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1902 CGEN_INSN_INT insn
= entire_insn
;
1903 #define FLD(f) abuf->fields.sfmt_st_plus.f
1907 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1908 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1910 /* Record the fields for the semantic handler. */
1913 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1914 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1915 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_stb", "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1917 #if WITH_PROFILE_MODEL_P
1918 /* Record the fields for profiling. */
1919 if (PROFILE_MODEL_P (current_cpu
))
1921 FLD (in_src1
) = f_r1
;
1922 FLD (in_src2
) = f_r2
;
1931 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1932 CGEN_INSN_INT insn
= entire_insn
;
1933 #define FLD(f) abuf->fields.sfmt_st_d.f
1938 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
1939 f_r2
= EXTRACT_MSB0_UINT (insn
, 32, 12, 4);
1940 f_simm16
= EXTRACT_MSB0_INT (insn
, 32, 16, 16);
1942 /* Record the fields for the semantic handler. */
1943 FLD (f_simm16
) = f_simm16
;
1946 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1947 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1948 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16
, "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1950 #if WITH_PROFILE_MODEL_P
1951 /* Record the fields for profiling. */
1952 if (PROFILE_MODEL_P (current_cpu
))
1954 FLD (in_src1
) = f_r1
;
1955 FLD (in_src2
) = f_r2
;
1964 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1965 CGEN_INSN_INT insn
= entire_insn
;
1966 #define FLD(f) abuf->fields.sfmt_st_plus.f
1970 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
1971 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
1973 /* Record the fields for the semantic handler. */
1976 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1977 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1978 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_sth", "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1980 #if WITH_PROFILE_MODEL_P
1981 /* Record the fields for profiling. */
1982 if (PROFILE_MODEL_P (current_cpu
))
1984 FLD (in_src1
) = f_r1
;
1985 FLD (in_src2
) = f_r2
;
1994 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
1995 CGEN_INSN_INT insn
= entire_insn
;
1996 #define FLD(f) abuf->fields.sfmt_st_d.f
2001 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
2002 f_r2
= EXTRACT_MSB0_UINT (insn
, 32, 12, 4);
2003 f_simm16
= EXTRACT_MSB0_INT (insn
, 32, 16, 16);
2005 /* Record the fields for the semantic handler. */
2006 FLD (f_simm16
) = f_simm16
;
2009 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2010 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2011 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16
, "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
2013 #if WITH_PROFILE_MODEL_P
2014 /* Record the fields for profiling. */
2015 if (PROFILE_MODEL_P (current_cpu
))
2017 FLD (in_src1
) = f_r1
;
2018 FLD (in_src2
) = f_r2
;
2025 extract_sfmt_st_plus
:
2027 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
2028 CGEN_INSN_INT insn
= entire_insn
;
2029 #define FLD(f) abuf->fields.sfmt_st_plus.f
2033 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
2034 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
2036 /* Record the fields for the semantic handler. */
2039 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2040 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2041 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
2043 #if WITH_PROFILE_MODEL_P
2044 /* Record the fields for profiling. */
2045 if (PROFILE_MODEL_P (current_cpu
))
2047 FLD (in_src1
) = f_r1
;
2048 FLD (in_src2
) = f_r2
;
2049 FLD (out_src2
) = f_r2
;
2058 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
2059 CGEN_INSN_INT insn
= entire_insn
;
2060 #define FLD(f) abuf->fields.sfmt_trap.f
2063 f_uimm4
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
2065 /* Record the fields for the semantic handler. */
2066 FLD (f_uimm4
) = f_uimm4
;
2067 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4
, (char *) 0));
2069 #if WITH_PROFILE_MODEL_P
2070 /* Record the fields for profiling. */
2071 if (PROFILE_MODEL_P (current_cpu
))
2079 extract_sfmt_unlock
:
2081 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
2082 CGEN_INSN_INT insn
= entire_insn
;
2083 #define FLD(f) abuf->fields.sfmt_st_plus.f
2087 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
2088 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
2090 /* Record the fields for the semantic handler. */
2093 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2094 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2095 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
2097 #if WITH_PROFILE_MODEL_P
2098 /* Record the fields for profiling. */
2099 if (PROFILE_MODEL_P (current_cpu
))
2101 FLD (in_src1
) = f_r1
;
2102 FLD (in_src2
) = f_r2
;
2111 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
2112 CGEN_INSN_INT insn
= entire_insn
;
2113 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2117 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
2118 f_r2
= EXTRACT_MSB0_UINT (insn
, 32, 12, 4);
2120 /* Record the fields for the semantic handler. */
2123 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
2124 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
2125 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_satb", "f_r2 0x%x", 'x', f_r2
, "f_r1 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
2127 #if WITH_PROFILE_MODEL_P
2128 /* Record the fields for profiling. */
2129 if (PROFILE_MODEL_P (current_cpu
))
2132 FLD (out_dr
) = f_r1
;
2141 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
2142 CGEN_INSN_INT insn
= entire_insn
;
2143 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2147 f_r1
= EXTRACT_MSB0_UINT (insn
, 32, 4, 4);
2148 f_r2
= EXTRACT_MSB0_UINT (insn
, 32, 12, 4);
2150 /* Record the fields for the semantic handler. */
2153 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
2154 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
2155 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_sat", "f_r2 0x%x", 'x', f_r2
, "f_r1 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
2157 #if WITH_PROFILE_MODEL_P
2158 /* Record the fields for profiling. */
2159 if (PROFILE_MODEL_P (current_cpu
))
2162 FLD (out_dr
) = f_r1
;
2171 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
2172 CGEN_INSN_INT insn
= entire_insn
;
2173 #define FLD(f) abuf->fields.fmt_empty.f
2176 /* Record the fields for the semantic handler. */
2177 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_sadd", (char *) 0));
2183 extract_sfmt_macwu1
:
2185 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
2186 CGEN_INSN_INT insn
= entire_insn
;
2187 #define FLD(f) abuf->fields.sfmt_st_plus.f
2191 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
2192 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
2194 /* Record the fields for the semantic handler. */
2197 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2198 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2199 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
2201 #if WITH_PROFILE_MODEL_P
2202 /* Record the fields for profiling. */
2203 if (PROFILE_MODEL_P (current_cpu
))
2205 FLD (in_src1
) = f_r1
;
2206 FLD (in_src2
) = f_r2
;
2215 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
2216 CGEN_INSN_INT insn
= entire_insn
;
2217 #define FLD(f) abuf->fields.sfmt_st_plus.f
2221 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
2222 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
2224 /* Record the fields for the semantic handler. */
2227 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2228 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2229 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
2231 #if WITH_PROFILE_MODEL_P
2232 /* Record the fields for profiling. */
2233 if (PROFILE_MODEL_P (current_cpu
))
2235 FLD (in_src1
) = f_r1
;
2236 FLD (in_src2
) = f_r2
;
2243 extract_sfmt_mulwu1
:
2245 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
2246 CGEN_INSN_INT insn
= entire_insn
;
2247 #define FLD(f) abuf->fields.sfmt_st_plus.f
2251 f_r1
= EXTRACT_MSB0_UINT (insn
, 16, 4, 4);
2252 f_r2
= EXTRACT_MSB0_UINT (insn
, 16, 12, 4);
2254 /* Record the fields for the semantic handler. */
2257 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2258 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2259 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1
, "f_r2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
2261 #if WITH_PROFILE_MODEL_P
2262 /* Record the fields for profiling. */
2263 if (PROFILE_MODEL_P (current_cpu
))
2265 FLD (in_src1
) = f_r1
;
2266 FLD (in_src2
) = f_r2
;
2275 const IDESC
*idesc
= &m32rxf_insn_data
[itype
];
2276 CGEN_INSN_INT insn
= entire_insn
;
2277 #define FLD(f) abuf->fields.fmt_empty.f
2280 /* Record the fields for the semantic handler. */
2281 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "sfmt_sc", (char *) 0));