sim/m32r/mloopx.in

   1 # Simulator main loop for m32rx. -*- C -*-
   2 # Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   3 #
   4 # This file is part of the GNU Simulators.
   5 #
   6 # This program is free software; you can redistribute it and/or modify
   7 # it under the terms of the GNU General Public License as published by
   8 # the Free Software Foundation; either version 2, or (at your option)
   9 # any later version.
  10 #
  11 # This program is distributed in the hope that it will be useful,
  12 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 # GNU General Public License for more details.
  15 #
  16 # You should have received a copy of the GNU General Public License along
  17 # with this program; if not, write to the Free Software Foundation, Inc.,
  18 # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19
  20 # Syntax:
  21 # /bin/sh mainloop.in init|support|{full,fast}-{extract,exec}-{scache,noscache}
  22
  23 # ??? After a few more ports are done, revisit.
  24 # Will eventually need to machine generate a lot of this.
  25
  26 case "x$1" in
  27
  28 xsupport)
  29
  30 cat <<EOF
  31
  32 EOF
  33
  34 ;;
  35
  36 xinit)
  37
  38 cat <<EOF
  39   const IDESC *d1,*d2;
  40   ARGBUF abufs[MAX_PARALLEL_INSNS];
  41   PAREXEC pbufs[MAX_PARALLEL_INSNS];
  42 EOF
  43
  44 ;;
  45
  46 xfull-extract-* | xfast-extract-*)
  47
  48 cat <<EOF
  49 {
  50   PCADDR pc = CPU (h_pc);
  51
  52   /* ??? This code isn't very fast.  Let's get it working first.  */
  53
  54   if ((pc & 3) != 0)
  55     {
  56       USI insn = GETIMEMUHI (current_cpu, pc);
  57       insn &= 0x7fff;
  58       d1 = m32rx_decode (current_cpu, pc, insn);
  59       abufs[0].insn = insn;
  60       abufs[0].idesc = d1;
  61       icount = 1;
  62     }
  63   else
  64     {
  65       USI insn = GETIMEMUSI (current_cpu, pc);
  66       if ((SI) insn < 0)
  67         {
  68           d1 = m32rx_decode (current_cpu, pc, insn >> 16);
  69           abufs[0].insn = insn;
  70           abufs[0].idesc = d1;
  71           icount = 1;
  72         }
  73       else
  74         {
  75           if (insn & 0x8000)
  76             {
  77               d1 = m32rx_decode (current_cpu, pc, insn >> 16);
  78               abufs[0].insn = insn >> 16;
  79               abufs[0].idesc = d1;
  80               d2 = m32rx_decode (current_cpu, pc, insn & 0x7fff);
  81               abufs[1].insn = insn & 0x7fff;
  82               abufs[1].idesc = d2;
  83               icount = 2;
  84             }
  85           else
  86             {
  87               d1 = m32rx_decode (current_cpu, pc, insn >> 16);
  88               abufs[0].insn = insn >> 16;
  89               abufs[0].idesc = d1;
  90               icount = 1;
  91             }
  92         }
  93     }
  94
  95   {
  96     int icount2 = icount;
  97     USI insn = abufs[0].insn;
  98     const IDESC *decode = d1;
  99     /* decode, par_exec, and insn are refered to by readx.c.  */
 100     PAREXEC *par_exec = &pbufs[0];
 101     do
 102       {
 103 #define DEFINE_SWITCH
 104 #include "readx.c"
 105
 106         decode = d2;
 107         insn = abufs[1].insn;
 108         ++par_exec;
 109       }
 110     while (--icount2 != 0);
 111   }
 112 }
 113 EOF
 114
 115 ;;
 116
 117 xfull-exec-* | xfast-exec-*)
 118
 119 cat <<EOF
 120 {
 121   SEM_ARG sem_arg = &abufs[0];
 122   PAREXEC *par_exec = &pbufs[0];
 123   PCADDR new_pc;
 124
 125 #if 0 /* wip */
 126   /* If doing parallel execution, verify insns are in the right pipeline.  */
 127   if (icount == 2)
 128     {
 129       ...
 130     }
 131 #endif
 132
 133   TRACE_INSN_INIT (current_cpu, 1);
 134   TRACE_INSN (current_cpu, d1->opcode, sem_arg, CPU (h_pc));
 135   new_pc = (*d1->sem_full) (current_cpu, sem_arg, par_exec);
 136   TRACE_INSN_FINI (current_cpu, icount == 1);
 137
 138   /* The result of the semantic fn is one of:
 139      - next address, branch only
 140      - NEW_PC_SKIP, sc/snc insn
 141      - NEW_PC_2, 2 byte non-branch non-sc/snc insn
 142      - NEW_PC_4, 4 byte non-branch insn
 143      */
 144
 145   /* The tests are ordered to try to favor the more frequent cases, while
 146      keeping the over all costs down.  */
 147   if (new_pc == NEW_PC_4)
 148     CPU (h_pc) += 4;
 149   else if (icount == 2)
 150     {
 151       /* Note that we only get here if doing parallel execution.  */
 152
 153       if (new_pc == NEW_PC_SKIP)
 154         {
 155           /* ??? Need generic notion of bypassing an insn for the name of
 156              this macro.  Annulled?  On the otherhand such tracing can go
 157              in the sc/snc semantic fn.  */
 158           ; /*TRACE_INSN_SKIPPED (current_cpu);*/
 159           CPU (h_pc) += 4;
 160         }
 161       else
 162         {
 163           PCADDR pc2;
 164
 165           ++sem_arg;
 166           ++par_exec;
 167           TRACE_INSN_INIT (current_cpu, 0);
 168           TRACE_INSN (current_cpu, d2->opcode, sem_arg, CPU (h_pc) + 2);
 169           /* pc2 isn't used.  It's assigned a value for debugging.  */
 170           pc2 = (*d2->sem_full) (current_cpu, sem_arg, par_exec);
 171           TRACE_INSN_FINI (current_cpu, 1);
 172
 173           if (NEW_PC_BRANCH_P (new_pc))
 174             CPU (h_pc) = new_pc;
 175           else
 176             CPU (h_pc) += 4;
 177         }
 178     }
 179   else if (NEW_PC_BRANCH_P (new_pc))
 180     CPU (h_pc) = new_pc;
 181   else
 182     CPU (h_pc) += 2;
 183 }
 184 EOF
 185
 186 ;;
 187
 188 *)
 189   echo "Invalid argument to mainloop.in: $1" >&2
 190   exit 1
 191   ;;
 192
 193 esac