sim/m32r/model.c

   1 /* Simulator model support for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #define WANT_CPU m32rbf
  26 #define WANT_CPU_M32RBF
  27
  28 #include "sim-main.h"
  29
  30 /* The profiling data is recorded here, but is accessed via the profiling
  31    mechanism.  After all, this is information for profiling.  */
  32
  33 #if WITH_PROFILE_MODEL_P
  34
  35 /* Model handlers for each insn.  */
  36
  37 static int
  38 model_m32r_d_add (SIM_CPU *current_cpu, void *sem_arg)
  39 {
  40 #define FLD(f) abuf->fields.fmt_add.f
  41   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
  42   const IDESC * UNUSED idesc = abuf->idesc;
  43   int cycles = 0;
  44   {
  45     int referenced = 0;
  46     int UNUSED insn_referenced = abuf->written;
  47     INT sr = -1;
  48     INT sr2 = -1;
  49     INT dr = -1;
  50     sr = FLD (in_sr);
  51     dr = FLD (out_dr);
  52     referenced |= 1 << 0;
  53     referenced |= 1 << 2;
  54     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
  55   }
  56   return cycles;
  57 #undef FLD
  58 }
  59
  60 static int
  61 model_m32r_d_add3 (SIM_CPU *current_cpu, void *sem_arg)
  62 {
  63 #define FLD(f) abuf->fields.fmt_add3.f
  64   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
  65   const IDESC * UNUSED idesc = abuf->idesc;
  66   int cycles = 0;
  67   {
  68     int referenced = 0;
  69     int UNUSED insn_referenced = abuf->written;
  70     INT sr = -1;
  71     INT sr2 = -1;
  72     INT dr = -1;
  73     sr = FLD (in_sr);
  74     dr = FLD (out_dr);
  75     referenced |= 1 << 0;
  76     referenced |= 1 << 2;
  77     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
  78   }
  79   return cycles;
  80 #undef FLD
  81 }
  82
  83 static int
  84 model_m32r_d_and (SIM_CPU *current_cpu, void *sem_arg)
  85 {
  86 #define FLD(f) abuf->fields.fmt_add.f
  87   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
  88   const IDESC * UNUSED idesc = abuf->idesc;
  89   int cycles = 0;
  90   {
  91     int referenced = 0;
  92     int UNUSED insn_referenced = abuf->written;
  93     INT sr = -1;
  94     INT sr2 = -1;
  95     INT dr = -1;
  96     sr = FLD (in_sr);
  97     dr = FLD (out_dr);
  98     referenced |= 1 << 0;
  99     referenced |= 1 << 2;
 100     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
 101   }
 102   return cycles;
 103 #undef FLD
 104 }
 105
 106 static int
 107 model_m32r_d_and3 (SIM_CPU *current_cpu, void *sem_arg)
 108 {
 109 #define FLD(f) abuf->fields.fmt_and3.f
 110   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 111   const IDESC * UNUSED idesc = abuf->idesc;
 112   int cycles = 0;
 113   {
 114     int referenced = 0;
 115     int UNUSED insn_referenced = abuf->written;
 116     INT sr = -1;
 117     INT sr2 = -1;
 118     INT dr = -1;
 119     sr = FLD (in_sr);
 120     dr = FLD (out_dr);
 121     referenced |= 1 << 0;
 122     referenced |= 1 << 2;
 123     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
 124   }
 125   return cycles;
 126 #undef FLD
 127 }
 128
 129 static int
 130 model_m32r_d_or (SIM_CPU *current_cpu, void *sem_arg)
 131 {
 132 #define FLD(f) abuf->fields.fmt_add.f
 133   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 134   const IDESC * UNUSED idesc = abuf->idesc;
 135   int cycles = 0;
 136   {
 137     int referenced = 0;
 138     int UNUSED insn_referenced = abuf->written;
 139     INT sr = -1;
 140     INT sr2 = -1;
 141     INT dr = -1;
 142     sr = FLD (in_sr);
 143     dr = FLD (out_dr);
 144     referenced |= 1 << 0;
 145     referenced |= 1 << 2;
 146     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
 147   }
 148   return cycles;
 149 #undef FLD
 150 }
 151
 152 static int
 153 model_m32r_d_or3 (SIM_CPU *current_cpu, void *sem_arg)
 154 {
 155 #define FLD(f) abuf->fields.fmt_or3.f
 156   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 157   const IDESC * UNUSED idesc = abuf->idesc;
 158   int cycles = 0;
 159   {
 160     int referenced = 0;
 161     int UNUSED insn_referenced = abuf->written;
 162     INT sr = -1;
 163     INT sr2 = -1;
 164     INT dr = -1;
 165     sr = FLD (in_sr);
 166     dr = FLD (out_dr);
 167     referenced |= 1 << 0;
 168     referenced |= 1 << 2;
 169     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
 170   }
 171   return cycles;
 172 #undef FLD
 173 }
 174
 175 static int
 176 model_m32r_d_xor (SIM_CPU *current_cpu, void *sem_arg)
 177 {
 178 #define FLD(f) abuf->fields.fmt_add.f
 179   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 180   const IDESC * UNUSED idesc = abuf->idesc;
 181   int cycles = 0;
 182   {
 183     int referenced = 0;
 184     int UNUSED insn_referenced = abuf->written;
 185     INT sr = -1;
 186     INT sr2 = -1;
 187     INT dr = -1;
 188     sr = FLD (in_sr);
 189     dr = FLD (out_dr);
 190     referenced |= 1 << 0;
 191     referenced |= 1 << 2;
 192     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
 193   }
 194   return cycles;
 195 #undef FLD
 196 }
 197
 198 static int
 199 model_m32r_d_xor3 (SIM_CPU *current_cpu, void *sem_arg)
 200 {
 201 #define FLD(f) abuf->fields.fmt_and3.f
 202   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 203   const IDESC * UNUSED idesc = abuf->idesc;
 204   int cycles = 0;
 205   {
 206     int referenced = 0;
 207     int UNUSED insn_referenced = abuf->written;
 208     INT sr = -1;
 209     INT sr2 = -1;
 210     INT dr = -1;
 211     sr = FLD (in_sr);
 212     dr = FLD (out_dr);
 213     referenced |= 1 << 0;
 214     referenced |= 1 << 2;
 215     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
 216   }
 217   return cycles;
 218 #undef FLD
 219 }
 220
 221 static int
 222 model_m32r_d_addi (SIM_CPU *current_cpu, void *sem_arg)
 223 {
 224 #define FLD(f) abuf->fields.fmt_addi.f
 225   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 226   const IDESC * UNUSED idesc = abuf->idesc;
 227   int cycles = 0;
 228   {
 229     int referenced = 0;
 230     int UNUSED insn_referenced = abuf->written;
 231     INT sr = -1;
 232     INT sr2 = -1;
 233     INT dr = -1;
 234     dr = FLD (out_dr);
 235     sr = FLD (in_dr);
 236     referenced |= 1 << 0;
 237     referenced |= 1 << 2;
 238     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
 239   }
 240   return cycles;
 241 #undef FLD
 242 }
 243
 244 static int
 245 model_m32r_d_addv (SIM_CPU *current_cpu, void *sem_arg)
 246 {
 247 #define FLD(f) abuf->fields.fmt_addv.f
 248   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 249   const IDESC * UNUSED idesc = abuf->idesc;
 250   int cycles = 0;
 251   {
 252     int referenced = 0;
 253     int UNUSED insn_referenced = abuf->written;
 254     INT sr = -1;
 255     INT sr2 = -1;
 256     INT dr = -1;
 257     sr = FLD (in_sr);
 258     dr = FLD (out_dr);
 259     referenced |= 1 << 0;
 260     referenced |= 1 << 2;
 261     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
 262   }
 263   return cycles;
 264 #undef FLD
 265 }
 266
 267 static int
 268 model_m32r_d_addv3 (SIM_CPU *current_cpu, void *sem_arg)
 269 {
 270 #define FLD(f) abuf->fields.fmt_addv3.f
 271   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 272   const IDESC * UNUSED idesc = abuf->idesc;
 273   int cycles = 0;
 274   {
 275     int referenced = 0;
 276     int UNUSED insn_referenced = abuf->written;
 277     INT sr = -1;
 278     INT sr2 = -1;
 279     INT dr = -1;
 280     sr = FLD (in_sr);
 281     dr = FLD (out_dr);
 282     referenced |= 1 << 0;
 283     referenced |= 1 << 2;
 284     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
 285   }
 286   return cycles;
 287 #undef FLD
 288 }
 289
 290 static int
 291 model_m32r_d_addx (SIM_CPU *current_cpu, void *sem_arg)
 292 {
 293 #define FLD(f) abuf->fields.fmt_addx.f
 294   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 295   const IDESC * UNUSED idesc = abuf->idesc;
 296   int cycles = 0;
 297   {
 298     int referenced = 0;
 299     int UNUSED insn_referenced = abuf->written;
 300     INT sr = -1;
 301     INT sr2 = -1;
 302     INT dr = -1;
 303     sr = FLD (in_sr);
 304     dr = FLD (out_dr);
 305     referenced |= 1 << 0;
 306     referenced |= 1 << 2;
 307     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
 308   }
 309   return cycles;
 310 #undef FLD
 311 }
 312
 313 static int
 314 model_m32r_d_bc8 (SIM_CPU *current_cpu, void *sem_arg)
 315 {
 316 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
 317   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 318   const IDESC * UNUSED idesc = abuf->idesc;
 319   int cycles = 0;
 320   {
 321     int referenced = 0;
 322     int UNUSED insn_referenced = abuf->written;
 323     INT sr = -1;
 324     if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
 325     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 326   }
 327   return cycles;
 328 #undef FLD
 329 }
 330
 331 static int
 332 model_m32r_d_bc24 (SIM_CPU *current_cpu, void *sem_arg)
 333 {
 334 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
 335   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 336   const IDESC * UNUSED idesc = abuf->idesc;
 337   int cycles = 0;
 338   {
 339     int referenced = 0;
 340     int UNUSED insn_referenced = abuf->written;
 341     INT sr = -1;
 342     if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
 343     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 344   }
 345   return cycles;
 346 #undef FLD
 347 }
 348
 349 static int
 350 model_m32r_d_beq (SIM_CPU *current_cpu, void *sem_arg)
 351 {
 352 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
 353   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 354   const IDESC * UNUSED idesc = abuf->idesc;
 355   int cycles = 0;
 356   {
 357     int referenced = 0;
 358     int UNUSED insn_referenced = abuf->written;
 359     INT sr = -1;
 360     if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
 361     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 362   }
 363   {
 364     int referenced = 0;
 365     int UNUSED insn_referenced = abuf->written;
 366     INT src1 = -1;
 367     INT src2 = -1;
 368     src1 = FLD (in_src1);
 369     src2 = FLD (in_src2);
 370     referenced |= 1 << 0;
 371     referenced |= 1 << 1;
 372     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
 373   }
 374   return cycles;
 375 #undef FLD
 376 }
 377
 378 static int
 379 model_m32r_d_beqz (SIM_CPU *current_cpu, void *sem_arg)
 380 {
 381 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
 382   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 383   const IDESC * UNUSED idesc = abuf->idesc;
 384   int cycles = 0;
 385   {
 386     int referenced = 0;
 387     int UNUSED insn_referenced = abuf->written;
 388     INT sr = -1;
 389     if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
 390     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 391   }
 392   {
 393     int referenced = 0;
 394     int UNUSED insn_referenced = abuf->written;
 395     INT src1 = -1;
 396     INT src2 = -1;
 397     src2 = FLD (in_src2);
 398     referenced |= 1 << 1;
 399     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
 400   }
 401   return cycles;
 402 #undef FLD
 403 }
 404
 405 static int
 406 model_m32r_d_bgez (SIM_CPU *current_cpu, void *sem_arg)
 407 {
 408 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
 409   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 410   const IDESC * UNUSED idesc = abuf->idesc;
 411   int cycles = 0;
 412   {
 413     int referenced = 0;
 414     int UNUSED insn_referenced = abuf->written;
 415     INT sr = -1;
 416     if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
 417     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 418   }
 419   {
 420     int referenced = 0;
 421     int UNUSED insn_referenced = abuf->written;
 422     INT src1 = -1;
 423     INT src2 = -1;
 424     src2 = FLD (in_src2);
 425     referenced |= 1 << 1;
 426     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
 427   }
 428   return cycles;
 429 #undef FLD
 430 }
 431
 432 static int
 433 model_m32r_d_bgtz (SIM_CPU *current_cpu, void *sem_arg)
 434 {
 435 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
 436   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 437   const IDESC * UNUSED idesc = abuf->idesc;
 438   int cycles = 0;
 439   {
 440     int referenced = 0;
 441     int UNUSED insn_referenced = abuf->written;
 442     INT sr = -1;
 443     if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
 444     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 445   }
 446   {
 447     int referenced = 0;
 448     int UNUSED insn_referenced = abuf->written;
 449     INT src1 = -1;
 450     INT src2 = -1;
 451     src2 = FLD (in_src2);
 452     referenced |= 1 << 1;
 453     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
 454   }
 455   return cycles;
 456 #undef FLD
 457 }
 458
 459 static int
 460 model_m32r_d_blez (SIM_CPU *current_cpu, void *sem_arg)
 461 {
 462 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
 463   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 464   const IDESC * UNUSED idesc = abuf->idesc;
 465   int cycles = 0;
 466   {
 467     int referenced = 0;
 468     int UNUSED insn_referenced = abuf->written;
 469     INT sr = -1;
 470     if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
 471     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 472   }
 473   {
 474     int referenced = 0;
 475     int UNUSED insn_referenced = abuf->written;
 476     INT src1 = -1;
 477     INT src2 = -1;
 478     src2 = FLD (in_src2);
 479     referenced |= 1 << 1;
 480     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
 481   }
 482   return cycles;
 483 #undef FLD
 484 }
 485
 486 static int
 487 model_m32r_d_bltz (SIM_CPU *current_cpu, void *sem_arg)
 488 {
 489 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
 490   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 491   const IDESC * UNUSED idesc = abuf->idesc;
 492   int cycles = 0;
 493   {
 494     int referenced = 0;
 495     int UNUSED insn_referenced = abuf->written;
 496     INT sr = -1;
 497     if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
 498     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 499   }
 500   {
 501     int referenced = 0;
 502     int UNUSED insn_referenced = abuf->written;
 503     INT src1 = -1;
 504     INT src2 = -1;
 505     src2 = FLD (in_src2);
 506     referenced |= 1 << 1;
 507     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
 508   }
 509   return cycles;
 510 #undef FLD
 511 }
 512
 513 static int
 514 model_m32r_d_bnez (SIM_CPU *current_cpu, void *sem_arg)
 515 {
 516 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
 517   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 518   const IDESC * UNUSED idesc = abuf->idesc;
 519   int cycles = 0;
 520   {
 521     int referenced = 0;
 522     int UNUSED insn_referenced = abuf->written;
 523     INT sr = -1;
 524     if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
 525     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 526   }
 527   {
 528     int referenced = 0;
 529     int UNUSED insn_referenced = abuf->written;
 530     INT src1 = -1;
 531     INT src2 = -1;
 532     src2 = FLD (in_src2);
 533     referenced |= 1 << 1;
 534     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
 535   }
 536   return cycles;
 537 #undef FLD
 538 }
 539
 540 static int
 541 model_m32r_d_bl8 (SIM_CPU *current_cpu, void *sem_arg)
 542 {
 543 #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
 544   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 545   const IDESC * UNUSED idesc = abuf->idesc;
 546   int cycles = 0;
 547   {
 548     int referenced = 0;
 549     int UNUSED insn_referenced = abuf->written;
 550     INT sr = -1;
 551     referenced |= 1 << 1;
 552     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 553   }
 554   return cycles;
 555 #undef FLD
 556 }
 557
 558 static int
 559 model_m32r_d_bl24 (SIM_CPU *current_cpu, void *sem_arg)
 560 {
 561 #define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
 562   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 563   const IDESC * UNUSED idesc = abuf->idesc;
 564   int cycles = 0;
 565   {
 566     int referenced = 0;
 567     int UNUSED insn_referenced = abuf->written;
 568     INT sr = -1;
 569     referenced |= 1 << 1;
 570     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 571   }
 572   return cycles;
 573 #undef FLD
 574 }
 575
 576 static int
 577 model_m32r_d_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
 578 {
 579 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
 580   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 581   const IDESC * UNUSED idesc = abuf->idesc;
 582   int cycles = 0;
 583   {
 584     int referenced = 0;
 585     int UNUSED insn_referenced = abuf->written;
 586     INT sr = -1;
 587     if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
 588     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 589   }
 590   return cycles;
 591 #undef FLD
 592 }
 593
 594 static int
 595 model_m32r_d_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
 596 {
 597 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
 598   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 599   const IDESC * UNUSED idesc = abuf->idesc;
 600   int cycles = 0;
 601   {
 602     int referenced = 0;
 603     int UNUSED insn_referenced = abuf->written;
 604     INT sr = -1;
 605     if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
 606     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 607   }
 608   return cycles;
 609 #undef FLD
 610 }
 611
 612 static int
 613 model_m32r_d_bne (SIM_CPU *current_cpu, void *sem_arg)
 614 {
 615 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
 616   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 617   const IDESC * UNUSED idesc = abuf->idesc;
 618   int cycles = 0;
 619   {
 620     int referenced = 0;
 621     int UNUSED insn_referenced = abuf->written;
 622     INT sr = -1;
 623     if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
 624     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 625   }
 626   {
 627     int referenced = 0;
 628     int UNUSED insn_referenced = abuf->written;
 629     INT src1 = -1;
 630     INT src2 = -1;
 631     src1 = FLD (in_src1);
 632     src2 = FLD (in_src2);
 633     referenced |= 1 << 0;
 634     referenced |= 1 << 1;
 635     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
 636   }
 637   return cycles;
 638 #undef FLD
 639 }
 640
 641 static int
 642 model_m32r_d_bra8 (SIM_CPU *current_cpu, void *sem_arg)
 643 {
 644 #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
 645   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 646   const IDESC * UNUSED idesc = abuf->idesc;
 647   int cycles = 0;
 648   {
 649     int referenced = 0;
 650     int UNUSED insn_referenced = abuf->written;
 651     INT sr = -1;
 652     referenced |= 1 << 1;
 653     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 654   }
 655   return cycles;
 656 #undef FLD
 657 }
 658
 659 static int
 660 model_m32r_d_bra24 (SIM_CPU *current_cpu, void *sem_arg)
 661 {
 662 #define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
 663   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 664   const IDESC * UNUSED idesc = abuf->idesc;
 665   int cycles = 0;
 666   {
 667     int referenced = 0;
 668     int UNUSED insn_referenced = abuf->written;
 669     INT sr = -1;
 670     referenced |= 1 << 1;
 671     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 672   }
 673   return cycles;
 674 #undef FLD
 675 }
 676
 677 static int
 678 model_m32r_d_cmp (SIM_CPU *current_cpu, void *sem_arg)
 679 {
 680 #define FLD(f) abuf->fields.fmt_cmp.f
 681   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 682   const IDESC * UNUSED idesc = abuf->idesc;
 683   int cycles = 0;
 684   {
 685     int referenced = 0;
 686     int UNUSED insn_referenced = abuf->written;
 687     INT src1 = -1;
 688     INT src2 = -1;
 689     src1 = FLD (in_src1);
 690     src2 = FLD (in_src2);
 691     referenced |= 1 << 0;
 692     referenced |= 1 << 1;
 693     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
 694   }
 695   return cycles;
 696 #undef FLD
 697 }
 698
 699 static int
 700 model_m32r_d_cmpi (SIM_CPU *current_cpu, void *sem_arg)
 701 {
 702 #define FLD(f) abuf->fields.fmt_cmpi.f
 703   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 704   const IDESC * UNUSED idesc = abuf->idesc;
 705   int cycles = 0;
 706   {
 707     int referenced = 0;
 708     int UNUSED insn_referenced = abuf->written;
 709     INT src1 = -1;
 710     INT src2 = -1;
 711     src2 = FLD (in_src2);
 712     referenced |= 1 << 1;
 713     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
 714   }
 715   return cycles;
 716 #undef FLD
 717 }
 718
 719 static int
 720 model_m32r_d_cmpu (SIM_CPU *current_cpu, void *sem_arg)
 721 {
 722 #define FLD(f) abuf->fields.fmt_cmp.f
 723   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 724   const IDESC * UNUSED idesc = abuf->idesc;
 725   int cycles = 0;
 726   {
 727     int referenced = 0;
 728     int UNUSED insn_referenced = abuf->written;
 729     INT src1 = -1;
 730     INT src2 = -1;
 731     src1 = FLD (in_src1);
 732     src2 = FLD (in_src2);
 733     referenced |= 1 << 0;
 734     referenced |= 1 << 1;
 735     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
 736   }
 737   return cycles;
 738 #undef FLD
 739 }
 740
 741 static int
 742 model_m32r_d_cmpui (SIM_CPU *current_cpu, void *sem_arg)
 743 {
 744 #define FLD(f) abuf->fields.fmt_cmpi.f
 745   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 746   const IDESC * UNUSED idesc = abuf->idesc;
 747   int cycles = 0;
 748   {
 749     int referenced = 0;
 750     int UNUSED insn_referenced = abuf->written;
 751     INT src1 = -1;
 752     INT src2 = -1;
 753     src2 = FLD (in_src2);
 754     referenced |= 1 << 1;
 755     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
 756   }
 757   return cycles;
 758 #undef FLD
 759 }
 760
 761 static int
 762 model_m32r_d_div (SIM_CPU *current_cpu, void *sem_arg)
 763 {
 764 #define FLD(f) abuf->fields.fmt_div.f
 765   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 766   const IDESC * UNUSED idesc = abuf->idesc;
 767   int cycles = 0;
 768   {
 769     int referenced = 0;
 770     int UNUSED insn_referenced = abuf->written;
 771     INT sr = -1;
 772     INT sr2 = -1;
 773     INT dr = -1;
 774     sr = FLD (in_sr);
 775     dr = FLD (out_dr);
 776     referenced |= 1 << 0;
 777     if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
 778     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
 779   }
 780   return cycles;
 781 #undef FLD
 782 }
 783
 784 static int
 785 model_m32r_d_divu (SIM_CPU *current_cpu, void *sem_arg)
 786 {
 787 #define FLD(f) abuf->fields.fmt_div.f
 788   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 789   const IDESC * UNUSED idesc = abuf->idesc;
 790   int cycles = 0;
 791   {
 792     int referenced = 0;
 793     int UNUSED insn_referenced = abuf->written;
 794     INT sr = -1;
 795     INT sr2 = -1;
 796     INT dr = -1;
 797     sr = FLD (in_sr);
 798     dr = FLD (out_dr);
 799     referenced |= 1 << 0;
 800     if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
 801     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
 802   }
 803   return cycles;
 804 #undef FLD
 805 }
 806
 807 static int
 808 model_m32r_d_rem (SIM_CPU *current_cpu, void *sem_arg)
 809 {
 810 #define FLD(f) abuf->fields.fmt_div.f
 811   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 812   const IDESC * UNUSED idesc = abuf->idesc;
 813   int cycles = 0;
 814   {
 815     int referenced = 0;
 816     int UNUSED insn_referenced = abuf->written;
 817     INT sr = -1;
 818     INT sr2 = -1;
 819     INT dr = -1;
 820     sr = FLD (in_sr);
 821     dr = FLD (out_dr);
 822     referenced |= 1 << 0;
 823     if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
 824     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
 825   }
 826   return cycles;
 827 #undef FLD
 828 }
 829
 830 static int
 831 model_m32r_d_remu (SIM_CPU *current_cpu, void *sem_arg)
 832 {
 833 #define FLD(f) abuf->fields.fmt_div.f
 834   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 835   const IDESC * UNUSED idesc = abuf->idesc;
 836   int cycles = 0;
 837   {
 838     int referenced = 0;
 839     int UNUSED insn_referenced = abuf->written;
 840     INT sr = -1;
 841     INT sr2 = -1;
 842     INT dr = -1;
 843     sr = FLD (in_sr);
 844     dr = FLD (out_dr);
 845     referenced |= 1 << 0;
 846     if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
 847     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
 848   }
 849   return cycles;
 850 #undef FLD
 851 }
 852
 853 static int
 854 model_m32r_d_jl (SIM_CPU *current_cpu, void *sem_arg)
 855 {
 856 #define FLD(f) abuf->fields.cti.fields.fmt_jl.f
 857   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 858   const IDESC * UNUSED idesc = abuf->idesc;
 859   int cycles = 0;
 860   {
 861     int referenced = 0;
 862     int UNUSED insn_referenced = abuf->written;
 863     INT sr = -1;
 864     sr = FLD (in_sr);
 865     referenced |= 1 << 0;
 866     referenced |= 1 << 1;
 867     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 868   }
 869   return cycles;
 870 #undef FLD
 871 }
 872
 873 static int
 874 model_m32r_d_jmp (SIM_CPU *current_cpu, void *sem_arg)
 875 {
 876 #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
 877   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 878   const IDESC * UNUSED idesc = abuf->idesc;
 879   int cycles = 0;
 880   {
 881     int referenced = 0;
 882     int UNUSED insn_referenced = abuf->written;
 883     INT sr = -1;
 884     sr = FLD (in_sr);
 885     referenced |= 1 << 0;
 886     referenced |= 1 << 1;
 887     cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
 888   }
 889   return cycles;
 890 #undef FLD
 891 }
 892
 893 static int
 894 model_m32r_d_ld (SIM_CPU *current_cpu, void *sem_arg)
 895 {
 896 #define FLD(f) abuf->fields.fmt_ld.f
 897   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 898   const IDESC * UNUSED idesc = abuf->idesc;
 899   int cycles = 0;
 900   {
 901     int referenced = 0;
 902     int UNUSED insn_referenced = abuf->written;
 903     INT sr = 0;
 904     INT dr = 0;
 905     sr = FLD (in_sr);
 906     dr = FLD (out_dr);
 907     referenced |= 1 << 0;
 908     referenced |= 1 << 1;
 909     cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
 910   }
 911   return cycles;
 912 #undef FLD
 913 }
 914
 915 static int
 916 model_m32r_d_ld_d (SIM_CPU *current_cpu, void *sem_arg)
 917 {
 918 #define FLD(f) abuf->fields.fmt_ld_d.f
 919   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 920   const IDESC * UNUSED idesc = abuf->idesc;
 921   int cycles = 0;
 922   {
 923     int referenced = 0;
 924     int UNUSED insn_referenced = abuf->written;
 925     INT sr = 0;
 926     INT dr = 0;
 927     sr = FLD (in_sr);
 928     dr = FLD (out_dr);
 929     referenced |= 1 << 0;
 930     referenced |= 1 << 1;
 931     cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
 932   }
 933   return cycles;
 934 #undef FLD
 935 }
 936
 937 static int
 938 model_m32r_d_ldb (SIM_CPU *current_cpu, void *sem_arg)
 939 {
 940 #define FLD(f) abuf->fields.fmt_ldb.f
 941   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 942   const IDESC * UNUSED idesc = abuf->idesc;
 943   int cycles = 0;
 944   {
 945     int referenced = 0;
 946     int UNUSED insn_referenced = abuf->written;
 947     INT sr = 0;
 948     INT dr = 0;
 949     sr = FLD (in_sr);
 950     dr = FLD (out_dr);
 951     referenced |= 1 << 0;
 952     referenced |= 1 << 1;
 953     cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
 954   }
 955   return cycles;
 956 #undef FLD
 957 }
 958
 959 static int
 960 model_m32r_d_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
 961 {
 962 #define FLD(f) abuf->fields.fmt_ldb_d.f
 963   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 964   const IDESC * UNUSED idesc = abuf->idesc;
 965   int cycles = 0;
 966   {
 967     int referenced = 0;
 968     int UNUSED insn_referenced = abuf->written;
 969     INT sr = 0;
 970     INT dr = 0;
 971     sr = FLD (in_sr);
 972     dr = FLD (out_dr);
 973     referenced |= 1 << 0;
 974     referenced |= 1 << 1;
 975     cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
 976   }
 977   return cycles;
 978 #undef FLD
 979 }
 980
 981 static int
 982 model_m32r_d_ldh (SIM_CPU *current_cpu, void *sem_arg)
 983 {
 984 #define FLD(f) abuf->fields.fmt_ldh.f
 985   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
 986   const IDESC * UNUSED idesc = abuf->idesc;
 987   int cycles = 0;
 988   {
 989     int referenced = 0;
 990     int UNUSED insn_referenced = abuf->written;
 991     INT sr = 0;
 992     INT dr = 0;
 993     sr = FLD (in_sr);
 994     dr = FLD (out_dr);
 995     referenced |= 1 << 0;
 996     referenced |= 1 << 1;
 997     cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
 998   }
 999   return cycles;
1000 #undef FLD
1001 }
1002
1003 static int
1004 model_m32r_d_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
1005 {
1006 #define FLD(f) abuf->fields.fmt_ldh_d.f
1007   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1008   const IDESC * UNUSED idesc = abuf->idesc;
1009   int cycles = 0;
1010   {
1011     int referenced = 0;
1012     int UNUSED insn_referenced = abuf->written;
1013     INT sr = 0;
1014     INT dr = 0;
1015     sr = FLD (in_sr);
1016     dr = FLD (out_dr);
1017     referenced |= 1 << 0;
1018     referenced |= 1 << 1;
1019     cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1020   }
1021   return cycles;
1022 #undef FLD
1023 }
1024
1025 static int
1026 model_m32r_d_ldub (SIM_CPU *current_cpu, void *sem_arg)
1027 {
1028 #define FLD(f) abuf->fields.fmt_ldb.f
1029   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1030   const IDESC * UNUSED idesc = abuf->idesc;
1031   int cycles = 0;
1032   {
1033     int referenced = 0;
1034     int UNUSED insn_referenced = abuf->written;
1035     INT sr = 0;
1036     INT dr = 0;
1037     sr = FLD (in_sr);
1038     dr = FLD (out_dr);
1039     referenced |= 1 << 0;
1040     referenced |= 1 << 1;
1041     cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1042   }
1043   return cycles;
1044 #undef FLD
1045 }
1046
1047 static int
1048 model_m32r_d_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
1049 {
1050 #define FLD(f) abuf->fields.fmt_ldb_d.f
1051   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1052   const IDESC * UNUSED idesc = abuf->idesc;
1053   int cycles = 0;
1054   {
1055     int referenced = 0;
1056     int UNUSED insn_referenced = abuf->written;
1057     INT sr = 0;
1058     INT dr = 0;
1059     sr = FLD (in_sr);
1060     dr = FLD (out_dr);
1061     referenced |= 1 << 0;
1062     referenced |= 1 << 1;
1063     cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1064   }
1065   return cycles;
1066 #undef FLD
1067 }
1068
1069 static int
1070 model_m32r_d_lduh (SIM_CPU *current_cpu, void *sem_arg)
1071 {
1072 #define FLD(f) abuf->fields.fmt_ldh.f
1073   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1074   const IDESC * UNUSED idesc = abuf->idesc;
1075   int cycles = 0;
1076   {
1077     int referenced = 0;
1078     int UNUSED insn_referenced = abuf->written;
1079     INT sr = 0;
1080     INT dr = 0;
1081     sr = FLD (in_sr);
1082     dr = FLD (out_dr);
1083     referenced |= 1 << 0;
1084     referenced |= 1 << 1;
1085     cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1086   }
1087   return cycles;
1088 #undef FLD
1089 }
1090
1091 static int
1092 model_m32r_d_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
1093 {
1094 #define FLD(f) abuf->fields.fmt_ldh_d.f
1095   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1096   const IDESC * UNUSED idesc = abuf->idesc;
1097   int cycles = 0;
1098   {
1099     int referenced = 0;
1100     int UNUSED insn_referenced = abuf->written;
1101     INT sr = 0;
1102     INT dr = 0;
1103     sr = FLD (in_sr);
1104     dr = FLD (out_dr);
1105     referenced |= 1 << 0;
1106     referenced |= 1 << 1;
1107     cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1108   }
1109   return cycles;
1110 #undef FLD
1111 }
1112
1113 static int
1114 model_m32r_d_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
1115 {
1116 #define FLD(f) abuf->fields.fmt_ld_plus.f
1117   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1118   const IDESC * UNUSED idesc = abuf->idesc;
1119   int cycles = 0;
1120   {
1121     int referenced = 0;
1122     int UNUSED insn_referenced = abuf->written;
1123     INT sr = 0;
1124     INT dr = 0;
1125     sr = FLD (in_sr);
1126     dr = FLD (out_dr);
1127     referenced |= 1 << 0;
1128     referenced |= 1 << 1;
1129     cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1130   }
1131   {
1132     int referenced = 0;
1133     int UNUSED insn_referenced = abuf->written;
1134     INT sr = -1;
1135     INT sr2 = -1;
1136     INT dr = -1;
1137     sr = FLD (in_sr);
1138     dr = FLD (out_sr);
1139     referenced |= 1 << 0;
1140     referenced |= 1 << 2;
1141     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, sr, sr2, dr);
1142   }
1143   return cycles;
1144 #undef FLD
1145 }
1146
1147 static int
1148 model_m32r_d_ld24 (SIM_CPU *current_cpu, void *sem_arg)
1149 {
1150 #define FLD(f) abuf->fields.fmt_ld24.f
1151   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1152   const IDESC * UNUSED idesc = abuf->idesc;
1153   int cycles = 0;
1154   {
1155     int referenced = 0;
1156     int UNUSED insn_referenced = abuf->written;
1157     INT sr = -1;
1158     INT sr2 = -1;
1159     INT dr = -1;
1160     dr = FLD (out_dr);
1161     referenced |= 1 << 2;
1162     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1163   }
1164   return cycles;
1165 #undef FLD
1166 }
1167
1168 static int
1169 model_m32r_d_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
1170 {
1171 #define FLD(f) abuf->fields.fmt_ldi8.f
1172   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1173   const IDESC * UNUSED idesc = abuf->idesc;
1174   int cycles = 0;
1175   {
1176     int referenced = 0;
1177     int UNUSED insn_referenced = abuf->written;
1178     INT sr = -1;
1179     INT sr2 = -1;
1180     INT dr = -1;
1181     dr = FLD (out_dr);
1182     referenced |= 1 << 2;
1183     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1184   }
1185   return cycles;
1186 #undef FLD
1187 }
1188
1189 static int
1190 model_m32r_d_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
1191 {
1192 #define FLD(f) abuf->fields.fmt_ldi16.f
1193   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1194   const IDESC * UNUSED idesc = abuf->idesc;
1195   int cycles = 0;
1196   {
1197     int referenced = 0;
1198     int UNUSED insn_referenced = abuf->written;
1199     INT sr = -1;
1200     INT sr2 = -1;
1201     INT dr = -1;
1202     dr = FLD (out_dr);
1203     referenced |= 1 << 2;
1204     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1205   }
1206   return cycles;
1207 #undef FLD
1208 }
1209
1210 static int
1211 model_m32r_d_lock (SIM_CPU *current_cpu, void *sem_arg)
1212 {
1213 #define FLD(f) abuf->fields.fmt_lock.f
1214   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1215   const IDESC * UNUSED idesc = abuf->idesc;
1216   int cycles = 0;
1217   {
1218     int referenced = 0;
1219     int UNUSED insn_referenced = abuf->written;
1220     INT sr = 0;
1221     INT dr = 0;
1222     sr = FLD (in_sr);
1223     dr = FLD (out_dr);
1224     referenced |= 1 << 0;
1225     referenced |= 1 << 1;
1226     cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
1227   }
1228   return cycles;
1229 #undef FLD
1230 }
1231
1232 static int
1233 model_m32r_d_machi (SIM_CPU *current_cpu, void *sem_arg)
1234 {
1235 #define FLD(f) abuf->fields.fmt_machi.f
1236   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1237   const IDESC * UNUSED idesc = abuf->idesc;
1238   int cycles = 0;
1239   {
1240     int referenced = 0;
1241     int UNUSED insn_referenced = abuf->written;
1242     INT src1 = -1;
1243     INT src2 = -1;
1244     src1 = FLD (in_src1);
1245     src2 = FLD (in_src2);
1246     referenced |= 1 << 0;
1247     referenced |= 1 << 1;
1248     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1249   }
1250   return cycles;
1251 #undef FLD
1252 }
1253
1254 static int
1255 model_m32r_d_maclo (SIM_CPU *current_cpu, void *sem_arg)
1256 {
1257 #define FLD(f) abuf->fields.fmt_machi.f
1258   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1259   const IDESC * UNUSED idesc = abuf->idesc;
1260   int cycles = 0;
1261   {
1262     int referenced = 0;
1263     int UNUSED insn_referenced = abuf->written;
1264     INT src1 = -1;
1265     INT src2 = -1;
1266     src1 = FLD (in_src1);
1267     src2 = FLD (in_src2);
1268     referenced |= 1 << 0;
1269     referenced |= 1 << 1;
1270     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1271   }
1272   return cycles;
1273 #undef FLD
1274 }
1275
1276 static int
1277 model_m32r_d_macwhi (SIM_CPU *current_cpu, void *sem_arg)
1278 {
1279 #define FLD(f) abuf->fields.fmt_machi.f
1280   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1281   const IDESC * UNUSED idesc = abuf->idesc;
1282   int cycles = 0;
1283   {
1284     int referenced = 0;
1285     int UNUSED insn_referenced = abuf->written;
1286     INT src1 = -1;
1287     INT src2 = -1;
1288     src1 = FLD (in_src1);
1289     src2 = FLD (in_src2);
1290     referenced |= 1 << 0;
1291     referenced |= 1 << 1;
1292     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1293   }
1294   return cycles;
1295 #undef FLD
1296 }
1297
1298 static int
1299 model_m32r_d_macwlo (SIM_CPU *current_cpu, void *sem_arg)
1300 {
1301 #define FLD(f) abuf->fields.fmt_machi.f
1302   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1303   const IDESC * UNUSED idesc = abuf->idesc;
1304   int cycles = 0;
1305   {
1306     int referenced = 0;
1307     int UNUSED insn_referenced = abuf->written;
1308     INT src1 = -1;
1309     INT src2 = -1;
1310     src1 = FLD (in_src1);
1311     src2 = FLD (in_src2);
1312     referenced |= 1 << 0;
1313     referenced |= 1 << 1;
1314     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1315   }
1316   return cycles;
1317 #undef FLD
1318 }
1319
1320 static int
1321 model_m32r_d_mul (SIM_CPU *current_cpu, void *sem_arg)
1322 {
1323 #define FLD(f) abuf->fields.fmt_add.f
1324   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1325   const IDESC * UNUSED idesc = abuf->idesc;
1326   int cycles = 0;
1327   {
1328     int referenced = 0;
1329     int UNUSED insn_referenced = abuf->written;
1330     INT sr = -1;
1331     INT sr2 = -1;
1332     INT dr = -1;
1333     sr = FLD (in_sr);
1334     dr = FLD (out_dr);
1335     referenced |= 1 << 0;
1336     referenced |= 1 << 2;
1337     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1338   }
1339   return cycles;
1340 #undef FLD
1341 }
1342
1343 static int
1344 model_m32r_d_mulhi (SIM_CPU *current_cpu, void *sem_arg)
1345 {
1346 #define FLD(f) abuf->fields.fmt_mulhi.f
1347   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1348   const IDESC * UNUSED idesc = abuf->idesc;
1349   int cycles = 0;
1350   {
1351     int referenced = 0;
1352     int UNUSED insn_referenced = abuf->written;
1353     INT src1 = -1;
1354     INT src2 = -1;
1355     src1 = FLD (in_src1);
1356     src2 = FLD (in_src2);
1357     referenced |= 1 << 0;
1358     referenced |= 1 << 1;
1359     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1360   }
1361   return cycles;
1362 #undef FLD
1363 }
1364
1365 static int
1366 model_m32r_d_mullo (SIM_CPU *current_cpu, void *sem_arg)
1367 {
1368 #define FLD(f) abuf->fields.fmt_mulhi.f
1369   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1370   const IDESC * UNUSED idesc = abuf->idesc;
1371   int cycles = 0;
1372   {
1373     int referenced = 0;
1374     int UNUSED insn_referenced = abuf->written;
1375     INT src1 = -1;
1376     INT src2 = -1;
1377     src1 = FLD (in_src1);
1378     src2 = FLD (in_src2);
1379     referenced |= 1 << 0;
1380     referenced |= 1 << 1;
1381     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1382   }
1383   return cycles;
1384 #undef FLD
1385 }
1386
1387 static int
1388 model_m32r_d_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
1389 {
1390 #define FLD(f) abuf->fields.fmt_mulhi.f
1391   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1392   const IDESC * UNUSED idesc = abuf->idesc;
1393   int cycles = 0;
1394   {
1395     int referenced = 0;
1396     int UNUSED insn_referenced = abuf->written;
1397     INT src1 = -1;
1398     INT src2 = -1;
1399     src1 = FLD (in_src1);
1400     src2 = FLD (in_src2);
1401     referenced |= 1 << 0;
1402     referenced |= 1 << 1;
1403     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1404   }
1405   return cycles;
1406 #undef FLD
1407 }
1408
1409 static int
1410 model_m32r_d_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
1411 {
1412 #define FLD(f) abuf->fields.fmt_mulhi.f
1413   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1414   const IDESC * UNUSED idesc = abuf->idesc;
1415   int cycles = 0;
1416   {
1417     int referenced = 0;
1418     int UNUSED insn_referenced = abuf->written;
1419     INT src1 = -1;
1420     INT src2 = -1;
1421     src1 = FLD (in_src1);
1422     src2 = FLD (in_src2);
1423     referenced |= 1 << 0;
1424     referenced |= 1 << 1;
1425     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1426   }
1427   return cycles;
1428 #undef FLD
1429 }
1430
1431 static int
1432 model_m32r_d_mv (SIM_CPU *current_cpu, void *sem_arg)
1433 {
1434 #define FLD(f) abuf->fields.fmt_mv.f
1435   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1436   const IDESC * UNUSED idesc = abuf->idesc;
1437   int cycles = 0;
1438   {
1439     int referenced = 0;
1440     int UNUSED insn_referenced = abuf->written;
1441     INT sr = -1;
1442     INT sr2 = -1;
1443     INT dr = -1;
1444     sr = FLD (in_sr);
1445     dr = FLD (out_dr);
1446     referenced |= 1 << 0;
1447     referenced |= 1 << 2;
1448     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1449   }
1450   return cycles;
1451 #undef FLD
1452 }
1453
1454 static int
1455 model_m32r_d_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
1456 {
1457 #define FLD(f) abuf->fields.fmt_mvfachi.f
1458   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1459   const IDESC * UNUSED idesc = abuf->idesc;
1460   int cycles = 0;
1461   {
1462     int referenced = 0;
1463     int UNUSED insn_referenced = abuf->written;
1464     INT sr = -1;
1465     INT sr2 = -1;
1466     INT dr = -1;
1467     dr = FLD (out_dr);
1468     referenced |= 1 << 2;
1469     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1470   }
1471   return cycles;
1472 #undef FLD
1473 }
1474
1475 static int
1476 model_m32r_d_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
1477 {
1478 #define FLD(f) abuf->fields.fmt_mvfachi.f
1479   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1480   const IDESC * UNUSED idesc = abuf->idesc;
1481   int cycles = 0;
1482   {
1483     int referenced = 0;
1484     int UNUSED insn_referenced = abuf->written;
1485     INT sr = -1;
1486     INT sr2 = -1;
1487     INT dr = -1;
1488     dr = FLD (out_dr);
1489     referenced |= 1 << 2;
1490     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1491   }
1492   return cycles;
1493 #undef FLD
1494 }
1495
1496 static int
1497 model_m32r_d_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
1498 {
1499 #define FLD(f) abuf->fields.fmt_mvfachi.f
1500   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1501   const IDESC * UNUSED idesc = abuf->idesc;
1502   int cycles = 0;
1503   {
1504     int referenced = 0;
1505     int UNUSED insn_referenced = abuf->written;
1506     INT sr = -1;
1507     INT sr2 = -1;
1508     INT dr = -1;
1509     dr = FLD (out_dr);
1510     referenced |= 1 << 2;
1511     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1512   }
1513   return cycles;
1514 #undef FLD
1515 }
1516
1517 static int
1518 model_m32r_d_mvfc (SIM_CPU *current_cpu, void *sem_arg)
1519 {
1520 #define FLD(f) abuf->fields.fmt_mvfc.f
1521   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1522   const IDESC * UNUSED idesc = abuf->idesc;
1523   int cycles = 0;
1524   {
1525     int referenced = 0;
1526     int UNUSED insn_referenced = abuf->written;
1527     INT sr = -1;
1528     INT sr2 = -1;
1529     INT dr = -1;
1530     dr = FLD (out_dr);
1531     referenced |= 1 << 2;
1532     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1533   }
1534   return cycles;
1535 #undef FLD
1536 }
1537
1538 static int
1539 model_m32r_d_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
1540 {
1541 #define FLD(f) abuf->fields.fmt_mvtachi.f
1542   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1543   const IDESC * UNUSED idesc = abuf->idesc;
1544   int cycles = 0;
1545   {
1546     int referenced = 0;
1547     int UNUSED insn_referenced = abuf->written;
1548     INT sr = -1;
1549     INT sr2 = -1;
1550     INT dr = -1;
1551     sr = FLD (in_src1);
1552     referenced |= 1 << 0;
1553     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1554   }
1555   return cycles;
1556 #undef FLD
1557 }
1558
1559 static int
1560 model_m32r_d_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
1561 {
1562 #define FLD(f) abuf->fields.fmt_mvtachi.f
1563   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1564   const IDESC * UNUSED idesc = abuf->idesc;
1565   int cycles = 0;
1566   {
1567     int referenced = 0;
1568     int UNUSED insn_referenced = abuf->written;
1569     INT sr = -1;
1570     INT sr2 = -1;
1571     INT dr = -1;
1572     sr = FLD (in_src1);
1573     referenced |= 1 << 0;
1574     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1575   }
1576   return cycles;
1577 #undef FLD
1578 }
1579
1580 static int
1581 model_m32r_d_mvtc (SIM_CPU *current_cpu, void *sem_arg)
1582 {
1583 #define FLD(f) abuf->fields.fmt_mvtc.f
1584   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1585   const IDESC * UNUSED idesc = abuf->idesc;
1586   int cycles = 0;
1587   {
1588     int referenced = 0;
1589     int UNUSED insn_referenced = abuf->written;
1590     INT sr = -1;
1591     INT sr2 = -1;
1592     INT dr = -1;
1593     sr = FLD (in_sr);
1594     referenced |= 1 << 0;
1595     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1596   }
1597   return cycles;
1598 #undef FLD
1599 }
1600
1601 static int
1602 model_m32r_d_neg (SIM_CPU *current_cpu, void *sem_arg)
1603 {
1604 #define FLD(f) abuf->fields.fmt_mv.f
1605   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1606   const IDESC * UNUSED idesc = abuf->idesc;
1607   int cycles = 0;
1608   {
1609     int referenced = 0;
1610     int UNUSED insn_referenced = abuf->written;
1611     INT sr = -1;
1612     INT sr2 = -1;
1613     INT dr = -1;
1614     sr = FLD (in_sr);
1615     dr = FLD (out_dr);
1616     referenced |= 1 << 0;
1617     referenced |= 1 << 2;
1618     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1619   }
1620   return cycles;
1621 #undef FLD
1622 }
1623
1624 static int
1625 model_m32r_d_nop (SIM_CPU *current_cpu, void *sem_arg)
1626 {
1627 #define FLD(f) abuf->fields.fmt_nop.f
1628   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1629   const IDESC * UNUSED idesc = abuf->idesc;
1630   int cycles = 0;
1631   {
1632     int referenced = 0;
1633     int UNUSED insn_referenced = abuf->written;
1634     INT sr = -1;
1635     INT sr2 = -1;
1636     INT dr = -1;
1637     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1638   }
1639   return cycles;
1640 #undef FLD
1641 }
1642
1643 static int
1644 model_m32r_d_not (SIM_CPU *current_cpu, void *sem_arg)
1645 {
1646 #define FLD(f) abuf->fields.fmt_mv.f
1647   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1648   const IDESC * UNUSED idesc = abuf->idesc;
1649   int cycles = 0;
1650   {
1651     int referenced = 0;
1652     int UNUSED insn_referenced = abuf->written;
1653     INT sr = -1;
1654     INT sr2 = -1;
1655     INT dr = -1;
1656     sr = FLD (in_sr);
1657     dr = FLD (out_dr);
1658     referenced |= 1 << 0;
1659     referenced |= 1 << 2;
1660     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1661   }
1662   return cycles;
1663 #undef FLD
1664 }
1665
1666 static int
1667 model_m32r_d_rac (SIM_CPU *current_cpu, void *sem_arg)
1668 {
1669 #define FLD(f) abuf->fields.fmt_rac.f
1670   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1671   const IDESC * UNUSED idesc = abuf->idesc;
1672   int cycles = 0;
1673   {
1674     int referenced = 0;
1675     int UNUSED insn_referenced = abuf->written;
1676     INT src1 = -1;
1677     INT src2 = -1;
1678     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1679   }
1680   return cycles;
1681 #undef FLD
1682 }
1683
1684 static int
1685 model_m32r_d_rach (SIM_CPU *current_cpu, void *sem_arg)
1686 {
1687 #define FLD(f) abuf->fields.fmt_rac.f
1688   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1689   const IDESC * UNUSED idesc = abuf->idesc;
1690   int cycles = 0;
1691   {
1692     int referenced = 0;
1693     int UNUSED insn_referenced = abuf->written;
1694     INT src1 = -1;
1695     INT src2 = -1;
1696     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
1697   }
1698   return cycles;
1699 #undef FLD
1700 }
1701
1702 static int
1703 model_m32r_d_rte (SIM_CPU *current_cpu, void *sem_arg)
1704 {
1705 #define FLD(f) abuf->fields.cti.fields.fmt_rte.f
1706   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1707   const IDESC * UNUSED idesc = abuf->idesc;
1708   int cycles = 0;
1709   {
1710     int referenced = 0;
1711     int UNUSED insn_referenced = abuf->written;
1712     INT sr = -1;
1713     INT sr2 = -1;
1714     INT dr = -1;
1715     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1716   }
1717   return cycles;
1718 #undef FLD
1719 }
1720
1721 static int
1722 model_m32r_d_seth (SIM_CPU *current_cpu, void *sem_arg)
1723 {
1724 #define FLD(f) abuf->fields.fmt_seth.f
1725   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1726   const IDESC * UNUSED idesc = abuf->idesc;
1727   int cycles = 0;
1728   {
1729     int referenced = 0;
1730     int UNUSED insn_referenced = abuf->written;
1731     INT sr = -1;
1732     INT sr2 = -1;
1733     INT dr = -1;
1734     dr = FLD (out_dr);
1735     referenced |= 1 << 2;
1736     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1737   }
1738   return cycles;
1739 #undef FLD
1740 }
1741
1742 static int
1743 model_m32r_d_sll (SIM_CPU *current_cpu, void *sem_arg)
1744 {
1745 #define FLD(f) abuf->fields.fmt_add.f
1746   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1747   const IDESC * UNUSED idesc = abuf->idesc;
1748   int cycles = 0;
1749   {
1750     int referenced = 0;
1751     int UNUSED insn_referenced = abuf->written;
1752     INT sr = -1;
1753     INT sr2 = -1;
1754     INT dr = -1;
1755     sr = FLD (in_sr);
1756     dr = FLD (out_dr);
1757     referenced |= 1 << 0;
1758     referenced |= 1 << 2;
1759     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1760   }
1761   return cycles;
1762 #undef FLD
1763 }
1764
1765 static int
1766 model_m32r_d_sll3 (SIM_CPU *current_cpu, void *sem_arg)
1767 {
1768 #define FLD(f) abuf->fields.fmt_sll3.f
1769   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1770   const IDESC * UNUSED idesc = abuf->idesc;
1771   int cycles = 0;
1772   {
1773     int referenced = 0;
1774     int UNUSED insn_referenced = abuf->written;
1775     INT sr = -1;
1776     INT sr2 = -1;
1777     INT dr = -1;
1778     sr = FLD (in_sr);
1779     dr = FLD (out_dr);
1780     referenced |= 1 << 0;
1781     referenced |= 1 << 2;
1782     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1783   }
1784   return cycles;
1785 #undef FLD
1786 }
1787
1788 static int
1789 model_m32r_d_slli (SIM_CPU *current_cpu, void *sem_arg)
1790 {
1791 #define FLD(f) abuf->fields.fmt_slli.f
1792   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1793   const IDESC * UNUSED idesc = abuf->idesc;
1794   int cycles = 0;
1795   {
1796     int referenced = 0;
1797     int UNUSED insn_referenced = abuf->written;
1798     INT sr = -1;
1799     INT sr2 = -1;
1800     INT dr = -1;
1801     dr = FLD (out_dr);
1802     referenced |= 1 << 2;
1803     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1804   }
1805   return cycles;
1806 #undef FLD
1807 }
1808
1809 static int
1810 model_m32r_d_sra (SIM_CPU *current_cpu, void *sem_arg)
1811 {
1812 #define FLD(f) abuf->fields.fmt_add.f
1813   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1814   const IDESC * UNUSED idesc = abuf->idesc;
1815   int cycles = 0;
1816   {
1817     int referenced = 0;
1818     int UNUSED insn_referenced = abuf->written;
1819     INT sr = -1;
1820     INT sr2 = -1;
1821     INT dr = -1;
1822     sr = FLD (in_sr);
1823     dr = FLD (out_dr);
1824     referenced |= 1 << 0;
1825     referenced |= 1 << 2;
1826     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1827   }
1828   return cycles;
1829 #undef FLD
1830 }
1831
1832 static int
1833 model_m32r_d_sra3 (SIM_CPU *current_cpu, void *sem_arg)
1834 {
1835 #define FLD(f) abuf->fields.fmt_sll3.f
1836   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1837   const IDESC * UNUSED idesc = abuf->idesc;
1838   int cycles = 0;
1839   {
1840     int referenced = 0;
1841     int UNUSED insn_referenced = abuf->written;
1842     INT sr = -1;
1843     INT sr2 = -1;
1844     INT dr = -1;
1845     sr = FLD (in_sr);
1846     dr = FLD (out_dr);
1847     referenced |= 1 << 0;
1848     referenced |= 1 << 2;
1849     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1850   }
1851   return cycles;
1852 #undef FLD
1853 }
1854
1855 static int
1856 model_m32r_d_srai (SIM_CPU *current_cpu, void *sem_arg)
1857 {
1858 #define FLD(f) abuf->fields.fmt_slli.f
1859   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1860   const IDESC * UNUSED idesc = abuf->idesc;
1861   int cycles = 0;
1862   {
1863     int referenced = 0;
1864     int UNUSED insn_referenced = abuf->written;
1865     INT sr = -1;
1866     INT sr2 = -1;
1867     INT dr = -1;
1868     dr = FLD (out_dr);
1869     referenced |= 1 << 2;
1870     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1871   }
1872   return cycles;
1873 #undef FLD
1874 }
1875
1876 static int
1877 model_m32r_d_srl (SIM_CPU *current_cpu, void *sem_arg)
1878 {
1879 #define FLD(f) abuf->fields.fmt_add.f
1880   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1881   const IDESC * UNUSED idesc = abuf->idesc;
1882   int cycles = 0;
1883   {
1884     int referenced = 0;
1885     int UNUSED insn_referenced = abuf->written;
1886     INT sr = -1;
1887     INT sr2 = -1;
1888     INT dr = -1;
1889     sr = FLD (in_sr);
1890     dr = FLD (out_dr);
1891     referenced |= 1 << 0;
1892     referenced |= 1 << 2;
1893     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1894   }
1895   return cycles;
1896 #undef FLD
1897 }
1898
1899 static int
1900 model_m32r_d_srl3 (SIM_CPU *current_cpu, void *sem_arg)
1901 {
1902 #define FLD(f) abuf->fields.fmt_sll3.f
1903   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1904   const IDESC * UNUSED idesc = abuf->idesc;
1905   int cycles = 0;
1906   {
1907     int referenced = 0;
1908     int UNUSED insn_referenced = abuf->written;
1909     INT sr = -1;
1910     INT sr2 = -1;
1911     INT dr = -1;
1912     sr = FLD (in_sr);
1913     dr = FLD (out_dr);
1914     referenced |= 1 << 0;
1915     referenced |= 1 << 2;
1916     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1917   }
1918   return cycles;
1919 #undef FLD
1920 }
1921
1922 static int
1923 model_m32r_d_srli (SIM_CPU *current_cpu, void *sem_arg)
1924 {
1925 #define FLD(f) abuf->fields.fmt_slli.f
1926   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1927   const IDESC * UNUSED idesc = abuf->idesc;
1928   int cycles = 0;
1929   {
1930     int referenced = 0;
1931     int UNUSED insn_referenced = abuf->written;
1932     INT sr = -1;
1933     INT sr2 = -1;
1934     INT dr = -1;
1935     dr = FLD (out_dr);
1936     referenced |= 1 << 2;
1937     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
1938   }
1939   return cycles;
1940 #undef FLD
1941 }
1942
1943 static int
1944 model_m32r_d_st (SIM_CPU *current_cpu, void *sem_arg)
1945 {
1946 #define FLD(f) abuf->fields.fmt_st.f
1947   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1948   const IDESC * UNUSED idesc = abuf->idesc;
1949   int cycles = 0;
1950   {
1951     int referenced = 0;
1952     int UNUSED insn_referenced = abuf->written;
1953     INT src1 = 0;
1954     INT src2 = 0;
1955     src1 = FLD (in_src1);
1956     src2 = FLD (in_src2);
1957     referenced |= 1 << 0;
1958     referenced |= 1 << 1;
1959     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
1960   }
1961   return cycles;
1962 #undef FLD
1963 }
1964
1965 static int
1966 model_m32r_d_st_d (SIM_CPU *current_cpu, void *sem_arg)
1967 {
1968 #define FLD(f) abuf->fields.fmt_st_d.f
1969   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1970   const IDESC * UNUSED idesc = abuf->idesc;
1971   int cycles = 0;
1972   {
1973     int referenced = 0;
1974     int UNUSED insn_referenced = abuf->written;
1975     INT src1 = 0;
1976     INT src2 = 0;
1977     src1 = FLD (in_src1);
1978     src2 = FLD (in_src2);
1979     referenced |= 1 << 0;
1980     referenced |= 1 << 1;
1981     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
1982   }
1983   return cycles;
1984 #undef FLD
1985 }
1986
1987 static int
1988 model_m32r_d_stb (SIM_CPU *current_cpu, void *sem_arg)
1989 {
1990 #define FLD(f) abuf->fields.fmt_stb.f
1991   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1992   const IDESC * UNUSED idesc = abuf->idesc;
1993   int cycles = 0;
1994   {
1995     int referenced = 0;
1996     int UNUSED insn_referenced = abuf->written;
1997     INT src1 = 0;
1998     INT src2 = 0;
1999     src1 = FLD (in_src1);
2000     src2 = FLD (in_src2);
2001     referenced |= 1 << 0;
2002     referenced |= 1 << 1;
2003     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
2004   }
2005   return cycles;
2006 #undef FLD
2007 }
2008
2009 static int
2010 model_m32r_d_stb_d (SIM_CPU *current_cpu, void *sem_arg)
2011 {
2012 #define FLD(f) abuf->fields.fmt_stb_d.f
2013   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2014   const IDESC * UNUSED idesc = abuf->idesc;
2015   int cycles = 0;
2016   {
2017     int referenced = 0;
2018     int UNUSED insn_referenced = abuf->written;
2019     INT src1 = 0;
2020     INT src2 = 0;
2021     src1 = FLD (in_src1);
2022     src2 = FLD (in_src2);
2023     referenced |= 1 << 0;
2024     referenced |= 1 << 1;
2025     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
2026   }
2027   return cycles;
2028 #undef FLD
2029 }
2030
2031 static int
2032 model_m32r_d_sth (SIM_CPU *current_cpu, void *sem_arg)
2033 {
2034 #define FLD(f) abuf->fields.fmt_sth.f
2035   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2036   const IDESC * UNUSED idesc = abuf->idesc;
2037   int cycles = 0;
2038   {
2039     int referenced = 0;
2040     int UNUSED insn_referenced = abuf->written;
2041     INT src1 = 0;
2042     INT src2 = 0;
2043     src1 = FLD (in_src1);
2044     src2 = FLD (in_src2);
2045     referenced |= 1 << 0;
2046     referenced |= 1 << 1;
2047     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
2048   }
2049   return cycles;
2050 #undef FLD
2051 }
2052
2053 static int
2054 model_m32r_d_sth_d (SIM_CPU *current_cpu, void *sem_arg)
2055 {
2056 #define FLD(f) abuf->fields.fmt_sth_d.f
2057   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2058   const IDESC * UNUSED idesc = abuf->idesc;
2059   int cycles = 0;
2060   {
2061     int referenced = 0;
2062     int UNUSED insn_referenced = abuf->written;
2063     INT src1 = 0;
2064     INT src2 = 0;
2065     src1 = FLD (in_src1);
2066     src2 = FLD (in_src2);
2067     referenced |= 1 << 0;
2068     referenced |= 1 << 1;
2069     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
2070   }
2071   return cycles;
2072 #undef FLD
2073 }
2074
2075 static int
2076 model_m32r_d_st_plus (SIM_CPU *current_cpu, void *sem_arg)
2077 {
2078 #define FLD(f) abuf->fields.fmt_st_plus.f
2079   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2080   const IDESC * UNUSED idesc = abuf->idesc;
2081   int cycles = 0;
2082   {
2083     int referenced = 0;
2084     int UNUSED insn_referenced = abuf->written;
2085     INT src1 = 0;
2086     INT src2 = 0;
2087     src1 = FLD (in_src1);
2088     src2 = FLD (in_src2);
2089     referenced |= 1 << 0;
2090     referenced |= 1 << 1;
2091     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
2092   }
2093   {
2094     int referenced = 0;
2095     int UNUSED insn_referenced = abuf->written;
2096     INT sr = -1;
2097     INT sr2 = -1;
2098     INT dr = -1;
2099     dr = FLD (out_src2);
2100     sr = FLD (in_src2);
2101     referenced |= 1 << 0;
2102     referenced |= 1 << 2;
2103     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, sr, sr2, dr);
2104   }
2105   return cycles;
2106 #undef FLD
2107 }
2108
2109 static int
2110 model_m32r_d_st_minus (SIM_CPU *current_cpu, void *sem_arg)
2111 {
2112 #define FLD(f) abuf->fields.fmt_st_plus.f
2113   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2114   const IDESC * UNUSED idesc = abuf->idesc;
2115   int cycles = 0;
2116   {
2117     int referenced = 0;
2118     int UNUSED insn_referenced = abuf->written;
2119     INT src1 = 0;
2120     INT src2 = 0;
2121     src1 = FLD (in_src1);
2122     src2 = FLD (in_src2);
2123     referenced |= 1 << 0;
2124     referenced |= 1 << 1;
2125     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
2126   }
2127   {
2128     int referenced = 0;
2129     int UNUSED insn_referenced = abuf->written;
2130     INT sr = -1;
2131     INT sr2 = -1;
2132     INT dr = -1;
2133     dr = FLD (out_src2);
2134     sr = FLD (in_src2);
2135     referenced |= 1 << 0;
2136     referenced |= 1 << 2;
2137     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, sr, sr2, dr);
2138   }
2139   return cycles;
2140 #undef FLD
2141 }
2142
2143 static int
2144 model_m32r_d_sub (SIM_CPU *current_cpu, void *sem_arg)
2145 {
2146 #define FLD(f) abuf->fields.fmt_add.f
2147   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2148   const IDESC * UNUSED idesc = abuf->idesc;
2149   int cycles = 0;
2150   {
2151     int referenced = 0;
2152     int UNUSED insn_referenced = abuf->written;
2153     INT sr = -1;
2154     INT sr2 = -1;
2155     INT dr = -1;
2156     sr = FLD (in_sr);
2157     dr = FLD (out_dr);
2158     referenced |= 1 << 0;
2159     referenced |= 1 << 2;
2160     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2161   }
2162   return cycles;
2163 #undef FLD
2164 }
2165
2166 static int
2167 model_m32r_d_subv (SIM_CPU *current_cpu, void *sem_arg)
2168 {
2169 #define FLD(f) abuf->fields.fmt_addv.f
2170   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2171   const IDESC * UNUSED idesc = abuf->idesc;
2172   int cycles = 0;
2173   {
2174     int referenced = 0;
2175     int UNUSED insn_referenced = abuf->written;
2176     INT sr = -1;
2177     INT sr2 = -1;
2178     INT dr = -1;
2179     sr = FLD (in_sr);
2180     dr = FLD (out_dr);
2181     referenced |= 1 << 0;
2182     referenced |= 1 << 2;
2183     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2184   }
2185   return cycles;
2186 #undef FLD
2187 }
2188
2189 static int
2190 model_m32r_d_subx (SIM_CPU *current_cpu, void *sem_arg)
2191 {
2192 #define FLD(f) abuf->fields.fmt_addx.f
2193   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2194   const IDESC * UNUSED idesc = abuf->idesc;
2195   int cycles = 0;
2196   {
2197     int referenced = 0;
2198     int UNUSED insn_referenced = abuf->written;
2199     INT sr = -1;
2200     INT sr2 = -1;
2201     INT dr = -1;
2202     sr = FLD (in_sr);
2203     dr = FLD (out_dr);
2204     referenced |= 1 << 0;
2205     referenced |= 1 << 2;
2206     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2207   }
2208   return cycles;
2209 #undef FLD
2210 }
2211
2212 static int
2213 model_m32r_d_trap (SIM_CPU *current_cpu, void *sem_arg)
2214 {
2215 #define FLD(f) abuf->fields.cti.fields.fmt_trap.f
2216   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2217   const IDESC * UNUSED idesc = abuf->idesc;
2218   int cycles = 0;
2219   {
2220     int referenced = 0;
2221     int UNUSED insn_referenced = abuf->written;
2222     INT sr = -1;
2223     INT sr2 = -1;
2224     INT dr = -1;
2225     cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
2226   }
2227   return cycles;
2228 #undef FLD
2229 }
2230
2231 static int
2232 model_m32r_d_unlock (SIM_CPU *current_cpu, void *sem_arg)
2233 {
2234 #define FLD(f) abuf->fields.fmt_unlock.f
2235   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2236   const IDESC * UNUSED idesc = abuf->idesc;
2237   int cycles = 0;
2238   {
2239     int referenced = 0;
2240     int UNUSED insn_referenced = abuf->written;
2241     INT sr = 0;
2242     INT dr = 0;
2243     cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
2244   }
2245   return cycles;
2246 #undef FLD
2247 }
2248
2249 static int
2250 model_test_add (SIM_CPU *current_cpu, void *sem_arg)
2251 {
2252 #define FLD(f) abuf->fields.fmt_add.f
2253   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2254   const IDESC * UNUSED idesc = abuf->idesc;
2255   int cycles = 0;
2256   {
2257     int referenced = 0;
2258     int UNUSED insn_referenced = abuf->written;
2259     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2260   }
2261   return cycles;
2262 #undef FLD
2263 }
2264
2265 static int
2266 model_test_add3 (SIM_CPU *current_cpu, void *sem_arg)
2267 {
2268 #define FLD(f) abuf->fields.fmt_add3.f
2269   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2270   const IDESC * UNUSED idesc = abuf->idesc;
2271   int cycles = 0;
2272   {
2273     int referenced = 0;
2274     int UNUSED insn_referenced = abuf->written;
2275     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2276   }
2277   return cycles;
2278 #undef FLD
2279 }
2280
2281 static int
2282 model_test_and (SIM_CPU *current_cpu, void *sem_arg)
2283 {
2284 #define FLD(f) abuf->fields.fmt_add.f
2285   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2286   const IDESC * UNUSED idesc = abuf->idesc;
2287   int cycles = 0;
2288   {
2289     int referenced = 0;
2290     int UNUSED insn_referenced = abuf->written;
2291     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2292   }
2293   return cycles;
2294 #undef FLD
2295 }
2296
2297 static int
2298 model_test_and3 (SIM_CPU *current_cpu, void *sem_arg)
2299 {
2300 #define FLD(f) abuf->fields.fmt_and3.f
2301   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2302   const IDESC * UNUSED idesc = abuf->idesc;
2303   int cycles = 0;
2304   {
2305     int referenced = 0;
2306     int UNUSED insn_referenced = abuf->written;
2307     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2308   }
2309   return cycles;
2310 #undef FLD
2311 }
2312
2313 static int
2314 model_test_or (SIM_CPU *current_cpu, void *sem_arg)
2315 {
2316 #define FLD(f) abuf->fields.fmt_add.f
2317   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2318   const IDESC * UNUSED idesc = abuf->idesc;
2319   int cycles = 0;
2320   {
2321     int referenced = 0;
2322     int UNUSED insn_referenced = abuf->written;
2323     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2324   }
2325   return cycles;
2326 #undef FLD
2327 }
2328
2329 static int
2330 model_test_or3 (SIM_CPU *current_cpu, void *sem_arg)
2331 {
2332 #define FLD(f) abuf->fields.fmt_or3.f
2333   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2334   const IDESC * UNUSED idesc = abuf->idesc;
2335   int cycles = 0;
2336   {
2337     int referenced = 0;
2338     int UNUSED insn_referenced = abuf->written;
2339     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2340   }
2341   return cycles;
2342 #undef FLD
2343 }
2344
2345 static int
2346 model_test_xor (SIM_CPU *current_cpu, void *sem_arg)
2347 {
2348 #define FLD(f) abuf->fields.fmt_add.f
2349   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2350   const IDESC * UNUSED idesc = abuf->idesc;
2351   int cycles = 0;
2352   {
2353     int referenced = 0;
2354     int UNUSED insn_referenced = abuf->written;
2355     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2356   }
2357   return cycles;
2358 #undef FLD
2359 }
2360
2361 static int
2362 model_test_xor3 (SIM_CPU *current_cpu, void *sem_arg)
2363 {
2364 #define FLD(f) abuf->fields.fmt_and3.f
2365   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2366   const IDESC * UNUSED idesc = abuf->idesc;
2367   int cycles = 0;
2368   {
2369     int referenced = 0;
2370     int UNUSED insn_referenced = abuf->written;
2371     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2372   }
2373   return cycles;
2374 #undef FLD
2375 }
2376
2377 static int
2378 model_test_addi (SIM_CPU *current_cpu, void *sem_arg)
2379 {
2380 #define FLD(f) abuf->fields.fmt_addi.f
2381   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2382   const IDESC * UNUSED idesc = abuf->idesc;
2383   int cycles = 0;
2384   {
2385     int referenced = 0;
2386     int UNUSED insn_referenced = abuf->written;
2387     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2388   }
2389   return cycles;
2390 #undef FLD
2391 }
2392
2393 static int
2394 model_test_addv (SIM_CPU *current_cpu, void *sem_arg)
2395 {
2396 #define FLD(f) abuf->fields.fmt_addv.f
2397   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2398   const IDESC * UNUSED idesc = abuf->idesc;
2399   int cycles = 0;
2400   {
2401     int referenced = 0;
2402     int UNUSED insn_referenced = abuf->written;
2403     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2404   }
2405   return cycles;
2406 #undef FLD
2407 }
2408
2409 static int
2410 model_test_addv3 (SIM_CPU *current_cpu, void *sem_arg)
2411 {
2412 #define FLD(f) abuf->fields.fmt_addv3.f
2413   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2414   const IDESC * UNUSED idesc = abuf->idesc;
2415   int cycles = 0;
2416   {
2417     int referenced = 0;
2418     int UNUSED insn_referenced = abuf->written;
2419     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2420   }
2421   return cycles;
2422 #undef FLD
2423 }
2424
2425 static int
2426 model_test_addx (SIM_CPU *current_cpu, void *sem_arg)
2427 {
2428 #define FLD(f) abuf->fields.fmt_addx.f
2429   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2430   const IDESC * UNUSED idesc = abuf->idesc;
2431   int cycles = 0;
2432   {
2433     int referenced = 0;
2434     int UNUSED insn_referenced = abuf->written;
2435     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2436   }
2437   return cycles;
2438 #undef FLD
2439 }
2440
2441 static int
2442 model_test_bc8 (SIM_CPU *current_cpu, void *sem_arg)
2443 {
2444 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
2445   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2446   const IDESC * UNUSED idesc = abuf->idesc;
2447   int cycles = 0;
2448   {
2449     int referenced = 0;
2450     int UNUSED insn_referenced = abuf->written;
2451     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2452   }
2453   return cycles;
2454 #undef FLD
2455 }
2456
2457 static int
2458 model_test_bc24 (SIM_CPU *current_cpu, void *sem_arg)
2459 {
2460 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
2461   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2462   const IDESC * UNUSED idesc = abuf->idesc;
2463   int cycles = 0;
2464   {
2465     int referenced = 0;
2466     int UNUSED insn_referenced = abuf->written;
2467     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2468   }
2469   return cycles;
2470 #undef FLD
2471 }
2472
2473 static int
2474 model_test_beq (SIM_CPU *current_cpu, void *sem_arg)
2475 {
2476 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
2477   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2478   const IDESC * UNUSED idesc = abuf->idesc;
2479   int cycles = 0;
2480   {
2481     int referenced = 0;
2482     int UNUSED insn_referenced = abuf->written;
2483     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2484   }
2485   return cycles;
2486 #undef FLD
2487 }
2488
2489 static int
2490 model_test_beqz (SIM_CPU *current_cpu, void *sem_arg)
2491 {
2492 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
2493   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2494   const IDESC * UNUSED idesc = abuf->idesc;
2495   int cycles = 0;
2496   {
2497     int referenced = 0;
2498     int UNUSED insn_referenced = abuf->written;
2499     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2500   }
2501   return cycles;
2502 #undef FLD
2503 }
2504
2505 static int
2506 model_test_bgez (SIM_CPU *current_cpu, void *sem_arg)
2507 {
2508 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
2509   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2510   const IDESC * UNUSED idesc = abuf->idesc;
2511   int cycles = 0;
2512   {
2513     int referenced = 0;
2514     int UNUSED insn_referenced = abuf->written;
2515     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2516   }
2517   return cycles;
2518 #undef FLD
2519 }
2520
2521 static int
2522 model_test_bgtz (SIM_CPU *current_cpu, void *sem_arg)
2523 {
2524 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
2525   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2526   const IDESC * UNUSED idesc = abuf->idesc;
2527   int cycles = 0;
2528   {
2529     int referenced = 0;
2530     int UNUSED insn_referenced = abuf->written;
2531     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2532   }
2533   return cycles;
2534 #undef FLD
2535 }
2536
2537 static int
2538 model_test_blez (SIM_CPU *current_cpu, void *sem_arg)
2539 {
2540 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
2541   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2542   const IDESC * UNUSED idesc = abuf->idesc;
2543   int cycles = 0;
2544   {
2545     int referenced = 0;
2546     int UNUSED insn_referenced = abuf->written;
2547     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2548   }
2549   return cycles;
2550 #undef FLD
2551 }
2552
2553 static int
2554 model_test_bltz (SIM_CPU *current_cpu, void *sem_arg)
2555 {
2556 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
2557   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2558   const IDESC * UNUSED idesc = abuf->idesc;
2559   int cycles = 0;
2560   {
2561     int referenced = 0;
2562     int UNUSED insn_referenced = abuf->written;
2563     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2564   }
2565   return cycles;
2566 #undef FLD
2567 }
2568
2569 static int
2570 model_test_bnez (SIM_CPU *current_cpu, void *sem_arg)
2571 {
2572 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
2573   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2574   const IDESC * UNUSED idesc = abuf->idesc;
2575   int cycles = 0;
2576   {
2577     int referenced = 0;
2578     int UNUSED insn_referenced = abuf->written;
2579     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2580   }
2581   return cycles;
2582 #undef FLD
2583 }
2584
2585 static int
2586 model_test_bl8 (SIM_CPU *current_cpu, void *sem_arg)
2587 {
2588 #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
2589   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2590   const IDESC * UNUSED idesc = abuf->idesc;
2591   int cycles = 0;
2592   {
2593     int referenced = 0;
2594     int UNUSED insn_referenced = abuf->written;
2595     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2596   }
2597   return cycles;
2598 #undef FLD
2599 }
2600
2601 static int
2602 model_test_bl24 (SIM_CPU *current_cpu, void *sem_arg)
2603 {
2604 #define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
2605   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2606   const IDESC * UNUSED idesc = abuf->idesc;
2607   int cycles = 0;
2608   {
2609     int referenced = 0;
2610     int UNUSED insn_referenced = abuf->written;
2611     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2612   }
2613   return cycles;
2614 #undef FLD
2615 }
2616
2617 static int
2618 model_test_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
2619 {
2620 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
2621   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2622   const IDESC * UNUSED idesc = abuf->idesc;
2623   int cycles = 0;
2624   {
2625     int referenced = 0;
2626     int UNUSED insn_referenced = abuf->written;
2627     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2628   }
2629   return cycles;
2630 #undef FLD
2631 }
2632
2633 static int
2634 model_test_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
2635 {
2636 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
2637   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2638   const IDESC * UNUSED idesc = abuf->idesc;
2639   int cycles = 0;
2640   {
2641     int referenced = 0;
2642     int UNUSED insn_referenced = abuf->written;
2643     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2644   }
2645   return cycles;
2646 #undef FLD
2647 }
2648
2649 static int
2650 model_test_bne (SIM_CPU *current_cpu, void *sem_arg)
2651 {
2652 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
2653   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2654   const IDESC * UNUSED idesc = abuf->idesc;
2655   int cycles = 0;
2656   {
2657     int referenced = 0;
2658     int UNUSED insn_referenced = abuf->written;
2659     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2660   }
2661   return cycles;
2662 #undef FLD
2663 }
2664
2665 static int
2666 model_test_bra8 (SIM_CPU *current_cpu, void *sem_arg)
2667 {
2668 #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
2669   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2670   const IDESC * UNUSED idesc = abuf->idesc;
2671   int cycles = 0;
2672   {
2673     int referenced = 0;
2674     int UNUSED insn_referenced = abuf->written;
2675     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2676   }
2677   return cycles;
2678 #undef FLD
2679 }
2680
2681 static int
2682 model_test_bra24 (SIM_CPU *current_cpu, void *sem_arg)
2683 {
2684 #define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
2685   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2686   const IDESC * UNUSED idesc = abuf->idesc;
2687   int cycles = 0;
2688   {
2689     int referenced = 0;
2690     int UNUSED insn_referenced = abuf->written;
2691     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2692   }
2693   return cycles;
2694 #undef FLD
2695 }
2696
2697 static int
2698 model_test_cmp (SIM_CPU *current_cpu, void *sem_arg)
2699 {
2700 #define FLD(f) abuf->fields.fmt_cmp.f
2701   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2702   const IDESC * UNUSED idesc = abuf->idesc;
2703   int cycles = 0;
2704   {
2705     int referenced = 0;
2706     int UNUSED insn_referenced = abuf->written;
2707     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2708   }
2709   return cycles;
2710 #undef FLD
2711 }
2712
2713 static int
2714 model_test_cmpi (SIM_CPU *current_cpu, void *sem_arg)
2715 {
2716 #define FLD(f) abuf->fields.fmt_cmpi.f
2717   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2718   const IDESC * UNUSED idesc = abuf->idesc;
2719   int cycles = 0;
2720   {
2721     int referenced = 0;
2722     int UNUSED insn_referenced = abuf->written;
2723     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2724   }
2725   return cycles;
2726 #undef FLD
2727 }
2728
2729 static int
2730 model_test_cmpu (SIM_CPU *current_cpu, void *sem_arg)
2731 {
2732 #define FLD(f) abuf->fields.fmt_cmp.f
2733   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2734   const IDESC * UNUSED idesc = abuf->idesc;
2735   int cycles = 0;
2736   {
2737     int referenced = 0;
2738     int UNUSED insn_referenced = abuf->written;
2739     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2740   }
2741   return cycles;
2742 #undef FLD
2743 }
2744
2745 static int
2746 model_test_cmpui (SIM_CPU *current_cpu, void *sem_arg)
2747 {
2748 #define FLD(f) abuf->fields.fmt_cmpi.f
2749   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2750   const IDESC * UNUSED idesc = abuf->idesc;
2751   int cycles = 0;
2752   {
2753     int referenced = 0;
2754     int UNUSED insn_referenced = abuf->written;
2755     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2756   }
2757   return cycles;
2758 #undef FLD
2759 }
2760
2761 static int
2762 model_test_div (SIM_CPU *current_cpu, void *sem_arg)
2763 {
2764 #define FLD(f) abuf->fields.fmt_div.f
2765   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2766   const IDESC * UNUSED idesc = abuf->idesc;
2767   int cycles = 0;
2768   {
2769     int referenced = 0;
2770     int UNUSED insn_referenced = abuf->written;
2771     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2772   }
2773   return cycles;
2774 #undef FLD
2775 }
2776
2777 static int
2778 model_test_divu (SIM_CPU *current_cpu, void *sem_arg)
2779 {
2780 #define FLD(f) abuf->fields.fmt_div.f
2781   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2782   const IDESC * UNUSED idesc = abuf->idesc;
2783   int cycles = 0;
2784   {
2785     int referenced = 0;
2786     int UNUSED insn_referenced = abuf->written;
2787     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2788   }
2789   return cycles;
2790 #undef FLD
2791 }
2792
2793 static int
2794 model_test_rem (SIM_CPU *current_cpu, void *sem_arg)
2795 {
2796 #define FLD(f) abuf->fields.fmt_div.f
2797   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2798   const IDESC * UNUSED idesc = abuf->idesc;
2799   int cycles = 0;
2800   {
2801     int referenced = 0;
2802     int UNUSED insn_referenced = abuf->written;
2803     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2804   }
2805   return cycles;
2806 #undef FLD
2807 }
2808
2809 static int
2810 model_test_remu (SIM_CPU *current_cpu, void *sem_arg)
2811 {
2812 #define FLD(f) abuf->fields.fmt_div.f
2813   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2814   const IDESC * UNUSED idesc = abuf->idesc;
2815   int cycles = 0;
2816   {
2817     int referenced = 0;
2818     int UNUSED insn_referenced = abuf->written;
2819     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2820   }
2821   return cycles;
2822 #undef FLD
2823 }
2824
2825 static int
2826 model_test_jl (SIM_CPU *current_cpu, void *sem_arg)
2827 {
2828 #define FLD(f) abuf->fields.cti.fields.fmt_jl.f
2829   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2830   const IDESC * UNUSED idesc = abuf->idesc;
2831   int cycles = 0;
2832   {
2833     int referenced = 0;
2834     int UNUSED insn_referenced = abuf->written;
2835     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2836   }
2837   return cycles;
2838 #undef FLD
2839 }
2840
2841 static int
2842 model_test_jmp (SIM_CPU *current_cpu, void *sem_arg)
2843 {
2844 #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
2845   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2846   const IDESC * UNUSED idesc = abuf->idesc;
2847   int cycles = 0;
2848   {
2849     int referenced = 0;
2850     int UNUSED insn_referenced = abuf->written;
2851     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2852   }
2853   return cycles;
2854 #undef FLD
2855 }
2856
2857 static int
2858 model_test_ld (SIM_CPU *current_cpu, void *sem_arg)
2859 {
2860 #define FLD(f) abuf->fields.fmt_ld.f
2861   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2862   const IDESC * UNUSED idesc = abuf->idesc;
2863   int cycles = 0;
2864   {
2865     int referenced = 0;
2866     int UNUSED insn_referenced = abuf->written;
2867     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2868   }
2869   return cycles;
2870 #undef FLD
2871 }
2872
2873 static int
2874 model_test_ld_d (SIM_CPU *current_cpu, void *sem_arg)
2875 {
2876 #define FLD(f) abuf->fields.fmt_ld_d.f
2877   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2878   const IDESC * UNUSED idesc = abuf->idesc;
2879   int cycles = 0;
2880   {
2881     int referenced = 0;
2882     int UNUSED insn_referenced = abuf->written;
2883     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2884   }
2885   return cycles;
2886 #undef FLD
2887 }
2888
2889 static int
2890 model_test_ldb (SIM_CPU *current_cpu, void *sem_arg)
2891 {
2892 #define FLD(f) abuf->fields.fmt_ldb.f
2893   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2894   const IDESC * UNUSED idesc = abuf->idesc;
2895   int cycles = 0;
2896   {
2897     int referenced = 0;
2898     int UNUSED insn_referenced = abuf->written;
2899     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2900   }
2901   return cycles;
2902 #undef FLD
2903 }
2904
2905 static int
2906 model_test_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
2907 {
2908 #define FLD(f) abuf->fields.fmt_ldb_d.f
2909   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2910   const IDESC * UNUSED idesc = abuf->idesc;
2911   int cycles = 0;
2912   {
2913     int referenced = 0;
2914     int UNUSED insn_referenced = abuf->written;
2915     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2916   }
2917   return cycles;
2918 #undef FLD
2919 }
2920
2921 static int
2922 model_test_ldh (SIM_CPU *current_cpu, void *sem_arg)
2923 {
2924 #define FLD(f) abuf->fields.fmt_ldh.f
2925   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2926   const IDESC * UNUSED idesc = abuf->idesc;
2927   int cycles = 0;
2928   {
2929     int referenced = 0;
2930     int UNUSED insn_referenced = abuf->written;
2931     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2932   }
2933   return cycles;
2934 #undef FLD
2935 }
2936
2937 static int
2938 model_test_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
2939 {
2940 #define FLD(f) abuf->fields.fmt_ldh_d.f
2941   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2942   const IDESC * UNUSED idesc = abuf->idesc;
2943   int cycles = 0;
2944   {
2945     int referenced = 0;
2946     int UNUSED insn_referenced = abuf->written;
2947     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2948   }
2949   return cycles;
2950 #undef FLD
2951 }
2952
2953 static int
2954 model_test_ldub (SIM_CPU *current_cpu, void *sem_arg)
2955 {
2956 #define FLD(f) abuf->fields.fmt_ldb.f
2957   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2958   const IDESC * UNUSED idesc = abuf->idesc;
2959   int cycles = 0;
2960   {
2961     int referenced = 0;
2962     int UNUSED insn_referenced = abuf->written;
2963     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2964   }
2965   return cycles;
2966 #undef FLD
2967 }
2968
2969 static int
2970 model_test_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
2971 {
2972 #define FLD(f) abuf->fields.fmt_ldb_d.f
2973   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2974   const IDESC * UNUSED idesc = abuf->idesc;
2975   int cycles = 0;
2976   {
2977     int referenced = 0;
2978     int UNUSED insn_referenced = abuf->written;
2979     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2980   }
2981   return cycles;
2982 #undef FLD
2983 }
2984
2985 static int
2986 model_test_lduh (SIM_CPU *current_cpu, void *sem_arg)
2987 {
2988 #define FLD(f) abuf->fields.fmt_ldh.f
2989   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2990   const IDESC * UNUSED idesc = abuf->idesc;
2991   int cycles = 0;
2992   {
2993     int referenced = 0;
2994     int UNUSED insn_referenced = abuf->written;
2995     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2996   }
2997   return cycles;
2998 #undef FLD
2999 }
3000
3001 static int
3002 model_test_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
3003 {
3004 #define FLD(f) abuf->fields.fmt_ldh_d.f
3005   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3006   const IDESC * UNUSED idesc = abuf->idesc;
3007   int cycles = 0;
3008   {
3009     int referenced = 0;
3010     int UNUSED insn_referenced = abuf->written;
3011     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3012   }
3013   return cycles;
3014 #undef FLD
3015 }
3016
3017 static int
3018 model_test_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
3019 {
3020 #define FLD(f) abuf->fields.fmt_ld_plus.f
3021   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3022   const IDESC * UNUSED idesc = abuf->idesc;
3023   int cycles = 0;
3024   {
3025     int referenced = 0;
3026     int UNUSED insn_referenced = abuf->written;
3027     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3028   }
3029   return cycles;
3030 #undef FLD
3031 }
3032
3033 static int
3034 model_test_ld24 (SIM_CPU *current_cpu, void *sem_arg)
3035 {
3036 #define FLD(f) abuf->fields.fmt_ld24.f
3037   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3038   const IDESC * UNUSED idesc = abuf->idesc;
3039   int cycles = 0;
3040   {
3041     int referenced = 0;
3042     int UNUSED insn_referenced = abuf->written;
3043     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3044   }
3045   return cycles;
3046 #undef FLD
3047 }
3048
3049 static int
3050 model_test_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
3051 {
3052 #define FLD(f) abuf->fields.fmt_ldi8.f
3053   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3054   const IDESC * UNUSED idesc = abuf->idesc;
3055   int cycles = 0;
3056   {
3057     int referenced = 0;
3058     int UNUSED insn_referenced = abuf->written;
3059     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3060   }
3061   return cycles;
3062 #undef FLD
3063 }
3064
3065 static int
3066 model_test_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
3067 {
3068 #define FLD(f) abuf->fields.fmt_ldi16.f
3069   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3070   const IDESC * UNUSED idesc = abuf->idesc;
3071   int cycles = 0;
3072   {
3073     int referenced = 0;
3074     int UNUSED insn_referenced = abuf->written;
3075     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3076   }
3077   return cycles;
3078 #undef FLD
3079 }
3080
3081 static int
3082 model_test_lock (SIM_CPU *current_cpu, void *sem_arg)
3083 {
3084 #define FLD(f) abuf->fields.fmt_lock.f
3085   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3086   const IDESC * UNUSED idesc = abuf->idesc;
3087   int cycles = 0;
3088   {
3089     int referenced = 0;
3090     int UNUSED insn_referenced = abuf->written;
3091     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3092   }
3093   return cycles;
3094 #undef FLD
3095 }
3096
3097 static int
3098 model_test_machi (SIM_CPU *current_cpu, void *sem_arg)
3099 {
3100 #define FLD(f) abuf->fields.fmt_machi.f
3101   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3102   const IDESC * UNUSED idesc = abuf->idesc;
3103   int cycles = 0;
3104   {
3105     int referenced = 0;
3106     int UNUSED insn_referenced = abuf->written;
3107     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3108   }
3109   return cycles;
3110 #undef FLD
3111 }
3112
3113 static int
3114 model_test_maclo (SIM_CPU *current_cpu, void *sem_arg)
3115 {
3116 #define FLD(f) abuf->fields.fmt_machi.f
3117   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3118   const IDESC * UNUSED idesc = abuf->idesc;
3119   int cycles = 0;
3120   {
3121     int referenced = 0;
3122     int UNUSED insn_referenced = abuf->written;
3123     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3124   }
3125   return cycles;
3126 #undef FLD
3127 }
3128
3129 static int
3130 model_test_macwhi (SIM_CPU *current_cpu, void *sem_arg)
3131 {
3132 #define FLD(f) abuf->fields.fmt_machi.f
3133   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3134   const IDESC * UNUSED idesc = abuf->idesc;
3135   int cycles = 0;
3136   {
3137     int referenced = 0;
3138     int UNUSED insn_referenced = abuf->written;
3139     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3140   }
3141   return cycles;
3142 #undef FLD
3143 }
3144
3145 static int
3146 model_test_macwlo (SIM_CPU *current_cpu, void *sem_arg)
3147 {
3148 #define FLD(f) abuf->fields.fmt_machi.f
3149   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3150   const IDESC * UNUSED idesc = abuf->idesc;
3151   int cycles = 0;
3152   {
3153     int referenced = 0;
3154     int UNUSED insn_referenced = abuf->written;
3155     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3156   }
3157   return cycles;
3158 #undef FLD
3159 }
3160
3161 static int
3162 model_test_mul (SIM_CPU *current_cpu, void *sem_arg)
3163 {
3164 #define FLD(f) abuf->fields.fmt_add.f
3165   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3166   const IDESC * UNUSED idesc = abuf->idesc;
3167   int cycles = 0;
3168   {
3169     int referenced = 0;
3170     int UNUSED insn_referenced = abuf->written;
3171     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3172   }
3173   return cycles;
3174 #undef FLD
3175 }
3176
3177 static int
3178 model_test_mulhi (SIM_CPU *current_cpu, void *sem_arg)
3179 {
3180 #define FLD(f) abuf->fields.fmt_mulhi.f
3181   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3182   const IDESC * UNUSED idesc = abuf->idesc;
3183   int cycles = 0;
3184   {
3185     int referenced = 0;
3186     int UNUSED insn_referenced = abuf->written;
3187     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3188   }
3189   return cycles;
3190 #undef FLD
3191 }
3192
3193 static int
3194 model_test_mullo (SIM_CPU *current_cpu, void *sem_arg)
3195 {
3196 #define FLD(f) abuf->fields.fmt_mulhi.f
3197   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3198   const IDESC * UNUSED idesc = abuf->idesc;
3199   int cycles = 0;
3200   {
3201     int referenced = 0;
3202     int UNUSED insn_referenced = abuf->written;
3203     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3204   }
3205   return cycles;
3206 #undef FLD
3207 }
3208
3209 static int
3210 model_test_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
3211 {
3212 #define FLD(f) abuf->fields.fmt_mulhi.f
3213   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3214   const IDESC * UNUSED idesc = abuf->idesc;
3215   int cycles = 0;
3216   {
3217     int referenced = 0;
3218     int UNUSED insn_referenced = abuf->written;
3219     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3220   }
3221   return cycles;
3222 #undef FLD
3223 }
3224
3225 static int
3226 model_test_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
3227 {
3228 #define FLD(f) abuf->fields.fmt_mulhi.f
3229   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3230   const IDESC * UNUSED idesc = abuf->idesc;
3231   int cycles = 0;
3232   {
3233     int referenced = 0;
3234     int UNUSED insn_referenced = abuf->written;
3235     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3236   }
3237   return cycles;
3238 #undef FLD
3239 }
3240
3241 static int
3242 model_test_mv (SIM_CPU *current_cpu, void *sem_arg)
3243 {
3244 #define FLD(f) abuf->fields.fmt_mv.f
3245   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3246   const IDESC * UNUSED idesc = abuf->idesc;
3247   int cycles = 0;
3248   {
3249     int referenced = 0;
3250     int UNUSED insn_referenced = abuf->written;
3251     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3252   }
3253   return cycles;
3254 #undef FLD
3255 }
3256
3257 static int
3258 model_test_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
3259 {
3260 #define FLD(f) abuf->fields.fmt_mvfachi.f
3261   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3262   const IDESC * UNUSED idesc = abuf->idesc;
3263   int cycles = 0;
3264   {
3265     int referenced = 0;
3266     int UNUSED insn_referenced = abuf->written;
3267     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3268   }
3269   return cycles;
3270 #undef FLD
3271 }
3272
3273 static int
3274 model_test_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
3275 {
3276 #define FLD(f) abuf->fields.fmt_mvfachi.f
3277   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3278   const IDESC * UNUSED idesc = abuf->idesc;
3279   int cycles = 0;
3280   {
3281     int referenced = 0;
3282     int UNUSED insn_referenced = abuf->written;
3283     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3284   }
3285   return cycles;
3286 #undef FLD
3287 }
3288
3289 static int
3290 model_test_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
3291 {
3292 #define FLD(f) abuf->fields.fmt_mvfachi.f
3293   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3294   const IDESC * UNUSED idesc = abuf->idesc;
3295   int cycles = 0;
3296   {
3297     int referenced = 0;
3298     int UNUSED insn_referenced = abuf->written;
3299     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3300   }
3301   return cycles;
3302 #undef FLD
3303 }
3304
3305 static int
3306 model_test_mvfc (SIM_CPU *current_cpu, void *sem_arg)
3307 {
3308 #define FLD(f) abuf->fields.fmt_mvfc.f
3309   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3310   const IDESC * UNUSED idesc = abuf->idesc;
3311   int cycles = 0;
3312   {
3313     int referenced = 0;
3314     int UNUSED insn_referenced = abuf->written;
3315     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3316   }
3317   return cycles;
3318 #undef FLD
3319 }
3320
3321 static int
3322 model_test_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
3323 {
3324 #define FLD(f) abuf->fields.fmt_mvtachi.f
3325   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3326   const IDESC * UNUSED idesc = abuf->idesc;
3327   int cycles = 0;
3328   {
3329     int referenced = 0;
3330     int UNUSED insn_referenced = abuf->written;
3331     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3332   }
3333   return cycles;
3334 #undef FLD
3335 }
3336
3337 static int
3338 model_test_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
3339 {
3340 #define FLD(f) abuf->fields.fmt_mvtachi.f
3341   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3342   const IDESC * UNUSED idesc = abuf->idesc;
3343   int cycles = 0;
3344   {
3345     int referenced = 0;
3346     int UNUSED insn_referenced = abuf->written;
3347     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3348   }
3349   return cycles;
3350 #undef FLD
3351 }
3352
3353 static int
3354 model_test_mvtc (SIM_CPU *current_cpu, void *sem_arg)
3355 {
3356 #define FLD(f) abuf->fields.fmt_mvtc.f
3357   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3358   const IDESC * UNUSED idesc = abuf->idesc;
3359   int cycles = 0;
3360   {
3361     int referenced = 0;
3362     int UNUSED insn_referenced = abuf->written;
3363     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3364   }
3365   return cycles;
3366 #undef FLD
3367 }
3368
3369 static int
3370 model_test_neg (SIM_CPU *current_cpu, void *sem_arg)
3371 {
3372 #define FLD(f) abuf->fields.fmt_mv.f
3373   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3374   const IDESC * UNUSED idesc = abuf->idesc;
3375   int cycles = 0;
3376   {
3377     int referenced = 0;
3378     int UNUSED insn_referenced = abuf->written;
3379     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3380   }
3381   return cycles;
3382 #undef FLD
3383 }
3384
3385 static int
3386 model_test_nop (SIM_CPU *current_cpu, void *sem_arg)
3387 {
3388 #define FLD(f) abuf->fields.fmt_nop.f
3389   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3390   const IDESC * UNUSED idesc = abuf->idesc;
3391   int cycles = 0;
3392   {
3393     int referenced = 0;
3394     int UNUSED insn_referenced = abuf->written;
3395     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3396   }
3397   return cycles;
3398 #undef FLD
3399 }
3400
3401 static int
3402 model_test_not (SIM_CPU *current_cpu, void *sem_arg)
3403 {
3404 #define FLD(f) abuf->fields.fmt_mv.f
3405   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3406   const IDESC * UNUSED idesc = abuf->idesc;
3407   int cycles = 0;
3408   {
3409     int referenced = 0;
3410     int UNUSED insn_referenced = abuf->written;
3411     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3412   }
3413   return cycles;
3414 #undef FLD
3415 }
3416
3417 static int
3418 model_test_rac (SIM_CPU *current_cpu, void *sem_arg)
3419 {
3420 #define FLD(f) abuf->fields.fmt_rac.f
3421   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3422   const IDESC * UNUSED idesc = abuf->idesc;
3423   int cycles = 0;
3424   {
3425     int referenced = 0;
3426     int UNUSED insn_referenced = abuf->written;
3427     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3428   }
3429   return cycles;
3430 #undef FLD
3431 }
3432
3433 static int
3434 model_test_rach (SIM_CPU *current_cpu, void *sem_arg)
3435 {
3436 #define FLD(f) abuf->fields.fmt_rac.f
3437   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3438   const IDESC * UNUSED idesc = abuf->idesc;
3439   int cycles = 0;
3440   {
3441     int referenced = 0;
3442     int UNUSED insn_referenced = abuf->written;
3443     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3444   }
3445   return cycles;
3446 #undef FLD
3447 }
3448
3449 static int
3450 model_test_rte (SIM_CPU *current_cpu, void *sem_arg)
3451 {
3452 #define FLD(f) abuf->fields.cti.fields.fmt_rte.f
3453   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3454   const IDESC * UNUSED idesc = abuf->idesc;
3455   int cycles = 0;
3456   {
3457     int referenced = 0;
3458     int UNUSED insn_referenced = abuf->written;
3459     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3460   }
3461   return cycles;
3462 #undef FLD
3463 }
3464
3465 static int
3466 model_test_seth (SIM_CPU *current_cpu, void *sem_arg)
3467 {
3468 #define FLD(f) abuf->fields.fmt_seth.f
3469   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3470   const IDESC * UNUSED idesc = abuf->idesc;
3471   int cycles = 0;
3472   {
3473     int referenced = 0;
3474     int UNUSED insn_referenced = abuf->written;
3475     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3476   }
3477   return cycles;
3478 #undef FLD
3479 }
3480
3481 static int
3482 model_test_sll (SIM_CPU *current_cpu, void *sem_arg)
3483 {
3484 #define FLD(f) abuf->fields.fmt_add.f
3485   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3486   const IDESC * UNUSED idesc = abuf->idesc;
3487   int cycles = 0;
3488   {
3489     int referenced = 0;
3490     int UNUSED insn_referenced = abuf->written;
3491     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3492   }
3493   return cycles;
3494 #undef FLD
3495 }
3496
3497 static int
3498 model_test_sll3 (SIM_CPU *current_cpu, void *sem_arg)
3499 {
3500 #define FLD(f) abuf->fields.fmt_sll3.f
3501   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3502   const IDESC * UNUSED idesc = abuf->idesc;
3503   int cycles = 0;
3504   {
3505     int referenced = 0;
3506     int UNUSED insn_referenced = abuf->written;
3507     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3508   }
3509   return cycles;
3510 #undef FLD
3511 }
3512
3513 static int
3514 model_test_slli (SIM_CPU *current_cpu, void *sem_arg)
3515 {
3516 #define FLD(f) abuf->fields.fmt_slli.f
3517   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3518   const IDESC * UNUSED idesc = abuf->idesc;
3519   int cycles = 0;
3520   {
3521     int referenced = 0;
3522     int UNUSED insn_referenced = abuf->written;
3523     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3524   }
3525   return cycles;
3526 #undef FLD
3527 }
3528
3529 static int
3530 model_test_sra (SIM_CPU *current_cpu, void *sem_arg)
3531 {
3532 #define FLD(f) abuf->fields.fmt_add.f
3533   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3534   const IDESC * UNUSED idesc = abuf->idesc;
3535   int cycles = 0;
3536   {
3537     int referenced = 0;
3538     int UNUSED insn_referenced = abuf->written;
3539     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3540   }
3541   return cycles;
3542 #undef FLD
3543 }
3544
3545 static int
3546 model_test_sra3 (SIM_CPU *current_cpu, void *sem_arg)
3547 {
3548 #define FLD(f) abuf->fields.fmt_sll3.f
3549   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3550   const IDESC * UNUSED idesc = abuf->idesc;
3551   int cycles = 0;
3552   {
3553     int referenced = 0;
3554     int UNUSED insn_referenced = abuf->written;
3555     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3556   }
3557   return cycles;
3558 #undef FLD
3559 }
3560
3561 static int
3562 model_test_srai (SIM_CPU *current_cpu, void *sem_arg)
3563 {
3564 #define FLD(f) abuf->fields.fmt_slli.f
3565   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3566   const IDESC * UNUSED idesc = abuf->idesc;
3567   int cycles = 0;
3568   {
3569     int referenced = 0;
3570     int UNUSED insn_referenced = abuf->written;
3571     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3572   }
3573   return cycles;
3574 #undef FLD
3575 }
3576
3577 static int
3578 model_test_srl (SIM_CPU *current_cpu, void *sem_arg)
3579 {
3580 #define FLD(f) abuf->fields.fmt_add.f
3581   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3582   const IDESC * UNUSED idesc = abuf->idesc;
3583   int cycles = 0;
3584   {
3585     int referenced = 0;
3586     int UNUSED insn_referenced = abuf->written;
3587     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3588   }
3589   return cycles;
3590 #undef FLD
3591 }
3592
3593 static int
3594 model_test_srl3 (SIM_CPU *current_cpu, void *sem_arg)
3595 {
3596 #define FLD(f) abuf->fields.fmt_sll3.f
3597   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3598   const IDESC * UNUSED idesc = abuf->idesc;
3599   int cycles = 0;
3600   {
3601     int referenced = 0;
3602     int UNUSED insn_referenced = abuf->written;
3603     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3604   }
3605   return cycles;
3606 #undef FLD
3607 }
3608
3609 static int
3610 model_test_srli (SIM_CPU *current_cpu, void *sem_arg)
3611 {
3612 #define FLD(f) abuf->fields.fmt_slli.f
3613   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3614   const IDESC * UNUSED idesc = abuf->idesc;
3615   int cycles = 0;
3616   {
3617     int referenced = 0;
3618     int UNUSED insn_referenced = abuf->written;
3619     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3620   }
3621   return cycles;
3622 #undef FLD
3623 }
3624
3625 static int
3626 model_test_st (SIM_CPU *current_cpu, void *sem_arg)
3627 {
3628 #define FLD(f) abuf->fields.fmt_st.f
3629   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3630   const IDESC * UNUSED idesc = abuf->idesc;
3631   int cycles = 0;
3632   {
3633     int referenced = 0;
3634     int UNUSED insn_referenced = abuf->written;
3635     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3636   }
3637   return cycles;
3638 #undef FLD
3639 }
3640
3641 static int
3642 model_test_st_d (SIM_CPU *current_cpu, void *sem_arg)
3643 {
3644 #define FLD(f) abuf->fields.fmt_st_d.f
3645   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3646   const IDESC * UNUSED idesc = abuf->idesc;
3647   int cycles = 0;
3648   {
3649     int referenced = 0;
3650     int UNUSED insn_referenced = abuf->written;
3651     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3652   }
3653   return cycles;
3654 #undef FLD
3655 }
3656
3657 static int
3658 model_test_stb (SIM_CPU *current_cpu, void *sem_arg)
3659 {
3660 #define FLD(f) abuf->fields.fmt_stb.f
3661   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3662   const IDESC * UNUSED idesc = abuf->idesc;
3663   int cycles = 0;
3664   {
3665     int referenced = 0;
3666     int UNUSED insn_referenced = abuf->written;
3667     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3668   }
3669   return cycles;
3670 #undef FLD
3671 }
3672
3673 static int
3674 model_test_stb_d (SIM_CPU *current_cpu, void *sem_arg)
3675 {
3676 #define FLD(f) abuf->fields.fmt_stb_d.f
3677   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3678   const IDESC * UNUSED idesc = abuf->idesc;
3679   int cycles = 0;
3680   {
3681     int referenced = 0;
3682     int UNUSED insn_referenced = abuf->written;
3683     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3684   }
3685   return cycles;
3686 #undef FLD
3687 }
3688
3689 static int
3690 model_test_sth (SIM_CPU *current_cpu, void *sem_arg)
3691 {
3692 #define FLD(f) abuf->fields.fmt_sth.f
3693   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3694   const IDESC * UNUSED idesc = abuf->idesc;
3695   int cycles = 0;
3696   {
3697     int referenced = 0;
3698     int UNUSED insn_referenced = abuf->written;
3699     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3700   }
3701   return cycles;
3702 #undef FLD
3703 }
3704
3705 static int
3706 model_test_sth_d (SIM_CPU *current_cpu, void *sem_arg)
3707 {
3708 #define FLD(f) abuf->fields.fmt_sth_d.f
3709   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3710   const IDESC * UNUSED idesc = abuf->idesc;
3711   int cycles = 0;
3712   {
3713     int referenced = 0;
3714     int UNUSED insn_referenced = abuf->written;
3715     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3716   }
3717   return cycles;
3718 #undef FLD
3719 }
3720
3721 static int
3722 model_test_st_plus (SIM_CPU *current_cpu, void *sem_arg)
3723 {
3724 #define FLD(f) abuf->fields.fmt_st_plus.f
3725   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3726   const IDESC * UNUSED idesc = abuf->idesc;
3727   int cycles = 0;
3728   {
3729     int referenced = 0;
3730     int UNUSED insn_referenced = abuf->written;
3731     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3732   }
3733   return cycles;
3734 #undef FLD
3735 }
3736
3737 static int
3738 model_test_st_minus (SIM_CPU *current_cpu, void *sem_arg)
3739 {
3740 #define FLD(f) abuf->fields.fmt_st_plus.f
3741   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3742   const IDESC * UNUSED idesc = abuf->idesc;
3743   int cycles = 0;
3744   {
3745     int referenced = 0;
3746     int UNUSED insn_referenced = abuf->written;
3747     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3748   }
3749   return cycles;
3750 #undef FLD
3751 }
3752
3753 static int
3754 model_test_sub (SIM_CPU *current_cpu, void *sem_arg)
3755 {
3756 #define FLD(f) abuf->fields.fmt_add.f
3757   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3758   const IDESC * UNUSED idesc = abuf->idesc;
3759   int cycles = 0;
3760   {
3761     int referenced = 0;
3762     int UNUSED insn_referenced = abuf->written;
3763     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3764   }
3765   return cycles;
3766 #undef FLD
3767 }
3768
3769 static int
3770 model_test_subv (SIM_CPU *current_cpu, void *sem_arg)
3771 {
3772 #define FLD(f) abuf->fields.fmt_addv.f
3773   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3774   const IDESC * UNUSED idesc = abuf->idesc;
3775   int cycles = 0;
3776   {
3777     int referenced = 0;
3778     int UNUSED insn_referenced = abuf->written;
3779     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3780   }
3781   return cycles;
3782 #undef FLD
3783 }
3784
3785 static int
3786 model_test_subx (SIM_CPU *current_cpu, void *sem_arg)
3787 {
3788 #define FLD(f) abuf->fields.fmt_addx.f
3789   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3790   const IDESC * UNUSED idesc = abuf->idesc;
3791   int cycles = 0;
3792   {
3793     int referenced = 0;
3794     int UNUSED insn_referenced = abuf->written;
3795     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3796   }
3797   return cycles;
3798 #undef FLD
3799 }
3800
3801 static int
3802 model_test_trap (SIM_CPU *current_cpu, void *sem_arg)
3803 {
3804 #define FLD(f) abuf->fields.cti.fields.fmt_trap.f
3805   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3806   const IDESC * UNUSED idesc = abuf->idesc;
3807   int cycles = 0;
3808   {
3809     int referenced = 0;
3810     int UNUSED insn_referenced = abuf->written;
3811     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3812   }
3813   return cycles;
3814 #undef FLD
3815 }
3816
3817 static int
3818 model_test_unlock (SIM_CPU *current_cpu, void *sem_arg)
3819 {
3820 #define FLD(f) abuf->fields.fmt_unlock.f
3821   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3822   const IDESC * UNUSED idesc = abuf->idesc;
3823   int cycles = 0;
3824   {
3825     int referenced = 0;
3826     int UNUSED insn_referenced = abuf->written;
3827     cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3828   }
3829   return cycles;
3830 #undef FLD
3831 }
3832
3833 /* We assume UNIT_NONE == 0 because the tables don't always terminate
3834    entries with it.  */
3835
3836 /* Model timing data for `m32r/d'.  */
3837
3838 static const INSN_TIMING m32r_d_timing[] = {
3839   { M32RBF_INSN_X_INVALID, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3840   { M32RBF_INSN_X_AFTER, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3841   { M32RBF_INSN_X_BEFORE, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3842   { M32RBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3843   { M32RBF_INSN_X_CHAIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3844   { M32RBF_INSN_X_BEGIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3845   { M32RBF_INSN_ADD, model_m32r_d_add, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3846   { M32RBF_INSN_ADD3, model_m32r_d_add3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3847   { M32RBF_INSN_AND, model_m32r_d_and, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3848   { M32RBF_INSN_AND3, model_m32r_d_and3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3849   { M32RBF_INSN_OR, model_m32r_d_or, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3850   { M32RBF_INSN_OR3, model_m32r_d_or3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3851   { M32RBF_INSN_XOR, model_m32r_d_xor, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3852   { M32RBF_INSN_XOR3, model_m32r_d_xor3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3853   { M32RBF_INSN_ADDI, model_m32r_d_addi, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3854   { M32RBF_INSN_ADDV, model_m32r_d_addv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3855   { M32RBF_INSN_ADDV3, model_m32r_d_addv3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3856   { M32RBF_INSN_ADDX, model_m32r_d_addx, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3857   { M32RBF_INSN_BC8, model_m32r_d_bc8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3858   { M32RBF_INSN_BC24, model_m32r_d_bc24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3859   { M32RBF_INSN_BEQ, model_m32r_d_beq, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3860   { M32RBF_INSN_BEQZ, model_m32r_d_beqz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3861   { M32RBF_INSN_BGEZ, model_m32r_d_bgez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3862   { M32RBF_INSN_BGTZ, model_m32r_d_bgtz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3863   { M32RBF_INSN_BLEZ, model_m32r_d_blez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3864   { M32RBF_INSN_BLTZ, model_m32r_d_bltz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3865   { M32RBF_INSN_BNEZ, model_m32r_d_bnez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3866   { M32RBF_INSN_BL8, model_m32r_d_bl8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3867   { M32RBF_INSN_BL24, model_m32r_d_bl24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3868   { M32RBF_INSN_BNC8, model_m32r_d_bnc8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3869   { M32RBF_INSN_BNC24, model_m32r_d_bnc24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3870   { M32RBF_INSN_BNE, model_m32r_d_bne, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3871   { M32RBF_INSN_BRA8, model_m32r_d_bra8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3872   { M32RBF_INSN_BRA24, model_m32r_d_bra24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3873   { M32RBF_INSN_CMP, model_m32r_d_cmp, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
3874   { M32RBF_INSN_CMPI, model_m32r_d_cmpi, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
3875   { M32RBF_INSN_CMPU, model_m32r_d_cmpu, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
3876   { M32RBF_INSN_CMPUI, model_m32r_d_cmpui, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
3877   { M32RBF_INSN_DIV, model_m32r_d_div, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
3878   { M32RBF_INSN_DIVU, model_m32r_d_divu, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
3879   { M32RBF_INSN_REM, model_m32r_d_rem, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
3880   { M32RBF_INSN_REMU, model_m32r_d_remu, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
3881   { M32RBF_INSN_JL, model_m32r_d_jl, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3882   { M32RBF_INSN_JMP, model_m32r_d_jmp, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3883   { M32RBF_INSN_LD, model_m32r_d_ld, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
3884   { M32RBF_INSN_LD_D, model_m32r_d_ld_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
3885   { M32RBF_INSN_LDB, model_m32r_d_ldb, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
3886   { M32RBF_INSN_LDB_D, model_m32r_d_ldb_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
3887   { M32RBF_INSN_LDH, model_m32r_d_ldh, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
3888   { M32RBF_INSN_LDH_D, model_m32r_d_ldh_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
3889   { M32RBF_INSN_LDUB, model_m32r_d_ldub, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
3890   { M32RBF_INSN_LDUB_D, model_m32r_d_ldub_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
3891   { M32RBF_INSN_LDUH, model_m32r_d_lduh, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
3892   { M32RBF_INSN_LDUH_D, model_m32r_d_lduh_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
3893   { M32RBF_INSN_LD_PLUS, model_m32r_d_ld_plus, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
3894   { M32RBF_INSN_LD24, model_m32r_d_ld24, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3895   { M32RBF_INSN_LDI8, model_m32r_d_ldi8, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3896   { M32RBF_INSN_LDI16, model_m32r_d_ldi16, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3897   { M32RBF_INSN_LOCK, model_m32r_d_lock, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
3898   { M32RBF_INSN_MACHI, model_m32r_d_machi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3899   { M32RBF_INSN_MACLO, model_m32r_d_maclo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3900   { M32RBF_INSN_MACWHI, model_m32r_d_macwhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3901   { M32RBF_INSN_MACWLO, model_m32r_d_macwlo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3902   { M32RBF_INSN_MUL, model_m32r_d_mul, { { (int) UNIT_M32R_D_U_EXEC, 1, 4 } } },
3903   { M32RBF_INSN_MULHI, model_m32r_d_mulhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3904   { M32RBF_INSN_MULLO, model_m32r_d_mullo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3905   { M32RBF_INSN_MULWHI, model_m32r_d_mulwhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3906   { M32RBF_INSN_MULWLO, model_m32r_d_mulwlo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3907   { M32RBF_INSN_MV, model_m32r_d_mv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3908   { M32RBF_INSN_MVFACHI, model_m32r_d_mvfachi, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
3909   { M32RBF_INSN_MVFACLO, model_m32r_d_mvfaclo, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
3910   { M32RBF_INSN_MVFACMI, model_m32r_d_mvfacmi, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
3911   { M32RBF_INSN_MVFC, model_m32r_d_mvfc, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3912   { M32RBF_INSN_MVTACHI, model_m32r_d_mvtachi, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3913   { M32RBF_INSN_MVTACLO, model_m32r_d_mvtaclo, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3914   { M32RBF_INSN_MVTC, model_m32r_d_mvtc, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3915   { M32RBF_INSN_NEG, model_m32r_d_neg, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3916   { M32RBF_INSN_NOP, model_m32r_d_nop, { { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
3917   { M32RBF_INSN_NOT, model_m32r_d_not, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3918   { M32RBF_INSN_RAC, model_m32r_d_rac, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3919   { M32RBF_INSN_RACH, model_m32r_d_rach, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3920   { M32RBF_INSN_RTE, model_m32r_d_rte, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3921   { M32RBF_INSN_SETH, model_m32r_d_seth, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3922   { M32RBF_INSN_SLL, model_m32r_d_sll, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3923   { M32RBF_INSN_SLL3, model_m32r_d_sll3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3924   { M32RBF_INSN_SLLI, model_m32r_d_slli, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3925   { M32RBF_INSN_SRA, model_m32r_d_sra, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3926   { M32RBF_INSN_SRA3, model_m32r_d_sra3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3927   { M32RBF_INSN_SRAI, model_m32r_d_srai, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3928   { M32RBF_INSN_SRL, model_m32r_d_srl, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3929   { M32RBF_INSN_SRL3, model_m32r_d_srl3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3930   { M32RBF_INSN_SRLI, model_m32r_d_srli, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3931   { M32RBF_INSN_ST, model_m32r_d_st, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
3932   { M32RBF_INSN_ST_D, model_m32r_d_st_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
3933   { M32RBF_INSN_STB, model_m32r_d_stb, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
3934   { M32RBF_INSN_STB_D, model_m32r_d_stb_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
3935   { M32RBF_INSN_STH, model_m32r_d_sth, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
3936   { M32RBF_INSN_STH_D, model_m32r_d_sth_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
3937   { M32RBF_INSN_ST_PLUS, model_m32r_d_st_plus, { { (int) UNIT_M32R_D_U_STORE, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
3938   { M32RBF_INSN_ST_MINUS, model_m32r_d_st_minus, { { (int) UNIT_M32R_D_U_STORE, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
3939   { M32RBF_INSN_SUB, model_m32r_d_sub, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3940   { M32RBF_INSN_SUBV, model_m32r_d_subv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3941   { M32RBF_INSN_SUBX, model_m32r_d_subx, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3942   { M32RBF_INSN_TRAP, model_m32r_d_trap, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3943   { M32RBF_INSN_UNLOCK, model_m32r_d_unlock, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
3944 };
3945
3946 /* Model timing data for `test'.  */
3947
3948 static const INSN_TIMING test_timing[] = {
3949   { M32RBF_INSN_X_INVALID, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3950   { M32RBF_INSN_X_AFTER, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3951   { M32RBF_INSN_X_BEFORE, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3952   { M32RBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3953   { M32RBF_INSN_X_CHAIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3954   { M32RBF_INSN_X_BEGIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3955   { M32RBF_INSN_ADD, model_test_add, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3956   { M32RBF_INSN_ADD3, model_test_add3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3957   { M32RBF_INSN_AND, model_test_and, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3958   { M32RBF_INSN_AND3, model_test_and3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3959   { M32RBF_INSN_OR, model_test_or, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3960   { M32RBF_INSN_OR3, model_test_or3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3961   { M32RBF_INSN_XOR, model_test_xor, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3962   { M32RBF_INSN_XOR3, model_test_xor3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3963   { M32RBF_INSN_ADDI, model_test_addi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3964   { M32RBF_INSN_ADDV, model_test_addv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3965   { M32RBF_INSN_ADDV3, model_test_addv3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3966   { M32RBF_INSN_ADDX, model_test_addx, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3967   { M32RBF_INSN_BC8, model_test_bc8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3968   { M32RBF_INSN_BC24, model_test_bc24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3969   { M32RBF_INSN_BEQ, model_test_beq, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3970   { M32RBF_INSN_BEQZ, model_test_beqz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3971   { M32RBF_INSN_BGEZ, model_test_bgez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3972   { M32RBF_INSN_BGTZ, model_test_bgtz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3973   { M32RBF_INSN_BLEZ, model_test_blez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3974   { M32RBF_INSN_BLTZ, model_test_bltz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3975   { M32RBF_INSN_BNEZ, model_test_bnez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3976   { M32RBF_INSN_BL8, model_test_bl8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3977   { M32RBF_INSN_BL24, model_test_bl24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3978   { M32RBF_INSN_BNC8, model_test_bnc8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3979   { M32RBF_INSN_BNC24, model_test_bnc24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3980   { M32RBF_INSN_BNE, model_test_bne, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3981   { M32RBF_INSN_BRA8, model_test_bra8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3982   { M32RBF_INSN_BRA24, model_test_bra24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3983   { M32RBF_INSN_CMP, model_test_cmp, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3984   { M32RBF_INSN_CMPI, model_test_cmpi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3985   { M32RBF_INSN_CMPU, model_test_cmpu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3986   { M32RBF_INSN_CMPUI, model_test_cmpui, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3987   { M32RBF_INSN_DIV, model_test_div, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3988   { M32RBF_INSN_DIVU, model_test_divu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3989   { M32RBF_INSN_REM, model_test_rem, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3990   { M32RBF_INSN_REMU, model_test_remu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3991   { M32RBF_INSN_JL, model_test_jl, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3992   { M32RBF_INSN_JMP, model_test_jmp, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3993   { M32RBF_INSN_LD, model_test_ld, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3994   { M32RBF_INSN_LD_D, model_test_ld_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3995   { M32RBF_INSN_LDB, model_test_ldb, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3996   { M32RBF_INSN_LDB_D, model_test_ldb_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3997   { M32RBF_INSN_LDH, model_test_ldh, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3998   { M32RBF_INSN_LDH_D, model_test_ldh_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3999   { M32RBF_INSN_LDUB, model_test_ldub, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4000   { M32RBF_INSN_LDUB_D, model_test_ldub_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4001   { M32RBF_INSN_LDUH, model_test_lduh, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4002   { M32RBF_INSN_LDUH_D, model_test_lduh_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4003   { M32RBF_INSN_LD_PLUS, model_test_ld_plus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4004   { M32RBF_INSN_LD24, model_test_ld24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4005   { M32RBF_INSN_LDI8, model_test_ldi8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4006   { M32RBF_INSN_LDI16, model_test_ldi16, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4007   { M32RBF_INSN_LOCK, model_test_lock, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4008   { M32RBF_INSN_MACHI, model_test_machi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4009   { M32RBF_INSN_MACLO, model_test_maclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4010   { M32RBF_INSN_MACWHI, model_test_macwhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4011   { M32RBF_INSN_MACWLO, model_test_macwlo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4012   { M32RBF_INSN_MUL, model_test_mul, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4013   { M32RBF_INSN_MULHI, model_test_mulhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4014   { M32RBF_INSN_MULLO, model_test_mullo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4015   { M32RBF_INSN_MULWHI, model_test_mulwhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4016   { M32RBF_INSN_MULWLO, model_test_mulwlo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4017   { M32RBF_INSN_MV, model_test_mv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4018   { M32RBF_INSN_MVFACHI, model_test_mvfachi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4019   { M32RBF_INSN_MVFACLO, model_test_mvfaclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4020   { M32RBF_INSN_MVFACMI, model_test_mvfacmi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4021   { M32RBF_INSN_MVFC, model_test_mvfc, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4022   { M32RBF_INSN_MVTACHI, model_test_mvtachi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4023   { M32RBF_INSN_MVTACLO, model_test_mvtaclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4024   { M32RBF_INSN_MVTC, model_test_mvtc, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4025   { M32RBF_INSN_NEG, model_test_neg, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4026   { M32RBF_INSN_NOP, model_test_nop, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4027   { M32RBF_INSN_NOT, model_test_not, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4028   { M32RBF_INSN_RAC, model_test_rac, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4029   { M32RBF_INSN_RACH, model_test_rach, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4030   { M32RBF_INSN_RTE, model_test_rte, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4031   { M32RBF_INSN_SETH, model_test_seth, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4032   { M32RBF_INSN_SLL, model_test_sll, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4033   { M32RBF_INSN_SLL3, model_test_sll3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4034   { M32RBF_INSN_SLLI, model_test_slli, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4035   { M32RBF_INSN_SRA, model_test_sra, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4036   { M32RBF_INSN_SRA3, model_test_sra3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4037   { M32RBF_INSN_SRAI, model_test_srai, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4038   { M32RBF_INSN_SRL, model_test_srl, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4039   { M32RBF_INSN_SRL3, model_test_srl3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4040   { M32RBF_INSN_SRLI, model_test_srli, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4041   { M32RBF_INSN_ST, model_test_st, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4042   { M32RBF_INSN_ST_D, model_test_st_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4043   { M32RBF_INSN_STB, model_test_stb, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4044   { M32RBF_INSN_STB_D, model_test_stb_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4045   { M32RBF_INSN_STH, model_test_sth, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4046   { M32RBF_INSN_STH_D, model_test_sth_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4047   { M32RBF_INSN_ST_PLUS, model_test_st_plus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4048   { M32RBF_INSN_ST_MINUS, model_test_st_minus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4049   { M32RBF_INSN_SUB, model_test_sub, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4050   { M32RBF_INSN_SUBV, model_test_subv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4051   { M32RBF_INSN_SUBX, model_test_subx, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4052   { M32RBF_INSN_TRAP, model_test_trap, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4053   { M32RBF_INSN_UNLOCK, model_test_unlock, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4054 };
4055
4056 #endif /* WITH_PROFILE_MODEL_P */
4057
4058 static void
4059 m32r_d_model_init (SIM_CPU *cpu)
4060 {
4061   CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32R_D_DATA));
4062 }
4063
4064 static void
4065 test_model_init (SIM_CPU *cpu)
4066 {
4067   CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_TEST_DATA));
4068 }
4069
4070 #if WITH_PROFILE_MODEL_P
4071 #define TIMING_DATA(td) td
4072 #else
4073 #define TIMING_DATA(td) 0
4074 #endif
4075
4076 static const MODEL m32r_models[] =
4077 {
4078   { "m32r/d", & m32r_mach, MODEL_M32R_D, TIMING_DATA (& m32r_d_timing[0]), m32r_d_model_init },
4079   { "test", & m32r_mach, MODEL_TEST, TIMING_DATA (& test_timing[0]), test_model_init },
4080   { 0 }
4081 };
4082
4083 /* The properties of this cpu's implementation.  */
4084
4085 static const MACH_IMP_PROPERTIES m32rbf_imp_properties =
4086 {
4087   sizeof (SIM_CPU),
4088 #if WITH_SCACHE
4089   sizeof (SCACHE)
4090 #else
4091   0
4092 #endif
4093 };
4094
4095 static const CGEN_INSN *
4096 m32rbf_opcode (SIM_CPU *cpu, int inum)
4097 {
4098   return CPU_IDESC (cpu) [inum].opcode;
4099 }
4100
4101 static void
4102 m32r_init_cpu (SIM_CPU *cpu)
4103 {
4104   CPU_REG_FETCH (cpu) = m32rbf_fetch_register;
4105   CPU_REG_STORE (cpu) = m32rbf_store_register;
4106   CPU_PC_FETCH (cpu) = m32rbf_h_pc_get;
4107   CPU_PC_STORE (cpu) = m32rbf_h_pc_set;
4108   CPU_OPCODE (cpu) = m32rbf_opcode;
4109   CPU_MAX_INSNS (cpu) = M32RBF_INSN_MAX;
4110   CPU_INSN_NAME (cpu) = cgen_insn_name;
4111   CPU_FULL_ENGINE_FN (cpu) = m32rbf_engine_run_full;
4112 #if WITH_FAST
4113   CPU_FAST_ENGINE_FN (cpu) = m32rbf_engine_run_fast;
4114 #else
4115   CPU_FAST_ENGINE_FN (cpu) = m32rbf_engine_run_full;
4116 #endif
4117   m32rbf_init_idesc_table (cpu);
4118 }
4119
4120 const MACH m32r_mach =
4121 {
4122   "m32r", "m32r",
4123   32, 32, & m32r_models[0], & m32rbf_imp_properties,
4124   m32r_init_cpu
4125 };
4126