sim/m32r/readx.c

   1 /* Simulator instruction operand reader for m32r.
   2
   3 This file is machine generated with CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #define WANT_CPU
  26 #define WANT_CPU_M32RX
  27
  28 #include "sim-main.h"
  29 #include "cpu-sim.h"
  30
  31 #ifdef DEFINE_LABELS
  32 #undef DEFINE_LABELS
  33
  34   /* The labels have the case they have because the enum of insn types
  35      is all uppercase and in the non-stdc case the fmt symbol is built
  36      into the enum name.
  37
  38      The order here must match the order in m32rx_decode_vars in decode.c.  */
  39
  40   static void *labels[] = {
  41     && case_read_READ_ILLEGAL,
  42     && case_read_READ_FMT_0_ADD,
  43     && case_read_READ_FMT_1_ADD3,
  44     && case_read_READ_FMT_2_AND3,
  45     && case_read_READ_FMT_3_OR3,
  46     && case_read_READ_FMT_4_ADDI,
  47     && case_read_READ_FMT_5_ADDV3,
  48     && case_read_READ_FMT_6_ADDX,
  49     && case_read_READ_FMT_7_BC8,
  50     && case_read_READ_FMT_8_BC24,
  51     && case_read_READ_FMT_9_BEQ,
  52     && case_read_READ_FMT_10_BEQZ,
  53     && case_read_READ_FMT_11_BL8,
  54     && case_read_READ_FMT_12_BL24,
  55     && case_read_READ_FMT_13_BCL8,
  56     && case_read_READ_FMT_14_BCL24,
  57     && case_read_READ_FMT_15_BRA8,
  58     && case_read_READ_FMT_16_BRA24,
  59     && case_read_READ_FMT_17_CMP,
  60     && case_read_READ_FMT_18_CMPI,
  61     && case_read_READ_FMT_19_CMPUI,
  62     && case_read_READ_FMT_20_CMPZ,
  63     && case_read_READ_FMT_21_DIV,
  64     && case_read_READ_FMT_22_JC,
  65     && case_read_READ_FMT_23_JL,
  66     && case_read_READ_FMT_24_JMP,
  67     && case_read_READ_FMT_25_LD,
  68     && case_read_READ_FMT_26_LD_D,
  69     && case_read_READ_FMT_27_LDB,
  70     && case_read_READ_FMT_28_LDB_D,
  71     && case_read_READ_FMT_29_LDH,
  72     && case_read_READ_FMT_30_LDH_D,
  73     && case_read_READ_FMT_31_LD24,
  74     && case_read_READ_FMT_32_LDI8,
  75     && case_read_READ_FMT_33_LDI16,
  76     && case_read_READ_FMT_34_MACHI_A,
  77     && case_read_READ_FMT_35_MULHI_A,
  78     && case_read_READ_FMT_36_MV,
  79     && case_read_READ_FMT_37_MVFACHI_A,
  80     && case_read_READ_FMT_38_MVFC,
  81     && case_read_READ_FMT_39_MVTACHI_A,
  82     && case_read_READ_FMT_40_MVTC,
  83     && case_read_READ_FMT_41_NOP,
  84     && case_read_READ_FMT_42_RAC_A,
  85     && case_read_READ_FMT_43_RTE,
  86     && case_read_READ_FMT_44_SETH,
  87     && case_read_READ_FMT_45_SLLI,
  88     && case_read_READ_FMT_46_ST_D,
  89     && case_read_READ_FMT_47_TRAP,
  90     && case_read_READ_FMT_48_SATB,
  91     && case_read_READ_FMT_49_SAT,
  92     && case_read_READ_FMT_50_SADD,
  93     && case_read_READ_FMT_51_MACWU1,
  94     && case_read_READ_FMT_52_MSBLO,
  95     && case_read_READ_FMT_53_SC,
  96     0
  97   };
  98   extern DECODE *m32rx_decode_vars[];
  99   int i;
 100
 101   for (i = 0; m32rx_decode_vars[i] != 0; ++i)
 102     m32rx_decode_vars[i]->read = labels[i];
 103
 104 #endif /* DEFINE_LABELS */
 105
 106 #ifdef DEFINE_SWITCH
 107 #undef DEFINE_SWITCH
 108
 109 {
 110   SWITCH (read, decode->read)
 111     {
 112
 113     CASE (read, READ_ILLEGAL) :
 114     {
 115       sim_engine_illegal_insn (current_cpu, NULL_CIA /*FIXME*/);
 116     }
 117     BREAK (read);
 118
 119     CASE (read, READ_FMT_0_ADD) : /* e.g. add $dr,$sr */
 120     {
 121 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
 122   EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
 123   EXTRACT_FMT_0_ADD_CODE
 124
 125       /* Fetch the input operands for the semantic handler.  */
 126       OPRND (dr) = CPU (h_gr[f_r1]);
 127       OPRND (sr) = CPU (h_gr[f_r2]);
 128 #undef OPRND
 129     }
 130     BREAK (read);
 131
 132     CASE (read, READ_FMT_1_ADD3) : /* e.g. add3 $dr,$sr,#$slo16 */
 133     {
 134 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_1_add3.f
 135   EXTRACT_FMT_1_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 136   EXTRACT_FMT_1_ADD3_CODE
 137
 138       /* Fetch the input operands for the semantic handler.  */
 139       OPRND (slo16) = f_simm16;
 140       OPRND (sr) = CPU (h_gr[f_r2]);
 141 #undef OPRND
 142     }
 143     BREAK (read);
 144
 145     CASE (read, READ_FMT_2_AND3) : /* e.g. and3 $dr,$sr,#$uimm16 */
 146     {
 147 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_2_and3.f
 148   EXTRACT_FMT_2_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 149   EXTRACT_FMT_2_AND3_CODE
 150
 151       /* Fetch the input operands for the semantic handler.  */
 152       OPRND (sr) = CPU (h_gr[f_r2]);
 153       OPRND (uimm16) = f_uimm16;
 154 #undef OPRND
 155     }
 156     BREAK (read);
 157
 158     CASE (read, READ_FMT_3_OR3) : /* e.g. or3 $dr,$sr,#$ulo16 */
 159     {
 160 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_3_or3.f
 161   EXTRACT_FMT_3_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 162   EXTRACT_FMT_3_OR3_CODE
 163
 164       /* Fetch the input operands for the semantic handler.  */
 165       OPRND (sr) = CPU (h_gr[f_r2]);
 166       OPRND (ulo16) = f_uimm16;
 167 #undef OPRND
 168     }
 169     BREAK (read);
 170
 171     CASE (read, READ_FMT_4_ADDI) : /* e.g. addi $dr,#$simm8 */
 172     {
 173 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_4_addi.f
 174   EXTRACT_FMT_4_ADDI_VARS /* f-op1 f-r1 f-simm8 */
 175   EXTRACT_FMT_4_ADDI_CODE
 176
 177       /* Fetch the input operands for the semantic handler.  */
 178       OPRND (dr) = CPU (h_gr[f_r1]);
 179       OPRND (simm8) = f_simm8;
 180 #undef OPRND
 181     }
 182     BREAK (read);
 183
 184     CASE (read, READ_FMT_5_ADDV3) : /* e.g. addv3 $dr,$sr,#$simm16 */
 185     {
 186 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f
 187   EXTRACT_FMT_5_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 188   EXTRACT_FMT_5_ADDV3_CODE
 189
 190       /* Fetch the input operands for the semantic handler.  */
 191       OPRND (simm16) = f_simm16;
 192       OPRND (sr) = CPU (h_gr[f_r2]);
 193 #undef OPRND
 194     }
 195     BREAK (read);
 196
 197     CASE (read, READ_FMT_6_ADDX) : /* e.g. addx $dr,$sr */
 198     {
 199 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_6_addx.f
 200   EXTRACT_FMT_6_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
 201   EXTRACT_FMT_6_ADDX_CODE
 202
 203       /* Fetch the input operands for the semantic handler.  */
 204       OPRND (condbit) = CPU (h_cond);
 205       OPRND (dr) = CPU (h_gr[f_r1]);
 206       OPRND (sr) = CPU (h_gr[f_r2]);
 207 #undef OPRND
 208     }
 209     BREAK (read);
 210
 211     CASE (read, READ_FMT_7_BC8) : /* e.g. bc $disp8 */
 212     {
 213 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_7_bc8.f
 214   EXTRACT_FMT_7_BC8_VARS /* f-op1 f-r1 f-disp8 */
 215   EXTRACT_FMT_7_BC8_CODE
 216
 217       /* Fetch the input operands for the semantic handler.  */
 218       OPRND (condbit) = CPU (h_cond);
 219       OPRND (disp8) = f_disp8;
 220 #undef OPRND
 221     }
 222     BREAK (read);
 223
 224     CASE (read, READ_FMT_8_BC24) : /* e.g. bc $disp24 */
 225     {
 226 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_8_bc24.f
 227   EXTRACT_FMT_8_BC24_VARS /* f-op1 f-r1 f-disp24 */
 228   EXTRACT_FMT_8_BC24_CODE
 229
 230       /* Fetch the input operands for the semantic handler.  */
 231       OPRND (condbit) = CPU (h_cond);
 232       OPRND (disp24) = f_disp24;
 233 #undef OPRND
 234     }
 235     BREAK (read);
 236
 237     CASE (read, READ_FMT_9_BEQ) : /* e.g. beq $src1,$src2,$disp16 */
 238     {
 239 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_9_beq.f
 240   EXTRACT_FMT_9_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 241   EXTRACT_FMT_9_BEQ_CODE
 242
 243       /* Fetch the input operands for the semantic handler.  */
 244       OPRND (disp16) = f_disp16;
 245       OPRND (src1) = CPU (h_gr[f_r1]);
 246       OPRND (src2) = CPU (h_gr[f_r2]);
 247 #undef OPRND
 248     }
 249     BREAK (read);
 250
 251     CASE (read, READ_FMT_10_BEQZ) : /* e.g. beqz $src2,$disp16 */
 252     {
 253 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
 254   EXTRACT_FMT_10_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 255   EXTRACT_FMT_10_BEQZ_CODE
 256
 257       /* Fetch the input operands for the semantic handler.  */
 258       OPRND (disp16) = f_disp16;
 259       OPRND (src2) = CPU (h_gr[f_r2]);
 260 #undef OPRND
 261     }
 262     BREAK (read);
 263
 264     CASE (read, READ_FMT_11_BL8) : /* e.g. bl $disp8 */
 265     {
 266 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_11_bl8.f
 267   EXTRACT_FMT_11_BL8_VARS /* f-op1 f-r1 f-disp8 */
 268   EXTRACT_FMT_11_BL8_CODE
 269
 270       /* Fetch the input operands for the semantic handler.  */
 271       OPRND (disp8) = f_disp8;
 272       OPRND (pc) = CPU (h_pc);
 273 #undef OPRND
 274     }
 275     BREAK (read);
 276
 277     CASE (read, READ_FMT_12_BL24) : /* e.g. bl $disp24 */
 278     {
 279 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_12_bl24.f
 280   EXTRACT_FMT_12_BL24_VARS /* f-op1 f-r1 f-disp24 */
 281   EXTRACT_FMT_12_BL24_CODE
 282
 283       /* Fetch the input operands for the semantic handler.  */
 284       OPRND (disp24) = f_disp24;
 285       OPRND (pc) = CPU (h_pc);
 286 #undef OPRND
 287     }
 288     BREAK (read);
 289
 290     CASE (read, READ_FMT_13_BCL8) : /* e.g. bcl $disp8 */
 291     {
 292 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_13_bcl8.f
 293   EXTRACT_FMT_13_BCL8_VARS /* f-op1 f-r1 f-disp8 */
 294   EXTRACT_FMT_13_BCL8_CODE
 295
 296       /* Fetch the input operands for the semantic handler.  */
 297       OPRND (condbit) = CPU (h_cond);
 298       OPRND (disp8) = f_disp8;
 299       OPRND (pc) = CPU (h_pc);
 300 #undef OPRND
 301     }
 302     BREAK (read);
 303
 304     CASE (read, READ_FMT_14_BCL24) : /* e.g. bcl $disp24 */
 305     {
 306 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_14_bcl24.f
 307   EXTRACT_FMT_14_BCL24_VARS /* f-op1 f-r1 f-disp24 */
 308   EXTRACT_FMT_14_BCL24_CODE
 309
 310       /* Fetch the input operands for the semantic handler.  */
 311       OPRND (condbit) = CPU (h_cond);
 312       OPRND (disp24) = f_disp24;
 313       OPRND (pc) = CPU (h_pc);
 314 #undef OPRND
 315     }
 316     BREAK (read);
 317
 318     CASE (read, READ_FMT_15_BRA8) : /* e.g. bra $disp8 */
 319     {
 320 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_15_bra8.f
 321   EXTRACT_FMT_15_BRA8_VARS /* f-op1 f-r1 f-disp8 */
 322   EXTRACT_FMT_15_BRA8_CODE
 323
 324       /* Fetch the input operands for the semantic handler.  */
 325       OPRND (disp8) = f_disp8;
 326 #undef OPRND
 327     }
 328     BREAK (read);
 329
 330     CASE (read, READ_FMT_16_BRA24) : /* e.g. bra $disp24 */
 331     {
 332 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_16_bra24.f
 333   EXTRACT_FMT_16_BRA24_VARS /* f-op1 f-r1 f-disp24 */
 334   EXTRACT_FMT_16_BRA24_CODE
 335
 336       /* Fetch the input operands for the semantic handler.  */
 337       OPRND (disp24) = f_disp24;
 338 #undef OPRND
 339     }
 340     BREAK (read);
 341
 342     CASE (read, READ_FMT_17_CMP) : /* e.g. cmp $src1,$src2 */
 343     {
 344 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
 345   EXTRACT_FMT_17_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
 346   EXTRACT_FMT_17_CMP_CODE
 347
 348       /* Fetch the input operands for the semantic handler.  */
 349       OPRND (src1) = CPU (h_gr[f_r1]);
 350       OPRND (src2) = CPU (h_gr[f_r2]);
 351 #undef OPRND
 352     }
 353     BREAK (read);
 354
 355     CASE (read, READ_FMT_18_CMPI) : /* e.g. cmpi $src2,#$simm16 */
 356     {
 357 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_18_cmpi.f
 358   EXTRACT_FMT_18_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 359   EXTRACT_FMT_18_CMPI_CODE
 360
 361       /* Fetch the input operands for the semantic handler.  */
 362       OPRND (simm16) = f_simm16;
 363       OPRND (src2) = CPU (h_gr[f_r2]);
 364 #undef OPRND
 365     }
 366     BREAK (read);
 367
 368     CASE (read, READ_FMT_19_CMPUI) : /* e.g. cmpui $src2,#$uimm16 */
 369     {
 370 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_19_cmpui.f
 371   EXTRACT_FMT_19_CMPUI_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 372   EXTRACT_FMT_19_CMPUI_CODE
 373
 374       /* Fetch the input operands for the semantic handler.  */
 375       OPRND (src2) = CPU (h_gr[f_r2]);
 376       OPRND (uimm16) = f_uimm16;
 377 #undef OPRND
 378     }
 379     BREAK (read);
 380
 381     CASE (read, READ_FMT_20_CMPZ) : /* e.g. cmpz $src2 */
 382     {
 383 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_20_cmpz.f
 384   EXTRACT_FMT_20_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
 385   EXTRACT_FMT_20_CMPZ_CODE
 386
 387       /* Fetch the input operands for the semantic handler.  */
 388       OPRND (src2) = CPU (h_gr[f_r2]);
 389 #undef OPRND
 390     }
 391     BREAK (read);
 392
 393     CASE (read, READ_FMT_21_DIV) : /* e.g. div $dr,$sr */
 394     {
 395 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f
 396   EXTRACT_FMT_21_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 397   EXTRACT_FMT_21_DIV_CODE
 398
 399       /* Fetch the input operands for the semantic handler.  */
 400       OPRND (dr) = CPU (h_gr[f_r1]);
 401       OPRND (sr) = CPU (h_gr[f_r2]);
 402 #undef OPRND
 403     }
 404     BREAK (read);
 405
 406     CASE (read, READ_FMT_22_JC) : /* e.g. jc $sr */
 407     {
 408 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_22_jc.f
 409   EXTRACT_FMT_22_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
 410   EXTRACT_FMT_22_JC_CODE
 411
 412       /* Fetch the input operands for the semantic handler.  */
 413       OPRND (condbit) = CPU (h_cond);
 414       OPRND (sr) = CPU (h_gr[f_r2]);
 415 #undef OPRND
 416     }
 417     BREAK (read);
 418
 419     CASE (read, READ_FMT_23_JL) : /* e.g. jl $sr */
 420     {
 421 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_23_jl.f
 422   EXTRACT_FMT_23_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
 423   EXTRACT_FMT_23_JL_CODE
 424
 425       /* Fetch the input operands for the semantic handler.  */
 426       OPRND (pc) = CPU (h_pc);
 427       OPRND (sr) = CPU (h_gr[f_r2]);
 428 #undef OPRND
 429     }
 430     BREAK (read);
 431
 432     CASE (read, READ_FMT_24_JMP) : /* e.g. jmp $sr */
 433     {
 434 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_24_jmp.f
 435   EXTRACT_FMT_24_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
 436   EXTRACT_FMT_24_JMP_CODE
 437
 438       /* Fetch the input operands for the semantic handler.  */
 439       OPRND (sr) = CPU (h_gr[f_r2]);
 440 #undef OPRND
 441     }
 442     BREAK (read);
 443
 444     CASE (read, READ_FMT_25_LD) : /* e.g. ld $dr,@$sr */
 445     {
 446 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_25_ld.f
 447   EXTRACT_FMT_25_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */
 448   EXTRACT_FMT_25_LD_CODE
 449
 450       /* Fetch the input operands for the semantic handler.  */
 451       OPRND (h_memory_sr) = GETMEMSI (current_cpu, CPU (h_gr[f_r2]));
 452       OPRND (sr) = CPU (h_gr[f_r2]);
 453 #undef OPRND
 454     }
 455     BREAK (read);
 456
 457     CASE (read, READ_FMT_26_LD_D) : /* e.g. ld $dr,@($slo16,$sr) */
 458     {
 459 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_26_ld_d.f
 460   EXTRACT_FMT_26_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 461   EXTRACT_FMT_26_LD_D_CODE
 462
 463       /* Fetch the input operands for the semantic handler.  */
 464       OPRND (h_memory_add_WI_sr_slo16) = GETMEMSI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
 465       OPRND (slo16) = f_simm16;
 466       OPRND (sr) = CPU (h_gr[f_r2]);
 467 #undef OPRND
 468     }
 469     BREAK (read);
 470
 471     CASE (read, READ_FMT_27_LDB) : /* e.g. ldb $dr,@$sr */
 472     {
 473 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_27_ldb.f
 474   EXTRACT_FMT_27_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
 475   EXTRACT_FMT_27_LDB_CODE
 476
 477       /* Fetch the input operands for the semantic handler.  */
 478       OPRND (h_memory_sr) = GETMEMQI (current_cpu, CPU (h_gr[f_r2]));
 479       OPRND (sr) = CPU (h_gr[f_r2]);
 480 #undef OPRND
 481     }
 482     BREAK (read);
 483
 484     CASE (read, READ_FMT_28_LDB_D) : /* e.g. ldb $dr,@($slo16,$sr) */
 485     {
 486 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_28_ldb_d.f
 487   EXTRACT_FMT_28_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 488   EXTRACT_FMT_28_LDB_D_CODE
 489
 490       /* Fetch the input operands for the semantic handler.  */
 491       OPRND (h_memory_add_WI_sr_slo16) = GETMEMQI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
 492       OPRND (slo16) = f_simm16;
 493       OPRND (sr) = CPU (h_gr[f_r2]);
 494 #undef OPRND
 495     }
 496     BREAK (read);
 497
 498     CASE (read, READ_FMT_29_LDH) : /* e.g. ldh $dr,@$sr */
 499     {
 500 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_29_ldh.f
 501   EXTRACT_FMT_29_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
 502   EXTRACT_FMT_29_LDH_CODE
 503
 504       /* Fetch the input operands for the semantic handler.  */
 505       OPRND (h_memory_sr) = GETMEMHI (current_cpu, CPU (h_gr[f_r2]));
 506       OPRND (sr) = CPU (h_gr[f_r2]);
 507 #undef OPRND
 508     }
 509     BREAK (read);
 510
 511     CASE (read, READ_FMT_30_LDH_D) : /* e.g. ldh $dr,@($slo16,$sr) */
 512     {
 513 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_30_ldh_d.f
 514   EXTRACT_FMT_30_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 515   EXTRACT_FMT_30_LDH_D_CODE
 516
 517       /* Fetch the input operands for the semantic handler.  */
 518       OPRND (h_memory_add_WI_sr_slo16) = GETMEMHI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
 519       OPRND (slo16) = f_simm16;
 520       OPRND (sr) = CPU (h_gr[f_r2]);
 521 #undef OPRND
 522     }
 523     BREAK (read);
 524
 525     CASE (read, READ_FMT_31_LD24) : /* e.g. ld24 $dr,#$uimm24 */
 526     {
 527 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_31_ld24.f
 528   EXTRACT_FMT_31_LD24_VARS /* f-op1 f-r1 f-uimm24 */
 529   EXTRACT_FMT_31_LD24_CODE
 530
 531       /* Fetch the input operands for the semantic handler.  */
 532       OPRND (uimm24) = f_uimm24;
 533 #undef OPRND
 534     }
 535     BREAK (read);
 536
 537     CASE (read, READ_FMT_32_LDI8) : /* e.g. ldi $dr,#$simm8 */
 538     {
 539 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_32_ldi8.f
 540   EXTRACT_FMT_32_LDI8_VARS /* f-op1 f-r1 f-simm8 */
 541   EXTRACT_FMT_32_LDI8_CODE
 542
 543       /* Fetch the input operands for the semantic handler.  */
 544       OPRND (simm8) = f_simm8;
 545 #undef OPRND
 546     }
 547     BREAK (read);
 548
 549     CASE (read, READ_FMT_33_LDI16) : /* e.g. ldi $dr,$slo16 */
 550     {
 551 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_33_ldi16.f
 552   EXTRACT_FMT_33_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 553   EXTRACT_FMT_33_LDI16_CODE
 554
 555       /* Fetch the input operands for the semantic handler.  */
 556       OPRND (slo16) = f_simm16;
 557 #undef OPRND
 558     }
 559     BREAK (read);
 560
 561     CASE (read, READ_FMT_34_MACHI_A) : /* e.g. machi $src1,$src2,$acc */
 562     {
 563 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi_a.f
 564   EXTRACT_FMT_34_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
 565   EXTRACT_FMT_34_MACHI_A_CODE
 566
 567       /* Fetch the input operands for the semantic handler.  */
 568       OPRND (acc) = m32rx_h_accums_get (current_cpu, f_acc);
 569       OPRND (src1) = CPU (h_gr[f_r1]);
 570       OPRND (src2) = CPU (h_gr[f_r2]);
 571 #undef OPRND
 572     }
 573     BREAK (read);
 574
 575     CASE (read, READ_FMT_35_MULHI_A) : /* e.g. mulhi $src1,$src2,$acc */
 576     {
 577 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_mulhi_a.f
 578   EXTRACT_FMT_35_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
 579   EXTRACT_FMT_35_MULHI_A_CODE
 580
 581       /* Fetch the input operands for the semantic handler.  */
 582       OPRND (src1) = CPU (h_gr[f_r1]);
 583       OPRND (src2) = CPU (h_gr[f_r2]);
 584 #undef OPRND
 585     }
 586     BREAK (read);
 587
 588     CASE (read, READ_FMT_36_MV) : /* e.g. mv $dr,$sr */
 589     {
 590 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mv.f
 591   EXTRACT_FMT_36_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
 592   EXTRACT_FMT_36_MV_CODE
 593
 594       /* Fetch the input operands for the semantic handler.  */
 595       OPRND (sr) = CPU (h_gr[f_r2]);
 596 #undef OPRND
 597     }
 598     BREAK (read);
 599
 600     CASE (read, READ_FMT_37_MVFACHI_A) : /* e.g. mvfachi $dr,$accs */
 601     {
 602 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mvfachi_a.f
 603   EXTRACT_FMT_37_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
 604   EXTRACT_FMT_37_MVFACHI_A_CODE
 605
 606       /* Fetch the input operands for the semantic handler.  */
 607       OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
 608 #undef OPRND
 609     }
 610     BREAK (read);
 611
 612     CASE (read, READ_FMT_38_MVFC) : /* e.g. mvfc $dr,$scr */
 613     {
 614 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfc.f
 615   EXTRACT_FMT_38_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
 616   EXTRACT_FMT_38_MVFC_CODE
 617
 618       /* Fetch the input operands for the semantic handler.  */
 619       OPRND (scr) = m32rx_h_cr_get (current_cpu, f_r2);
 620 #undef OPRND
 621     }
 622     BREAK (read);
 623
 624     CASE (read, READ_FMT_39_MVTACHI_A) : /* e.g. mvtachi $src1,$accs */
 625     {
 626 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvtachi_a.f
 627   EXTRACT_FMT_39_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
 628   EXTRACT_FMT_39_MVTACHI_A_CODE
 629
 630       /* Fetch the input operands for the semantic handler.  */
 631       OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
 632       OPRND (src1) = CPU (h_gr[f_r1]);
 633 #undef OPRND
 634     }
 635     BREAK (read);
 636
 637     CASE (read, READ_FMT_40_MVTC) : /* e.g. mvtc $sr,$dcr */
 638     {
 639 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_40_mvtc.f
 640   EXTRACT_FMT_40_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
 641   EXTRACT_FMT_40_MVTC_CODE
 642
 643       /* Fetch the input operands for the semantic handler.  */
 644       OPRND (sr) = CPU (h_gr[f_r2]);
 645 #undef OPRND
 646     }
 647     BREAK (read);
 648
 649     CASE (read, READ_FMT_41_NOP) : /* e.g. nop */
 650     {
 651 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_41_nop.f
 652   EXTRACT_FMT_41_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
 653   EXTRACT_FMT_41_NOP_CODE
 654
 655       /* Fetch the input operands for the semantic handler.  */
 656 #undef OPRND
 657     }
 658     BREAK (read);
 659
 660     CASE (read, READ_FMT_42_RAC_A) : /* e.g. rac $accs */
 661     {
 662 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_42_rac_a.f
 663   EXTRACT_FMT_42_RAC_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
 664   EXTRACT_FMT_42_RAC_A_CODE
 665
 666       /* Fetch the input operands for the semantic handler.  */
 667       OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
 668 #undef OPRND
 669     }
 670     BREAK (read);
 671
 672     CASE (read, READ_FMT_43_RTE) : /* e.g. rte */
 673     {
 674 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_43_rte.f
 675   EXTRACT_FMT_43_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
 676   EXTRACT_FMT_43_RTE_CODE
 677
 678       /* Fetch the input operands for the semantic handler.  */
 679       OPRND (h_bcond_0) = CPU (h_bcond);
 680       OPRND (h_bie_0) = CPU (h_bie);
 681       OPRND (h_bpc_0) = CPU (h_bpc);
 682       OPRND (h_bsm_0) = CPU (h_bsm);
 683 #undef OPRND
 684     }
 685     BREAK (read);
 686
 687     CASE (read, READ_FMT_44_SETH) : /* e.g. seth $dr,#$hi16 */
 688     {
 689 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_44_seth.f
 690   EXTRACT_FMT_44_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
 691   EXTRACT_FMT_44_SETH_CODE
 692
 693       /* Fetch the input operands for the semantic handler.  */
 694       OPRND (hi16) = f_hi16;
 695 #undef OPRND
 696     }
 697     BREAK (read);
 698
 699     CASE (read, READ_FMT_45_SLLI) : /* e.g. slli $dr,#$uimm5 */
 700     {
 701 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_45_slli.f
 702   EXTRACT_FMT_45_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
 703   EXTRACT_FMT_45_SLLI_CODE
 704
 705       /* Fetch the input operands for the semantic handler.  */
 706       OPRND (dr) = CPU (h_gr[f_r1]);
 707       OPRND (uimm5) = f_uimm5;
 708 #undef OPRND
 709     }
 710     BREAK (read);
 711
 712     CASE (read, READ_FMT_46_ST_D) : /* e.g. st $src1,@($slo16,$src2) */
 713     {
 714 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_46_st_d.f
 715   EXTRACT_FMT_46_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 716   EXTRACT_FMT_46_ST_D_CODE
 717
 718       /* Fetch the input operands for the semantic handler.  */
 719       OPRND (slo16) = f_simm16;
 720       OPRND (src1) = CPU (h_gr[f_r1]);
 721       OPRND (src2) = CPU (h_gr[f_r2]);
 722 #undef OPRND
 723     }
 724     BREAK (read);
 725
 726     CASE (read, READ_FMT_47_TRAP) : /* e.g. trap #$uimm4 */
 727     {
 728 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_47_trap.f
 729   EXTRACT_FMT_47_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
 730   EXTRACT_FMT_47_TRAP_CODE
 731
 732       /* Fetch the input operands for the semantic handler.  */
 733       OPRND (uimm4) = f_uimm4;
 734 #undef OPRND
 735     }
 736     BREAK (read);
 737
 738     CASE (read, READ_FMT_48_SATB) : /* e.g. satb $dr,$src2 */
 739     {
 740 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_satb.f
 741   EXTRACT_FMT_48_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 742   EXTRACT_FMT_48_SATB_CODE
 743
 744       /* Fetch the input operands for the semantic handler.  */
 745       OPRND (src2) = CPU (h_gr[f_r2]);
 746 #undef OPRND
 747     }
 748     BREAK (read);
 749
 750     CASE (read, READ_FMT_49_SAT) : /* e.g. sat $dr,$src2 */
 751     {
 752 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_sat.f
 753   EXTRACT_FMT_49_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 754   EXTRACT_FMT_49_SAT_CODE
 755
 756       /* Fetch the input operands for the semantic handler.  */
 757       OPRND (condbit) = CPU (h_cond);
 758       OPRND (src2) = CPU (h_gr[f_r2]);
 759 #undef OPRND
 760     }
 761     BREAK (read);
 762
 763     CASE (read, READ_FMT_50_SADD) : /* e.g. sadd */
 764     {
 765 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_50_sadd.f
 766   EXTRACT_FMT_50_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
 767   EXTRACT_FMT_50_SADD_CODE
 768
 769       /* Fetch the input operands for the semantic handler.  */
 770       OPRND (h_accums_0) = m32rx_h_accums_get (current_cpu, 0);
 771       OPRND (h_accums_1) = m32rx_h_accums_get (current_cpu, 1);
 772 #undef OPRND
 773     }
 774     BREAK (read);
 775
 776     CASE (read, READ_FMT_51_MACWU1) : /* e.g. macwu1 $src1,$src2 */
 777     {
 778 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_macwu1.f
 779   EXTRACT_FMT_51_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
 780   EXTRACT_FMT_51_MACWU1_CODE
 781
 782       /* Fetch the input operands for the semantic handler.  */
 783       OPRND (h_accums_1) = m32rx_h_accums_get (current_cpu, 1);
 784       OPRND (src1) = CPU (h_gr[f_r1]);
 785       OPRND (src2) = CPU (h_gr[f_r2]);
 786 #undef OPRND
 787     }
 788     BREAK (read);
 789
 790     CASE (read, READ_FMT_52_MSBLO) : /* e.g. msblo $src1,$src2 */
 791     {
 792 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_52_msblo.f
 793   EXTRACT_FMT_52_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */
 794   EXTRACT_FMT_52_MSBLO_CODE
 795
 796       /* Fetch the input operands for the semantic handler.  */
 797       OPRND (accum) = CPU (h_accum);
 798       OPRND (src1) = CPU (h_gr[f_r1]);
 799       OPRND (src2) = CPU (h_gr[f_r2]);
 800 #undef OPRND
 801     }
 802     BREAK (read);
 803
 804     CASE (read, READ_FMT_53_SC) : /* e.g. sc */
 805     {
 806 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_53_sc.f
 807   EXTRACT_FMT_53_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
 808   EXTRACT_FMT_53_SC_CODE
 809
 810       /* Fetch the input operands for the semantic handler.  */
 811       OPRND (condbit) = CPU (h_cond);
 812 #undef OPRND
 813     }
 814     BREAK (read);
 815
 816     }
 817   ENDSWITCH (read) /* End of read switch.  */
 818 }
 819
 820 #endif /* DEFINE_SWITCH */