sim/m32r/sem-switch.c

   1 /* Simulator instruction semantics for m32r.
   2
   3 This file is machine generated with CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifdef DEFINE_LABELS
  26 #undef DEFINE_LABELS
  27
  28   /* The labels have the case they have because the enum of insn types
  29      is all uppercase and in the non-stdc case the insn symbol is built
  30      into the enum name.
  31
  32      The order here must match the order in m32r_decode_vars in decode.c.  */
  33
  34   static void *labels[] = {
  35     && case_sem_INSN_ILLEGAL,
  36     && case_sem_INSN_ADD,
  37     && case_sem_INSN_ADD3,
  38     && case_sem_INSN_AND,
  39     && case_sem_INSN_AND3,
  40     && case_sem_INSN_OR,
  41     && case_sem_INSN_OR3,
  42     && case_sem_INSN_XOR,
  43     && case_sem_INSN_XOR3,
  44     && case_sem_INSN_ADDI,
  45     && case_sem_INSN_ADDV,
  46     && case_sem_INSN_ADDV3,
  47     && case_sem_INSN_ADDX,
  48     && case_sem_INSN_BC8,
  49     && case_sem_INSN_BC24,
  50     && case_sem_INSN_BEQ,
  51     && case_sem_INSN_BEQZ,
  52     && case_sem_INSN_BGEZ,
  53     && case_sem_INSN_BGTZ,
  54     && case_sem_INSN_BLEZ,
  55     && case_sem_INSN_BLTZ,
  56     && case_sem_INSN_BNEZ,
  57     && case_sem_INSN_BL8,
  58     && case_sem_INSN_BL24,
  59     && case_sem_INSN_BNC8,
  60     && case_sem_INSN_BNC24,
  61     && case_sem_INSN_BNE,
  62     && case_sem_INSN_BRA8,
  63     && case_sem_INSN_BRA24,
  64     && case_sem_INSN_CMP,
  65     && case_sem_INSN_CMPI,
  66     && case_sem_INSN_CMPU,
  67     && case_sem_INSN_CMPUI,
  68     && case_sem_INSN_DIV,
  69     && case_sem_INSN_DIVU,
  70     && case_sem_INSN_REM,
  71     && case_sem_INSN_REMU,
  72     && case_sem_INSN_DIVH,
  73     && case_sem_INSN_JL,
  74     && case_sem_INSN_JMP,
  75     && case_sem_INSN_LD,
  76     && case_sem_INSN_LD_D,
  77     && case_sem_INSN_LDB,
  78     && case_sem_INSN_LDB_D,
  79     && case_sem_INSN_LDH,
  80     && case_sem_INSN_LDH_D,
  81     && case_sem_INSN_LDUB,
  82     && case_sem_INSN_LDUB_D,
  83     && case_sem_INSN_LDUH,
  84     && case_sem_INSN_LDUH_D,
  85     && case_sem_INSN_LD_PLUS,
  86     && case_sem_INSN_LD24,
  87     && case_sem_INSN_LDI8,
  88     && case_sem_INSN_LDI16,
  89     && case_sem_INSN_LOCK,
  90     && case_sem_INSN_MACHI,
  91     && case_sem_INSN_MACLO,
  92     && case_sem_INSN_MACWHI,
  93     && case_sem_INSN_MACWLO,
  94     && case_sem_INSN_MUL,
  95     && case_sem_INSN_MULHI,
  96     && case_sem_INSN_MULLO,
  97     && case_sem_INSN_MULWHI,
  98     && case_sem_INSN_MULWLO,
  99     && case_sem_INSN_MV,
 100     && case_sem_INSN_MVFACHI,
 101     && case_sem_INSN_MVFACLO,
 102     && case_sem_INSN_MVFACMI,
 103     && case_sem_INSN_MVFC,
 104     && case_sem_INSN_MVTACHI,
 105     && case_sem_INSN_MVTACLO,
 106     && case_sem_INSN_MVTC,
 107     && case_sem_INSN_NEG,
 108     && case_sem_INSN_NOP,
 109     && case_sem_INSN_NOT,
 110     && case_sem_INSN_RAC,
 111     && case_sem_INSN_RACH,
 112     && case_sem_INSN_RTE,
 113     && case_sem_INSN_SETH,
 114     && case_sem_INSN_SLL,
 115     && case_sem_INSN_SLL3,
 116     && case_sem_INSN_SLLI,
 117     && case_sem_INSN_SRA,
 118     && case_sem_INSN_SRA3,
 119     && case_sem_INSN_SRAI,
 120     && case_sem_INSN_SRL,
 121     && case_sem_INSN_SRL3,
 122     && case_sem_INSN_SRLI,
 123     && case_sem_INSN_ST,
 124     && case_sem_INSN_ST_D,
 125     && case_sem_INSN_STB,
 126     && case_sem_INSN_STB_D,
 127     && case_sem_INSN_STH,
 128     && case_sem_INSN_STH_D,
 129     && case_sem_INSN_ST_PLUS,
 130     && case_sem_INSN_ST_MINUS,
 131     && case_sem_INSN_SUB,
 132     && case_sem_INSN_SUBV,
 133     && case_sem_INSN_SUBX,
 134     && case_sem_INSN_TRAP,
 135     && case_sem_INSN_UNLOCK,
 136     0
 137   };
 138   extern DECODE *m32r_decode_vars[];
 139   int i;
 140
 141   for (i = 0; m32r_decode_vars[i] != 0; ++i)
 142     m32r_decode_vars[i]->semantic_lab = labels[i];
 143
 144 #endif /* DEFINE_LABELS */
 145
 146 #ifdef DEFINE_SWITCH
 147 #undef DEFINE_SWITCH
 148
 149 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
 150    off frills like tracing and profiling.  */
 151 /* FIXME: A better way would be to have TRACE_RESULT check for something
 152    that can cause it to be optimized out.  */
 153
 154 #if FAST_P
 155 #undef TRACE_RESULT
 156 #define TRACE_RESULT(cpu, name, type, val)
 157 #endif
 158
 159 #undef GET_ATTR
 160 #define GET_ATTR(cpu, num, attr) CGEN_INSN_ATTR (abuf->opcode, CGEN_INSN_##attr)
 161
 162 {
 163   SEM_ARG sem_arg = sc;
 164   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 165   CIA new_pc;
 166
 167   SWITCH (sem, sem_arg->semantic.sem_case)
 168     {
 169
 170   CASE (sem, INSN_ILLEGAL) :
 171 {
 172   sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, NULL_CIA/*FIXME*/,
 173                    sim_stopped, SIM_SIGILL);
 174   BREAK (sem);
 175 }
 176
 177   CASE (sem, INSN_ADD) : /* add $dr,$sr */
 178 {
 179 #define FLD(f) abuf->fields.fmt_0_add.f
 180   new_pc = SEM_NEXT_PC (sem_arg);
 181
 182 * FLD (f_r1) = ADDSI (* FLD (f_r1), * FLD (f_r2));
 183   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 184
 185 #undef FLD
 186 }
 187   BREAK (sem);
 188
 189   CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,#$slo16 */
 190 {
 191 #define FLD(f) abuf->fields.fmt_1_add3.f
 192   new_pc = SEM_NEXT_PC (sem_arg);
 193
 194 * FLD (f_r1) = ADDSI (* FLD (f_r2), FLD (f_simm16));
 195   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 196
 197 #undef FLD
 198 }
 199   BREAK (sem);
 200
 201   CASE (sem, INSN_AND) : /* and $dr,$sr */
 202 {
 203 #define FLD(f) abuf->fields.fmt_0_add.f
 204   new_pc = SEM_NEXT_PC (sem_arg);
 205
 206 * FLD (f_r1) = ANDSI (* FLD (f_r1), * FLD (f_r2));
 207   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 208
 209 #undef FLD
 210 }
 211   BREAK (sem);
 212
 213   CASE (sem, INSN_AND3) : /* and3 $dr,$sr,#$uimm16 */
 214 {
 215 #define FLD(f) abuf->fields.fmt_2_and3.f
 216   new_pc = SEM_NEXT_PC (sem_arg);
 217
 218 * FLD (f_r1) = ANDSI (* FLD (f_r2), FLD (f_uimm16));
 219   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 220
 221 #undef FLD
 222 }
 223   BREAK (sem);
 224
 225   CASE (sem, INSN_OR) : /* or $dr,$sr */
 226 {
 227 #define FLD(f) abuf->fields.fmt_0_add.f
 228   new_pc = SEM_NEXT_PC (sem_arg);
 229
 230 * FLD (f_r1) = ORSI (* FLD (f_r1), * FLD (f_r2));
 231   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 232
 233 #undef FLD
 234 }
 235   BREAK (sem);
 236
 237   CASE (sem, INSN_OR3) : /* or3 $dr,$sr,#$ulo16 */
 238 {
 239 #define FLD(f) abuf->fields.fmt_3_or3.f
 240   new_pc = SEM_NEXT_PC (sem_arg);
 241
 242 * FLD (f_r1) = ORSI (* FLD (f_r2), FLD (f_uimm16));
 243   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 244
 245 #undef FLD
 246 }
 247   BREAK (sem);
 248
 249   CASE (sem, INSN_XOR) : /* xor $dr,$sr */
 250 {
 251 #define FLD(f) abuf->fields.fmt_0_add.f
 252   new_pc = SEM_NEXT_PC (sem_arg);
 253
 254 * FLD (f_r1) = XORSI (* FLD (f_r1), * FLD (f_r2));
 255   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 256
 257 #undef FLD
 258 }
 259   BREAK (sem);
 260
 261   CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,#$uimm16 */
 262 {
 263 #define FLD(f) abuf->fields.fmt_2_and3.f
 264   new_pc = SEM_NEXT_PC (sem_arg);
 265
 266 * FLD (f_r1) = XORSI (* FLD (f_r2), FLD (f_uimm16));
 267   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 268
 269 #undef FLD
 270 }
 271   BREAK (sem);
 272
 273   CASE (sem, INSN_ADDI) : /* addi $dr,#$simm8 */
 274 {
 275 #define FLD(f) abuf->fields.fmt_4_addi.f
 276   new_pc = SEM_NEXT_PC (sem_arg);
 277
 278 * FLD (f_r1) = ADDSI (* FLD (f_r1), FLD (f_simm8));
 279   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 280
 281 #undef FLD
 282 }
 283   BREAK (sem);
 284
 285   CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
 286 {
 287 #define FLD(f) abuf->fields.fmt_0_add.f
 288   new_pc = SEM_NEXT_PC (sem_arg);
 289
 290 do {
 291   BI temp1;SI temp0;
 292   temp0 = ADDSI (* FLD (f_r1), * FLD (f_r2));
 293   temp1 = ADDOFSI (* FLD (f_r1), * FLD (f_r2), 0);
 294 * FLD (f_r1) = temp0;
 295   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 296   CPU (h_cond) = temp1;
 297   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 298 } while (0);
 299
 300 #undef FLD
 301 }
 302   BREAK (sem);
 303
 304   CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,#$simm16 */
 305 {
 306 #define FLD(f) abuf->fields.fmt_5_addv3.f
 307   new_pc = SEM_NEXT_PC (sem_arg);
 308
 309 do {
 310   BI temp1;SI temp0;
 311   temp0 = ADDSI (* FLD (f_r2), FLD (f_simm16));
 312   temp1 = ADDOFSI (* FLD (f_r2), FLD (f_simm16), 0);
 313 * FLD (f_r1) = temp0;
 314   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 315   CPU (h_cond) = temp1;
 316   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 317 } while (0);
 318
 319 #undef FLD
 320 }
 321   BREAK (sem);
 322
 323   CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
 324 {
 325 #define FLD(f) abuf->fields.fmt_6_addx.f
 326   new_pc = SEM_NEXT_PC (sem_arg);
 327
 328 do {
 329   BI temp1;SI temp0;
 330   temp0 = ADDCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
 331   temp1 = ADDCFSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
 332 * FLD (f_r1) = temp0;
 333   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 334   CPU (h_cond) = temp1;
 335   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 336 } while (0);
 337
 338 #undef FLD
 339 }
 340   BREAK (sem);
 341
 342   CASE (sem, INSN_BC8) : /* bc $disp8 */
 343 {
 344 #define FLD(f) abuf->fields.fmt_7_bc8.f
 345   new_pc = SEM_NEXT_PC (sem_arg);
 346
 347 if (CPU (h_cond)) {
 348   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
 349 }
 350
 351 #undef FLD
 352 }
 353   BREAK (sem);
 354
 355   CASE (sem, INSN_BC24) : /* bc $disp24 */
 356 {
 357 #define FLD(f) abuf->fields.fmt_8_bc24.f
 358   new_pc = SEM_NEXT_PC (sem_arg);
 359
 360 if (CPU (h_cond)) {
 361   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
 362 }
 363
 364 #undef FLD
 365 }
 366   BREAK (sem);
 367
 368   CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
 369 {
 370 #define FLD(f) abuf->fields.fmt_9_beq.f
 371   new_pc = SEM_NEXT_PC (sem_arg);
 372
 373 if (EQSI (* FLD (f_r1), * FLD (f_r2))) {
 374   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 375 }
 376
 377 #undef FLD
 378 }
 379   BREAK (sem);
 380
 381   CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
 382 {
 383 #define FLD(f) abuf->fields.fmt_10_beqz.f
 384   new_pc = SEM_NEXT_PC (sem_arg);
 385
 386 if (EQSI (* FLD (f_r2), 0)) {
 387   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 388 }
 389
 390 #undef FLD
 391 }
 392   BREAK (sem);
 393
 394   CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
 395 {
 396 #define FLD(f) abuf->fields.fmt_10_beqz.f
 397   new_pc = SEM_NEXT_PC (sem_arg);
 398
 399 if (GESI (* FLD (f_r2), 0)) {
 400   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 401 }
 402
 403 #undef FLD
 404 }
 405   BREAK (sem);
 406
 407   CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
 408 {
 409 #define FLD(f) abuf->fields.fmt_10_beqz.f
 410   new_pc = SEM_NEXT_PC (sem_arg);
 411
 412 if (GTSI (* FLD (f_r2), 0)) {
 413   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 414 }
 415
 416 #undef FLD
 417 }
 418   BREAK (sem);
 419
 420   CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
 421 {
 422 #define FLD(f) abuf->fields.fmt_10_beqz.f
 423   new_pc = SEM_NEXT_PC (sem_arg);
 424
 425 if (LESI (* FLD (f_r2), 0)) {
 426   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 427 }
 428
 429 #undef FLD
 430 }
 431   BREAK (sem);
 432
 433   CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
 434 {
 435 #define FLD(f) abuf->fields.fmt_10_beqz.f
 436   new_pc = SEM_NEXT_PC (sem_arg);
 437
 438 if (LTSI (* FLD (f_r2), 0)) {
 439   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 440 }
 441
 442 #undef FLD
 443 }
 444   BREAK (sem);
 445
 446   CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
 447 {
 448 #define FLD(f) abuf->fields.fmt_10_beqz.f
 449   new_pc = SEM_NEXT_PC (sem_arg);
 450
 451 if (NESI (* FLD (f_r2), 0)) {
 452   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 453 }
 454
 455 #undef FLD
 456 }
 457   BREAK (sem);
 458
 459   CASE (sem, INSN_BL8) : /* bl $disp8 */
 460 {
 461 #define FLD(f) abuf->fields.fmt_11_bl8.f
 462   new_pc = SEM_NEXT_PC (sem_arg);
 463
 464 do {
 465   CPU (h_gr[14]) = ADDSI (ANDSI (CPU (h_pc), -4), 4);
 466   TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
 467   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
 468 } while (0);
 469
 470 #undef FLD
 471 }
 472   BREAK (sem);
 473
 474   CASE (sem, INSN_BL24) : /* bl $disp24 */
 475 {
 476 #define FLD(f) abuf->fields.fmt_12_bl24.f
 477   new_pc = SEM_NEXT_PC (sem_arg);
 478
 479 do {
 480   CPU (h_gr[14]) = ADDSI (CPU (h_pc), 4);
 481   TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
 482   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
 483 } while (0);
 484
 485 #undef FLD
 486 }
 487   BREAK (sem);
 488
 489   CASE (sem, INSN_BNC8) : /* bnc $disp8 */
 490 {
 491 #define FLD(f) abuf->fields.fmt_7_bc8.f
 492   new_pc = SEM_NEXT_PC (sem_arg);
 493
 494 if (NOTBI (CPU (h_cond))) {
 495   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
 496 }
 497
 498 #undef FLD
 499 }
 500   BREAK (sem);
 501
 502   CASE (sem, INSN_BNC24) : /* bnc $disp24 */
 503 {
 504 #define FLD(f) abuf->fields.fmt_8_bc24.f
 505   new_pc = SEM_NEXT_PC (sem_arg);
 506
 507 if (NOTBI (CPU (h_cond))) {
 508   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
 509 }
 510
 511 #undef FLD
 512 }
 513   BREAK (sem);
 514
 515   CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
 516 {
 517 #define FLD(f) abuf->fields.fmt_9_beq.f
 518   new_pc = SEM_NEXT_PC (sem_arg);
 519
 520 if (NESI (* FLD (f_r1), * FLD (f_r2))) {
 521   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 522 }
 523
 524 #undef FLD
 525 }
 526   BREAK (sem);
 527
 528   CASE (sem, INSN_BRA8) : /* bra $disp8 */
 529 {
 530 #define FLD(f) abuf->fields.fmt_13_bra8.f
 531   new_pc = SEM_NEXT_PC (sem_arg);
 532
 533   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
 534
 535 #undef FLD
 536 }
 537   BREAK (sem);
 538
 539   CASE (sem, INSN_BRA24) : /* bra $disp24 */
 540 {
 541 #define FLD(f) abuf->fields.fmt_14_bra24.f
 542   new_pc = SEM_NEXT_PC (sem_arg);
 543
 544   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
 545
 546 #undef FLD
 547 }
 548   BREAK (sem);
 549
 550   CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
 551 {
 552 #define FLD(f) abuf->fields.fmt_15_cmp.f
 553   new_pc = SEM_NEXT_PC (sem_arg);
 554
 555   CPU (h_cond) = LTSI (* FLD (f_r1), * FLD (f_r2));
 556   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 557
 558 #undef FLD
 559 }
 560   BREAK (sem);
 561
 562   CASE (sem, INSN_CMPI) : /* cmpi $src2,#$simm16 */
 563 {
 564 #define FLD(f) abuf->fields.fmt_16_cmpi.f
 565   new_pc = SEM_NEXT_PC (sem_arg);
 566
 567   CPU (h_cond) = LTSI (* FLD (f_r2), FLD (f_simm16));
 568   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 569
 570 #undef FLD
 571 }
 572   BREAK (sem);
 573
 574   CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
 575 {
 576 #define FLD(f) abuf->fields.fmt_15_cmp.f
 577   new_pc = SEM_NEXT_PC (sem_arg);
 578
 579   CPU (h_cond) = LTUSI (* FLD (f_r1), * FLD (f_r2));
 580   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 581
 582 #undef FLD
 583 }
 584   BREAK (sem);
 585
 586   CASE (sem, INSN_CMPUI) : /* cmpui $src2,#$uimm16 */
 587 {
 588 #define FLD(f) abuf->fields.fmt_17_cmpui.f
 589   new_pc = SEM_NEXT_PC (sem_arg);
 590
 591   CPU (h_cond) = LTUSI (* FLD (f_r2), FLD (f_uimm16));
 592   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 593
 594 #undef FLD
 595 }
 596   BREAK (sem);
 597
 598   CASE (sem, INSN_DIV) : /* div $dr,$sr */
 599 {
 600 #define FLD(f) abuf->fields.fmt_18_div.f
 601   new_pc = SEM_NEXT_PC (sem_arg);
 602
 603 if (NESI (* FLD (f_r2), 0)) {
 604 * FLD (f_r1) = DIVSI (* FLD (f_r1), * FLD (f_r2));
 605   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 606 }
 607
 608 #undef FLD
 609 }
 610   BREAK (sem);
 611
 612   CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
 613 {
 614 #define FLD(f) abuf->fields.fmt_18_div.f
 615   new_pc = SEM_NEXT_PC (sem_arg);
 616
 617 if (NESI (* FLD (f_r2), 0)) {
 618 * FLD (f_r1) = UDIVSI (* FLD (f_r1), * FLD (f_r2));
 619   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 620 }
 621
 622 #undef FLD
 623 }
 624   BREAK (sem);
 625
 626   CASE (sem, INSN_REM) : /* rem $dr,$sr */
 627 {
 628 #define FLD(f) abuf->fields.fmt_18_div.f
 629   new_pc = SEM_NEXT_PC (sem_arg);
 630
 631 if (NESI (* FLD (f_r2), 0)) {
 632 * FLD (f_r1) = MODSI (* FLD (f_r1), * FLD (f_r2));
 633   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 634 }
 635
 636 #undef FLD
 637 }
 638   BREAK (sem);
 639
 640   CASE (sem, INSN_REMU) : /* remu $dr,$sr */
 641 {
 642 #define FLD(f) abuf->fields.fmt_18_div.f
 643   new_pc = SEM_NEXT_PC (sem_arg);
 644
 645 if (NESI (* FLD (f_r2), 0)) {
 646 * FLD (f_r1) = UMODSI (* FLD (f_r1), * FLD (f_r2));
 647   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 648 }
 649
 650 #undef FLD
 651 }
 652   BREAK (sem);
 653
 654   CASE (sem, INSN_DIVH) : /* divh $dr,$sr */
 655 {
 656 #define FLD(f) abuf->fields.fmt_18_div.f
 657   new_pc = SEM_NEXT_PC (sem_arg);
 658
 659 if (NESI (* FLD (f_r2), 0)) {
 660 * FLD (f_r1) = DIVSI (EXTHISI (TRUNCSIHI (* FLD (f_r1))), * FLD (f_r2));
 661   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 662 }
 663
 664 #undef FLD
 665 }
 666   BREAK (sem);
 667
 668   CASE (sem, INSN_JL) : /* jl $sr */
 669 {
 670 #define FLD(f) abuf->fields.fmt_19_jl.f
 671   new_pc = SEM_NEXT_PC (sem_arg);
 672
 673 do {
 674   SI temp1;SI temp0;
 675   temp0 = ADDSI (ANDSI (CPU (h_pc), -4), 4);
 676   temp1 = * FLD (f_r2);
 677   CPU (h_gr[14]) = temp0;
 678   TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
 679   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, temp1));
 680 } while (0);
 681
 682 #undef FLD
 683 }
 684   BREAK (sem);
 685
 686   CASE (sem, INSN_JMP) : /* jmp $sr */
 687 {
 688 #define FLD(f) abuf->fields.fmt_20_jmp.f
 689   new_pc = SEM_NEXT_PC (sem_arg);
 690
 691   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, * FLD (f_r2)));
 692
 693 #undef FLD
 694 }
 695   BREAK (sem);
 696
 697   CASE (sem, INSN_LD) : /* ld $dr,@$sr */
 698 {
 699 #define FLD(f) abuf->fields.fmt_21_ld.f
 700   new_pc = SEM_NEXT_PC (sem_arg);
 701
 702 * FLD (f_r1) = GETMEMSI (current_cpu, * FLD (f_r2));
 703   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 704
 705 #undef FLD
 706 }
 707   BREAK (sem);
 708
 709   CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
 710 {
 711 #define FLD(f) abuf->fields.fmt_22_ld_d.f
 712   new_pc = SEM_NEXT_PC (sem_arg);
 713
 714 * FLD (f_r1) = GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)));
 715   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 716
 717 #undef FLD
 718 }
 719   BREAK (sem);
 720
 721   CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
 722 {
 723 #define FLD(f) abuf->fields.fmt_23_ldb.f
 724   new_pc = SEM_NEXT_PC (sem_arg);
 725
 726 * FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
 727   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 728
 729 #undef FLD
 730 }
 731   BREAK (sem);
 732
 733   CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
 734 {
 735 #define FLD(f) abuf->fields.fmt_24_ldb_d.f
 736   new_pc = SEM_NEXT_PC (sem_arg);
 737
 738 * FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
 739   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 740
 741 #undef FLD
 742 }
 743   BREAK (sem);
 744
 745   CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
 746 {
 747 #define FLD(f) abuf->fields.fmt_25_ldh.f
 748   new_pc = SEM_NEXT_PC (sem_arg);
 749
 750 * FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
 751   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 752
 753 #undef FLD
 754 }
 755   BREAK (sem);
 756
 757   CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
 758 {
 759 #define FLD(f) abuf->fields.fmt_26_ldh_d.f
 760   new_pc = SEM_NEXT_PC (sem_arg);
 761
 762 * FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
 763   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 764
 765 #undef FLD
 766 }
 767   BREAK (sem);
 768
 769   CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
 770 {
 771 #define FLD(f) abuf->fields.fmt_23_ldb.f
 772   new_pc = SEM_NEXT_PC (sem_arg);
 773
 774 * FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
 775   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 776
 777 #undef FLD
 778 }
 779   BREAK (sem);
 780
 781   CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
 782 {
 783 #define FLD(f) abuf->fields.fmt_24_ldb_d.f
 784   new_pc = SEM_NEXT_PC (sem_arg);
 785
 786 * FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
 787   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 788
 789 #undef FLD
 790 }
 791   BREAK (sem);
 792
 793   CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
 794 {
 795 #define FLD(f) abuf->fields.fmt_25_ldh.f
 796   new_pc = SEM_NEXT_PC (sem_arg);
 797
 798 * FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
 799   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 800
 801 #undef FLD
 802 }
 803   BREAK (sem);
 804
 805   CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
 806 {
 807 #define FLD(f) abuf->fields.fmt_26_ldh_d.f
 808   new_pc = SEM_NEXT_PC (sem_arg);
 809
 810 * FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
 811   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 812
 813 #undef FLD
 814 }
 815   BREAK (sem);
 816
 817   CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
 818 {
 819 #define FLD(f) abuf->fields.fmt_21_ld.f
 820   new_pc = SEM_NEXT_PC (sem_arg);
 821
 822 do {
 823   SI temp1;SI temp0;
 824   temp0 = GETMEMSI (current_cpu, * FLD (f_r2));
 825   temp1 = ADDSI (* FLD (f_r2), 4);
 826 * FLD (f_r1) = temp0;
 827   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 828 * FLD (f_r2) = temp1;
 829   TRACE_RESULT (current_cpu, "sr", 'x', * FLD (f_r2));
 830 } while (0);
 831
 832 #undef FLD
 833 }
 834   BREAK (sem);
 835
 836   CASE (sem, INSN_LD24) : /* ld24 $dr,#$uimm24 */
 837 {
 838 #define FLD(f) abuf->fields.fmt_27_ld24.f
 839   new_pc = SEM_NEXT_PC (sem_arg);
 840
 841 * FLD (f_r1) = FLD (f_uimm24);
 842   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 843
 844 #undef FLD
 845 }
 846   BREAK (sem);
 847
 848   CASE (sem, INSN_LDI8) : /* ldi $dr,#$simm8 */
 849 {
 850 #define FLD(f) abuf->fields.fmt_28_ldi8.f
 851   new_pc = SEM_NEXT_PC (sem_arg);
 852
 853 * FLD (f_r1) = FLD (f_simm8);
 854   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 855
 856 #undef FLD
 857 }
 858   BREAK (sem);
 859
 860   CASE (sem, INSN_LDI16) : /* ldi $dr,$slo16 */
 861 {
 862 #define FLD(f) abuf->fields.fmt_29_ldi16.f
 863   new_pc = SEM_NEXT_PC (sem_arg);
 864
 865 * FLD (f_r1) = FLD (f_simm16);
 866   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 867
 868 #undef FLD
 869 }
 870   BREAK (sem);
 871
 872   CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
 873 {
 874 #define FLD(f) abuf->fields.fmt_0_add.f
 875   new_pc = SEM_NEXT_PC (sem_arg);
 876
 877 do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
 878
 879 #undef FLD
 880 }
 881   BREAK (sem);
 882
 883   CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */
 884 {
 885 #define FLD(f) abuf->fields.fmt_30_machi.f
 886   new_pc = SEM_NEXT_PC (sem_arg);
 887
 888   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
 889   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 890
 891 #undef FLD
 892 }
 893   BREAK (sem);
 894
 895   CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */
 896 {
 897 #define FLD(f) abuf->fields.fmt_30_machi.f
 898   new_pc = SEM_NEXT_PC (sem_arg);
 899
 900   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
 901   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 902
 903 #undef FLD
 904 }
 905   BREAK (sem);
 906
 907   CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */
 908 {
 909 #define FLD(f) abuf->fields.fmt_30_machi.f
 910   new_pc = SEM_NEXT_PC (sem_arg);
 911
 912   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
 913   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 914
 915 #undef FLD
 916 }
 917   BREAK (sem);
 918
 919   CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */
 920 {
 921 #define FLD(f) abuf->fields.fmt_30_machi.f
 922   new_pc = SEM_NEXT_PC (sem_arg);
 923
 924   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
 925   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 926
 927 #undef FLD
 928 }
 929   BREAK (sem);
 930
 931   CASE (sem, INSN_MUL) : /* mul $dr,$sr */
 932 {
 933 #define FLD(f) abuf->fields.fmt_0_add.f
 934   new_pc = SEM_NEXT_PC (sem_arg);
 935
 936 * FLD (f_r1) = MULSI (* FLD (f_r1), * FLD (f_r2));
 937   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 938
 939 #undef FLD
 940 }
 941   BREAK (sem);
 942
 943   CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */
 944 {
 945 #define FLD(f) abuf->fields.fmt_15_cmp.f
 946   new_pc = SEM_NEXT_PC (sem_arg);
 947
 948   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 16), 16);
 949   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 950
 951 #undef FLD
 952 }
 953   BREAK (sem);
 954
 955   CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */
 956 {
 957 #define FLD(f) abuf->fields.fmt_15_cmp.f
 958   new_pc = SEM_NEXT_PC (sem_arg);
 959
 960   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 16), 16);
 961   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 962
 963 #undef FLD
 964 }
 965   BREAK (sem);
 966
 967   CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */
 968 {
 969 #define FLD(f) abuf->fields.fmt_15_cmp.f
 970   new_pc = SEM_NEXT_PC (sem_arg);
 971
 972   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 8), 8);
 973   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 974
 975 #undef FLD
 976 }
 977   BREAK (sem);
 978
 979   CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */
 980 {
 981 #define FLD(f) abuf->fields.fmt_15_cmp.f
 982   new_pc = SEM_NEXT_PC (sem_arg);
 983
 984   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 8), 8);
 985   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 986
 987 #undef FLD
 988 }
 989   BREAK (sem);
 990
 991   CASE (sem, INSN_MV) : /* mv $dr,$sr */
 992 {
 993 #define FLD(f) abuf->fields.fmt_31_mv.f
 994   new_pc = SEM_NEXT_PC (sem_arg);
 995
 996 * FLD (f_r1) = * FLD (f_r2);
 997   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 998
 999 #undef FLD
1000 }
1001   BREAK (sem);
1002
1003   CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */
1004 {
1005 #define FLD(f) abuf->fields.fmt_32_mvfachi.f
1006   new_pc = SEM_NEXT_PC (sem_arg);
1007
1008 * FLD (f_r1) = TRUNCDISI (SRADI (CPU (h_accum), 32));
1009   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1010
1011 #undef FLD
1012 }
1013   BREAK (sem);
1014
1015   CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */
1016 {
1017 #define FLD(f) abuf->fields.fmt_32_mvfachi.f
1018   new_pc = SEM_NEXT_PC (sem_arg);
1019
1020 * FLD (f_r1) = TRUNCDISI (CPU (h_accum));
1021   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1022
1023 #undef FLD
1024 }
1025   BREAK (sem);
1026
1027   CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */
1028 {
1029 #define FLD(f) abuf->fields.fmt_32_mvfachi.f
1030   new_pc = SEM_NEXT_PC (sem_arg);
1031
1032 * FLD (f_r1) = TRUNCDISI (SRADI (CPU (h_accum), 16));
1033   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1034
1035 #undef FLD
1036 }
1037   BREAK (sem);
1038
1039   CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
1040 {
1041 #define FLD(f) abuf->fields.fmt_33_mvfc.f
1042   new_pc = SEM_NEXT_PC (sem_arg);
1043
1044 * FLD (f_r1) = m32r_h_cr_get (current_cpu, FLD (f_r2));
1045   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1046
1047 #undef FLD
1048 }
1049   BREAK (sem);
1050
1051   CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */
1052 {
1053 #define FLD(f) abuf->fields.fmt_34_mvtachi.f
1054   new_pc = SEM_NEXT_PC (sem_arg);
1055
1056   CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (f_r1)), 32));
1057   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
1058
1059 #undef FLD
1060 }
1061   BREAK (sem);
1062
1063   CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */
1064 {
1065 #define FLD(f) abuf->fields.fmt_34_mvtachi.f
1066   new_pc = SEM_NEXT_PC (sem_arg);
1067
1068   CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0xffffffff, 0)), EXTSIDI (* FLD (f_r1)));
1069   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
1070
1071 #undef FLD
1072 }
1073   BREAK (sem);
1074
1075   CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
1076 {
1077 #define FLD(f) abuf->fields.fmt_35_mvtc.f
1078   new_pc = SEM_NEXT_PC (sem_arg);
1079
1080 m32r_h_cr_set (current_cpu, FLD (f_r1), * FLD (f_r2));
1081   TRACE_RESULT (current_cpu, "dcr", 'x', m32r_h_cr_get (current_cpu, FLD (f_r1)));
1082
1083 #undef FLD
1084 }
1085   BREAK (sem);
1086
1087   CASE (sem, INSN_NEG) : /* neg $dr,$sr */
1088 {
1089 #define FLD(f) abuf->fields.fmt_31_mv.f
1090   new_pc = SEM_NEXT_PC (sem_arg);
1091
1092 * FLD (f_r1) = NEGSI (* FLD (f_r2));
1093   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1094
1095 #undef FLD
1096 }
1097   BREAK (sem);
1098
1099   CASE (sem, INSN_NOP) : /* nop */
1100 {
1101 #define FLD(f) abuf->fields.fmt_36_nop.f
1102   new_pc = SEM_NEXT_PC (sem_arg);
1103
1104 PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
1105
1106 #undef FLD
1107 }
1108   BREAK (sem);
1109
1110   CASE (sem, INSN_NOT) : /* not $dr,$sr */
1111 {
1112 #define FLD(f) abuf->fields.fmt_31_mv.f
1113   new_pc = SEM_NEXT_PC (sem_arg);
1114
1115 * FLD (f_r1) = INVSI (* FLD (f_r2));
1116   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1117
1118 #undef FLD
1119 }
1120   BREAK (sem);
1121
1122   CASE (sem, INSN_RAC) : /* rac */
1123 {
1124 #define FLD(f) abuf->fields.fmt_37_rac.f
1125   new_pc = SEM_NEXT_PC (sem_arg);
1126
1127 do {
1128   DI tmp_tmp1;
1129   tmp_tmp1 = SLLDI (CPU (h_accum), 1);
1130   tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
1131   CPU (h_accum) = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
1132   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
1133 } while (0);
1134
1135 #undef FLD
1136 }
1137   BREAK (sem);
1138
1139   CASE (sem, INSN_RACH) : /* rach */
1140 {
1141 #define FLD(f) abuf->fields.fmt_37_rac.f
1142   new_pc = SEM_NEXT_PC (sem_arg);
1143
1144 do {
1145   DI tmp_tmp1;
1146   tmp_tmp1 = ANDDI (CPU (h_accum), MAKEDI (16777215, 0xffffffff));
1147 if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
1148   tmp_tmp1 = MAKEDI (16383, 0x80000000);
1149 } else {
1150 if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
1151   tmp_tmp1 = MAKEDI (16760832, 0);
1152 } else {
1153   tmp_tmp1 = ANDDI (ADDDI (CPU (h_accum), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
1154 }
1155 }
1156   tmp_tmp1 = SLLDI (tmp_tmp1, 1);
1157   CPU (h_accum) = SRADI (SLLDI (tmp_tmp1, 7), 7);
1158   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
1159 } while (0);
1160
1161 #undef FLD
1162 }
1163   BREAK (sem);
1164
1165   CASE (sem, INSN_RTE) : /* rte */
1166 {
1167 #define FLD(f) abuf->fields.fmt_38_rte.f
1168   new_pc = SEM_NEXT_PC (sem_arg);
1169
1170 do {
1171   CPU (h_sm) = CPU (h_bsm);
1172   TRACE_RESULT (current_cpu, "h-sm-0", 'x', CPU (h_sm));
1173   CPU (h_ie) = CPU (h_bie);
1174   TRACE_RESULT (current_cpu, "h-ie-0", 'x', CPU (h_ie));
1175   CPU (h_cond) = CPU (h_bcond);
1176   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
1177   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, CPU (h_bpc)));
1178   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
1179 } while (0);
1180
1181 #undef FLD
1182 }
1183   BREAK (sem);
1184
1185   CASE (sem, INSN_SETH) : /* seth $dr,#$hi16 */
1186 {
1187 #define FLD(f) abuf->fields.fmt_39_seth.f
1188   new_pc = SEM_NEXT_PC (sem_arg);
1189
1190 * FLD (f_r1) = SLLSI (FLD (f_hi16), 16);
1191   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1192
1193 #undef FLD
1194 }
1195   BREAK (sem);
1196
1197   CASE (sem, INSN_SLL) : /* sll $dr,$sr */
1198 {
1199 #define FLD(f) abuf->fields.fmt_0_add.f
1200   new_pc = SEM_NEXT_PC (sem_arg);
1201
1202 * FLD (f_r1) = SLLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
1203   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1204
1205 #undef FLD
1206 }
1207   BREAK (sem);
1208
1209   CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,#$simm16 */
1210 {
1211 #define FLD(f) abuf->fields.fmt_5_addv3.f
1212   new_pc = SEM_NEXT_PC (sem_arg);
1213
1214 * FLD (f_r1) = SLLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
1215   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1216
1217 #undef FLD
1218 }
1219   BREAK (sem);
1220
1221   CASE (sem, INSN_SLLI) : /* slli $dr,#$uimm5 */
1222 {
1223 #define FLD(f) abuf->fields.fmt_40_slli.f
1224   new_pc = SEM_NEXT_PC (sem_arg);
1225
1226 * FLD (f_r1) = SLLSI (* FLD (f_r1), FLD (f_uimm5));
1227   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1228
1229 #undef FLD
1230 }
1231   BREAK (sem);
1232
1233   CASE (sem, INSN_SRA) : /* sra $dr,$sr */
1234 {
1235 #define FLD(f) abuf->fields.fmt_0_add.f
1236   new_pc = SEM_NEXT_PC (sem_arg);
1237
1238 * FLD (f_r1) = SRASI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
1239   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1240
1241 #undef FLD
1242 }
1243   BREAK (sem);
1244
1245   CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,#$simm16 */
1246 {
1247 #define FLD(f) abuf->fields.fmt_5_addv3.f
1248   new_pc = SEM_NEXT_PC (sem_arg);
1249
1250 * FLD (f_r1) = SRASI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
1251   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1252
1253 #undef FLD
1254 }
1255   BREAK (sem);
1256
1257   CASE (sem, INSN_SRAI) : /* srai $dr,#$uimm5 */
1258 {
1259 #define FLD(f) abuf->fields.fmt_40_slli.f
1260   new_pc = SEM_NEXT_PC (sem_arg);
1261
1262 * FLD (f_r1) = SRASI (* FLD (f_r1), FLD (f_uimm5));
1263   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1264
1265 #undef FLD
1266 }
1267   BREAK (sem);
1268
1269   CASE (sem, INSN_SRL) : /* srl $dr,$sr */
1270 {
1271 #define FLD(f) abuf->fields.fmt_0_add.f
1272   new_pc = SEM_NEXT_PC (sem_arg);
1273
1274 * FLD (f_r1) = SRLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
1275   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1276
1277 #undef FLD
1278 }
1279   BREAK (sem);
1280
1281   CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,#$simm16 */
1282 {
1283 #define FLD(f) abuf->fields.fmt_5_addv3.f
1284   new_pc = SEM_NEXT_PC (sem_arg);
1285
1286 * FLD (f_r1) = SRLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
1287   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1288
1289 #undef FLD
1290 }
1291   BREAK (sem);
1292
1293   CASE (sem, INSN_SRLI) : /* srli $dr,#$uimm5 */
1294 {
1295 #define FLD(f) abuf->fields.fmt_40_slli.f
1296   new_pc = SEM_NEXT_PC (sem_arg);
1297
1298 * FLD (f_r1) = SRLSI (* FLD (f_r1), FLD (f_uimm5));
1299   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1300
1301 #undef FLD
1302 }
1303   BREAK (sem);
1304
1305   CASE (sem, INSN_ST) : /* st $src1,@$src2 */
1306 {
1307 #define FLD(f) abuf->fields.fmt_15_cmp.f
1308   new_pc = SEM_NEXT_PC (sem_arg);
1309
1310 SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
1311   TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
1312
1313 #undef FLD
1314 }
1315   BREAK (sem);
1316
1317   CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
1318 {
1319 #define FLD(f) abuf->fields.fmt_41_st_d.f
1320   new_pc = SEM_NEXT_PC (sem_arg);
1321
1322 SETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
1323   TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
1324
1325 #undef FLD
1326 }
1327   BREAK (sem);
1328
1329   CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
1330 {
1331 #define FLD(f) abuf->fields.fmt_15_cmp.f
1332   new_pc = SEM_NEXT_PC (sem_arg);
1333
1334 SETMEMQI (current_cpu, * FLD (f_r2), * FLD (f_r1));
1335   TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMQI (current_cpu, * FLD (f_r2)));
1336
1337 #undef FLD
1338 }
1339   BREAK (sem);
1340
1341   CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
1342 {
1343 #define FLD(f) abuf->fields.fmt_41_st_d.f
1344   new_pc = SEM_NEXT_PC (sem_arg);
1345
1346 SETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
1347   TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
1348
1349 #undef FLD
1350 }
1351   BREAK (sem);
1352
1353   CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
1354 {
1355 #define FLD(f) abuf->fields.fmt_15_cmp.f
1356   new_pc = SEM_NEXT_PC (sem_arg);
1357
1358 SETMEMHI (current_cpu, * FLD (f_r2), * FLD (f_r1));
1359   TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMHI (current_cpu, * FLD (f_r2)));
1360
1361 #undef FLD
1362 }
1363   BREAK (sem);
1364
1365   CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
1366 {
1367 #define FLD(f) abuf->fields.fmt_41_st_d.f
1368   new_pc = SEM_NEXT_PC (sem_arg);
1369
1370 SETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
1371   TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
1372
1373 #undef FLD
1374 }
1375   BREAK (sem);
1376
1377   CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
1378 {
1379 #define FLD(f) abuf->fields.fmt_15_cmp.f
1380   new_pc = SEM_NEXT_PC (sem_arg);
1381
1382 do {
1383 * FLD (f_r2) = ADDSI (* FLD (f_r2), 4);
1384   TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2));
1385 SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
1386   TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
1387 } while (0);
1388
1389 #undef FLD
1390 }
1391   BREAK (sem);
1392
1393   CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
1394 {
1395 #define FLD(f) abuf->fields.fmt_15_cmp.f
1396   new_pc = SEM_NEXT_PC (sem_arg);
1397
1398 do {
1399 * FLD (f_r2) = SUBSI (* FLD (f_r2), 4);
1400   TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2));
1401 SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
1402   TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
1403 } while (0);
1404
1405 #undef FLD
1406 }
1407   BREAK (sem);
1408
1409   CASE (sem, INSN_SUB) : /* sub $dr,$sr */
1410 {
1411 #define FLD(f) abuf->fields.fmt_0_add.f
1412   new_pc = SEM_NEXT_PC (sem_arg);
1413
1414 * FLD (f_r1) = SUBSI (* FLD (f_r1), * FLD (f_r2));
1415   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1416
1417 #undef FLD
1418 }
1419   BREAK (sem);
1420
1421   CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
1422 {
1423 #define FLD(f) abuf->fields.fmt_0_add.f
1424   new_pc = SEM_NEXT_PC (sem_arg);
1425
1426 do {
1427   BI temp1;SI temp0;
1428   temp0 = SUBSI (* FLD (f_r1), * FLD (f_r2));
1429   temp1 = SUBOFSI (* FLD (f_r1), * FLD (f_r2), 0);
1430 * FLD (f_r1) = temp0;
1431   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1432   CPU (h_cond) = temp1;
1433   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
1434 } while (0);
1435
1436 #undef FLD
1437 }
1438   BREAK (sem);
1439
1440   CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
1441 {
1442 #define FLD(f) abuf->fields.fmt_6_addx.f
1443   new_pc = SEM_NEXT_PC (sem_arg);
1444
1445 do {
1446   BI temp1;SI temp0;
1447   temp0 = SUBCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
1448   temp1 = SUBCFSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
1449 * FLD (f_r1) = temp0;
1450   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1451   CPU (h_cond) = temp1;
1452   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
1453 } while (0);
1454
1455 #undef FLD
1456 }
1457   BREAK (sem);
1458
1459   CASE (sem, INSN_TRAP) : /* trap #$uimm4 */
1460 {
1461 #define FLD(f) abuf->fields.fmt_42_trap.f
1462   new_pc = SEM_NEXT_PC (sem_arg);
1463
1464 do_trap (current_cpu, FLD (f_uimm4));
1465
1466 #undef FLD
1467 }
1468   BREAK (sem);
1469
1470   CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
1471 {
1472 #define FLD(f) abuf->fields.fmt_15_cmp.f
1473   new_pc = SEM_NEXT_PC (sem_arg);
1474
1475 do_unlock (current_cpu, * FLD (f_r1), * FLD (f_r2));
1476
1477 #undef FLD
1478 }
1479   BREAK (sem);
1480
1481
1482     }
1483   ENDSWITCH (sem) /* End of semantic switch.  */
1484
1485   PC = new_pc;
1486 }
1487
1488 #endif /* DEFINE_SWITCH */