sim/m32r/sem-switch.c

   1 /* Simulator instruction semantics for m32r.
   2
   3 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   4
   5 This file is part of the GNU Simulators.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20
  21 */
  22
  23 #ifdef DEFINE_LABELS
  24 #undef DEFINE_LABELS
  25
  26
  27   /* The labels have the case they have because the enum of insn types
  28      is all uppercase and in the non-stdc case the insn symbol is built
  29      into the enum name.
  30
  31      The order here must match the order in m32r_decode_vars in decode.c.  */
  32
  33   static void *labels[] = {
  34     && case_sem_INSN_ILLEGAL,
  35     && case_sem_INSN_ADD,
  36     && case_sem_INSN_ADD3,
  37     && case_sem_INSN_AND,
  38     && case_sem_INSN_AND3,
  39     && case_sem_INSN_OR,
  40     && case_sem_INSN_OR3,
  41     && case_sem_INSN_XOR,
  42     && case_sem_INSN_XOR3,
  43     && case_sem_INSN_ADDI,
  44     && case_sem_INSN_ADDV,
  45     && case_sem_INSN_ADDV3,
  46     && case_sem_INSN_ADDX,
  47     && case_sem_INSN_BC8,
  48     && case_sem_INSN_BC24,
  49     && case_sem_INSN_BEQ,
  50     && case_sem_INSN_BEQZ,
  51     && case_sem_INSN_BGEZ,
  52     && case_sem_INSN_BGTZ,
  53     && case_sem_INSN_BLEZ,
  54     && case_sem_INSN_BLTZ,
  55     && case_sem_INSN_BNEZ,
  56     && case_sem_INSN_BL8,
  57     && case_sem_INSN_BL24,
  58     && case_sem_INSN_BNC8,
  59     && case_sem_INSN_BNC24,
  60     && case_sem_INSN_BNE,
  61     && case_sem_INSN_BRA8,
  62     && case_sem_INSN_BRA24,
  63     && case_sem_INSN_CMP,
  64     && case_sem_INSN_CMPI,
  65     && case_sem_INSN_CMPU,
  66     && case_sem_INSN_CMPUI,
  67     && case_sem_INSN_DIV,
  68     && case_sem_INSN_DIVU,
  69     && case_sem_INSN_REM,
  70     && case_sem_INSN_REMU,
  71     && case_sem_INSN_JL,
  72     && case_sem_INSN_JMP,
  73     && case_sem_INSN_LD,
  74     && case_sem_INSN_LD_D,
  75     && case_sem_INSN_LDB,
  76     && case_sem_INSN_LDB_D,
  77     && case_sem_INSN_LDH,
  78     && case_sem_INSN_LDH_D,
  79     && case_sem_INSN_LDUB,
  80     && case_sem_INSN_LDUB_D,
  81     && case_sem_INSN_LDUH,
  82     && case_sem_INSN_LDUH_D,
  83     && case_sem_INSN_LD_PLUS,
  84     && case_sem_INSN_LD24,
  85     && case_sem_INSN_LDI8,
  86     && case_sem_INSN_LDI16,
  87     && case_sem_INSN_LOCK,
  88     && case_sem_INSN_MACHI,
  89     && case_sem_INSN_MACLO,
  90     && case_sem_INSN_MACWHI,
  91     && case_sem_INSN_MACWLO,
  92     && case_sem_INSN_MUL,
  93     && case_sem_INSN_MULHI,
  94     && case_sem_INSN_MULLO,
  95     && case_sem_INSN_MULWHI,
  96     && case_sem_INSN_MULWLO,
  97     && case_sem_INSN_MV,
  98     && case_sem_INSN_MVFACHI,
  99     && case_sem_INSN_MVFACLO,
 100     && case_sem_INSN_MVFACMI,
 101     && case_sem_INSN_MVFC,
 102     && case_sem_INSN_MVTACHI,
 103     && case_sem_INSN_MVTACLO,
 104     && case_sem_INSN_MVTC,
 105     && case_sem_INSN_NEG,
 106     && case_sem_INSN_NOP,
 107     && case_sem_INSN_NOT,
 108     && case_sem_INSN_RAC,
 109     && case_sem_INSN_RACH,
 110     && case_sem_INSN_RTE,
 111     && case_sem_INSN_SETH,
 112     && case_sem_INSN_SLL,
 113     && case_sem_INSN_SLL3,
 114     && case_sem_INSN_SLLI,
 115     && case_sem_INSN_SRA,
 116     && case_sem_INSN_SRA3,
 117     && case_sem_INSN_SRAI,
 118     && case_sem_INSN_SRL,
 119     && case_sem_INSN_SRL3,
 120     && case_sem_INSN_SRLI,
 121     && case_sem_INSN_ST,
 122     && case_sem_INSN_ST_D,
 123     && case_sem_INSN_STB,
 124     && case_sem_INSN_STB_D,
 125     && case_sem_INSN_STH,
 126     && case_sem_INSN_STH_D,
 127     && case_sem_INSN_ST_PLUS,
 128     && case_sem_INSN_ST_MINUS,
 129     && case_sem_INSN_SUB,
 130     && case_sem_INSN_SUBV,
 131     && case_sem_INSN_SUBX,
 132     && case_sem_INSN_TRAP,
 133     && case_sem_INSN_UNLOCK,
 134     0
 135   };
 136   extern DECODE *m32r_decode_vars[];
 137   int i;
 138
 139   for (i = 0; m32r_decode_vars[i] != 0; ++i)
 140     m32r_decode_vars[i]->semantic_lab = labels[i];
 141
 142 #endif /* DEFINE_LABELS */
 143
 144 #ifdef DEFINE_SWITCH
 145 #undef DEFINE_SWITCH
 146
 147 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
 148    off frills like tracing and profiling.  */
 149 /* FIXME: A better way would be to have TRACE_RESULT check for something
 150    that can cause it to be optimized out.  */
 151
 152 #if FAST_P
 153 #undef TRACE_RESULT
 154 #define TRACE_RESULT(cpu, name, type, val)
 155 #endif
 156
 157 #undef GET_ATTR
 158 #define GET_ATTR(cpu, num, attr) CGEN_INSN_ATTR (abuf->opcode, CGEN_INSN_##attr)
 159
 160 {
 161   SEM_ARG sem_arg = sc;
 162   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 163   CIA new_pc = SEM_NEXT_PC (sem_arg);
 164
 165   SWITCH (sem, sem_arg->semantic.sem_case)
 166     {
 167
 168   CASE (sem, INSN_ILLEGAL) :
 169 {
 170   sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, NULL_CIA/*FIXME*/,
 171                    sim_stopped, SIM_SIGILL);
 172   BREAK (sem);
 173 }
 174
 175   CASE (sem, INSN_ADD) : /* add $dr,$sr */
 176 {
 177 #define FLD(f) abuf->fields.fmt_0_add.f
 178 * FLD (f_r1) = ADDSI (* FLD (f_r1), * FLD (f_r2));
 179   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 180 #undef FLD
 181 }
 182   BREAK (sem);
 183
 184   CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$slo16 */
 185 {
 186 #define FLD(f) abuf->fields.fmt_1_add3.f
 187 * FLD (f_r1) = ADDSI (* FLD (f_r2), FLD (f_simm16));
 188   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 189 #undef FLD
 190 }
 191   BREAK (sem);
 192
 193   CASE (sem, INSN_AND) : /* and $dr,$sr */
 194 {
 195 #define FLD(f) abuf->fields.fmt_0_add.f
 196 * FLD (f_r1) = ANDSI (* FLD (f_r1), * FLD (f_r2));
 197   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 198 #undef FLD
 199 }
 200   BREAK (sem);
 201
 202   CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
 203 {
 204 #define FLD(f) abuf->fields.fmt_2_and3.f
 205 * FLD (f_r1) = ANDSI (* FLD (f_r2), FLD (f_uimm16));
 206   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 207 #undef FLD
 208 }
 209   BREAK (sem);
 210
 211   CASE (sem, INSN_OR) : /* or $dr,$sr */
 212 {
 213 #define FLD(f) abuf->fields.fmt_0_add.f
 214 * FLD (f_r1) = ORSI (* FLD (f_r1), * FLD (f_r2));
 215   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 216 #undef FLD
 217 }
 218   BREAK (sem);
 219
 220   CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$ulo16 */
 221 {
 222 #define FLD(f) abuf->fields.fmt_3_or3.f
 223 * FLD (f_r1) = ORSI (* FLD (f_r2), FLD (f_uimm16));
 224   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 225 #undef FLD
 226 }
 227   BREAK (sem);
 228
 229   CASE (sem, INSN_XOR) : /* xor $dr,$sr */
 230 {
 231 #define FLD(f) abuf->fields.fmt_0_add.f
 232 * FLD (f_r1) = XORSI (* FLD (f_r1), * FLD (f_r2));
 233   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 234 #undef FLD
 235 }
 236   BREAK (sem);
 237
 238   CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
 239 {
 240 #define FLD(f) abuf->fields.fmt_2_and3.f
 241 * FLD (f_r1) = XORSI (* FLD (f_r2), FLD (f_uimm16));
 242   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 243 #undef FLD
 244 }
 245   BREAK (sem);
 246
 247   CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
 248 {
 249 #define FLD(f) abuf->fields.fmt_4_addi.f
 250 * FLD (f_r1) = ADDSI (* FLD (f_r1), FLD (f_simm8));
 251   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 252 #undef FLD
 253 }
 254   BREAK (sem);
 255
 256   CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
 257 {
 258 #define FLD(f) abuf->fields.fmt_0_add.f
 259 do {
 260   BI temp1;SI temp0;
 261   temp0 = ADDSI (* FLD (f_r1), * FLD (f_r2));
 262   temp1 = ADDOFSI (* FLD (f_r1), * FLD (f_r2), 0);
 263 * FLD (f_r1) = temp0;
 264   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 265   CPU (h_cond) = temp1;
 266   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 267 } while (0);
 268 #undef FLD
 269 }
 270   BREAK (sem);
 271
 272   CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
 273 {
 274 #define FLD(f) abuf->fields.fmt_5_addv3.f
 275 do {
 276   BI temp1;SI temp0;
 277   temp0 = ADDSI (* FLD (f_r2), FLD (f_simm16));
 278   temp1 = ADDOFSI (* FLD (f_r2), FLD (f_simm16), 0);
 279 * FLD (f_r1) = temp0;
 280   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 281   CPU (h_cond) = temp1;
 282   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 283 } while (0);
 284 #undef FLD
 285 }
 286   BREAK (sem);
 287
 288   CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
 289 {
 290 #define FLD(f) abuf->fields.fmt_6_addx.f
 291 do {
 292   BI temp1;SI temp0;
 293   temp0 = ADDCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
 294   temp1 = ADDCFSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
 295 * FLD (f_r1) = temp0;
 296   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 297   CPU (h_cond) = temp1;
 298   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 299 } while (0);
 300 #undef FLD
 301 }
 302   BREAK (sem);
 303
 304   CASE (sem, INSN_BC8) : /* bc $disp8 */
 305 {
 306 #define FLD(f) abuf->fields.fmt_7_bc8.f
 307 if (CPU (h_cond)) {
 308   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
 309 }
 310 #undef FLD
 311 }
 312   BREAK (sem);
 313
 314   CASE (sem, INSN_BC24) : /* bc $disp24 */
 315 {
 316 #define FLD(f) abuf->fields.fmt_8_bc24.f
 317 if (CPU (h_cond)) {
 318   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
 319 }
 320 #undef FLD
 321 }
 322   BREAK (sem);
 323
 324   CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
 325 {
 326 #define FLD(f) abuf->fields.fmt_9_beq.f
 327 if (EQSI (* FLD (f_r1), * FLD (f_r2))) {
 328   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 329 }
 330 #undef FLD
 331 }
 332   BREAK (sem);
 333
 334   CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
 335 {
 336 #define FLD(f) abuf->fields.fmt_10_beqz.f
 337 if (EQSI (* FLD (f_r2), 0)) {
 338   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 339 }
 340 #undef FLD
 341 }
 342   BREAK (sem);
 343
 344   CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
 345 {
 346 #define FLD(f) abuf->fields.fmt_10_beqz.f
 347 if (GESI (* FLD (f_r2), 0)) {
 348   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 349 }
 350 #undef FLD
 351 }
 352   BREAK (sem);
 353
 354   CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
 355 {
 356 #define FLD(f) abuf->fields.fmt_10_beqz.f
 357 if (GTSI (* FLD (f_r2), 0)) {
 358   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 359 }
 360 #undef FLD
 361 }
 362   BREAK (sem);
 363
 364   CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
 365 {
 366 #define FLD(f) abuf->fields.fmt_10_beqz.f
 367 if (LESI (* FLD (f_r2), 0)) {
 368   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 369 }
 370 #undef FLD
 371 }
 372   BREAK (sem);
 373
 374   CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
 375 {
 376 #define FLD(f) abuf->fields.fmt_10_beqz.f
 377 if (LTSI (* FLD (f_r2), 0)) {
 378   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 379 }
 380 #undef FLD
 381 }
 382   BREAK (sem);
 383
 384   CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
 385 {
 386 #define FLD(f) abuf->fields.fmt_10_beqz.f
 387 if (NESI (* FLD (f_r2), 0)) {
 388   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 389 }
 390 #undef FLD
 391 }
 392   BREAK (sem);
 393
 394   CASE (sem, INSN_BL8) : /* bl $disp8 */
 395 {
 396 #define FLD(f) abuf->fields.fmt_11_bl8.f
 397 do {
 398   CPU (h_gr[14]) = ADDSI (ANDSI (CPU (h_pc), -4), 4);
 399   TRACE_RESULT (current_cpu, "h-gr", 'x', CPU (h_gr[14]));
 400   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
 401 } while (0);
 402 #undef FLD
 403 }
 404   BREAK (sem);
 405
 406   CASE (sem, INSN_BL24) : /* bl $disp24 */
 407 {
 408 #define FLD(f) abuf->fields.fmt_12_bl24.f
 409 do {
 410   CPU (h_gr[14]) = ADDSI (CPU (h_pc), 4);
 411   TRACE_RESULT (current_cpu, "h-gr", 'x', CPU (h_gr[14]));
 412   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
 413 } while (0);
 414 #undef FLD
 415 }
 416   BREAK (sem);
 417
 418   CASE (sem, INSN_BNC8) : /* bnc $disp8 */
 419 {
 420 #define FLD(f) abuf->fields.fmt_7_bc8.f
 421 if (NOTBI (CPU (h_cond))) {
 422   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
 423 }
 424 #undef FLD
 425 }
 426   BREAK (sem);
 427
 428   CASE (sem, INSN_BNC24) : /* bnc $disp24 */
 429 {
 430 #define FLD(f) abuf->fields.fmt_8_bc24.f
 431 if (NOTBI (CPU (h_cond))) {
 432   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
 433 }
 434 #undef FLD
 435 }
 436   BREAK (sem);
 437
 438   CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
 439 {
 440 #define FLD(f) abuf->fields.fmt_9_beq.f
 441 if (NESI (* FLD (f_r1), * FLD (f_r2))) {
 442   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 443 }
 444 #undef FLD
 445 }
 446   BREAK (sem);
 447
 448   CASE (sem, INSN_BRA8) : /* bra $disp8 */
 449 {
 450 #define FLD(f) abuf->fields.fmt_13_bra8.f
 451   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
 452 #undef FLD
 453 }
 454   BREAK (sem);
 455
 456   CASE (sem, INSN_BRA24) : /* bra $disp24 */
 457 {
 458 #define FLD(f) abuf->fields.fmt_14_bra24.f
 459   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
 460 #undef FLD
 461 }
 462   BREAK (sem);
 463
 464   CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
 465 {
 466 #define FLD(f) abuf->fields.fmt_15_cmp.f
 467   CPU (h_cond) = LTSI (* FLD (f_r1), * FLD (f_r2));
 468   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 469 #undef FLD
 470 }
 471   BREAK (sem);
 472
 473   CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
 474 {
 475 #define FLD(f) abuf->fields.fmt_16_cmpi.f
 476   CPU (h_cond) = LTSI (* FLD (f_r2), FLD (f_simm16));
 477   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 478 #undef FLD
 479 }
 480   BREAK (sem);
 481
 482   CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
 483 {
 484 #define FLD(f) abuf->fields.fmt_15_cmp.f
 485   CPU (h_cond) = LTUSI (* FLD (f_r1), * FLD (f_r2));
 486   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 487 #undef FLD
 488 }
 489   BREAK (sem);
 490
 491   CASE (sem, INSN_CMPUI) : /* cmpui $src2,$uimm16 */
 492 {
 493 #define FLD(f) abuf->fields.fmt_17_cmpui.f
 494   CPU (h_cond) = LTUSI (* FLD (f_r2), FLD (f_uimm16));
 495   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 496 #undef FLD
 497 }
 498   BREAK (sem);
 499
 500   CASE (sem, INSN_DIV) : /* div $dr,$sr */
 501 {
 502 #define FLD(f) abuf->fields.fmt_18_div.f
 503 if (NESI (* FLD (f_r2), 0)) {
 504 * FLD (f_r1) = DIVSI (* FLD (f_r1), * FLD (f_r2));
 505   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 506 }
 507 #undef FLD
 508 }
 509   BREAK (sem);
 510
 511   CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
 512 {
 513 #define FLD(f) abuf->fields.fmt_18_div.f
 514 if (NESI (* FLD (f_r2), 0)) {
 515 * FLD (f_r1) = UDIVSI (* FLD (f_r1), * FLD (f_r2));
 516   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 517 }
 518 #undef FLD
 519 }
 520   BREAK (sem);
 521
 522   CASE (sem, INSN_REM) : /* rem $dr,$sr */
 523 {
 524 #define FLD(f) abuf->fields.fmt_18_div.f
 525 if (NESI (* FLD (f_r2), 0)) {
 526 * FLD (f_r1) = MODSI (* FLD (f_r1), * FLD (f_r2));
 527   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 528 }
 529 #undef FLD
 530 }
 531   BREAK (sem);
 532
 533   CASE (sem, INSN_REMU) : /* remu $dr,$sr */
 534 {
 535 #define FLD(f) abuf->fields.fmt_18_div.f
 536 if (NESI (* FLD (f_r2), 0)) {
 537 * FLD (f_r1) = UMODSI (* FLD (f_r1), * FLD (f_r2));
 538   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 539 }
 540 #undef FLD
 541 }
 542   BREAK (sem);
 543
 544   CASE (sem, INSN_JL) : /* jl $sr */
 545 {
 546 #define FLD(f) abuf->fields.fmt_19_jl.f
 547 do {
 548   USI temp1;SI temp0;
 549   temp0 = ADDSI (ANDSI (CPU (h_pc), -4), 4);
 550   temp1 = * FLD (f_r2);
 551   CPU (h_gr[14]) = temp0;
 552   TRACE_RESULT (current_cpu, "h-gr", 'x', CPU (h_gr[14]));
 553   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, temp1));
 554 } while (0);
 555 #undef FLD
 556 }
 557   BREAK (sem);
 558
 559   CASE (sem, INSN_JMP) : /* jmp $sr */
 560 {
 561 #define FLD(f) abuf->fields.fmt_20_jmp.f
 562   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, * FLD (f_r2)));
 563 #undef FLD
 564 }
 565   BREAK (sem);
 566
 567   CASE (sem, INSN_LD) : /* ld $dr,@$sr */
 568 {
 569 #define FLD(f) abuf->fields.fmt_21_ld.f
 570 * FLD (f_r1) = GETMEMSI (current_cpu, * FLD (f_r2));
 571   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 572 #undef FLD
 573 }
 574   BREAK (sem);
 575
 576   CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
 577 {
 578 #define FLD(f) abuf->fields.fmt_22_ld_d.f
 579 * FLD (f_r1) = GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)));
 580   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 581 #undef FLD
 582 }
 583   BREAK (sem);
 584
 585   CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
 586 {
 587 #define FLD(f) abuf->fields.fmt_23_ldb.f
 588 * FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
 589   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 590 #undef FLD
 591 }
 592   BREAK (sem);
 593
 594   CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
 595 {
 596 #define FLD(f) abuf->fields.fmt_24_ldb_d.f
 597 * FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
 598   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 599 #undef FLD
 600 }
 601   BREAK (sem);
 602
 603   CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
 604 {
 605 #define FLD(f) abuf->fields.fmt_25_ldh.f
 606 * FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
 607   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 608 #undef FLD
 609 }
 610   BREAK (sem);
 611
 612   CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
 613 {
 614 #define FLD(f) abuf->fields.fmt_26_ldh_d.f
 615 * FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
 616   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 617 #undef FLD
 618 }
 619   BREAK (sem);
 620
 621   CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
 622 {
 623 #define FLD(f) abuf->fields.fmt_23_ldb.f
 624 * FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
 625   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 626 #undef FLD
 627 }
 628   BREAK (sem);
 629
 630   CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
 631 {
 632 #define FLD(f) abuf->fields.fmt_24_ldb_d.f
 633 * FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
 634   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 635 #undef FLD
 636 }
 637   BREAK (sem);
 638
 639   CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
 640 {
 641 #define FLD(f) abuf->fields.fmt_25_ldh.f
 642 * FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
 643   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 644 #undef FLD
 645 }
 646   BREAK (sem);
 647
 648   CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
 649 {
 650 #define FLD(f) abuf->fields.fmt_26_ldh_d.f
 651 * FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
 652   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 653 #undef FLD
 654 }
 655   BREAK (sem);
 656
 657   CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
 658 {
 659 #define FLD(f) abuf->fields.fmt_21_ld.f
 660 do {
 661   SI temp1;SI temp0;
 662   temp0 = GETMEMSI (current_cpu, * FLD (f_r2));
 663   temp1 = ADDSI (* FLD (f_r2), 4);
 664 * FLD (f_r1) = temp0;
 665   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 666 * FLD (f_r2) = temp1;
 667   TRACE_RESULT (current_cpu, "sr", 'x', * FLD (f_r2));
 668 } while (0);
 669 #undef FLD
 670 }
 671   BREAK (sem);
 672
 673   CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
 674 {
 675 #define FLD(f) abuf->fields.fmt_27_ld24.f
 676 * FLD (f_r1) = FLD (f_uimm24);
 677   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 678 #undef FLD
 679 }
 680   BREAK (sem);
 681
 682   CASE (sem, INSN_LDI8) : /* ldi $dr,$simm8 */
 683 {
 684 #define FLD(f) abuf->fields.fmt_28_ldi8.f
 685 * FLD (f_r1) = FLD (f_simm8);
 686   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 687 #undef FLD
 688 }
 689   BREAK (sem);
 690
 691   CASE (sem, INSN_LDI16) : /* ldi $dr,$slo16 */
 692 {
 693 #define FLD(f) abuf->fields.fmt_29_ldi16.f
 694 * FLD (f_r1) = FLD (f_simm16);
 695   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 696 #undef FLD
 697 }
 698   BREAK (sem);
 699
 700   CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
 701 {
 702 #define FLD(f) abuf->fields.fmt_0_add.f
 703 do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
 704 #undef FLD
 705 }
 706   BREAK (sem);
 707
 708   CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */
 709 {
 710 #define FLD(f) abuf->fields.fmt_30_machi.f
 711   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
 712   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 713 #undef FLD
 714 }
 715   BREAK (sem);
 716
 717   CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */
 718 {
 719 #define FLD(f) abuf->fields.fmt_30_machi.f
 720   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
 721   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 722 #undef FLD
 723 }
 724   BREAK (sem);
 725
 726   CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */
 727 {
 728 #define FLD(f) abuf->fields.fmt_30_machi.f
 729   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
 730   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 731 #undef FLD
 732 }
 733   BREAK (sem);
 734
 735   CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */
 736 {
 737 #define FLD(f) abuf->fields.fmt_30_machi.f
 738   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
 739   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 740 #undef FLD
 741 }
 742   BREAK (sem);
 743
 744   CASE (sem, INSN_MUL) : /* mul $dr,$sr */
 745 {
 746 #define FLD(f) abuf->fields.fmt_0_add.f
 747 * FLD (f_r1) = MULSI (* FLD (f_r1), * FLD (f_r2));
 748   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 749 #undef FLD
 750 }
 751   BREAK (sem);
 752
 753   CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */
 754 {
 755 #define FLD(f) abuf->fields.fmt_15_cmp.f
 756   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 16), 16);
 757   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 758 #undef FLD
 759 }
 760   BREAK (sem);
 761
 762   CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */
 763 {
 764 #define FLD(f) abuf->fields.fmt_15_cmp.f
 765   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 16), 16);
 766   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 767 #undef FLD
 768 }
 769   BREAK (sem);
 770
 771   CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */
 772 {
 773 #define FLD(f) abuf->fields.fmt_15_cmp.f
 774   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 8), 8);
 775   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 776 #undef FLD
 777 }
 778   BREAK (sem);
 779
 780   CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */
 781 {
 782 #define FLD(f) abuf->fields.fmt_15_cmp.f
 783   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 8), 8);
 784   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 785 #undef FLD
 786 }
 787   BREAK (sem);
 788
 789   CASE (sem, INSN_MV) : /* mv $dr,$sr */
 790 {
 791 #define FLD(f) abuf->fields.fmt_31_mv.f
 792 * FLD (f_r1) = * FLD (f_r2);
 793   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 794 #undef FLD
 795 }
 796   BREAK (sem);
 797
 798   CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */
 799 {
 800 #define FLD(f) abuf->fields.fmt_32_mvfachi.f
 801 * FLD (f_r1) = TRUNCDISI (SRADI (CPU (h_accum), 32));
 802   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 803 #undef FLD
 804 }
 805   BREAK (sem);
 806
 807   CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */
 808 {
 809 #define FLD(f) abuf->fields.fmt_32_mvfachi.f
 810 * FLD (f_r1) = TRUNCDISI (CPU (h_accum));
 811   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 812 #undef FLD
 813 }
 814   BREAK (sem);
 815
 816   CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */
 817 {
 818 #define FLD(f) abuf->fields.fmt_32_mvfachi.f
 819 * FLD (f_r1) = TRUNCDISI (SRADI (CPU (h_accum), 16));
 820   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 821 #undef FLD
 822 }
 823   BREAK (sem);
 824
 825   CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
 826 {
 827 #define FLD(f) abuf->fields.fmt_33_mvfc.f
 828 * FLD (f_r1) = m32r_h_cr_get (current_cpu, FLD (f_r2));
 829   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 830 #undef FLD
 831 }
 832   BREAK (sem);
 833
 834   CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */
 835 {
 836 #define FLD(f) abuf->fields.fmt_34_mvtachi.f
 837   CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (f_r1)), 32));
 838   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 839 #undef FLD
 840 }
 841   BREAK (sem);
 842
 843   CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */
 844 {
 845 #define FLD(f) abuf->fields.fmt_34_mvtachi.f
 846   CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0xffffffff, 0)), EXTSIDI (* FLD (f_r1)));
 847   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 848 #undef FLD
 849 }
 850   BREAK (sem);
 851
 852   CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
 853 {
 854 #define FLD(f) abuf->fields.fmt_35_mvtc.f
 855 m32r_h_cr_set (current_cpu, FLD (f_r1), * FLD (f_r2));
 856   TRACE_RESULT (current_cpu, "dcr", 'x', m32r_h_cr_get (current_cpu, FLD (f_r1)));
 857 #undef FLD
 858 }
 859   BREAK (sem);
 860
 861   CASE (sem, INSN_NEG) : /* neg $dr,$sr */
 862 {
 863 #define FLD(f) abuf->fields.fmt_31_mv.f
 864 * FLD (f_r1) = NEGSI (* FLD (f_r2));
 865   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 866 #undef FLD
 867 }
 868   BREAK (sem);
 869
 870   CASE (sem, INSN_NOP) : /* nop */
 871 {
 872 #define FLD(f) abuf->fields.fmt_36_nop.f
 873 PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
 874 #undef FLD
 875 }
 876   BREAK (sem);
 877
 878   CASE (sem, INSN_NOT) : /* not $dr,$sr */
 879 {
 880 #define FLD(f) abuf->fields.fmt_31_mv.f
 881 * FLD (f_r1) = INVSI (* FLD (f_r2));
 882   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 883 #undef FLD
 884 }
 885   BREAK (sem);
 886
 887   CASE (sem, INSN_RAC) : /* rac */
 888 {
 889 #define FLD(f) abuf->fields.fmt_37_rac.f
 890 do {
 891   DI tmp_tmp1;
 892   tmp_tmp1 = ANDDI (CPU (h_accum), MAKEDI (16777215, 0xffffffff));
 893 if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0xffff8000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
 894   tmp_tmp1 = MAKEDI (16383, 0xffff8000);
 895 } else {
 896 if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
 897   tmp_tmp1 = MAKEDI (16760832, 0);
 898 } else {
 899   tmp_tmp1 = ANDDI (ADDDI (CPU (h_accum), MAKEDI (0, 16384)), MAKEDI (16777215, 0xffff8000));
 900 }
 901 }
 902   tmp_tmp1 = SLLDI (tmp_tmp1, 1);
 903   CPU (h_accum) = SRADI (SLLDI (tmp_tmp1, 7), 7);
 904   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 905 } while (0);
 906 #undef FLD
 907 }
 908   BREAK (sem);
 909
 910   CASE (sem, INSN_RACH) : /* rach */
 911 {
 912 #define FLD(f) abuf->fields.fmt_37_rac.f
 913 do {
 914   DI tmp_tmp1;
 915   tmp_tmp1 = ANDDI (CPU (h_accum), MAKEDI (16777215, 0xffffffff));
 916 if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
 917   tmp_tmp1 = MAKEDI (16383, 0x80000000);
 918 } else {
 919 if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
 920   tmp_tmp1 = MAKEDI (16760832, 0);
 921 } else {
 922   tmp_tmp1 = ANDDI (ADDDI (CPU (h_accum), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
 923 }
 924 }
 925   tmp_tmp1 = SLLDI (tmp_tmp1, 1);
 926   CPU (h_accum) = SRADI (SLLDI (tmp_tmp1, 7), 7);
 927   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 928 } while (0);
 929 #undef FLD
 930 }
 931   BREAK (sem);
 932
 933   CASE (sem, INSN_RTE) : /* rte */
 934 {
 935 #define FLD(f) abuf->fields.fmt_36_nop.f
 936 do {
 937   CPU (h_sm) = CPU (h_bsm);
 938   TRACE_RESULT (current_cpu, "h-sm", 'x', CPU (h_sm));
 939   CPU (h_ie) = CPU (h_bie);
 940   TRACE_RESULT (current_cpu, "h-ie", 'x', CPU (h_ie));
 941   CPU (h_cond) = CPU (h_bcond);
 942   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 943   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, CPU (h_bpc)));
 944   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 945 } while (0);
 946 #undef FLD
 947 }
 948   BREAK (sem);
 949
 950   CASE (sem, INSN_SETH) : /* seth $dr,$hi16 */
 951 {
 952 #define FLD(f) abuf->fields.fmt_38_seth.f
 953 * FLD (f_r1) = SLLSI (FLD (f_hi16), 16);
 954   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 955 #undef FLD
 956 }
 957   BREAK (sem);
 958
 959   CASE (sem, INSN_SLL) : /* sll $dr,$sr */
 960 {
 961 #define FLD(f) abuf->fields.fmt_0_add.f
 962 * FLD (f_r1) = SLLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
 963   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 964 #undef FLD
 965 }
 966   BREAK (sem);
 967
 968   CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
 969 {
 970 #define FLD(f) abuf->fields.fmt_5_addv3.f
 971 * FLD (f_r1) = SLLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
 972   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 973 #undef FLD
 974 }
 975   BREAK (sem);
 976
 977   CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
 978 {
 979 #define FLD(f) abuf->fields.fmt_39_slli.f
 980 * FLD (f_r1) = SLLSI (* FLD (f_r1), FLD (f_uimm5));
 981   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 982 #undef FLD
 983 }
 984   BREAK (sem);
 985
 986   CASE (sem, INSN_SRA) : /* sra $dr,$sr */
 987 {
 988 #define FLD(f) abuf->fields.fmt_0_add.f
 989 * FLD (f_r1) = SRASI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
 990   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 991 #undef FLD
 992 }
 993   BREAK (sem);
 994
 995   CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
 996 {
 997 #define FLD(f) abuf->fields.fmt_5_addv3.f
 998 * FLD (f_r1) = SRASI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
 999   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1000 #undef FLD
1001 }
1002   BREAK (sem);
1003
1004   CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
1005 {
1006 #define FLD(f) abuf->fields.fmt_39_slli.f
1007 * FLD (f_r1) = SRASI (* FLD (f_r1), FLD (f_uimm5));
1008   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1009 #undef FLD
1010 }
1011   BREAK (sem);
1012
1013   CASE (sem, INSN_SRL) : /* srl $dr,$sr */
1014 {
1015 #define FLD(f) abuf->fields.fmt_0_add.f
1016 * FLD (f_r1) = SRLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
1017   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1018 #undef FLD
1019 }
1020   BREAK (sem);
1021
1022   CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
1023 {
1024 #define FLD(f) abuf->fields.fmt_5_addv3.f
1025 * FLD (f_r1) = SRLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
1026   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1027 #undef FLD
1028 }
1029   BREAK (sem);
1030
1031   CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
1032 {
1033 #define FLD(f) abuf->fields.fmt_39_slli.f
1034 * FLD (f_r1) = SRLSI (* FLD (f_r1), FLD (f_uimm5));
1035   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1036 #undef FLD
1037 }
1038   BREAK (sem);
1039
1040   CASE (sem, INSN_ST) : /* st $src1,@$src2 */
1041 {
1042 #define FLD(f) abuf->fields.fmt_15_cmp.f
1043 SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
1044   TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
1045 #undef FLD
1046 }
1047   BREAK (sem);
1048
1049   CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
1050 {
1051 #define FLD(f) abuf->fields.fmt_40_st_d.f
1052 SETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
1053   TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
1054 #undef FLD
1055 }
1056   BREAK (sem);
1057
1058   CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
1059 {
1060 #define FLD(f) abuf->fields.fmt_15_cmp.f
1061 SETMEMQI (current_cpu, * FLD (f_r2), * FLD (f_r1));
1062   TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMQI (current_cpu, * FLD (f_r2)));
1063 #undef FLD
1064 }
1065   BREAK (sem);
1066
1067   CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
1068 {
1069 #define FLD(f) abuf->fields.fmt_40_st_d.f
1070 SETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
1071   TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
1072 #undef FLD
1073 }
1074   BREAK (sem);
1075
1076   CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
1077 {
1078 #define FLD(f) abuf->fields.fmt_15_cmp.f
1079 SETMEMHI (current_cpu, * FLD (f_r2), * FLD (f_r1));
1080   TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMHI (current_cpu, * FLD (f_r2)));
1081 #undef FLD
1082 }
1083   BREAK (sem);
1084
1085   CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
1086 {
1087 #define FLD(f) abuf->fields.fmt_40_st_d.f
1088 SETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
1089   TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
1090 #undef FLD
1091 }
1092   BREAK (sem);
1093
1094   CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
1095 {
1096 #define FLD(f) abuf->fields.fmt_15_cmp.f
1097 do {
1098 * FLD (f_r2) = ADDSI (* FLD (f_r2), 4);
1099   TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2));
1100 SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
1101   TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
1102 } while (0);
1103 #undef FLD
1104 }
1105   BREAK (sem);
1106
1107   CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
1108 {
1109 #define FLD(f) abuf->fields.fmt_15_cmp.f
1110 do {
1111 * FLD (f_r2) = SUBSI (* FLD (f_r2), 4);
1112   TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2));
1113 SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
1114   TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
1115 } while (0);
1116 #undef FLD
1117 }
1118   BREAK (sem);
1119
1120   CASE (sem, INSN_SUB) : /* sub $dr,$sr */
1121 {
1122 #define FLD(f) abuf->fields.fmt_0_add.f
1123 * FLD (f_r1) = SUBSI (* FLD (f_r1), * FLD (f_r2));
1124   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1125 #undef FLD
1126 }
1127   BREAK (sem);
1128
1129   CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
1130 {
1131 #define FLD(f) abuf->fields.fmt_0_add.f
1132 do {
1133   BI temp1;SI temp0;
1134   temp0 = SUBSI (* FLD (f_r1), * FLD (f_r2));
1135   temp1 = SUBOFSI (* FLD (f_r1), * FLD (f_r2), 0);
1136 * FLD (f_r1) = temp0;
1137   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1138   CPU (h_cond) = temp1;
1139   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
1140 } while (0);
1141 #undef FLD
1142 }
1143   BREAK (sem);
1144
1145   CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
1146 {
1147 #define FLD(f) abuf->fields.fmt_6_addx.f
1148 do {
1149   BI temp1;SI temp0;
1150   temp0 = SUBCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
1151   temp1 = SUBCFSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
1152 * FLD (f_r1) = temp0;
1153   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
1154   CPU (h_cond) = temp1;
1155   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
1156 } while (0);
1157 #undef FLD
1158 }
1159   BREAK (sem);
1160
1161   CASE (sem, INSN_TRAP) : /* trap $uimm4 */
1162 {
1163 #define FLD(f) abuf->fields.fmt_41_trap.f
1164 do_trap (current_cpu, FLD (f_uimm4));
1165 #undef FLD
1166 }
1167   BREAK (sem);
1168
1169   CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
1170 {
1171 #define FLD(f) abuf->fields.fmt_15_cmp.f
1172 do_unlock (current_cpu, * FLD (f_r1), * FLD (f_r2));
1173 #undef FLD
1174 }
1175   BREAK (sem);
1176
1177
1178     }
1179   ENDSWITCH (sem) /* End of semantic switch.  */
1180
1181   PC = new_pc;
1182 }
1183
1184 #endif /* DEFINE_SWITCH */