sim/m32r/sem-switch.c

   1 /* Simulator instruction semantics for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2009 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifdef DEFINE_LABELS
  26
  27   /* The labels have the case they have because the enum of insn types
  28      is all uppercase and in the non-stdc case the insn symbol is built
  29      into the enum name.  */
  30
  31   static struct {
  32     int index;
  33     void *label;
  34   } labels[] = {
  35     { M32RBF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
  36     { M32RBF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
  37     { M32RBF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
  38     { M32RBF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
  39     { M32RBF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
  40     { M32RBF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
  41     { M32RBF_INSN_ADD, && case_sem_INSN_ADD },
  42     { M32RBF_INSN_ADD3, && case_sem_INSN_ADD3 },
  43     { M32RBF_INSN_AND, && case_sem_INSN_AND },
  44     { M32RBF_INSN_AND3, && case_sem_INSN_AND3 },
  45     { M32RBF_INSN_OR, && case_sem_INSN_OR },
  46     { M32RBF_INSN_OR3, && case_sem_INSN_OR3 },
  47     { M32RBF_INSN_XOR, && case_sem_INSN_XOR },
  48     { M32RBF_INSN_XOR3, && case_sem_INSN_XOR3 },
  49     { M32RBF_INSN_ADDI, && case_sem_INSN_ADDI },
  50     { M32RBF_INSN_ADDV, && case_sem_INSN_ADDV },
  51     { M32RBF_INSN_ADDV3, && case_sem_INSN_ADDV3 },
  52     { M32RBF_INSN_ADDX, && case_sem_INSN_ADDX },
  53     { M32RBF_INSN_BC8, && case_sem_INSN_BC8 },
  54     { M32RBF_INSN_BC24, && case_sem_INSN_BC24 },
  55     { M32RBF_INSN_BEQ, && case_sem_INSN_BEQ },
  56     { M32RBF_INSN_BEQZ, && case_sem_INSN_BEQZ },
  57     { M32RBF_INSN_BGEZ, && case_sem_INSN_BGEZ },
  58     { M32RBF_INSN_BGTZ, && case_sem_INSN_BGTZ },
  59     { M32RBF_INSN_BLEZ, && case_sem_INSN_BLEZ },
  60     { M32RBF_INSN_BLTZ, && case_sem_INSN_BLTZ },
  61     { M32RBF_INSN_BNEZ, && case_sem_INSN_BNEZ },
  62     { M32RBF_INSN_BL8, && case_sem_INSN_BL8 },
  63     { M32RBF_INSN_BL24, && case_sem_INSN_BL24 },
  64     { M32RBF_INSN_BNC8, && case_sem_INSN_BNC8 },
  65     { M32RBF_INSN_BNC24, && case_sem_INSN_BNC24 },
  66     { M32RBF_INSN_BNE, && case_sem_INSN_BNE },
  67     { M32RBF_INSN_BRA8, && case_sem_INSN_BRA8 },
  68     { M32RBF_INSN_BRA24, && case_sem_INSN_BRA24 },
  69     { M32RBF_INSN_CMP, && case_sem_INSN_CMP },
  70     { M32RBF_INSN_CMPI, && case_sem_INSN_CMPI },
  71     { M32RBF_INSN_CMPU, && case_sem_INSN_CMPU },
  72     { M32RBF_INSN_CMPUI, && case_sem_INSN_CMPUI },
  73     { M32RBF_INSN_DIV, && case_sem_INSN_DIV },
  74     { M32RBF_INSN_DIVU, && case_sem_INSN_DIVU },
  75     { M32RBF_INSN_REM, && case_sem_INSN_REM },
  76     { M32RBF_INSN_REMU, && case_sem_INSN_REMU },
  77     { M32RBF_INSN_JL, && case_sem_INSN_JL },
  78     { M32RBF_INSN_JMP, && case_sem_INSN_JMP },
  79     { M32RBF_INSN_LD, && case_sem_INSN_LD },
  80     { M32RBF_INSN_LD_D, && case_sem_INSN_LD_D },
  81     { M32RBF_INSN_LDB, && case_sem_INSN_LDB },
  82     { M32RBF_INSN_LDB_D, && case_sem_INSN_LDB_D },
  83     { M32RBF_INSN_LDH, && case_sem_INSN_LDH },
  84     { M32RBF_INSN_LDH_D, && case_sem_INSN_LDH_D },
  85     { M32RBF_INSN_LDUB, && case_sem_INSN_LDUB },
  86     { M32RBF_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
  87     { M32RBF_INSN_LDUH, && case_sem_INSN_LDUH },
  88     { M32RBF_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
  89     { M32RBF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
  90     { M32RBF_INSN_LD24, && case_sem_INSN_LD24 },
  91     { M32RBF_INSN_LDI8, && case_sem_INSN_LDI8 },
  92     { M32RBF_INSN_LDI16, && case_sem_INSN_LDI16 },
  93     { M32RBF_INSN_LOCK, && case_sem_INSN_LOCK },
  94     { M32RBF_INSN_MACHI, && case_sem_INSN_MACHI },
  95     { M32RBF_INSN_MACLO, && case_sem_INSN_MACLO },
  96     { M32RBF_INSN_MACWHI, && case_sem_INSN_MACWHI },
  97     { M32RBF_INSN_MACWLO, && case_sem_INSN_MACWLO },
  98     { M32RBF_INSN_MUL, && case_sem_INSN_MUL },
  99     { M32RBF_INSN_MULHI, && case_sem_INSN_MULHI },
 100     { M32RBF_INSN_MULLO, && case_sem_INSN_MULLO },
 101     { M32RBF_INSN_MULWHI, && case_sem_INSN_MULWHI },
 102     { M32RBF_INSN_MULWLO, && case_sem_INSN_MULWLO },
 103     { M32RBF_INSN_MV, && case_sem_INSN_MV },
 104     { M32RBF_INSN_MVFACHI, && case_sem_INSN_MVFACHI },
 105     { M32RBF_INSN_MVFACLO, && case_sem_INSN_MVFACLO },
 106     { M32RBF_INSN_MVFACMI, && case_sem_INSN_MVFACMI },
 107     { M32RBF_INSN_MVFC, && case_sem_INSN_MVFC },
 108     { M32RBF_INSN_MVTACHI, && case_sem_INSN_MVTACHI },
 109     { M32RBF_INSN_MVTACLO, && case_sem_INSN_MVTACLO },
 110     { M32RBF_INSN_MVTC, && case_sem_INSN_MVTC },
 111     { M32RBF_INSN_NEG, && case_sem_INSN_NEG },
 112     { M32RBF_INSN_NOP, && case_sem_INSN_NOP },
 113     { M32RBF_INSN_NOT, && case_sem_INSN_NOT },
 114     { M32RBF_INSN_RAC, && case_sem_INSN_RAC },
 115     { M32RBF_INSN_RACH, && case_sem_INSN_RACH },
 116     { M32RBF_INSN_RTE, && case_sem_INSN_RTE },
 117     { M32RBF_INSN_SETH, && case_sem_INSN_SETH },
 118     { M32RBF_INSN_SLL, && case_sem_INSN_SLL },
 119     { M32RBF_INSN_SLL3, && case_sem_INSN_SLL3 },
 120     { M32RBF_INSN_SLLI, && case_sem_INSN_SLLI },
 121     { M32RBF_INSN_SRA, && case_sem_INSN_SRA },
 122     { M32RBF_INSN_SRA3, && case_sem_INSN_SRA3 },
 123     { M32RBF_INSN_SRAI, && case_sem_INSN_SRAI },
 124     { M32RBF_INSN_SRL, && case_sem_INSN_SRL },
 125     { M32RBF_INSN_SRL3, && case_sem_INSN_SRL3 },
 126     { M32RBF_INSN_SRLI, && case_sem_INSN_SRLI },
 127     { M32RBF_INSN_ST, && case_sem_INSN_ST },
 128     { M32RBF_INSN_ST_D, && case_sem_INSN_ST_D },
 129     { M32RBF_INSN_STB, && case_sem_INSN_STB },
 130     { M32RBF_INSN_STB_D, && case_sem_INSN_STB_D },
 131     { M32RBF_INSN_STH, && case_sem_INSN_STH },
 132     { M32RBF_INSN_STH_D, && case_sem_INSN_STH_D },
 133     { M32RBF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
 134     { M32RBF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
 135     { M32RBF_INSN_SUB, && case_sem_INSN_SUB },
 136     { M32RBF_INSN_SUBV, && case_sem_INSN_SUBV },
 137     { M32RBF_INSN_SUBX, && case_sem_INSN_SUBX },
 138     { M32RBF_INSN_TRAP, && case_sem_INSN_TRAP },
 139     { M32RBF_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
 140     { M32RBF_INSN_CLRPSW, && case_sem_INSN_CLRPSW },
 141     { M32RBF_INSN_SETPSW, && case_sem_INSN_SETPSW },
 142     { M32RBF_INSN_BSET, && case_sem_INSN_BSET },
 143     { M32RBF_INSN_BCLR, && case_sem_INSN_BCLR },
 144     { M32RBF_INSN_BTST, && case_sem_INSN_BTST },
 145     { 0, 0 }
 146   };
 147   int i;
 148
 149   for (i = 0; labels[i].label != 0; ++i)
 150     {
 151 #if FAST_P
 152       CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
 153 #else
 154       CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
 155 #endif
 156     }
 157
 158 #undef DEFINE_LABELS
 159 #endif /* DEFINE_LABELS */
 160
 161 #ifdef DEFINE_SWITCH
 162
 163 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
 164    off frills like tracing and profiling.  */
 165 /* FIXME: A better way would be to have TRACE_RESULT check for something
 166    that can cause it to be optimized out.  Another way would be to emit
 167    special handlers into the instruction "stream".  */
 168
 169 #if FAST_P
 170 #undef TRACE_RESULT
 171 #define TRACE_RESULT(cpu, abuf, name, type, val)
 172 #endif
 173
 174 #undef GET_ATTR
 175 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 176 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
 177 #else
 178 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
 179 #endif
 180
 181 {
 182
 183 #if WITH_SCACHE_PBB
 184
 185 /* Branch to next handler without going around main loop.  */
 186 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
 187 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 188
 189 #else /* ! WITH_SCACHE_PBB */
 190
 191 #define NEXT(vpc) BREAK (sem)
 192 #ifdef __GNUC__
 193 #if FAST_P
 194   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
 195 #else
 196   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
 197 #endif
 198 #else
 199   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
 200 #endif
 201
 202 #endif /* ! WITH_SCACHE_PBB */
 203
 204     {
 205
 206   CASE (sem, INSN_X_INVALID) : /* --invalid-- */
 207 {
 208   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 209   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 210 #define FLD(f) abuf->fields.fmt_empty.f
 211   int UNUSED written = 0;
 212   IADDR UNUSED pc = abuf->addr;
 213   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 214
 215   {
 216     /* Update the recorded pc in the cpu state struct.
 217        Only necessary for WITH_SCACHE case, but to avoid the
 218        conditional compilation ....  */
 219     SET_H_PC (pc);
 220     /* Virtual insns have zero size.  Overwrite vpc with address of next insn
 221        using the default-insn-bitsize spec.  When executing insns in parallel
 222        we may want to queue the fault and continue execution.  */
 223     vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 224     vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
 225   }
 226
 227 #undef FLD
 228 }
 229   NEXT (vpc);
 230
 231   CASE (sem, INSN_X_AFTER) : /* --after-- */
 232 {
 233   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 234   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 235 #define FLD(f) abuf->fields.fmt_empty.f
 236   int UNUSED written = 0;
 237   IADDR UNUSED pc = abuf->addr;
 238   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 239
 240   {
 241 #if WITH_SCACHE_PBB_M32RBF
 242     m32rbf_pbb_after (current_cpu, sem_arg);
 243 #endif
 244   }
 245
 246 #undef FLD
 247 }
 248   NEXT (vpc);
 249
 250   CASE (sem, INSN_X_BEFORE) : /* --before-- */
 251 {
 252   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 253   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 254 #define FLD(f) abuf->fields.fmt_empty.f
 255   int UNUSED written = 0;
 256   IADDR UNUSED pc = abuf->addr;
 257   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 258
 259   {
 260 #if WITH_SCACHE_PBB_M32RBF
 261     m32rbf_pbb_before (current_cpu, sem_arg);
 262 #endif
 263   }
 264
 265 #undef FLD
 266 }
 267   NEXT (vpc);
 268
 269   CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
 270 {
 271   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 272   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 273 #define FLD(f) abuf->fields.fmt_empty.f
 274   int UNUSED written = 0;
 275   IADDR UNUSED pc = abuf->addr;
 276   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 277
 278   {
 279 #if WITH_SCACHE_PBB_M32RBF
 280 #ifdef DEFINE_SWITCH
 281     vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
 282                                pbb_br_type, pbb_br_npc);
 283     BREAK (sem);
 284 #else
 285     /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
 286     vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
 287                                CPU_PBB_BR_TYPE (current_cpu),
 288                                CPU_PBB_BR_NPC (current_cpu));
 289 #endif
 290 #endif
 291   }
 292
 293 #undef FLD
 294 }
 295   NEXT (vpc);
 296
 297   CASE (sem, INSN_X_CHAIN) : /* --chain-- */
 298 {
 299   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 300   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 301 #define FLD(f) abuf->fields.fmt_empty.f
 302   int UNUSED written = 0;
 303   IADDR UNUSED pc = abuf->addr;
 304   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 305
 306   {
 307 #if WITH_SCACHE_PBB_M32RBF
 308     vpc = m32rbf_pbb_chain (current_cpu, sem_arg);
 309 #ifdef DEFINE_SWITCH
 310     BREAK (sem);
 311 #endif
 312 #endif
 313   }
 314
 315 #undef FLD
 316 }
 317   NEXT (vpc);
 318
 319   CASE (sem, INSN_X_BEGIN) : /* --begin-- */
 320 {
 321   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 322   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 323 #define FLD(f) abuf->fields.fmt_empty.f
 324   int UNUSED written = 0;
 325   IADDR UNUSED pc = abuf->addr;
 326   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 327
 328   {
 329 #if WITH_SCACHE_PBB_M32RBF
 330 #if defined DEFINE_SWITCH || defined FAST_P
 331     /* In the switch case FAST_P is a constant, allowing several optimizations
 332        in any called inline functions.  */
 333     vpc = m32rbf_pbb_begin (current_cpu, FAST_P);
 334 #else
 335 #if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
 336     vpc = m32rbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
 337 #else
 338     vpc = m32rbf_pbb_begin (current_cpu, 0);
 339 #endif
 340 #endif
 341 #endif
 342   }
 343
 344 #undef FLD
 345 }
 346   NEXT (vpc);
 347
 348   CASE (sem, INSN_ADD) : /* add $dr,$sr */
 349 {
 350   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 351   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 352 #define FLD(f) abuf->fields.sfmt_add.f
 353   int UNUSED written = 0;
 354   IADDR UNUSED pc = abuf->addr;
 355   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 356
 357   {
 358     SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
 359     * FLD (i_dr) = opval;
 360     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 361   }
 362
 363 #undef FLD
 364 }
 365   NEXT (vpc);
 366
 367   CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
 368 {
 369   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 370   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 371 #define FLD(f) abuf->fields.sfmt_add3.f
 372   int UNUSED written = 0;
 373   IADDR UNUSED pc = abuf->addr;
 374   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 375
 376   {
 377     SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
 378     * FLD (i_dr) = opval;
 379     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 380   }
 381
 382 #undef FLD
 383 }
 384   NEXT (vpc);
 385
 386   CASE (sem, INSN_AND) : /* and $dr,$sr */
 387 {
 388   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 389   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 390 #define FLD(f) abuf->fields.sfmt_add.f
 391   int UNUSED written = 0;
 392   IADDR UNUSED pc = abuf->addr;
 393   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 394
 395   {
 396     SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
 397     * FLD (i_dr) = opval;
 398     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 399   }
 400
 401 #undef FLD
 402 }
 403   NEXT (vpc);
 404
 405   CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
 406 {
 407   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 408   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 409 #define FLD(f) abuf->fields.sfmt_and3.f
 410   int UNUSED written = 0;
 411   IADDR UNUSED pc = abuf->addr;
 412   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 413
 414   {
 415     SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
 416     * FLD (i_dr) = opval;
 417     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 418   }
 419
 420 #undef FLD
 421 }
 422   NEXT (vpc);
 423
 424   CASE (sem, INSN_OR) : /* or $dr,$sr */
 425 {
 426   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 427   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 428 #define FLD(f) abuf->fields.sfmt_add.f
 429   int UNUSED written = 0;
 430   IADDR UNUSED pc = abuf->addr;
 431   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 432
 433   {
 434     SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
 435     * FLD (i_dr) = opval;
 436     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 437   }
 438
 439 #undef FLD
 440 }
 441   NEXT (vpc);
 442
 443   CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
 444 {
 445   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 446   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 447 #define FLD(f) abuf->fields.sfmt_and3.f
 448   int UNUSED written = 0;
 449   IADDR UNUSED pc = abuf->addr;
 450   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 451
 452   {
 453     SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
 454     * FLD (i_dr) = opval;
 455     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 456   }
 457
 458 #undef FLD
 459 }
 460   NEXT (vpc);
 461
 462   CASE (sem, INSN_XOR) : /* xor $dr,$sr */
 463 {
 464   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 465   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 466 #define FLD(f) abuf->fields.sfmt_add.f
 467   int UNUSED written = 0;
 468   IADDR UNUSED pc = abuf->addr;
 469   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 470
 471   {
 472     SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
 473     * FLD (i_dr) = opval;
 474     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 475   }
 476
 477 #undef FLD
 478 }
 479   NEXT (vpc);
 480
 481   CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
 482 {
 483   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 484   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 485 #define FLD(f) abuf->fields.sfmt_and3.f
 486   int UNUSED written = 0;
 487   IADDR UNUSED pc = abuf->addr;
 488   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 489
 490   {
 491     SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
 492     * FLD (i_dr) = opval;
 493     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 494   }
 495
 496 #undef FLD
 497 }
 498   NEXT (vpc);
 499
 500   CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
 501 {
 502   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 503   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 504 #define FLD(f) abuf->fields.sfmt_addi.f
 505   int UNUSED written = 0;
 506   IADDR UNUSED pc = abuf->addr;
 507   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 508
 509   {
 510     SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
 511     * FLD (i_dr) = opval;
 512     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 513   }
 514
 515 #undef FLD
 516 }
 517   NEXT (vpc);
 518
 519   CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
 520 {
 521   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 522   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 523 #define FLD(f) abuf->fields.sfmt_add.f
 524   int UNUSED written = 0;
 525   IADDR UNUSED pc = abuf->addr;
 526   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 527
 528 {
 529   SI temp0;BI temp1;
 530   temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
 531   temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
 532   {
 533     SI opval = temp0;
 534     * FLD (i_dr) = opval;
 535     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 536   }
 537   {
 538     BI opval = temp1;
 539     CPU (h_cond) = opval;
 540     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
 541   }
 542 }
 543
 544 #undef FLD
 545 }
 546   NEXT (vpc);
 547
 548   CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
 549 {
 550   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 551   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 552 #define FLD(f) abuf->fields.sfmt_add3.f
 553   int UNUSED written = 0;
 554   IADDR UNUSED pc = abuf->addr;
 555   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 556
 557 {
 558   SI temp0;BI temp1;
 559   temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
 560   temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
 561   {
 562     SI opval = temp0;
 563     * FLD (i_dr) = opval;
 564     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 565   }
 566   {
 567     BI opval = temp1;
 568     CPU (h_cond) = opval;
 569     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
 570   }
 571 }
 572
 573 #undef FLD
 574 }
 575   NEXT (vpc);
 576
 577   CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
 578 {
 579   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 580   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 581 #define FLD(f) abuf->fields.sfmt_add.f
 582   int UNUSED written = 0;
 583   IADDR UNUSED pc = abuf->addr;
 584   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 585
 586 {
 587   SI temp0;BI temp1;
 588   temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
 589   temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
 590   {
 591     SI opval = temp0;
 592     * FLD (i_dr) = opval;
 593     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 594   }
 595   {
 596     BI opval = temp1;
 597     CPU (h_cond) = opval;
 598     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
 599   }
 600 }
 601
 602 #undef FLD
 603 }
 604   NEXT (vpc);
 605
 606   CASE (sem, INSN_BC8) : /* bc.s $disp8 */
 607 {
 608   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 609   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 610 #define FLD(f) abuf->fields.sfmt_bl8.f
 611   int UNUSED written = 0;
 612   IADDR UNUSED pc = abuf->addr;
 613   SEM_BRANCH_INIT
 614   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 615
 616 if (CPU (h_cond)) {
 617   {
 618     USI opval = FLD (i_disp8);
 619     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 620     written |= (1 << 2);
 621     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 622   }
 623 }
 624
 625   abuf->written = written;
 626   SEM_BRANCH_FINI (vpc);
 627 #undef FLD
 628 }
 629   NEXT (vpc);
 630
 631   CASE (sem, INSN_BC24) : /* bc.l $disp24 */
 632 {
 633   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 634   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 635 #define FLD(f) abuf->fields.sfmt_bl24.f
 636   int UNUSED written = 0;
 637   IADDR UNUSED pc = abuf->addr;
 638   SEM_BRANCH_INIT
 639   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 640
 641 if (CPU (h_cond)) {
 642   {
 643     USI opval = FLD (i_disp24);
 644     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 645     written |= (1 << 2);
 646     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 647   }
 648 }
 649
 650   abuf->written = written;
 651   SEM_BRANCH_FINI (vpc);
 652 #undef FLD
 653 }
 654   NEXT (vpc);
 655
 656   CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
 657 {
 658   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 659   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 660 #define FLD(f) abuf->fields.sfmt_beq.f
 661   int UNUSED written = 0;
 662   IADDR UNUSED pc = abuf->addr;
 663   SEM_BRANCH_INIT
 664   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 665
 666 if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
 667   {
 668     USI opval = FLD (i_disp16);
 669     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 670     written |= (1 << 3);
 671     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 672   }
 673 }
 674
 675   abuf->written = written;
 676   SEM_BRANCH_FINI (vpc);
 677 #undef FLD
 678 }
 679   NEXT (vpc);
 680
 681   CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
 682 {
 683   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 684   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 685 #define FLD(f) abuf->fields.sfmt_beq.f
 686   int UNUSED written = 0;
 687   IADDR UNUSED pc = abuf->addr;
 688   SEM_BRANCH_INIT
 689   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 690
 691 if (EQSI (* FLD (i_src2), 0)) {
 692   {
 693     USI opval = FLD (i_disp16);
 694     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 695     written |= (1 << 2);
 696     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 697   }
 698 }
 699
 700   abuf->written = written;
 701   SEM_BRANCH_FINI (vpc);
 702 #undef FLD
 703 }
 704   NEXT (vpc);
 705
 706   CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
 707 {
 708   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 709   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 710 #define FLD(f) abuf->fields.sfmt_beq.f
 711   int UNUSED written = 0;
 712   IADDR UNUSED pc = abuf->addr;
 713   SEM_BRANCH_INIT
 714   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 715
 716 if (GESI (* FLD (i_src2), 0)) {
 717   {
 718     USI opval = FLD (i_disp16);
 719     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 720     written |= (1 << 2);
 721     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 722   }
 723 }
 724
 725   abuf->written = written;
 726   SEM_BRANCH_FINI (vpc);
 727 #undef FLD
 728 }
 729   NEXT (vpc);
 730
 731   CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
 732 {
 733   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 734   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 735 #define FLD(f) abuf->fields.sfmt_beq.f
 736   int UNUSED written = 0;
 737   IADDR UNUSED pc = abuf->addr;
 738   SEM_BRANCH_INIT
 739   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 740
 741 if (GTSI (* FLD (i_src2), 0)) {
 742   {
 743     USI opval = FLD (i_disp16);
 744     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 745     written |= (1 << 2);
 746     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 747   }
 748 }
 749
 750   abuf->written = written;
 751   SEM_BRANCH_FINI (vpc);
 752 #undef FLD
 753 }
 754   NEXT (vpc);
 755
 756   CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
 757 {
 758   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 759   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 760 #define FLD(f) abuf->fields.sfmt_beq.f
 761   int UNUSED written = 0;
 762   IADDR UNUSED pc = abuf->addr;
 763   SEM_BRANCH_INIT
 764   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 765
 766 if (LESI (* FLD (i_src2), 0)) {
 767   {
 768     USI opval = FLD (i_disp16);
 769     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 770     written |= (1 << 2);
 771     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 772   }
 773 }
 774
 775   abuf->written = written;
 776   SEM_BRANCH_FINI (vpc);
 777 #undef FLD
 778 }
 779   NEXT (vpc);
 780
 781   CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
 782 {
 783   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 784   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 785 #define FLD(f) abuf->fields.sfmt_beq.f
 786   int UNUSED written = 0;
 787   IADDR UNUSED pc = abuf->addr;
 788   SEM_BRANCH_INIT
 789   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 790
 791 if (LTSI (* FLD (i_src2), 0)) {
 792   {
 793     USI opval = FLD (i_disp16);
 794     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 795     written |= (1 << 2);
 796     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 797   }
 798 }
 799
 800   abuf->written = written;
 801   SEM_BRANCH_FINI (vpc);
 802 #undef FLD
 803 }
 804   NEXT (vpc);
 805
 806   CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
 807 {
 808   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 809   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 810 #define FLD(f) abuf->fields.sfmt_beq.f
 811   int UNUSED written = 0;
 812   IADDR UNUSED pc = abuf->addr;
 813   SEM_BRANCH_INIT
 814   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 815
 816 if (NESI (* FLD (i_src2), 0)) {
 817   {
 818     USI opval = FLD (i_disp16);
 819     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 820     written |= (1 << 2);
 821     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 822   }
 823 }
 824
 825   abuf->written = written;
 826   SEM_BRANCH_FINI (vpc);
 827 #undef FLD
 828 }
 829   NEXT (vpc);
 830
 831   CASE (sem, INSN_BL8) : /* bl.s $disp8 */
 832 {
 833   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 834   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 835 #define FLD(f) abuf->fields.sfmt_bl8.f
 836   int UNUSED written = 0;
 837   IADDR UNUSED pc = abuf->addr;
 838   SEM_BRANCH_INIT
 839   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 840
 841 {
 842   {
 843     SI opval = ADDSI (ANDSI (pc, -4), 4);
 844     CPU (h_gr[((UINT) 14)]) = opval;
 845     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 846   }
 847   {
 848     USI opval = FLD (i_disp8);
 849     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 850     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 851   }
 852 }
 853
 854   SEM_BRANCH_FINI (vpc);
 855 #undef FLD
 856 }
 857   NEXT (vpc);
 858
 859   CASE (sem, INSN_BL24) : /* bl.l $disp24 */
 860 {
 861   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 862   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 863 #define FLD(f) abuf->fields.sfmt_bl24.f
 864   int UNUSED written = 0;
 865   IADDR UNUSED pc = abuf->addr;
 866   SEM_BRANCH_INIT
 867   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 868
 869 {
 870   {
 871     SI opval = ADDSI (pc, 4);
 872     CPU (h_gr[((UINT) 14)]) = opval;
 873     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 874   }
 875   {
 876     USI opval = FLD (i_disp24);
 877     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 878     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 879   }
 880 }
 881
 882   SEM_BRANCH_FINI (vpc);
 883 #undef FLD
 884 }
 885   NEXT (vpc);
 886
 887   CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
 888 {
 889   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 890   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 891 #define FLD(f) abuf->fields.sfmt_bl8.f
 892   int UNUSED written = 0;
 893   IADDR UNUSED pc = abuf->addr;
 894   SEM_BRANCH_INIT
 895   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 896
 897 if (NOTBI (CPU (h_cond))) {
 898   {
 899     USI opval = FLD (i_disp8);
 900     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 901     written |= (1 << 2);
 902     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 903   }
 904 }
 905
 906   abuf->written = written;
 907   SEM_BRANCH_FINI (vpc);
 908 #undef FLD
 909 }
 910   NEXT (vpc);
 911
 912   CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
 913 {
 914   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 915   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 916 #define FLD(f) abuf->fields.sfmt_bl24.f
 917   int UNUSED written = 0;
 918   IADDR UNUSED pc = abuf->addr;
 919   SEM_BRANCH_INIT
 920   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 921
 922 if (NOTBI (CPU (h_cond))) {
 923   {
 924     USI opval = FLD (i_disp24);
 925     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 926     written |= (1 << 2);
 927     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 928   }
 929 }
 930
 931   abuf->written = written;
 932   SEM_BRANCH_FINI (vpc);
 933 #undef FLD
 934 }
 935   NEXT (vpc);
 936
 937   CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
 938 {
 939   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 940   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 941 #define FLD(f) abuf->fields.sfmt_beq.f
 942   int UNUSED written = 0;
 943   IADDR UNUSED pc = abuf->addr;
 944   SEM_BRANCH_INIT
 945   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 946
 947 if (NESI (* FLD (i_src1), * FLD (i_src2))) {
 948   {
 949     USI opval = FLD (i_disp16);
 950     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 951     written |= (1 << 3);
 952     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 953   }
 954 }
 955
 956   abuf->written = written;
 957   SEM_BRANCH_FINI (vpc);
 958 #undef FLD
 959 }
 960   NEXT (vpc);
 961
 962   CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
 963 {
 964   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 965   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 966 #define FLD(f) abuf->fields.sfmt_bl8.f
 967   int UNUSED written = 0;
 968   IADDR UNUSED pc = abuf->addr;
 969   SEM_BRANCH_INIT
 970   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 971
 972   {
 973     USI opval = FLD (i_disp8);
 974     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 975     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 976   }
 977
 978   SEM_BRANCH_FINI (vpc);
 979 #undef FLD
 980 }
 981   NEXT (vpc);
 982
 983   CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
 984 {
 985   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 986   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 987 #define FLD(f) abuf->fields.sfmt_bl24.f
 988   int UNUSED written = 0;
 989   IADDR UNUSED pc = abuf->addr;
 990   SEM_BRANCH_INIT
 991   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 992
 993   {
 994     USI opval = FLD (i_disp24);
 995     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
 996     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
 997   }
 998
 999   SEM_BRANCH_FINI (vpc);
1000 #undef FLD
1001 }
1002   NEXT (vpc);
1003
1004   CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
1005 {
1006   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1007   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1008 #define FLD(f) abuf->fields.sfmt_st_plus.f
1009   int UNUSED written = 0;
1010   IADDR UNUSED pc = abuf->addr;
1011   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1012
1013   {
1014     BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
1015     CPU (h_cond) = opval;
1016     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
1017   }
1018
1019 #undef FLD
1020 }
1021   NEXT (vpc);
1022
1023   CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
1024 {
1025   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1026   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1027 #define FLD(f) abuf->fields.sfmt_st_d.f
1028   int UNUSED written = 0;
1029   IADDR UNUSED pc = abuf->addr;
1030   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1031
1032   {
1033     BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
1034     CPU (h_cond) = opval;
1035     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
1036   }
1037
1038 #undef FLD
1039 }
1040   NEXT (vpc);
1041
1042   CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
1043 {
1044   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1045   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1046 #define FLD(f) abuf->fields.sfmt_st_plus.f
1047   int UNUSED written = 0;
1048   IADDR UNUSED pc = abuf->addr;
1049   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1050
1051   {
1052     BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
1053     CPU (h_cond) = opval;
1054     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
1055   }
1056
1057 #undef FLD
1058 }
1059   NEXT (vpc);
1060
1061   CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
1062 {
1063   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1064   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1065 #define FLD(f) abuf->fields.sfmt_st_d.f
1066   int UNUSED written = 0;
1067   IADDR UNUSED pc = abuf->addr;
1068   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1069
1070   {
1071     BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
1072     CPU (h_cond) = opval;
1073     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
1074   }
1075
1076 #undef FLD
1077 }
1078   NEXT (vpc);
1079
1080   CASE (sem, INSN_DIV) : /* div $dr,$sr */
1081 {
1082   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1083   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1084 #define FLD(f) abuf->fields.sfmt_add.f
1085   int UNUSED written = 0;
1086   IADDR UNUSED pc = abuf->addr;
1087   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1088
1089 if (NESI (* FLD (i_sr), 0)) {
1090   {
1091     SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
1092     * FLD (i_dr) = opval;
1093     written |= (1 << 2);
1094     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1095   }
1096 }
1097
1098   abuf->written = written;
1099 #undef FLD
1100 }
1101   NEXT (vpc);
1102
1103   CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
1104 {
1105   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1106   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1107 #define FLD(f) abuf->fields.sfmt_add.f
1108   int UNUSED written = 0;
1109   IADDR UNUSED pc = abuf->addr;
1110   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1111
1112 if (NESI (* FLD (i_sr), 0)) {
1113   {
1114     SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
1115     * FLD (i_dr) = opval;
1116     written |= (1 << 2);
1117     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1118   }
1119 }
1120
1121   abuf->written = written;
1122 #undef FLD
1123 }
1124   NEXT (vpc);
1125
1126   CASE (sem, INSN_REM) : /* rem $dr,$sr */
1127 {
1128   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1129   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1130 #define FLD(f) abuf->fields.sfmt_add.f
1131   int UNUSED written = 0;
1132   IADDR UNUSED pc = abuf->addr;
1133   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1134
1135 if (NESI (* FLD (i_sr), 0)) {
1136   {
1137     SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
1138     * FLD (i_dr) = opval;
1139     written |= (1 << 2);
1140     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1141   }
1142 }
1143
1144   abuf->written = written;
1145 #undef FLD
1146 }
1147   NEXT (vpc);
1148
1149   CASE (sem, INSN_REMU) : /* remu $dr,$sr */
1150 {
1151   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1152   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1153 #define FLD(f) abuf->fields.sfmt_add.f
1154   int UNUSED written = 0;
1155   IADDR UNUSED pc = abuf->addr;
1156   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1157
1158 if (NESI (* FLD (i_sr), 0)) {
1159   {
1160     SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
1161     * FLD (i_dr) = opval;
1162     written |= (1 << 2);
1163     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1164   }
1165 }
1166
1167   abuf->written = written;
1168 #undef FLD
1169 }
1170   NEXT (vpc);
1171
1172   CASE (sem, INSN_JL) : /* jl $sr */
1173 {
1174   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1175   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1176 #define FLD(f) abuf->fields.sfmt_jl.f
1177   int UNUSED written = 0;
1178   IADDR UNUSED pc = abuf->addr;
1179   SEM_BRANCH_INIT
1180   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1181
1182 {
1183   SI temp0;USI temp1;
1184   temp0 = ADDSI (ANDSI (pc, -4), 4);
1185   temp1 = ANDSI (* FLD (i_sr), -4);
1186   {
1187     SI opval = temp0;
1188     CPU (h_gr[((UINT) 14)]) = opval;
1189     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1190   }
1191   {
1192     USI opval = temp1;
1193     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1194     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1195   }
1196 }
1197
1198   SEM_BRANCH_FINI (vpc);
1199 #undef FLD
1200 }
1201   NEXT (vpc);
1202
1203   CASE (sem, INSN_JMP) : /* jmp $sr */
1204 {
1205   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1206   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1207 #define FLD(f) abuf->fields.sfmt_jl.f
1208   int UNUSED written = 0;
1209   IADDR UNUSED pc = abuf->addr;
1210   SEM_BRANCH_INIT
1211   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1212
1213   {
1214     USI opval = ANDSI (* FLD (i_sr), -4);
1215     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1216     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1217   }
1218
1219   SEM_BRANCH_FINI (vpc);
1220 #undef FLD
1221 }
1222   NEXT (vpc);
1223
1224   CASE (sem, INSN_LD) : /* ld $dr,@$sr */
1225 {
1226   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1227   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1228 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1229   int UNUSED written = 0;
1230   IADDR UNUSED pc = abuf->addr;
1231   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1232
1233   {
1234     SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
1235     * FLD (i_dr) = opval;
1236     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1237   }
1238
1239 #undef FLD
1240 }
1241   NEXT (vpc);
1242
1243   CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
1244 {
1245   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1246   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1247 #define FLD(f) abuf->fields.sfmt_add3.f
1248   int UNUSED written = 0;
1249   IADDR UNUSED pc = abuf->addr;
1250   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1251
1252   {
1253     SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
1254     * FLD (i_dr) = opval;
1255     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1256   }
1257
1258 #undef FLD
1259 }
1260   NEXT (vpc);
1261
1262   CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
1263 {
1264   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1265   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1266 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1267   int UNUSED written = 0;
1268   IADDR UNUSED pc = abuf->addr;
1269   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1270
1271   {
1272     SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
1273     * FLD (i_dr) = opval;
1274     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1275   }
1276
1277 #undef FLD
1278 }
1279   NEXT (vpc);
1280
1281   CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
1282 {
1283   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1284   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1285 #define FLD(f) abuf->fields.sfmt_add3.f
1286   int UNUSED written = 0;
1287   IADDR UNUSED pc = abuf->addr;
1288   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1289
1290   {
1291     SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1292     * FLD (i_dr) = opval;
1293     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1294   }
1295
1296 #undef FLD
1297 }
1298   NEXT (vpc);
1299
1300   CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
1301 {
1302   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1303   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1304 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1305   int UNUSED written = 0;
1306   IADDR UNUSED pc = abuf->addr;
1307   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1308
1309   {
1310     SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
1311     * FLD (i_dr) = opval;
1312     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1313   }
1314
1315 #undef FLD
1316 }
1317   NEXT (vpc);
1318
1319   CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
1320 {
1321   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1322   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1323 #define FLD(f) abuf->fields.sfmt_add3.f
1324   int UNUSED written = 0;
1325   IADDR UNUSED pc = abuf->addr;
1326   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1327
1328   {
1329     SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1330     * FLD (i_dr) = opval;
1331     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1332   }
1333
1334 #undef FLD
1335 }
1336   NEXT (vpc);
1337
1338   CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
1339 {
1340   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1341   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1342 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1343   int UNUSED written = 0;
1344   IADDR UNUSED pc = abuf->addr;
1345   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1346
1347   {
1348     SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
1349     * FLD (i_dr) = opval;
1350     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1351   }
1352
1353 #undef FLD
1354 }
1355   NEXT (vpc);
1356
1357   CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
1358 {
1359   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1360   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1361 #define FLD(f) abuf->fields.sfmt_add3.f
1362   int UNUSED written = 0;
1363   IADDR UNUSED pc = abuf->addr;
1364   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1365
1366   {
1367     SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1368     * FLD (i_dr) = opval;
1369     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1370   }
1371
1372 #undef FLD
1373 }
1374   NEXT (vpc);
1375
1376   CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
1377 {
1378   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1379   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1380 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1381   int UNUSED written = 0;
1382   IADDR UNUSED pc = abuf->addr;
1383   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1384
1385   {
1386     SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
1387     * FLD (i_dr) = opval;
1388     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1389   }
1390
1391 #undef FLD
1392 }
1393   NEXT (vpc);
1394
1395   CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
1396 {
1397   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1398   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1399 #define FLD(f) abuf->fields.sfmt_add3.f
1400   int UNUSED written = 0;
1401   IADDR UNUSED pc = abuf->addr;
1402   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1403
1404   {
1405     SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
1406     * FLD (i_dr) = opval;
1407     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1408   }
1409
1410 #undef FLD
1411 }
1412   NEXT (vpc);
1413
1414   CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
1415 {
1416   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1417   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1418 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1419   int UNUSED written = 0;
1420   IADDR UNUSED pc = abuf->addr;
1421   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1422
1423 {
1424   SI temp0;SI temp1;
1425   temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
1426   temp1 = ADDSI (* FLD (i_sr), 4);
1427   {
1428     SI opval = temp0;
1429     * FLD (i_dr) = opval;
1430     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1431   }
1432   {
1433     SI opval = temp1;
1434     * FLD (i_sr) = opval;
1435     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1436   }
1437 }
1438
1439 #undef FLD
1440 }
1441   NEXT (vpc);
1442
1443   CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
1444 {
1445   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1446   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1447 #define FLD(f) abuf->fields.sfmt_ld24.f
1448   int UNUSED written = 0;
1449   IADDR UNUSED pc = abuf->addr;
1450   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1451
1452   {
1453     SI opval = FLD (i_uimm24);
1454     * FLD (i_dr) = opval;
1455     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1456   }
1457
1458 #undef FLD
1459 }
1460   NEXT (vpc);
1461
1462   CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
1463 {
1464   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1465   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1466 #define FLD(f) abuf->fields.sfmt_addi.f
1467   int UNUSED written = 0;
1468   IADDR UNUSED pc = abuf->addr;
1469   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1470
1471   {
1472     SI opval = FLD (f_simm8);
1473     * FLD (i_dr) = opval;
1474     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1475   }
1476
1477 #undef FLD
1478 }
1479   NEXT (vpc);
1480
1481   CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
1482 {
1483   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1484   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1485 #define FLD(f) abuf->fields.sfmt_add3.f
1486   int UNUSED written = 0;
1487   IADDR UNUSED pc = abuf->addr;
1488   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1489
1490   {
1491     SI opval = FLD (f_simm16);
1492     * FLD (i_dr) = opval;
1493     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1494   }
1495
1496 #undef FLD
1497 }
1498   NEXT (vpc);
1499
1500   CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
1501 {
1502   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1503   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1504 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1505   int UNUSED written = 0;
1506   IADDR UNUSED pc = abuf->addr;
1507   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1508
1509 {
1510   {
1511     BI opval = 1;
1512     CPU (h_lock) = opval;
1513     TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
1514   }
1515   {
1516     SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
1517     * FLD (i_dr) = opval;
1518     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1519   }
1520 }
1521
1522 #undef FLD
1523 }
1524   NEXT (vpc);
1525
1526   CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */
1527 {
1528   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1529   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1530 #define FLD(f) abuf->fields.sfmt_st_plus.f
1531   int UNUSED written = 0;
1532   IADDR UNUSED pc = abuf->addr;
1533   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1534
1535   {
1536     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
1537     SET_H_ACCUM (opval);
1538     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1539   }
1540
1541 #undef FLD
1542 }
1543   NEXT (vpc);
1544
1545   CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */
1546 {
1547   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1548   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1549 #define FLD(f) abuf->fields.sfmt_st_plus.f
1550   int UNUSED written = 0;
1551   IADDR UNUSED pc = abuf->addr;
1552   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1553
1554   {
1555     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
1556     SET_H_ACCUM (opval);
1557     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1558   }
1559
1560 #undef FLD
1561 }
1562   NEXT (vpc);
1563
1564   CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */
1565 {
1566   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1567   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1568 #define FLD(f) abuf->fields.sfmt_st_plus.f
1569   int UNUSED written = 0;
1570   IADDR UNUSED pc = abuf->addr;
1571   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1572
1573   {
1574     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
1575     SET_H_ACCUM (opval);
1576     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1577   }
1578
1579 #undef FLD
1580 }
1581   NEXT (vpc);
1582
1583   CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */
1584 {
1585   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1586   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1587 #define FLD(f) abuf->fields.sfmt_st_plus.f
1588   int UNUSED written = 0;
1589   IADDR UNUSED pc = abuf->addr;
1590   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1591
1592   {
1593     DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
1594     SET_H_ACCUM (opval);
1595     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1596   }
1597
1598 #undef FLD
1599 }
1600   NEXT (vpc);
1601
1602   CASE (sem, INSN_MUL) : /* mul $dr,$sr */
1603 {
1604   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1605   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1606 #define FLD(f) abuf->fields.sfmt_add.f
1607   int UNUSED written = 0;
1608   IADDR UNUSED pc = abuf->addr;
1609   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1610
1611   {
1612     SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
1613     * FLD (i_dr) = opval;
1614     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1615   }
1616
1617 #undef FLD
1618 }
1619   NEXT (vpc);
1620
1621   CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */
1622 {
1623   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1624   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1625 #define FLD(f) abuf->fields.sfmt_st_plus.f
1626   int UNUSED written = 0;
1627   IADDR UNUSED pc = abuf->addr;
1628   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1629
1630   {
1631     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
1632     SET_H_ACCUM (opval);
1633     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1634   }
1635
1636 #undef FLD
1637 }
1638   NEXT (vpc);
1639
1640   CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */
1641 {
1642   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1643   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1644 #define FLD(f) abuf->fields.sfmt_st_plus.f
1645   int UNUSED written = 0;
1646   IADDR UNUSED pc = abuf->addr;
1647   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1648
1649   {
1650     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
1651     SET_H_ACCUM (opval);
1652     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1653   }
1654
1655 #undef FLD
1656 }
1657   NEXT (vpc);
1658
1659   CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */
1660 {
1661   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1662   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1663 #define FLD(f) abuf->fields.sfmt_st_plus.f
1664   int UNUSED written = 0;
1665   IADDR UNUSED pc = abuf->addr;
1666   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1667
1668   {
1669     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 8), 8);
1670     SET_H_ACCUM (opval);
1671     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1672   }
1673
1674 #undef FLD
1675 }
1676   NEXT (vpc);
1677
1678   CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */
1679 {
1680   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1681   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1682 #define FLD(f) abuf->fields.sfmt_st_plus.f
1683   int UNUSED written = 0;
1684   IADDR UNUSED pc = abuf->addr;
1685   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1686
1687   {
1688     DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 8), 8);
1689     SET_H_ACCUM (opval);
1690     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1691   }
1692
1693 #undef FLD
1694 }
1695   NEXT (vpc);
1696
1697   CASE (sem, INSN_MV) : /* mv $dr,$sr */
1698 {
1699   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1700   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1701 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1702   int UNUSED written = 0;
1703   IADDR UNUSED pc = abuf->addr;
1704   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1705
1706   {
1707     SI opval = * FLD (i_sr);
1708     * FLD (i_dr) = opval;
1709     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1710   }
1711
1712 #undef FLD
1713 }
1714   NEXT (vpc);
1715
1716   CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */
1717 {
1718   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1719   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1720 #define FLD(f) abuf->fields.sfmt_seth.f
1721   int UNUSED written = 0;
1722   IADDR UNUSED pc = abuf->addr;
1723   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1724
1725   {
1726     SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 32));
1727     * FLD (i_dr) = opval;
1728     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1729   }
1730
1731 #undef FLD
1732 }
1733   NEXT (vpc);
1734
1735   CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */
1736 {
1737   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1738   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1739 #define FLD(f) abuf->fields.sfmt_seth.f
1740   int UNUSED written = 0;
1741   IADDR UNUSED pc = abuf->addr;
1742   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1743
1744   {
1745     SI opval = TRUNCDISI (GET_H_ACCUM ());
1746     * FLD (i_dr) = opval;
1747     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1748   }
1749
1750 #undef FLD
1751 }
1752   NEXT (vpc);
1753
1754   CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */
1755 {
1756   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1757   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1758 #define FLD(f) abuf->fields.sfmt_seth.f
1759   int UNUSED written = 0;
1760   IADDR UNUSED pc = abuf->addr;
1761   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1762
1763   {
1764     SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 16));
1765     * FLD (i_dr) = opval;
1766     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1767   }
1768
1769 #undef FLD
1770 }
1771   NEXT (vpc);
1772
1773   CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
1774 {
1775   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1776   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1777 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1778   int UNUSED written = 0;
1779   IADDR UNUSED pc = abuf->addr;
1780   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1781
1782   {
1783     SI opval = GET_H_CR (FLD (f_r2));
1784     * FLD (i_dr) = opval;
1785     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1786   }
1787
1788 #undef FLD
1789 }
1790   NEXT (vpc);
1791
1792   CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */
1793 {
1794   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1795   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1796 #define FLD(f) abuf->fields.sfmt_st_plus.f
1797   int UNUSED written = 0;
1798   IADDR UNUSED pc = abuf->addr;
1799   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1800
1801   {
1802     DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
1803     SET_H_ACCUM (opval);
1804     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1805   }
1806
1807 #undef FLD
1808 }
1809   NEXT (vpc);
1810
1811   CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */
1812 {
1813   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1814   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1815 #define FLD(f) abuf->fields.sfmt_st_plus.f
1816   int UNUSED written = 0;
1817   IADDR UNUSED pc = abuf->addr;
1818   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1819
1820   {
1821     DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
1822     SET_H_ACCUM (opval);
1823     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1824   }
1825
1826 #undef FLD
1827 }
1828   NEXT (vpc);
1829
1830   CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
1831 {
1832   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1833   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1834 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1835   int UNUSED written = 0;
1836   IADDR UNUSED pc = abuf->addr;
1837   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1838
1839   {
1840     USI opval = * FLD (i_sr);
1841     SET_H_CR (FLD (f_r1), opval);
1842     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
1843   }
1844
1845 #undef FLD
1846 }
1847   NEXT (vpc);
1848
1849   CASE (sem, INSN_NEG) : /* neg $dr,$sr */
1850 {
1851   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1852   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1853 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1854   int UNUSED written = 0;
1855   IADDR UNUSED pc = abuf->addr;
1856   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1857
1858   {
1859     SI opval = NEGSI (* FLD (i_sr));
1860     * FLD (i_dr) = opval;
1861     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1862   }
1863
1864 #undef FLD
1865 }
1866   NEXT (vpc);
1867
1868   CASE (sem, INSN_NOP) : /* nop */
1869 {
1870   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1871   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1872 #define FLD(f) abuf->fields.fmt_empty.f
1873   int UNUSED written = 0;
1874   IADDR UNUSED pc = abuf->addr;
1875   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1876
1877 PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
1878
1879 #undef FLD
1880 }
1881   NEXT (vpc);
1882
1883   CASE (sem, INSN_NOT) : /* not $dr,$sr */
1884 {
1885   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1886   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1887 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1888   int UNUSED written = 0;
1889   IADDR UNUSED pc = abuf->addr;
1890   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1891
1892   {
1893     SI opval = INVSI (* FLD (i_sr));
1894     * FLD (i_dr) = opval;
1895     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1896   }
1897
1898 #undef FLD
1899 }
1900   NEXT (vpc);
1901
1902   CASE (sem, INSN_RAC) : /* rac */
1903 {
1904   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1905   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1906 #define FLD(f) abuf->fields.fmt_empty.f
1907   int UNUSED written = 0;
1908   IADDR UNUSED pc = abuf->addr;
1909   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1910
1911 {
1912   DI tmp_tmp1;
1913   tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1);
1914   tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
1915   {
1916     DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
1917     SET_H_ACCUM (opval);
1918     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1919   }
1920 }
1921
1922 #undef FLD
1923 }
1924   NEXT (vpc);
1925
1926   CASE (sem, INSN_RACH) : /* rach */
1927 {
1928   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1929   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1930 #define FLD(f) abuf->fields.fmt_empty.f
1931   int UNUSED written = 0;
1932   IADDR UNUSED pc = abuf->addr;
1933   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1934
1935 {
1936   DI tmp_tmp1;
1937   tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff));
1938 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
1939   tmp_tmp1 = MAKEDI (16383, 0x80000000);
1940 } else {
1941 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
1942   tmp_tmp1 = MAKEDI (16760832, 0);
1943 } else {
1944   tmp_tmp1 = ANDDI (ADDDI (GET_H_ACCUM (), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
1945 }
1946 }
1947   tmp_tmp1 = SLLDI (tmp_tmp1, 1);
1948   {
1949     DI opval = SRADI (SLLDI (tmp_tmp1, 7), 7);
1950     SET_H_ACCUM (opval);
1951     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
1952   }
1953 }
1954
1955 #undef FLD
1956 }
1957   NEXT (vpc);
1958
1959   CASE (sem, INSN_RTE) : /* rte */
1960 {
1961   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1962   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1963 #define FLD(f) abuf->fields.fmt_empty.f
1964   int UNUSED written = 0;
1965   IADDR UNUSED pc = abuf->addr;
1966   SEM_BRANCH_INIT
1967   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1968
1969 {
1970   {
1971     USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
1972     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1973     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1974   }
1975   {
1976     USI opval = GET_H_CR (((UINT) 14));
1977     SET_H_CR (((UINT) 6), opval);
1978     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
1979   }
1980   {
1981     UQI opval = CPU (h_bpsw);
1982     SET_H_PSW (opval);
1983     TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
1984   }
1985   {
1986     UQI opval = CPU (h_bbpsw);
1987     CPU (h_bpsw) = opval;
1988     TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
1989   }
1990 }
1991
1992   SEM_BRANCH_FINI (vpc);
1993 #undef FLD
1994 }
1995   NEXT (vpc);
1996
1997   CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
1998 {
1999   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2000   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2001 #define FLD(f) abuf->fields.sfmt_seth.f
2002   int UNUSED written = 0;
2003   IADDR UNUSED pc = abuf->addr;
2004   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2005
2006   {
2007     SI opval = SLLSI (FLD (f_hi16), 16);
2008     * FLD (i_dr) = opval;
2009     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2010   }
2011
2012 #undef FLD
2013 }
2014   NEXT (vpc);
2015
2016   CASE (sem, INSN_SLL) : /* sll $dr,$sr */
2017 {
2018   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2019   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2020 #define FLD(f) abuf->fields.sfmt_add.f
2021   int UNUSED written = 0;
2022   IADDR UNUSED pc = abuf->addr;
2023   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2024
2025   {
2026     SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
2027     * FLD (i_dr) = opval;
2028     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2029   }
2030
2031 #undef FLD
2032 }
2033   NEXT (vpc);
2034
2035   CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
2036 {
2037   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2038   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2039 #define FLD(f) abuf->fields.sfmt_add3.f
2040   int UNUSED written = 0;
2041   IADDR UNUSED pc = abuf->addr;
2042   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2043
2044   {
2045     SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
2046     * FLD (i_dr) = opval;
2047     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2048   }
2049
2050 #undef FLD
2051 }
2052   NEXT (vpc);
2053
2054   CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
2055 {
2056   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2057   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2058 #define FLD(f) abuf->fields.sfmt_slli.f
2059   int UNUSED written = 0;
2060   IADDR UNUSED pc = abuf->addr;
2061   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2062
2063   {
2064     SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
2065     * FLD (i_dr) = opval;
2066     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2067   }
2068
2069 #undef FLD
2070 }
2071   NEXT (vpc);
2072
2073   CASE (sem, INSN_SRA) : /* sra $dr,$sr */
2074 {
2075   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2076   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2077 #define FLD(f) abuf->fields.sfmt_add.f
2078   int UNUSED written = 0;
2079   IADDR UNUSED pc = abuf->addr;
2080   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2081
2082   {
2083     SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
2084     * FLD (i_dr) = opval;
2085     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2086   }
2087
2088 #undef FLD
2089 }
2090   NEXT (vpc);
2091
2092   CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
2093 {
2094   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2095   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2096 #define FLD(f) abuf->fields.sfmt_add3.f
2097   int UNUSED written = 0;
2098   IADDR UNUSED pc = abuf->addr;
2099   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2100
2101   {
2102     SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
2103     * FLD (i_dr) = opval;
2104     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2105   }
2106
2107 #undef FLD
2108 }
2109   NEXT (vpc);
2110
2111   CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
2112 {
2113   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2114   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2115 #define FLD(f) abuf->fields.sfmt_slli.f
2116   int UNUSED written = 0;
2117   IADDR UNUSED pc = abuf->addr;
2118   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2119
2120   {
2121     SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
2122     * FLD (i_dr) = opval;
2123     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2124   }
2125
2126 #undef FLD
2127 }
2128   NEXT (vpc);
2129
2130   CASE (sem, INSN_SRL) : /* srl $dr,$sr */
2131 {
2132   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2133   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2134 #define FLD(f) abuf->fields.sfmt_add.f
2135   int UNUSED written = 0;
2136   IADDR UNUSED pc = abuf->addr;
2137   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2138
2139   {
2140     SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
2141     * FLD (i_dr) = opval;
2142     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2143   }
2144
2145 #undef FLD
2146 }
2147   NEXT (vpc);
2148
2149   CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
2150 {
2151   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2152   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2153 #define FLD(f) abuf->fields.sfmt_add3.f
2154   int UNUSED written = 0;
2155   IADDR UNUSED pc = abuf->addr;
2156   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2157
2158   {
2159     SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
2160     * FLD (i_dr) = opval;
2161     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2162   }
2163
2164 #undef FLD
2165 }
2166   NEXT (vpc);
2167
2168   CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
2169 {
2170   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2171   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2172 #define FLD(f) abuf->fields.sfmt_slli.f
2173   int UNUSED written = 0;
2174   IADDR UNUSED pc = abuf->addr;
2175   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2176
2177   {
2178     SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
2179     * FLD (i_dr) = opval;
2180     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2181   }
2182
2183 #undef FLD
2184 }
2185   NEXT (vpc);
2186
2187   CASE (sem, INSN_ST) : /* st $src1,@$src2 */
2188 {
2189   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2190   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2191 #define FLD(f) abuf->fields.sfmt_st_plus.f
2192   int UNUSED written = 0;
2193   IADDR UNUSED pc = abuf->addr;
2194   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2195
2196   {
2197     SI opval = * FLD (i_src1);
2198     SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
2199     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2200   }
2201
2202 #undef FLD
2203 }
2204   NEXT (vpc);
2205
2206   CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
2207 {
2208   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2209   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2210 #define FLD(f) abuf->fields.sfmt_st_d.f
2211   int UNUSED written = 0;
2212   IADDR UNUSED pc = abuf->addr;
2213   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2214
2215   {
2216     SI opval = * FLD (i_src1);
2217     SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
2218     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2219   }
2220
2221 #undef FLD
2222 }
2223   NEXT (vpc);
2224
2225   CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
2226 {
2227   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2228   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2229 #define FLD(f) abuf->fields.sfmt_st_plus.f
2230   int UNUSED written = 0;
2231   IADDR UNUSED pc = abuf->addr;
2232   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2233
2234   {
2235     QI opval = * FLD (i_src1);
2236     SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
2237     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2238   }
2239
2240 #undef FLD
2241 }
2242   NEXT (vpc);
2243
2244   CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
2245 {
2246   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2247   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2248 #define FLD(f) abuf->fields.sfmt_st_d.f
2249   int UNUSED written = 0;
2250   IADDR UNUSED pc = abuf->addr;
2251   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2252
2253   {
2254     QI opval = * FLD (i_src1);
2255     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
2256     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2257   }
2258
2259 #undef FLD
2260 }
2261   NEXT (vpc);
2262
2263   CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
2264 {
2265   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2266   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2267 #define FLD(f) abuf->fields.sfmt_st_plus.f
2268   int UNUSED written = 0;
2269   IADDR UNUSED pc = abuf->addr;
2270   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2271
2272   {
2273     HI opval = * FLD (i_src1);
2274     SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
2275     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2276   }
2277
2278 #undef FLD
2279 }
2280   NEXT (vpc);
2281
2282   CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
2283 {
2284   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2285   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2286 #define FLD(f) abuf->fields.sfmt_st_d.f
2287   int UNUSED written = 0;
2288   IADDR UNUSED pc = abuf->addr;
2289   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2290
2291   {
2292     HI opval = * FLD (i_src1);
2293     SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
2294     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2295   }
2296
2297 #undef FLD
2298 }
2299   NEXT (vpc);
2300
2301   CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
2302 {
2303   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2304   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2305 #define FLD(f) abuf->fields.sfmt_st_plus.f
2306   int UNUSED written = 0;
2307   IADDR UNUSED pc = abuf->addr;
2308   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2309
2310 {
2311   SI tmp_new_src2;
2312   tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
2313   {
2314     SI opval = * FLD (i_src1);
2315     SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
2316     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2317   }
2318   {
2319     SI opval = tmp_new_src2;
2320     * FLD (i_src2) = opval;
2321     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2322   }
2323 }
2324
2325 #undef FLD
2326 }
2327   NEXT (vpc);
2328
2329   CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
2330 {
2331   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2332   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2333 #define FLD(f) abuf->fields.sfmt_st_plus.f
2334   int UNUSED written = 0;
2335   IADDR UNUSED pc = abuf->addr;
2336   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2337
2338 {
2339   SI tmp_new_src2;
2340   tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
2341   {
2342     SI opval = * FLD (i_src1);
2343     SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
2344     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2345   }
2346   {
2347     SI opval = tmp_new_src2;
2348     * FLD (i_src2) = opval;
2349     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2350   }
2351 }
2352
2353 #undef FLD
2354 }
2355   NEXT (vpc);
2356
2357   CASE (sem, INSN_SUB) : /* sub $dr,$sr */
2358 {
2359   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2360   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2361 #define FLD(f) abuf->fields.sfmt_add.f
2362   int UNUSED written = 0;
2363   IADDR UNUSED pc = abuf->addr;
2364   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2365
2366   {
2367     SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
2368     * FLD (i_dr) = opval;
2369     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2370   }
2371
2372 #undef FLD
2373 }
2374   NEXT (vpc);
2375
2376   CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
2377 {
2378   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2379   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2380 #define FLD(f) abuf->fields.sfmt_add.f
2381   int UNUSED written = 0;
2382   IADDR UNUSED pc = abuf->addr;
2383   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2384
2385 {
2386   SI temp0;BI temp1;
2387   temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
2388   temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
2389   {
2390     SI opval = temp0;
2391     * FLD (i_dr) = opval;
2392     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2393   }
2394   {
2395     BI opval = temp1;
2396     CPU (h_cond) = opval;
2397     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
2398   }
2399 }
2400
2401 #undef FLD
2402 }
2403   NEXT (vpc);
2404
2405   CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
2406 {
2407   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2408   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2409 #define FLD(f) abuf->fields.sfmt_add.f
2410   int UNUSED written = 0;
2411   IADDR UNUSED pc = abuf->addr;
2412   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2413
2414 {
2415   SI temp0;BI temp1;
2416   temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
2417   temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
2418   {
2419     SI opval = temp0;
2420     * FLD (i_dr) = opval;
2421     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2422   }
2423   {
2424     BI opval = temp1;
2425     CPU (h_cond) = opval;
2426     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
2427   }
2428 }
2429
2430 #undef FLD
2431 }
2432   NEXT (vpc);
2433
2434   CASE (sem, INSN_TRAP) : /* trap $uimm4 */
2435 {
2436   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2437   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2438 #define FLD(f) abuf->fields.sfmt_trap.f
2439   int UNUSED written = 0;
2440   IADDR UNUSED pc = abuf->addr;
2441   SEM_BRANCH_INIT
2442   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2443
2444 {
2445   {
2446     USI opval = GET_H_CR (((UINT) 6));
2447     SET_H_CR (((UINT) 14), opval);
2448     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
2449   }
2450   {
2451     USI opval = ADDSI (pc, 4);
2452     SET_H_CR (((UINT) 6), opval);
2453     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
2454   }
2455   {
2456     UQI opval = CPU (h_bpsw);
2457     CPU (h_bbpsw) = opval;
2458     TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
2459   }
2460   {
2461     UQI opval = GET_H_PSW ();
2462     CPU (h_bpsw) = opval;
2463     TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
2464   }
2465   {
2466     UQI opval = ANDQI (GET_H_PSW (), 128);
2467     SET_H_PSW (opval);
2468     TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
2469   }
2470   {
2471     SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
2472     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
2473     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
2474   }
2475 }
2476
2477   SEM_BRANCH_FINI (vpc);
2478 #undef FLD
2479 }
2480   NEXT (vpc);
2481
2482   CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
2483 {
2484   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2485   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2486 #define FLD(f) abuf->fields.sfmt_st_plus.f
2487   int UNUSED written = 0;
2488   IADDR UNUSED pc = abuf->addr;
2489   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2490
2491 {
2492 if (CPU (h_lock)) {
2493   {
2494     SI opval = * FLD (i_src1);
2495     SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
2496     written |= (1 << 4);
2497     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2498   }
2499 }
2500   {
2501     BI opval = 0;
2502     CPU (h_lock) = opval;
2503     TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
2504   }
2505 }
2506
2507   abuf->written = written;
2508 #undef FLD
2509 }
2510   NEXT (vpc);
2511
2512   CASE (sem, INSN_CLRPSW) : /* clrpsw $uimm8 */
2513 {
2514   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2515   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2516 #define FLD(f) abuf->fields.sfmt_clrpsw.f
2517   int UNUSED written = 0;
2518   IADDR UNUSED pc = abuf->addr;
2519   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2520
2521   {
2522     USI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (ZEXTQISI (INVQI (FLD (f_uimm8))), 65280));
2523     SET_H_CR (((UINT) 0), opval);
2524     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
2525   }
2526
2527 #undef FLD
2528 }
2529   NEXT (vpc);
2530
2531   CASE (sem, INSN_SETPSW) : /* setpsw $uimm8 */
2532 {
2533   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2534   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2535 #define FLD(f) abuf->fields.sfmt_clrpsw.f
2536   int UNUSED written = 0;
2537   IADDR UNUSED pc = abuf->addr;
2538   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2539
2540   {
2541     USI opval = FLD (f_uimm8);
2542     SET_H_CR (((UINT) 0), opval);
2543     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
2544   }
2545
2546 #undef FLD
2547 }
2548   NEXT (vpc);
2549
2550   CASE (sem, INSN_BSET) : /* bset $uimm3,@($slo16,$sr) */
2551 {
2552   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2553   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2554 #define FLD(f) abuf->fields.sfmt_bset.f
2555   int UNUSED written = 0;
2556   IADDR UNUSED pc = abuf->addr;
2557   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2558
2559   {
2560     QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLQI (1, SUBSI (7, FLD (f_uimm3))));
2561     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
2562     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2563   }
2564
2565 #undef FLD
2566 }
2567   NEXT (vpc);
2568
2569   CASE (sem, INSN_BCLR) : /* bclr $uimm3,@($slo16,$sr) */
2570 {
2571   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2572   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2573 #define FLD(f) abuf->fields.sfmt_bset.f
2574   int UNUSED written = 0;
2575   IADDR UNUSED pc = abuf->addr;
2576   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2577
2578   {
2579     QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLQI (1, SUBSI (7, FLD (f_uimm3)))));
2580     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
2581     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2582   }
2583
2584 #undef FLD
2585 }
2586   NEXT (vpc);
2587
2588   CASE (sem, INSN_BTST) : /* btst $uimm3,$sr */
2589 {
2590   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2591   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2592 #define FLD(f) abuf->fields.sfmt_bset.f
2593   int UNUSED written = 0;
2594   IADDR UNUSED pc = abuf->addr;
2595   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2596
2597   {
2598     BI opval = ANDQI (SRLQI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
2599     CPU (h_cond) = opval;
2600     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
2601   }
2602
2603 #undef FLD
2604 }
2605   NEXT (vpc);
2606
2607
2608     }
2609   ENDSWITCH (sem) /* End of semantic switch.  */
2610
2611   /* At this point `vpc' contains the next insn to execute.  */
2612 }
2613
2614 #undef DEFINE_SWITCH
2615 #endif /* DEFINE_SWITCH */