sim/m32r/sim-if.c

   1 /* Main simulator entry points specific to the M32R.
   2    Copyright (C) 1996-2021 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5    This file is part of GDB, the GNU debugger.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "sim-main.h"
  21 #include "sim-options.h"
  22 #include "libiberty.h"
  23 #include "bfd.h"
  24
  25 #include <string.h>
  26 #include <stdlib.h>
  27
  28 #include "dv-m32r_uart.h"
  29
  30 static void free_state (SIM_DESC);
  31 static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose);
  32 \f
  33 /* Cover function of sim_state_free to free the cpu buffers as well.  */
  34
  35 static void
  36 free_state (SIM_DESC sd)
  37 {
  38   if (STATE_MODULES (sd) != NULL)
  39     sim_module_uninstall (sd);
  40   sim_cpu_free_all (sd);
  41   sim_state_free (sd);
  42 }
  43
  44 /* Create an instance of the simulator.  */
  45
  46 SIM_DESC
  47 sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
  48           char * const *argv)
  49 {
  50   SIM_DESC sd = sim_state_alloc (kind, callback);
  51   char c;
  52   int i;
  53
  54   /* The cpu data is kept in a separately allocated chunk of memory.  */
  55   if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
  56     {
  57       free_state (sd);
  58       return 0;
  59     }
  60
  61   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
  62     {
  63       free_state (sd);
  64       return 0;
  65     }
  66
  67   /* The parser will print an error message for us, so we silently return.  */
  68   if (sim_parse_args (sd, argv) != SIM_RC_OK)
  69     {
  70       free_state (sd);
  71       return 0;
  72     }
  73
  74   /* Allocate a handler for the control registers and other devices
  75      if no memory for that range has been allocated by the user.
  76      All are allocated in one chunk to keep things from being
  77      unnecessarily complicated.
  78      TODO: Move these to the sim-model framework.  */
  79   sim_hw_parse (sd, "/core/%s/reg %#x %i", "m32r_uart", UART_BASE_ADDR, 0x100);
  80   sim_hw_parse (sd, "/core/%s/reg %#x %i", "m32r_cache", 0xfffffff0, 0x10);
  81
  82   /* Allocate core managed memory if none specified by user.
  83      Use address 4 here in case the user wanted address 0 unmapped.  */
  84   if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
  85     sim_do_commandf (sd, "memory region 0,0x%x", M32R_DEFAULT_MEM_SIZE);
  86
  87   /* check for/establish the reference program image */
  88   if (sim_analyze_program (sd,
  89                            (STATE_PROG_ARGV (sd) != NULL
  90                             ? *STATE_PROG_ARGV (sd)
  91                             : NULL),
  92                            abfd) != SIM_RC_OK)
  93     {
  94       free_state (sd);
  95       return 0;
  96     }
  97
  98   /* Establish any remaining configuration options.  */
  99   if (sim_config (sd) != SIM_RC_OK)
 100     {
 101       free_state (sd);
 102       return 0;
 103     }
 104
 105   if (sim_post_argv_init (sd) != SIM_RC_OK)
 106     {
 107       free_state (sd);
 108       return 0;
 109     }
 110
 111   /* Open a copy of the cpu descriptor table.  */
 112   {
 113     CGEN_CPU_DESC cd = m32r_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
 114                                              CGEN_ENDIAN_BIG);
 115     for (i = 0; i < MAX_NR_PROCESSORS; ++i)
 116       {
 117         SIM_CPU *cpu = STATE_CPU (sd, i);
 118         CPU_CPU_DESC (cpu) = cd;
 119         CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
 120       }
 121     m32r_cgen_init_dis (cd);
 122   }
 123
 124   /* Initialize various cgen things not done by common framework.
 125      Must be done after m32r_cgen_cpu_open.  */
 126   cgen_init (sd);
 127
 128   for (c = 0; c < MAX_NR_PROCESSORS; ++c)
 129     {
 130       /* Only needed for profiling, but the structure member is small.  */
 131       memset (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i)), 0,
 132               sizeof (* CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i))));
 133       /* Hook in callback for reporting these stats */
 134       PROFILE_INFO_CPU_CALLBACK (CPU_PROFILE_DATA (STATE_CPU (sd, i)))
 135         = print_m32r_misc_cpu;
 136     }
 137
 138   return sd;
 139 }
 140 \f
 141 SIM_RC
 142 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char * const *argv,
 143                      char * const *envp)
 144 {
 145   SIM_CPU *current_cpu = STATE_CPU (sd, 0);
 146   SIM_ADDR addr;
 147
 148   if (abfd != NULL)
 149     addr = bfd_get_start_address (abfd);
 150   else
 151     addr = 0;
 152   sim_pc_set (current_cpu, addr);
 153
 154 #ifdef M32R_LINUX
 155   m32rbf_h_cr_set (current_cpu,
 156                     m32r_decode_gdb_ctrl_regnum(SPI_REGNUM), 0x1f00000);
 157   m32rbf_h_cr_set (current_cpu,
 158                     m32r_decode_gdb_ctrl_regnum(SPU_REGNUM), 0x1f00000);
 159 #endif
 160
 161   /* Standalone mode (i.e. `run`) will take care of the argv for us in
 162      sim_open() -> sim_parse_args().  But in debug mode (i.e. 'target sim'
 163      with `gdb`), we need to handle it because the user can change the
 164      argv on the fly via gdb's 'run'.  */
 165   if (STATE_PROG_ARGV (sd) != argv)
 166     {
 167       freeargv (STATE_PROG_ARGV (sd));
 168       STATE_PROG_ARGV (sd) = dupargv (argv);
 169     }
 170
 171   return SIM_RC_OK;
 172 }
 173
 174 /* PROFILE_CPU_CALLBACK */
 175
 176 static void
 177 print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
 178 {
 179   SIM_DESC sd = CPU_STATE (cpu);
 180   char buf[20];
 181
 182   if (CPU_PROFILE_FLAGS (cpu) [PROFILE_INSN_IDX])
 183     {
 184       sim_io_printf (sd, "Miscellaneous Statistics\n\n");
 185       sim_io_printf (sd, "  %-*s %s\n\n",
 186                      PROFILE_LABEL_WIDTH, "Fill nops:",
 187                      sim_add_commas (buf, sizeof (buf),
 188                                      CPU_M32R_MISC_PROFILE (cpu)->fillnop_count));
 189       if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32rx)
 190         sim_io_printf (sd, "  %-*s %s\n\n",
 191                        PROFILE_LABEL_WIDTH, "Parallel insns:",
 192                        sim_add_commas (buf, sizeof (buf),
 193                                        CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
 194       if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32r2)
 195         sim_io_printf (sd, "  %-*s %s\n\n",
 196                        PROFILE_LABEL_WIDTH, "Parallel insns:",
 197                        sim_add_commas (buf, sizeof (buf),
 198                                        CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
 199     }
 200 }