1 /* dv-m68hc11tim.c -- Simulation of the 68HC11 timer devices.
2 Copyright (C) 1999, 2000, 2002 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@worldnet.fr)
4 (From a driver model Contributed by Cygnus Solutions.)
6 This file is part of the program GDB, the GNU debugger.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either vertimn 2 of the License, or
11 (at your option) any later vertimn.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 #include "sim-assert.h"
32 m68hc11tim - m68hc11 timer devices
37 Implements the m68hc11 timer as described in Chapter 10
50 Reset the timer device. This port must be connected to
51 the cpu-reset output port.
55 Input capture. This port must be connected to the input
56 captures. It latches the current TCNT free running counter
57 into one of the three input capture registers.
72 static const struct hw_port_descriptor m68hc11tim_ports
[] =
74 { "reset", RESET_PORT
, 0, input_port
, },
75 { "capture", CAPTURE
, 0, input_port
, },
80 /* Timer Controller information. */
83 unsigned long cop_delay
;
84 unsigned long rti_delay
;
85 unsigned long ovf_delay
;
86 signed64 clock_prescaler
;
88 signed64 cop_prev_interrupt
;
89 signed64 rti_prev_interrupt
;
91 /* Periodic timers. */
92 struct hw_event
*rti_timer_event
;
93 struct hw_event
*cop_timer_event
;
94 struct hw_event
*tof_timer_event
;
95 struct hw_event
*cmp_timer_event
;
100 /* Finish off the partially created hw device. Attach our local
101 callbacks. Wire up our port names etc. */
103 static hw_io_read_buffer_method m68hc11tim_io_read_buffer
;
104 static hw_io_write_buffer_method m68hc11tim_io_write_buffer
;
105 static hw_port_event_method m68hc11tim_port_event
;
106 static hw_ioctl_method m68hc11tim_ioctl
;
108 #define M6811_TIMER_FIRST_REG (M6811_TCTN)
109 #define M6811_TIMER_LAST_REG (M6811_PACNT)
113 attach_m68hc11tim_regs (struct hw
*me
,
114 struct m68hc11tim
*controller
)
116 hw_attach_address (hw_parent (me
), M6811_IO_LEVEL
, io_map
,
117 M6811_TIMER_FIRST_REG
,
118 M6811_TIMER_LAST_REG
- M6811_TIMER_FIRST_REG
+ 1,
123 m68hc11tim_finish (struct hw
*me
)
125 struct m68hc11tim
*controller
;
127 controller
= HW_ZALLOC (me
, struct m68hc11tim
);
128 set_hw_data (me
, controller
);
129 set_hw_io_read_buffer (me
, m68hc11tim_io_read_buffer
);
130 set_hw_io_write_buffer (me
, m68hc11tim_io_write_buffer
);
131 set_hw_ports (me
, m68hc11tim_ports
);
132 set_hw_port_event (me
, m68hc11tim_port_event
);
134 set_hw_ioctl (me
, m68hc11tim_ioctl
);
136 me
->to_ioctl
= m68hc11tim_ioctl
;
139 /* Preset defaults. */
140 controller
->clock_prescaler
= 1;
141 controller
->tcnt_adjust
= 0;
143 /* Attach ourself to our parent bus. */
144 attach_m68hc11tim_regs (me
, controller
);
148 /* An event arrives on an interrupt port. */
151 m68hc11tim_port_event (struct hw
*me
,
158 struct m68hc11tim
*controller
;
163 controller
= hw_data (me
);
165 cpu
= STATE_CPU (sd
, 0);
170 HW_TRACE ((me
, "Timer reset"));
172 /* Cancel all timer events. */
173 if (controller
->rti_timer_event
)
175 hw_event_queue_deschedule (me
, controller
->rti_timer_event
);
176 controller
->rti_timer_event
= 0;
177 controller
->rti_prev_interrupt
= 0;
179 if (controller
->cop_timer_event
)
181 hw_event_queue_deschedule (me
, controller
->cop_timer_event
);
182 controller
->cop_timer_event
= 0;
183 controller
->cop_prev_interrupt
= 0;
185 if (controller
->tof_timer_event
)
187 hw_event_queue_deschedule (me
, controller
->tof_timer_event
);
188 controller
->tof_timer_event
= 0;
190 if (controller
->cmp_timer_event
)
192 hw_event_queue_deschedule (me
, controller
->cmp_timer_event
);
193 controller
->cmp_timer_event
= 0;
196 /* Reset the state of Timer registers. This also restarts
197 the timer events (overflow and RTI clock). */
199 m68hc11tim_io_write_buffer (me
, &val
, io_map
,
200 (unsigned_word
) M6811_TMSK2
, 1);
201 m68hc11tim_io_write_buffer (me
, &val
, io_map
,
202 (unsigned_word
) M6811_TFLG2
, 1);
203 m68hc11tim_io_write_buffer (me
, &val
, io_map
,
204 (unsigned_word
) M6811_PACTL
, 1);
209 tcnt
= (uint16
) ((cpu
->cpu_absolute_cycle
- controller
->tcnt_adjust
)
210 / controller
->clock_prescaler
);
216 cpu
->ios
[level
] = tcnt
>> 8;
217 cpu
->ios
[level
+ 1] = tcnt
;
221 hw_abort (me
, "Invalid event parameter %d", level
);
227 hw_abort (me
, "Event on unknown port %d", my_port
);
241 m68hc11tim_timer_event (struct hw
*me
, void *data
)
244 struct m68hc11tim
*controller
;
246 enum event_type type
;
248 struct hw_event
**eventp
;
249 int check_interrupt
= 0;
252 unsigned long tcnt_internal
;
257 controller
= hw_data (me
);
259 cpu
= STATE_CPU (sd
, 0);
260 type
= (enum event_type
) ((long) data
) & 0x0FF;
261 events
= STATE_EVENTS (sd
);
267 eventp
= &controller
->cop_timer_event
;
268 delay
= controller
->cop_delay
;
269 delay
= controller
->cop_prev_interrupt
+ controller
->cop_delay
;
270 controller
->cop_prev_interrupt
= delay
;
271 delay
= delay
- cpu
->cpu_absolute_cycle
;
273 delay
+= events
->nr_ticks_to_process
;
277 eventp
= &controller
->rti_timer_event
;
278 delay
= controller
->rti_prev_interrupt
+ controller
->rti_delay
;
280 if (((long) (data
) & 0x0100) == 0)
282 cpu
->ios
[M6811_TFLG2
] |= M6811_RTIF
;
284 controller
->rti_prev_interrupt
= delay
;
285 delay
+= controller
->rti_delay
;
287 delay
= delay
- cpu
->cpu_absolute_cycle
;
288 delay
+= events
->nr_ticks_to_process
;
292 /* Compute the 68HC11 internal free running counter.
293 There may be 'nr_ticks_to_process' pending cycles that are
294 not (yet) taken into account by 'sim_events_time'. */
295 tcnt_internal
= sim_events_time (sd
) - controller
->tcnt_adjust
;
296 tcnt_internal
+= events
->nr_ticks_to_process
;
298 /* We must take into account the prescaler that comes
299 before the counter (it's a power of 2). */
300 tcnt_internal
&= 0x0ffff * controller
->clock_prescaler
;
302 /* Compute the time when the overflow will occur. It occurs when
303 the counter increments from 0x0ffff to 0x10000 (and thus resets). */
304 delay
= (0x10000 * controller
->clock_prescaler
) - tcnt_internal
;
306 /* The 'nr_ticks_to_process' will be subtracted when the event
308 delay
+= events
->nr_ticks_to_process
;
310 eventp
= &controller
->tof_timer_event
;
311 if (((long) (data
) & 0x100) == 0)
313 cpu
->ios
[M6811_TFLG2
] |= M6811_TOF
;
319 eventp
= &controller
->cmp_timer_event
;
321 /* Compute the 68HC11 internal free running counter.
322 There may be 'nr_ticks_to_process' pending cycles that are
323 not (yet) taken into account by 'sim_events_time'. */
324 events
= STATE_EVENTS (sd
);
325 tcnt_internal
= sim_events_time (sd
) - controller
->tcnt_adjust
;
326 tcnt_internal
+= events
->nr_ticks_to_process
;
328 /* We must take into account the prescaler that comes
329 before the counter (it's a power of 2). */
330 tcnt_internal
&= 0x0ffff * controller
->clock_prescaler
;
332 /* Get current visible TCNT register value. */
333 tcnt
= tcnt_internal
/ controller
->clock_prescaler
;
335 flags
= cpu
->ios
[M6811_TMSK1
];
337 delay
= 65536 * controller
->clock_prescaler
;
339 /* Scan each output compare register to see if one matches
340 the free running counter. Set the corresponding OCi flag
341 if the output compare is enabled. */
342 for (i
= M6811_TOC1
; i
<= M6811_TOC5
; i
+= 2, mask
>>= 1)
344 unsigned long compare
;
346 compare
= (cpu
->ios
[i
] << 8) + cpu
->ios
[i
+1];
347 if (compare
== tcnt
&& (flags
& mask
))
349 cpu
->ios
[M6811_TFLG1
] |= mask
;
353 /* Compute how many times for the next match.
354 Use the internal counter value to take into account the
355 prescaler accurately. */
356 compare
= compare
* controller
->clock_prescaler
;
357 if (compare
> tcnt_internal
)
358 compare
= compare
- tcnt_internal
;
360 compare
= compare
- tcnt_internal
361 + 65536 * controller
->clock_prescaler
;
367 /* Deactivate the compare timer if no output compare is enabled. */
368 if ((flags
& 0xF0) == 0)
379 hw_event_queue_deschedule (me
, *eventp
);
385 *eventp
= hw_event_queue_schedule (me
, delay
,
386 m68hc11tim_timer_event
,
391 interrupts_update_pending (&cpu
->cpu_interrupts
);
395 /* Descriptions of the Timer I/O ports. These descriptions are only used to
396 give information of the Timer device under GDB. */
397 io_reg_desc tmsk2_desc
[] = {
398 { M6811_TOI
, "TOI ", "Timer Overflow Interrupt Enable" },
399 { M6811_RTII
, "RTII ", "RTI Interrupt Enable" },
400 { M6811_PAOVI
, "PAOVI ", "Pulse Accumulator Overflow Interrupt Enable" },
401 { M6811_PAII
, "PAII ", "Pulse Accumulator Interrupt Enable" },
402 { M6811_PR1
, "PR1 ", "Timer prescaler (PR1)" },
403 { M6811_PR0
, "PR0 ", "Timer prescaler (PR0)" },
404 { M6811_TPR_1
, "TPR_1 ", "Timer prescaler div 1" },
405 { M6811_TPR_4
, "TPR_4 ", "Timer prescaler div 4" },
406 { M6811_TPR_8
, "TPR_8 ", "Timer prescaler div 8" },
407 { M6811_TPR_16
, "TPR_16", "Timer prescaler div 16" },
411 io_reg_desc tflg2_desc
[] = {
412 { M6811_TOF
, "TOF ", "Timer Overflow Bit" },
413 { M6811_RTIF
, "RTIF ", "Read Time Interrupt Flag" },
414 { M6811_PAOVF
, "PAOVF ", "Pulse Accumulator Overflow Interrupt Flag" },
415 { M6811_PAIF
, "PAIF ", "Pulse Accumulator Input Edge" },
419 io_reg_desc pactl_desc
[] = {
420 { M6811_DDRA7
, "DDRA7 ", "Data Direction for Port A bit-7" },
421 { M6811_PAEN
, "PAEN ", "Pulse Accumulator System Enable" },
422 { M6811_PAMOD
, "PAMOD ", "Pulse Accumulator Mode" },
423 { M6811_PEDGE
, "PEDGE ", "Pulse Accumulator Edge Control" },
424 { M6811_RTR1
, "RTR1 ", "RTI Interrupt rate select (RTR1)" },
425 { M6811_RTR0
, "RTR0 ", "RTI Interrupt rate select (RTR0)" },
430 to_realtime (sim_cpu
*cpu
, signed64 t
)
432 return (double) (t
) / (double) (cpu
->cpu_frequency
/ 4);
436 cycle_to_string (sim_cpu
*cpu
, signed64 t
)
441 dt
= to_realtime (cpu
, t
);
443 sprintf (buf
, "%llu cycle%s (%3.1f us)", t
,
444 (t
> 1 ? "s" : ""), dt
* 1000000.0);
446 sprintf (buf
, "%llu cycles (%3.1f ms)", t
, dt
* 1000.0);
448 sprintf (buf
, "%llu cycles (%3.1f s)", t
, dt
);
454 m68hc11tim_print_timer (struct hw
*me
, const char *name
,
455 struct hw_event
*event
)
462 sim_io_printf (sd
, " No %s interrupt will be raised.\n", name
);
469 cpu
= STATE_CPU (sd
, 0);
471 t
= hw_event_remain_time (me
, event
);
472 sim_io_printf (sd
, " Next %s interrupt in %s\n",
473 name
, cycle_to_string (cpu
, t
));
478 m68hc11tim_info (struct hw
*me
)
483 struct m68hc11tim
*controller
;
487 cpu
= STATE_CPU (sd
, 0);
488 controller
= hw_data (me
);
490 sim_io_printf (sd
, "M68HC11 Timer:\n");
492 base
= cpu_get_io_base (cpu
);
494 val
= cpu
->ios
[M6811_TMSK2
];
495 print_io_byte (sd
, "TMSK2 ", tmsk2_desc
, val
, base
+ M6811_TMSK2
);
496 sim_io_printf (sd
, "\n");
498 val
= cpu
->ios
[M6811_TFLG2
];
499 print_io_byte (sd
, "TFLG2", tflg2_desc
, val
, base
+ M6811_TFLG2
);
500 sim_io_printf (sd
, "\n");
502 val
= cpu
->ios
[M6811_PACTL
];
503 print_io_byte (sd
, "PACTL", pactl_desc
, val
, base
+ M6811_PACTL
);
504 sim_io_printf (sd
, "\n");
506 /* Give info about the next timer interrupts. */
507 m68hc11tim_print_timer (me
, "RTI", controller
->rti_timer_event
);
508 m68hc11tim_print_timer (me
, "COP", controller
->cop_timer_event
);
509 m68hc11tim_print_timer (me
, "OVERFLOW", controller
->tof_timer_event
);
510 m68hc11tim_print_timer (me
, "COMPARE", controller
->cmp_timer_event
);
514 m68hc11tim_ioctl (struct hw
*me
,
515 hw_ioctl_request request
,
518 m68hc11tim_info (me
);
522 /* generic read/write */
525 m68hc11tim_io_read_buffer (struct hw
*me
,
532 struct m68hc11tim
*controller
;
537 HW_TRACE ((me
, "read 0x%08lx %d", (long) base
, (int) nr_bytes
));
540 cpu
= STATE_CPU (sd
, 0);
541 controller
= hw_data (me
);
547 /* The cpu_absolute_cycle is updated after each instruction.
548 Reading in a 16-bit register will be split in two accesses
549 but this will be atomic within the simulator. */
551 val
= (uint8
) ((cpu
->cpu_absolute_cycle
- controller
->tcnt_adjust
)
552 / (controller
->clock_prescaler
* 256));
556 val
= (uint8
) ((cpu
->cpu_absolute_cycle
- controller
->tcnt_adjust
)
557 / controller
->clock_prescaler
);
561 val
= cpu
->ios
[base
];
564 *((unsigned8
*) dest
) = val
;
574 m68hc11tim_io_write_buffer (struct hw
*me
,
581 struct m68hc11tim
*controller
;
585 int reset_compare
= 0;
586 int reset_overflow
= 0;
589 HW_TRACE ((me
, "write 0x%08lx %d", (long) base
, (int) nr_bytes
));
592 cpu
= STATE_CPU (sd
, 0);
593 controller
= hw_data (me
);
597 val
= *((const unsigned8
*) source
);
600 /* Set the timer counter low part, trying to preserve the low part.
601 We compute the absolute cycle adjustment that we have to apply
602 to obtain the timer current value. Computation must be made
603 in 64-bit to avoid overflow problems. */
605 adj
= ((cpu
->cpu_absolute_cycle
- controller
->tcnt_adjust
)
606 / (controller
->clock_prescaler
* (signed64
) 256)) & 0x0FF;
607 adj
= cpu
->cpu_absolute_cycle
608 - (adj
* controller
->clock_prescaler
* (signed64
) 256)
609 - ((signed64
) adj
* controller
->clock_prescaler
);
610 controller
->tcnt_adjust
= adj
;
616 adj
= ((cpu
->cpu_absolute_cycle
- controller
->tcnt_adjust
)
617 / controller
->clock_prescaler
) & 0x0ff;
618 adj
= cpu
->cpu_absolute_cycle
619 - ((signed64
) val
* controller
->clock_prescaler
* (signed64
) 256)
620 - (adj
* controller
->clock_prescaler
);
621 controller
->tcnt_adjust
= adj
;
628 /* Timer prescaler cannot be changed after 64 bus cycles. */
629 if (cpu
->cpu_absolute_cycle
>= 64)
631 val
&= ~(M6811_PR1
| M6811_PR0
);
632 val
|= cpu
->ios
[M6811_TMSK2
] & (M6811_PR1
| M6811_PR0
);
634 switch (val
& (M6811_PR1
| M6811_PR0
))
646 case M6811_PR1
| M6811_PR0
:
650 if (cpu
->cpu_absolute_cycle
< 64)
653 controller
->clock_prescaler
= n
;
655 cpu
->ios
[base
] = val
;
656 interrupts_update_pending (&cpu
->cpu_interrupts
);
660 n
= (1 << ((val
& (M6811_RTR1
| M6811_RTR0
))));
661 cpu
->ios
[base
] = val
;
663 controller
->rti_delay
= (long) (n
) * 8192;
664 m68hc11tim_timer_event (me
, (void*) (RTI_EVENT
| 0x100));
671 val
|= cpu
->ios
[M6811_TFLG2
] & M6811_TOF
;
673 /* Clear the Real Time interrupt flag. */
674 if (val
& M6811_RTIF
)
677 val
|= cpu
->ios
[M6811_TFLG2
] & M6811_RTIF
;
679 cpu
->ios
[base
] = val
;
680 interrupts_update_pending (&cpu
->cpu_interrupts
);
688 cpu
->ios
[base
] = val
;
702 /* Re-compute the next timer compare event. */
705 m68hc11tim_timer_event (me
, (void*) (COMPARE_EVENT
));
709 m68hc11tim_timer_event (me
, (void*) (OVERFLOW_EVENT
| 0x100));
715 const struct hw_descriptor dv_m68hc11tim_descriptor
[] = {
716 { "m68hc11tim", m68hc11tim_finish
},
717 { "m68hc12tim", m68hc11tim_finish
},