sim/m68hc11/dv-m68hc11tim.c

   1 /*  dv-m68hc11tim.c -- Simulation of the 68HC11 timer devices.
   2     Copyright (C) 1999, 2000, 2002, 2003 Free Software Foundation, Inc.
   3     Written by Stephane Carrez (stcarrez@nerim.fr)
   4     (From a driver model Contributed by Cygnus Solutions.)
   5
   6     This file is part of the program GDB, the GNU debugger.
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either vertimn 2 of the License, or
  11     (at your option) any later vertimn.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  21
  22     */
  23
  24
  25 #include "sim-main.h"
  26 #include "hw-main.h"
  27 #include "sim-assert.h"
  28
  29
  30 /* DEVICE
  31
  32         m68hc11tim - m68hc11 timer devices
  33
  34
  35    DESCRIPTION
  36
  37         Implements the m68hc11 timer as described in Chapter 10
  38         of the pink book.
  39
  40
  41    PROPERTIES
  42
  43         none
  44
  45
  46    PORTS
  47
  48    reset (input)
  49
  50         Reset the timer device.  This port must be connected to
  51         the cpu-reset output port.
  52
  53    capture (input)
  54
  55         Input capture.  This port must be connected to the input
  56         captures.  It latches the current TCNT free running counter
  57         into one of the three input capture registers.
  58
  59    */
  60
  61
  62
  63 /* port ID's */
  64
  65 enum
  66 {
  67   RESET_PORT,
  68   CAPTURE
  69 };
  70
  71
  72 static const struct hw_port_descriptor m68hc11tim_ports[] =
  73 {
  74   { "reset",   RESET_PORT, 0, input_port, },
  75   { "capture", CAPTURE,    0, input_port, },
  76   { NULL, },
  77 };
  78
  79
  80 /* Timer Controller information.  */
  81 struct m68hc11tim
  82 {
  83   unsigned long cop_delay;
  84   unsigned long rti_delay;
  85   unsigned long ovf_delay;
  86   signed64      clock_prescaler;
  87   signed64      tcnt_adjust;
  88   signed64      cop_prev_interrupt;
  89   signed64      rti_prev_interrupt;
  90
  91   /* Periodic timers.  */
  92   struct hw_event *rti_timer_event;
  93   struct hw_event *cop_timer_event;
  94   struct hw_event *tof_timer_event;
  95   struct hw_event *cmp_timer_event;
  96 };
  97
  98
  99
 100 /* Finish off the partially created hw device.  Attach our local
 101    callbacks.  Wire up our port names etc.  */
 102
 103 static hw_io_read_buffer_method m68hc11tim_io_read_buffer;
 104 static hw_io_write_buffer_method m68hc11tim_io_write_buffer;
 105 static hw_port_event_method m68hc11tim_port_event;
 106 static hw_ioctl_method m68hc11tim_ioctl;
 107
 108 #define M6811_TIMER_FIRST_REG (M6811_TCTN)
 109 #define M6811_TIMER_LAST_REG  (M6811_PACNT)
 110
 111
 112 static void
 113 attach_m68hc11tim_regs (struct hw *me,
 114                         struct m68hc11tim *controller)
 115 {
 116   hw_attach_address (hw_parent (me), M6811_IO_LEVEL, io_map,
 117                      M6811_TIMER_FIRST_REG,
 118                      M6811_TIMER_LAST_REG - M6811_TIMER_FIRST_REG + 1,
 119                      me);
 120 }
 121
 122 static void
 123 m68hc11tim_finish (struct hw *me)
 124 {
 125   struct m68hc11tim *controller;
 126
 127   controller = HW_ZALLOC (me, struct m68hc11tim);
 128   set_hw_data (me, controller);
 129   set_hw_io_read_buffer (me, m68hc11tim_io_read_buffer);
 130   set_hw_io_write_buffer (me, m68hc11tim_io_write_buffer);
 131   set_hw_ports (me, m68hc11tim_ports);
 132   set_hw_port_event (me, m68hc11tim_port_event);
 133 #ifdef set_hw_ioctl
 134   set_hw_ioctl (me, m68hc11tim_ioctl);
 135 #else
 136   me->to_ioctl = m68hc11tim_ioctl;
 137 #endif
 138
 139   /* Preset defaults.  */
 140   controller->clock_prescaler = 1;
 141   controller->tcnt_adjust = 0;
 142
 143   /* Attach ourself to our parent bus.  */
 144   attach_m68hc11tim_regs (me, controller);
 145 }
 146
 147
 148 /* An event arrives on an interrupt port.  */
 149
 150 static void
 151 m68hc11tim_port_event (struct hw *me,
 152                        int my_port,
 153                        struct hw *source,
 154                        int source_port,
 155                        int level)
 156 {
 157   SIM_DESC sd;
 158   struct m68hc11tim *controller;
 159   sim_cpu *cpu;
 160   unsigned8 val;
 161   unsigned16 tcnt;
 162
 163   controller = hw_data (me);
 164   sd         = hw_system (me);
 165   cpu        = STATE_CPU (sd, 0);
 166   switch (my_port)
 167     {
 168     case RESET_PORT:
 169       {
 170         HW_TRACE ((me, "Timer reset"));
 171
 172         /* Cancel all timer events.  */
 173         if (controller->rti_timer_event)
 174           {
 175             hw_event_queue_deschedule (me, controller->rti_timer_event);
 176             controller->rti_timer_event = 0;
 177             controller->rti_prev_interrupt = 0;
 178           }
 179         if (controller->cop_timer_event)
 180           {
 181             hw_event_queue_deschedule (me, controller->cop_timer_event);
 182             controller->cop_timer_event = 0;
 183             controller->cop_prev_interrupt = 0;
 184           }
 185         if (controller->tof_timer_event)
 186           {
 187             hw_event_queue_deschedule (me, controller->tof_timer_event);
 188             controller->tof_timer_event = 0;
 189           }
 190         if (controller->cmp_timer_event)
 191           {
 192             hw_event_queue_deschedule (me, controller->cmp_timer_event);
 193             controller->cmp_timer_event = 0;
 194           }
 195
 196         /* Reset the state of Timer registers.  This also restarts
 197            the timer events (overflow and RTI clock).  The pending
 198            flags (TFLG2) must be cleared explicitly here.  */
 199         val = 0;
 200         cpu->ios[M6811_TFLG2] = 0;
 201         m68hc11tim_io_write_buffer (me, &val, io_map,
 202                                     (unsigned_word) M6811_TMSK2, 1);
 203         m68hc11tim_io_write_buffer (me, &val, io_map,
 204                                     (unsigned_word) M6811_PACTL, 1);
 205         break;
 206       }
 207
 208     case CAPTURE:
 209       tcnt = (uint16) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
 210                        / controller->clock_prescaler);
 211       switch (level)
 212         {
 213         case M6811_TIC1:
 214         case M6811_TIC2:
 215         case M6811_TIC3:
 216           cpu->ios[level] = tcnt >> 8;
 217           cpu->ios[level + 1] = tcnt;
 218           break;
 219
 220         default:
 221           hw_abort (me, "Invalid event parameter %d", level);
 222           break;
 223         }
 224       break;
 225
 226     default:
 227       hw_abort (me, "Event on unknown port %d", my_port);
 228       break;
 229     }
 230 }
 231
 232 enum event_type
 233 {
 234   COP_EVENT,
 235   RTI_EVENT,
 236   OVERFLOW_EVENT,
 237   COMPARE_EVENT
 238 };
 239
 240 void
 241 m68hc11tim_timer_event (struct hw *me, void *data)
 242 {
 243   SIM_DESC sd;
 244   struct m68hc11tim *controller;
 245   sim_cpu *cpu;
 246   enum event_type type;
 247   unsigned long delay;
 248   struct hw_event **eventp;
 249   int check_interrupt = 0;
 250   unsigned mask;
 251   unsigned flags;
 252   unsigned long tcnt_internal;
 253   unsigned long tcnt;
 254   int i;
 255   sim_events *events;
 256
 257   controller = hw_data (me);
 258   sd         = hw_system (me);
 259   cpu        = STATE_CPU (sd, 0);
 260   type       = (enum event_type) ((long) data) & 0x0FF;
 261   events     = STATE_EVENTS (sd);
 262
 263   delay = 0;
 264   switch (type)
 265     {
 266     case COP_EVENT:
 267       eventp = &controller->cop_timer_event;
 268       delay  = controller->cop_delay;
 269       delay  = controller->cop_prev_interrupt + controller->cop_delay;
 270       controller->cop_prev_interrupt = delay;
 271       delay  = delay - cpu->cpu_absolute_cycle;
 272       check_interrupt = 1;
 273       delay += events->nr_ticks_to_process;
 274       break;
 275
 276     case RTI_EVENT:
 277       eventp = &controller->rti_timer_event;
 278       delay  = controller->rti_prev_interrupt + controller->rti_delay;
 279
 280       if (((long) (data) & 0x0100) == 0)
 281         {
 282           cpu->ios[M6811_TFLG2] |= M6811_RTIF;
 283           check_interrupt = 1;
 284           controller->rti_prev_interrupt = delay;
 285           delay += controller->rti_delay;
 286         }
 287       delay = delay - cpu->cpu_absolute_cycle;
 288       delay += events->nr_ticks_to_process;
 289       break;
 290
 291     case OVERFLOW_EVENT:
 292       /* Compute the 68HC11 internal free running counter.
 293          There may be 'nr_ticks_to_process' pending cycles that are
 294          not (yet) taken into account by 'sim_events_time'.  */
 295       tcnt_internal = sim_events_time (sd) - controller->tcnt_adjust;
 296       tcnt_internal += events->nr_ticks_to_process;
 297
 298       /* We must take into account the prescaler that comes
 299          before the counter (it's a power of 2).  */
 300       tcnt_internal &= 0x0ffff * controller->clock_prescaler;
 301
 302       /* Compute the time when the overflow will occur.  It occurs when
 303          the counter increments from 0x0ffff to 0x10000 (and thus resets).  */
 304       delay = (0x10000 * controller->clock_prescaler) - tcnt_internal;
 305
 306       /* The 'nr_ticks_to_process' will be subtracted when the event
 307          is scheduled.  */
 308       delay += events->nr_ticks_to_process;
 309
 310       eventp = &controller->tof_timer_event;
 311       if (((long) (data) & 0x100) == 0)
 312         {
 313           cpu->ios[M6811_TFLG2] |= M6811_TOF;
 314           check_interrupt = 1;
 315         }
 316       break;
 317
 318     case COMPARE_EVENT:
 319       eventp = &controller->cmp_timer_event;
 320
 321       /* Compute the 68HC11 internal free running counter.
 322          There may be 'nr_ticks_to_process' pending cycles that are
 323          not (yet) taken into account by 'sim_events_time'.  */
 324       events = STATE_EVENTS (sd);
 325       tcnt_internal = sim_events_time (sd) - controller->tcnt_adjust;
 326       tcnt_internal += events->nr_ticks_to_process;
 327
 328       /* We must take into account the prescaler that comes
 329          before the counter (it's a power of 2).  */
 330       tcnt_internal &= 0x0ffff * controller->clock_prescaler;
 331
 332       /* Get current visible TCNT register value.  */
 333       tcnt = tcnt_internal / controller->clock_prescaler;
 334
 335       flags = cpu->ios[M6811_TMSK1];
 336       mask  = 0x80;
 337       delay = 65536 * controller->clock_prescaler;
 338
 339       /* Scan each output compare register to see if one matches
 340          the free running counter.  Set the corresponding OCi flag
 341          if the output compare is enabled.  */
 342       for (i = M6811_TOC1; i <= M6811_TOC5; i += 2, mask >>= 1)
 343         {
 344           unsigned long compare;
 345
 346           compare = (cpu->ios[i] << 8) + cpu->ios[i+1];
 347           if (compare == tcnt && (flags & mask))
 348             {
 349               cpu->ios[M6811_TFLG1] |= mask;
 350               check_interrupt++;
 351             }
 352
 353           /* Compute how many times for the next match.
 354              Use the internal counter value to take into account the
 355              prescaler accurately.  */
 356           compare = compare * controller->clock_prescaler;
 357           if (compare > tcnt_internal)
 358             compare = compare - tcnt_internal;
 359           else
 360             compare = compare - tcnt_internal
 361               + 65536 * controller->clock_prescaler;
 362
 363           if (compare < delay)
 364             delay = compare;
 365         }
 366
 367       /* Deactivate the compare timer if no output compare is enabled.  */
 368       if ((flags & 0xF0) == 0)
 369         delay = 0;
 370       break;
 371
 372     default:
 373       eventp = 0;
 374       break;
 375     }
 376
 377   if (*eventp)
 378     {
 379       hw_event_queue_deschedule (me, *eventp);
 380       *eventp = 0;
 381     }
 382
 383   if (delay != 0)
 384     {
 385       *eventp = hw_event_queue_schedule (me, delay,
 386                                          m68hc11tim_timer_event,
 387                                          (void*) type);
 388     }
 389
 390   if (check_interrupt)
 391     interrupts_update_pending (&cpu->cpu_interrupts);
 392 }
 393
 394
 395 /* Descriptions of the Timer I/O ports.  These descriptions are only used to
 396    give information of the Timer device under GDB.  */
 397 io_reg_desc tmsk1_desc[] = {
 398   { M6811_OC1I,  "OC1I ", "Timer Output Compare 1 Interrupt Enable" },
 399   { M6811_OC2I,  "OC2I ", "Timer Output Compare 2 Interrupt Enable" },
 400   { M6811_OC3I,  "OC3I ", "Timer Output Compare 3 Interrupt Enable" },
 401   { M6811_OC4I,  "OC4I ", "Timer Output Compare 4 Interrupt Enable" },
 402   { M6811_OC5I,  "OC5I ", "Timer Input Capture 4 / Output Compare 5 Enable" },
 403   { M6811_IC1I,  "IC1I ", "Timer Input Capture 1 Interrupt Enable" },
 404   { M6811_IC2I,  "IC2I ", "Timer Input Capture 2 Interrupt Enable" },
 405   { M6811_IC3I,  "IC3I ", "Timer Input Capture 3 Interrupt Enable" },
 406   { 0, 0, 0 }
 407 };
 408
 409 io_reg_desc tflg1_desc[] = {
 410   { M6811_OC1F,  "OC1F ", "Timer Output Compare 1 Interrupt Flag" },
 411   { M6811_OC2F,  "OC2F ", "Timer Output Compare 2 Interrupt Flag" },
 412   { M6811_OC3F,  "OC3F ", "Timer Output Compare 3 Interrupt Flag" },
 413   { M6811_OC4F,  "OC4F ", "Timer Output Compare 4 Interrupt Flag" },
 414   { M6811_OC5F,  "OC5F ", "Timer Input Capture 4 / Output Compare 5 Flag" },
 415   { M6811_IC1F,  "IC1F ", "Timer Input Capture 1 Interrupt Flag" },
 416   { M6811_IC2F,  "IC2F ", "Timer Input Capture 2 Interrupt Flag" },
 417   { M6811_IC3F,  "IC3F ", "Timer Input Capture 3 Interrupt Flag" },
 418   { 0, 0, 0 }
 419 };
 420
 421 io_reg_desc tmsk2_desc[] = {
 422   { M6811_TOI,    "TOI   ", "Timer Overflow Interrupt Enable" },
 423   { M6811_RTII,   "RTII  ", "RTI Interrupt Enable" },
 424   { M6811_PAOVI,  "PAOVI ", "Pulse Accumulator Overflow Interrupt Enable" },
 425   { M6811_PAII,   "PAII  ", "Pulse Accumulator Interrupt Enable" },
 426   { M6811_PR1,    "PR1   ", "Timer prescaler (PR1)" },
 427   { M6811_PR0,    "PR0   ", "Timer prescaler (PR0)" },
 428   { M6811_TPR_1,  "TPR_1 ", "Timer prescaler div 1" },
 429   { M6811_TPR_4,  "TPR_4 ", "Timer prescaler div 4" },
 430   { M6811_TPR_8,  "TPR_8 ", "Timer prescaler div 8" },
 431   { M6811_TPR_16, "TPR_16", "Timer prescaler div 16" },
 432   { 0,  0, 0 }
 433 };
 434
 435 io_reg_desc tflg2_desc[] = {
 436   { M6811_TOF,   "TOF   ", "Timer Overflow Bit" },
 437   { M6811_RTIF,  "RTIF  ", "Read Time Interrupt Flag" },
 438   { M6811_PAOVF, "PAOVF ", "Pulse Accumulator Overflow Interrupt Flag" },
 439   { M6811_PAIF,  "PAIF  ", "Pulse Accumulator Input Edge" },
 440   { 0,  0, 0 }
 441 };
 442
 443 io_reg_desc pactl_desc[] = {
 444   { M6811_DDRA7,  "DDRA7 ", "Data Direction for Port A bit-7" },
 445   { M6811_PAEN,   "PAEN  ", "Pulse Accumulator System Enable" },
 446   { M6811_PAMOD,  "PAMOD ", "Pulse Accumulator Mode" },
 447   { M6811_PEDGE,  "PEDGE ", "Pulse Accumulator Edge Control" },
 448   { M6811_RTR1,   "RTR1  ", "RTI Interrupt rate select (RTR1)" },
 449   { M6811_RTR0,   "RTR0  ", "RTI Interrupt rate select (RTR0)" },
 450   { 0,  0, 0 }
 451 };
 452
 453 static double
 454 to_realtime (sim_cpu *cpu, signed64 t)
 455 {
 456   return (double) (t) / (double) (cpu->cpu_frequency / 4);
 457 }
 458
 459 const char*
 460 cycle_to_string (sim_cpu *cpu, signed64 t)
 461 {
 462   double dt;
 463   char tbuf[32];
 464   static char buf[64];
 465
 466   dt = to_realtime (cpu, t);
 467   if (dt < 0.001)
 468     sprintf (tbuf, "(%3.1f us)", dt * 1000000.0);
 469   else if (dt < 1.0)
 470     sprintf (tbuf, "(%3.1f ms)", dt * 1000.0);
 471   else
 472     sprintf (tbuf, "(%3.1f s)", dt);
 473
 474   sprintf (buf, "%llu cycle%s %10.10s", t,
 475              (t > 1 ? "s" : ""), tbuf);
 476   return buf;
 477 }
 478
 479 static void
 480 m68hc11tim_print_timer (struct hw *me, const char *name,
 481                         struct hw_event *event)
 482 {
 483   SIM_DESC sd;
 484
 485   sd = hw_system (me);
 486   if (event == 0)
 487     {
 488       sim_io_printf (sd, "  No %s interrupt will be raised.\n", name);
 489     }
 490   else
 491     {
 492       signed64 t;
 493       sim_cpu* cpu;
 494
 495       cpu = STATE_CPU (sd, 0);
 496
 497       t  = hw_event_remain_time (me, event);
 498       sim_io_printf (sd, "  Next %s interrupt in %s\n",
 499                      name, cycle_to_string (cpu, t));
 500     }
 501 }
 502
 503 static void
 504 m68hc11tim_info (struct hw *me)
 505 {
 506   SIM_DESC sd;
 507   uint16 base = 0;
 508   sim_cpu *cpu;
 509   struct m68hc11tim *controller;
 510   uint8 val;
 511   uint16 val16;
 512
 513   sd = hw_system (me);
 514   cpu = STATE_CPU (sd, 0);
 515   controller = hw_data (me);
 516
 517   sim_io_printf (sd, "M68HC11 Timer:\n");
 518
 519   base = cpu_get_io_base (cpu);
 520
 521   /* Info for TIC1 */
 522   val16  = (cpu->ios[M6811_TIC1_H] << 8) + cpu->ios[M6811_TIC1_L];
 523   print_io_word (sd, "TIC1 ", 0, val16, base + M6811_TIC1);
 524   sim_io_printf (sd, "\n");
 525
 526   /* Info for TIC2 */
 527   val16  = (cpu->ios[M6811_TIC2_H] << 8) + cpu->ios[M6811_TIC2_L];
 528   print_io_word (sd, "TIC2 ", 0, val16, base + M6811_TIC2);
 529   sim_io_printf (sd, "\n");
 530
 531   /* Info for TIC3 */
 532   val16  = (cpu->ios[M6811_TIC3_H] << 8) + cpu->ios[M6811_TIC3_L];
 533   print_io_word (sd, "TIC3 ", 0, val16, base + M6811_TIC3);
 534   sim_io_printf (sd, "\n");
 535
 536   /* Info for TOC1 */
 537   val16  = (cpu->ios[M6811_TOC1_H] << 8) + cpu->ios[M6811_TOC1_L];
 538   print_io_word (sd, "TOC1 ", 0, val16, base + M6811_TOC1);
 539   sim_io_printf (sd, "\n");
 540
 541   /* Info for TOC2 */
 542   val16  = (cpu->ios[M6811_TOC2_H] << 8) + cpu->ios[M6811_TOC2_L];
 543   print_io_word (sd, "TOC2 ", 0, val16, base + M6811_TOC2);
 544   sim_io_printf (sd, "\n");
 545
 546   /* Info for TOC3 */
 547   val16  = (cpu->ios[M6811_TOC3_H] << 8) + cpu->ios[M6811_TOC3_L];
 548   print_io_word (sd, "TOC3 ", 0, val16, base + M6811_TOC3);
 549   sim_io_printf (sd, "\n");
 550
 551   /* Info for TOC4 */
 552   val16  = (cpu->ios[M6811_TOC4_H] << 8) + cpu->ios[M6811_TOC4_L];
 553   print_io_word (sd, "TOC4 ", 0, val16, base + M6811_TOC4);
 554   sim_io_printf (sd, "\n");
 555
 556   /* Info for TOC5 */
 557   val16  = (cpu->ios[M6811_TOC5_H] << 8) + cpu->ios[M6811_TOC5_L];
 558   print_io_word (sd, "TOC5 ", 0, val16, base + M6811_TOC5);
 559   sim_io_printf (sd, "\n");
 560
 561   /* Info for TMSK1 */
 562   val  = cpu->ios[M6811_TMSK1];
 563   print_io_byte (sd, "TMSK1 ", tmsk1_desc, val, base + M6811_TMSK1);
 564   sim_io_printf (sd, "\n");
 565
 566   /* Info for TFLG1 */
 567   val = cpu->ios[M6811_TFLG1];
 568   print_io_byte (sd, "TFLG1", tflg1_desc, val, base + M6811_TFLG1);
 569   sim_io_printf (sd, "\n");
 570
 571   val  = cpu->ios[M6811_TMSK2];
 572   print_io_byte (sd, "TMSK2 ", tmsk2_desc, val, base + M6811_TMSK2);
 573   sim_io_printf (sd, "\n");
 574
 575   val = cpu->ios[M6811_TFLG2];
 576   print_io_byte (sd, "TFLG2", tflg2_desc, val, base + M6811_TFLG2);
 577   sim_io_printf (sd, "\n");
 578
 579   val = cpu->ios[M6811_PACTL];
 580   print_io_byte (sd, "PACTL", pactl_desc, val, base + M6811_PACTL);
 581   sim_io_printf (sd, "\n");
 582
 583   val = cpu->ios[M6811_PACNT];
 584   print_io_byte (sd, "PACNT", 0, val, base + M6811_PACNT);
 585   sim_io_printf (sd, "\n");
 586
 587   /* Give info about the next timer interrupts.  */
 588   m68hc11tim_print_timer (me, "RTI", controller->rti_timer_event);
 589   m68hc11tim_print_timer (me, "COP", controller->cop_timer_event);
 590   m68hc11tim_print_timer (me, "OVERFLOW", controller->tof_timer_event);
 591   m68hc11tim_print_timer (me, "COMPARE", controller->cmp_timer_event);
 592 }
 593
 594 static int
 595 m68hc11tim_ioctl (struct hw *me,
 596                   hw_ioctl_request request,
 597                   va_list ap)
 598 {
 599   m68hc11tim_info (me);
 600   return 0;
 601 }
 602
 603 /* generic read/write */
 604
 605 static unsigned
 606 m68hc11tim_io_read_buffer (struct hw *me,
 607                            void *dest,
 608                            int space,
 609                            unsigned_word base,
 610                            unsigned nr_bytes)
 611 {
 612   SIM_DESC sd;
 613   struct m68hc11tim *controller;
 614   sim_cpu *cpu;
 615   unsigned8 val;
 616   unsigned cnt = 0;
 617
 618   HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
 619
 620   sd  = hw_system (me);
 621   cpu = STATE_CPU (sd, 0);
 622   controller = hw_data (me);
 623
 624   while (nr_bytes)
 625     {
 626       switch (base)
 627         {
 628           /* The cpu_absolute_cycle is updated after each instruction.
 629              Reading in a 16-bit register will be split in two accesses
 630              but this will be atomic within the simulator.  */
 631         case M6811_TCTN_H:
 632           val = (uint8) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
 633                          / (controller->clock_prescaler * 256));
 634           break;
 635
 636         case M6811_TCTN_L:
 637           val = (uint8) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
 638                          / controller->clock_prescaler);
 639           break;
 640
 641         default:
 642           val = cpu->ios[base];
 643           break;
 644         }
 645       *((unsigned8*) dest) = val;
 646       dest++;
 647       base++;
 648       nr_bytes--;
 649       cnt++;
 650     }
 651   return cnt;
 652 }
 653
 654 static unsigned
 655 m68hc11tim_io_write_buffer (struct hw *me,
 656                             const void *source,
 657                             int space,
 658                             unsigned_word base,
 659                             unsigned nr_bytes)
 660 {
 661   SIM_DESC sd;
 662   struct m68hc11tim *controller;
 663   sim_cpu *cpu;
 664   unsigned8 val, n;
 665   signed64 adj;
 666   int reset_compare = 0;
 667   int reset_overflow = 0;
 668   int cnt = 0;
 669
 670   HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
 671
 672   sd  = hw_system (me);
 673   cpu = STATE_CPU (sd, 0);
 674   controller = hw_data (me);
 675
 676   while (nr_bytes)
 677     {
 678       val = *((const unsigned8*) source);
 679       switch (base)
 680         {
 681           /* Set the timer counter low part, trying to preserve the low part.
 682              We compute the absolute cycle adjustment that we have to apply
 683              to obtain the timer current value.  Computation must be made
 684              in 64-bit to avoid overflow problems.  */
 685         case M6811_TCTN_L:
 686           adj = ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
 687                  / (controller->clock_prescaler * (signed64) 256)) & 0x0FF;
 688           adj = cpu->cpu_absolute_cycle
 689             - (adj * controller->clock_prescaler * (signed64) 256)
 690             - ((signed64) adj * controller->clock_prescaler);
 691           controller->tcnt_adjust = adj;
 692           reset_compare = 1;
 693           reset_overflow = 1;
 694           break;
 695
 696         case M6811_TCTN_H:
 697           adj = ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
 698                  / controller->clock_prescaler) & 0x0ff;
 699           adj = cpu->cpu_absolute_cycle
 700             - ((signed64) val * controller->clock_prescaler * (signed64) 256)
 701             - (adj * controller->clock_prescaler);
 702           controller->tcnt_adjust = adj;
 703           reset_compare = 1;
 704           reset_overflow = 1;
 705           break;
 706
 707         case M6811_TMSK2:
 708
 709           /* Timer prescaler cannot be changed after 64 bus cycles.  */
 710           if (cpu->cpu_absolute_cycle >= 64)
 711             {
 712               val &= ~(M6811_PR1 | M6811_PR0);
 713               val |= cpu->ios[M6811_TMSK2] & (M6811_PR1 | M6811_PR0);
 714             }
 715           switch (val & (M6811_PR1 | M6811_PR0))
 716             {
 717             case 0:
 718               n = 1;
 719               break;
 720             case M6811_PR0:
 721               n = 4;
 722               break;
 723             case M6811_PR1:
 724               n = 8;
 725               break;
 726             default:
 727             case M6811_PR1 | M6811_PR0:
 728               n = 16;
 729               break;
 730             }
 731           if (cpu->cpu_absolute_cycle < 64)
 732             {
 733               reset_overflow = 1;
 734               controller->clock_prescaler = n;
 735             }
 736           cpu->ios[base] = val;
 737           interrupts_update_pending (&cpu->cpu_interrupts);
 738           break;
 739
 740         case M6811_PACTL:
 741           n = (1 << ((val & (M6811_RTR1 | M6811_RTR0))));
 742           cpu->ios[base] = val;
 743
 744           controller->rti_delay = (long) (n) * 8192;
 745           m68hc11tim_timer_event (me, (void*) (RTI_EVENT| 0x100));
 746           break;
 747
 748         case M6811_TFLG2:
 749           val &= cpu->ios[M6811_TFLG2];
 750           cpu->ios[M6811_TFLG2] &= ~val;
 751           interrupts_update_pending (&cpu->cpu_interrupts);
 752           break;
 753
 754         case M6811_TMSK1:
 755           cpu->ios[M6811_TMSK1] = val;
 756           interrupts_update_pending (&cpu->cpu_interrupts);
 757           break;
 758
 759         case M6811_TFLG1:
 760           val &= cpu->ios[M6811_TFLG1];
 761           cpu->ios[M6811_TFLG1] &= ~val;
 762           interrupts_update_pending (&cpu->cpu_interrupts);
 763           break;
 764
 765         case M6811_TOC1:
 766         case M6811_TOC2:
 767         case M6811_TOC3:
 768         case M6811_TOC4:
 769         case M6811_TOC5:
 770           cpu->ios[base] = val;
 771           reset_compare = 1;
 772           break;
 773
 774         case M6811_TCTL1:
 775         case M6811_TCTL2:
 776           cpu->ios[base] = val;
 777           break;
 778
 779         default:
 780           cpu->ios[base] = val;
 781           break;
 782         }
 783
 784       base++;
 785       nr_bytes--;
 786       cnt++;
 787       source++;
 788     }
 789
 790   /* Re-compute the next timer compare event.  */
 791   if (reset_compare)
 792     {
 793       m68hc11tim_timer_event (me, (void*) (COMPARE_EVENT));
 794     }
 795   if (reset_overflow)
 796     {
 797       m68hc11tim_timer_event (me, (void*) (OVERFLOW_EVENT| 0x100));
 798     }
 799   return cnt;
 800 }
 801
 802
 803 const struct hw_descriptor dv_m68hc11tim_descriptor[] = {
 804   { "m68hc11tim", m68hc11tim_finish },
 805   { "m68hc12tim", m68hc11tim_finish },
 806   { NULL },
 807 };
 808