sim/m68hc11/sim-main.h

   1 /* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
   2    Copyright (C) 1999-2016 Free Software Foundation, Inc.
   3    Written by Stephane Carrez (stcarrez@nerim.fr)
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef _SIM_MAIN_H
  21 #define _SIM_MAIN_H
  22
  23 #include "sim-basics.h"
  24 #include "sim-signal.h"
  25 #include "sim-base.h"
  26
  27 #include "bfd.h"
  28
  29 #include "opcode/m68hc11.h"
  30
  31 #include "gdb/callback.h"
  32 #include "gdb/remote-sim.h"
  33 #include "opcode/m68hc11.h"
  34 #include "sim-types.h"
  35
  36 typedef unsigned8 uint8;
  37 typedef unsigned16 uint16;
  38 typedef signed16 int16;
  39 typedef unsigned32 uint32;
  40 typedef signed32 int32;
  41 typedef unsigned64 uint64;
  42 typedef signed64 int64;
  43
  44 struct _sim_cpu;
  45
  46 #include "interrupts.h"
  47 #include <setjmp.h>
  48
  49 /* Specifies the level of mapping for the IO, EEprom, nvram and external
  50    RAM.  IO registers are mapped over everything and the external RAM
  51    is last (ie, it can be hidden by everything above it in the list).  */
  52 enum m68hc11_map_level
  53 {
  54   M6811_IO_LEVEL,
  55   M6811_EEPROM_LEVEL,
  56   M6811_NVRAM_LEVEL,
  57   M6811_RAM_LEVEL
  58 };
  59
  60 enum cpu_type
  61 {
  62   CPU_M6811,
  63   CPU_M6812
  64 };
  65
  66 #define X_REGNUM        0
  67 #define D_REGNUM        1
  68 #define Y_REGNUM        2
  69 #define SP_REGNUM       3
  70 #define PC_REGNUM       4
  71 #define A_REGNUM        5
  72 #define B_REGNUM        6
  73 #define PSW_REGNUM      7
  74 #define PAGE_REGNUM     8
  75 #define Z_REGNUM        9
  76
  77 typedef struct m6811_regs {
  78     unsigned short      d;
  79     unsigned short      ix;
  80     unsigned short      iy;
  81     unsigned short      sp;
  82     unsigned short      pc;
  83     unsigned char       ccr;
  84   unsigned short      page;
  85 } m6811_regs;
  86
  87
  88 /* Description of 68HC11 IO registers.  Such description is only provided
  89    for the info command to display the current setting of IO registers
  90    from GDB.  */
  91 struct io_reg_desc
  92 {
  93   int        mask;
  94   const char *short_name;
  95   const char *long_name;
  96 };
  97 typedef struct io_reg_desc io_reg_desc;
  98
  99 extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
 100                                int mode);
 101 extern void print_io_byte (SIM_DESC sd, const char *name,
 102                            io_reg_desc *desc, uint8 val, uint16 addr);
 103 extern void print_io_word (SIM_DESC sd, const char *name,
 104                            io_reg_desc *desc, uint16 val, uint16 addr);
 105
 106
 107 /* List of special 68HC11&68HC12 instructions that are not handled by the
 108    'gencode.c' generator.  These complex instructions are implemented
 109    by 'cpu_special'.  */
 110 enum M6811_Special
 111 {
 112   /* 68HC11 instructions.  */
 113   M6811_DAA,
 114   M6811_EMUL_SYSCALL,
 115   M6811_ILLEGAL,
 116   M6811_RTI,
 117   M6811_STOP,
 118   M6811_SWI,
 119   M6811_TEST,
 120   M6811_WAI,
 121
 122   /* 68HC12 instructions.  */
 123   M6812_BGND,
 124   M6812_CALL,
 125   M6812_CALL_INDIRECT,
 126   M6812_IDIVS,
 127   M6812_EDIV,
 128   M6812_EDIVS,
 129   M6812_EMACS,
 130   M6812_EMUL,
 131   M6812_EMULS,
 132   M6812_ETBL,
 133   M6812_MEM,
 134   M6812_REV,
 135   M6812_REVW,
 136   M6812_RTC,
 137   M6812_RTI,
 138   M6812_WAV
 139 };
 140
 141 #define M6811_MAX_PORTS (0x03f+1)
 142 #define M6812_MAX_PORTS (0x3ff+1)
 143 #define MAX_PORTS       (M6812_MAX_PORTS)
 144
 145 struct _sim_cpu;
 146
 147 typedef void (* cpu_interp) (struct _sim_cpu*);
 148
 149 struct _sim_cpu {
 150   /* CPU registers.  */
 151   struct m6811_regs     cpu_regs;
 152
 153   /* CPU interrupts.  */
 154   struct interrupts     cpu_interrupts;
 155
 156   /* Pointer to the interpretor routine.  */
 157   cpu_interp            cpu_interpretor;
 158
 159   /* Pointer to the architecture currently configured in the simulator.  */
 160   const struct bfd_arch_info  *cpu_configured_arch;
 161
 162   /* CPU absolute cycle time.  The cycle time is updated after
 163      each instruction, by the number of cycles taken by the instruction.
 164      It is cleared only when reset occurs.  */
 165   signed64              cpu_absolute_cycle;
 166
 167   /* Number of cycles to increment after the current instruction.
 168      This is also the number of ticks for the generic event scheduler.  */
 169   uint8                 cpu_current_cycle;
 170   int                   cpu_emul_syscall;
 171   int                   cpu_is_initialized;
 172   int                   cpu_running;
 173   int                   cpu_check_memory;
 174   int                   cpu_stop_on_interrupt;
 175
 176   /* When this is set, start execution of program at address specified
 177      in the ELF header.  This is used for testing some programs that do not
 178      have an interrupt table linked with them.  Programs created during the
 179      GCC validation are like this. A normal 68HC11 does not behave like
 180      this (unless there is some OS or downloadable feature).  */
 181   int                   cpu_use_elf_start;
 182
 183   /* The starting address specified in ELF header.  */
 184   int                   cpu_elf_start;
 185
 186   uint16                cpu_insn_pc;
 187
 188   /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
 189      get the cycle time.  This is used for the timer rate and for the baud
 190      rate generation.  */
 191   unsigned long         cpu_frequency;
 192
 193   /* The mode in which the CPU is configured (MODA and MODB pins).  */
 194   unsigned int          cpu_mode;
 195   const char*           cpu_start_mode;
 196
 197   /* The cpu being configured.  */
 198   enum cpu_type         cpu_type;
 199
 200   /* Initial value of the CONFIG register.  */
 201   uint8                 cpu_config;
 202   uint8                 cpu_use_local_config;
 203
 204   uint8                 ios[MAX_PORTS];
 205
 206   /* Memory bank parameters which describe how the memory bank window
 207      is mapped in memory and how to convert it in virtual address.  */
 208   uint16                bank_start;
 209   uint16                bank_end;
 210   address_word          bank_virtual;
 211   unsigned              bank_shift;
 212
 213
 214   struct hw            *hw_cpu;
 215
 216   /* ... base type ... */
 217   sim_cpu_base base;
 218 };
 219
 220 /* Returns the cpu absolute cycle time (A virtual counter incremented
 221    at each 68HC11 E clock).  */
 222 #define cpu_current_cycle(cpu)    ((cpu)->cpu_absolute_cycle)
 223 #define cpu_add_cycles(cpu, T)    ((cpu)->cpu_current_cycle += (signed64) (T))
 224 #define cpu_is_running(cpu)       ((cpu)->cpu_running)
 225
 226 /* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
 227 #define cpu_get_io_base(cpu) \
 228   (((uint16)(((cpu)->ios[M6811_INIT]) & 0x0F)) << 12)
 229 #define cpu_get_reg_base(cpu) \
 230   (((uint16)(((cpu)->ios[M6811_INIT]) & 0xF0)) << 8)
 231
 232 /* Returns the different CPU registers.  */
 233 #define cpu_get_ccr(cpu)          ((cpu)->cpu_regs.ccr)
 234 #define cpu_get_pc(cpu)           ((cpu)->cpu_regs.pc)
 235 #define cpu_get_d(cpu)            ((cpu)->cpu_regs.d)
 236 #define cpu_get_x(cpu)            ((cpu)->cpu_regs.ix)
 237 #define cpu_get_y(cpu)            ((cpu)->cpu_regs.iy)
 238 #define cpu_get_sp(cpu)           ((cpu)->cpu_regs.sp)
 239 #define cpu_get_a(cpu)            (((cpu)->cpu_regs.d >> 8) & 0x0FF)
 240 #define cpu_get_b(cpu)            ((cpu)->cpu_regs.d & 0x0FF)
 241 #define cpu_get_page(cpu)         ((cpu)->cpu_regs.page)
 242
 243 /* 68HC12 specific and Motorola internal registers.  */
 244 #define cpu_get_tmp3(cpu)         (0)
 245 #define cpu_get_tmp2(cpu)         (0)
 246
 247 #define cpu_set_d(cpu, val)       ((cpu)->cpu_regs.d = (val))
 248 #define cpu_set_x(cpu, val)       ((cpu)->cpu_regs.ix = (val))
 249 #define cpu_set_y(cpu, val)       ((cpu)->cpu_regs.iy = (val))
 250 #define cpu_set_page(cpu, val)    ((cpu)->cpu_regs.page = (val))
 251
 252 /* 68HC12 specific and Motorola internal registers.  */
 253 #define cpu_set_tmp3(cpu, val)    (0)
 254 #define cpu_set_tmp2(cpu, val)    (void) (0)
 255
 256 #if 0
 257 /* This is a function in m68hc11_sim.c to keep track of the frame.  */
 258 #define cpu_set_sp(cpu, val)      ((cpu)->cpu_regs.sp = (val))
 259 #endif
 260
 261 #define cpu_set_pc(cpu, val)      ((cpu)->cpu_regs.pc = (val))
 262
 263 #define cpu_set_a(cpu, val)  \
 264   cpu_set_d(cpu, ((val) << 8) | cpu_get_b (cpu))
 265 #define cpu_set_b(cpu, val)  \
 266   cpu_set_d(cpu, ((cpu_get_a (cpu)) << 8) | ((val) & 0x0FF))
 267
 268 #define cpu_set_ccr(cpu, val)     ((cpu)->cpu_regs.ccr = (val))
 269 #define cpu_get_ccr_H(cpu)        ((cpu_get_ccr (cpu) & M6811_H_BIT) ? 1 : 0)
 270 #define cpu_get_ccr_X(cpu)        ((cpu_get_ccr (cpu) & M6811_X_BIT) ? 1 : 0)
 271 #define cpu_get_ccr_S(cpu)        ((cpu_get_ccr (cpu) & M6811_S_BIT) ? 1 : 0)
 272 #define cpu_get_ccr_N(cpu)        ((cpu_get_ccr (cpu) & M6811_N_BIT) ? 1 : 0)
 273 #define cpu_get_ccr_V(cpu)        ((cpu_get_ccr (cpu) & M6811_V_BIT) ? 1 : 0)
 274 #define cpu_get_ccr_C(cpu)        ((cpu_get_ccr (cpu) & M6811_C_BIT) ? 1 : 0)
 275 #define cpu_get_ccr_Z(cpu)        ((cpu_get_ccr (cpu) & M6811_Z_BIT) ? 1 : 0)
 276 #define cpu_get_ccr_I(cpu)        ((cpu_get_ccr (cpu) & M6811_I_BIT) ? 1 : 0)
 277
 278 #define cpu_set_ccr_flag(S, B, V) \
 279   cpu_set_ccr (S, (cpu_get_ccr (S) & ~(B)) | ((V) ? (B) : 0))
 280
 281 #define cpu_set_ccr_H(cpu, val)   cpu_set_ccr_flag (cpu, M6811_H_BIT, val)
 282 #define cpu_set_ccr_X(cpu, val)   cpu_set_ccr_flag (cpu, M6811_X_BIT, val)
 283 #define cpu_set_ccr_S(cpu, val)   cpu_set_ccr_flag (cpu, M6811_S_BIT, val)
 284 #define cpu_set_ccr_N(cpu, val)   cpu_set_ccr_flag (cpu, M6811_N_BIT, val)
 285 #define cpu_set_ccr_V(cpu, val)   cpu_set_ccr_flag (cpu, M6811_V_BIT, val)
 286 #define cpu_set_ccr_C(cpu, val)   cpu_set_ccr_flag (cpu, M6811_C_BIT, val)
 287 #define cpu_set_ccr_Z(cpu, val)   cpu_set_ccr_flag (cpu, M6811_Z_BIT, val)
 288 #define cpu_set_ccr_I(cpu, val)   cpu_set_ccr_flag (cpu, M6811_I_BIT, val)
 289
 290 #undef inline
 291 #define inline static __inline__
 292
 293 extern void cpu_memory_exception (sim_cpu *cpu,
 294                                   SIM_SIGNAL excep,
 295                                   uint16 addr,
 296                                   const char *message);
 297
 298 inline address_word
 299 phys_to_virt (sim_cpu *cpu, address_word addr)
 300 {
 301   if (addr >= cpu->bank_start && addr < cpu->bank_end)
 302     return ((address_word) (addr - cpu->bank_start)
 303             + (((address_word) cpu->cpu_regs.page) << cpu->bank_shift)
 304             + cpu->bank_virtual);
 305   else
 306     return (address_word) (addr);
 307 }
 308
 309 inline uint8
 310 memory_read8 (sim_cpu *cpu, uint16 addr)
 311 {
 312   uint8 val;
 313
 314   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 315     {
 316       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 317                             "Read error");
 318     }
 319   return val;
 320 }
 321
 322 inline void
 323 memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
 324 {
 325   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 326     {
 327       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 328                             "Write error");
 329     }
 330 }
 331
 332 inline uint16
 333 memory_read16 (sim_cpu *cpu, uint16 addr)
 334 {
 335   uint8 b[2];
 336
 337   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 338     {
 339       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 340                             "Read error");
 341     }
 342   return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
 343 }
 344
 345 inline void
 346 memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
 347 {
 348   uint8 b[2];
 349
 350   b[0] = val >> 8;
 351   b[1] = val;
 352   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 353     {
 354       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 355                             "Write error");
 356     }
 357 }
 358 extern void
 359 cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val);
 360
 361      inline void
 362 cpu_ccr_update_tst16 (sim_cpu *cpu, uint16 val)
 363 {
 364   cpu_set_ccr_V (cpu, 0);
 365   cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
 366   cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 367 }
 368
 369      inline void
 370 cpu_ccr_update_shift8 (sim_cpu *cpu, uint8 val)
 371 {
 372   cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
 373   cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 374   cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
 375 }
 376
 377      inline void
 378 cpu_ccr_update_shift16 (sim_cpu *cpu, uint16 val)
 379 {
 380   cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
 381   cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 382   cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
 383 }
 384
 385 inline void
 386 cpu_ccr_update_add8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
 387 {
 388   cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
 389   cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
 390   cpu_set_ccr_Z (cpu, r == 0);
 391   cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
 392 }
 393
 394
 395 inline void
 396 cpu_ccr_update_sub8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
 397 {
 398   cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
 399   cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
 400   cpu_set_ccr_Z (cpu, r == 0);
 401   cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
 402 }
 403
 404 inline void
 405 cpu_ccr_update_add16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
 406 {
 407   cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
 408   cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
 409   cpu_set_ccr_Z (cpu, r == 0);
 410   cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
 411 }
 412
 413 inline void
 414 cpu_ccr_update_sub16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
 415 {
 416   cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
 417   cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
 418   cpu_set_ccr_Z (cpu, r == 0);
 419   cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
 420 }
 421
 422 /* Push and pop instructions for 68HC11 (next-available stack mode).  */
 423 inline void
 424 cpu_m68hc11_push_uint8 (sim_cpu *cpu, uint8 val)
 425 {
 426   uint16 addr = cpu->cpu_regs.sp;
 427
 428   memory_write8 (cpu, addr, val);
 429   cpu->cpu_regs.sp = addr - 1;
 430 }
 431
 432 inline void
 433 cpu_m68hc11_push_uint16 (sim_cpu *cpu, uint16 val)
 434 {
 435   uint16 addr = cpu->cpu_regs.sp - 1;
 436
 437   memory_write16 (cpu, addr, val);
 438   cpu->cpu_regs.sp = addr - 1;
 439 }
 440
 441 inline uint8
 442 cpu_m68hc11_pop_uint8 (sim_cpu *cpu)
 443 {
 444   uint16 addr = cpu->cpu_regs.sp;
 445   uint8 val;
 446
 447   val = memory_read8 (cpu, addr + 1);
 448   cpu->cpu_regs.sp = addr + 1;
 449   return val;
 450 }
 451
 452 inline uint16
 453 cpu_m68hc11_pop_uint16 (sim_cpu *cpu)
 454 {
 455   uint16 addr = cpu->cpu_regs.sp;
 456   uint16 val;
 457
 458   val = memory_read16 (cpu, addr + 1);
 459   cpu->cpu_regs.sp = addr + 2;
 460   return val;
 461 }
 462
 463 /* Push and pop instructions for 68HC12 (last-used stack mode).  */
 464 inline void
 465 cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8 val)
 466 {
 467   uint16 addr = cpu->cpu_regs.sp;
 468
 469   addr --;
 470   memory_write8 (cpu, addr, val);
 471   cpu->cpu_regs.sp = addr;
 472 }
 473
 474 inline void
 475 cpu_m68hc12_push_uint16 (sim_cpu *cpu, uint16 val)
 476 {
 477   uint16 addr = cpu->cpu_regs.sp;
 478
 479   addr -= 2;
 480   memory_write16 (cpu, addr, val);
 481   cpu->cpu_regs.sp = addr;
 482 }
 483
 484 inline uint8
 485 cpu_m68hc12_pop_uint8 (sim_cpu *cpu)
 486 {
 487   uint16 addr = cpu->cpu_regs.sp;
 488   uint8 val;
 489
 490   val = memory_read8 (cpu, addr);
 491   cpu->cpu_regs.sp = addr + 1;
 492   return val;
 493 }
 494
 495 inline uint16
 496 cpu_m68hc12_pop_uint16 (sim_cpu *cpu)
 497 {
 498   uint16 addr = cpu->cpu_regs.sp;
 499   uint16 val;
 500
 501   val = memory_read16 (cpu, addr);
 502   cpu->cpu_regs.sp = addr + 2;
 503   return val;
 504 }
 505
 506 /* Fetch a 8/16 bit value and update the PC.  */
 507 inline uint8
 508 cpu_fetch8 (sim_cpu *cpu)
 509 {
 510   uint16 addr = cpu->cpu_regs.pc;
 511   uint8 val;
 512
 513   val = memory_read8 (cpu, addr);
 514   cpu->cpu_regs.pc = addr + 1;
 515   return val;
 516 }
 517
 518 inline uint16
 519 cpu_fetch16 (sim_cpu *cpu)
 520 {
 521   uint16 addr = cpu->cpu_regs.pc;
 522   uint16 val;
 523
 524   val = memory_read16 (cpu, addr);
 525   cpu->cpu_regs.pc = addr + 2;
 526   return val;
 527 }
 528
 529 extern void cpu_call (sim_cpu *cpu, uint16 addr);
 530 extern void cpu_exg (sim_cpu *cpu, uint8 code);
 531 extern void cpu_dbcc (sim_cpu *cpu);
 532 extern void cpu_special (sim_cpu *cpu, enum M6811_Special special);
 533 extern void cpu_move8 (sim_cpu *cpu, uint8 op);
 534 extern void cpu_move16 (sim_cpu *cpu, uint8 op);
 535
 536 extern uint16 cpu_fetch_relbranch (sim_cpu *cpu);
 537 extern uint16 cpu_fetch_relbranch16 (sim_cpu *cpu);
 538 extern void cpu_push_all (sim_cpu *cpu);
 539 extern void cpu_single_step (sim_cpu *cpu);
 540
 541 extern void cpu_info (SIM_DESC sd, sim_cpu *cpu);
 542
 543 extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
 544
 545 /* Returns the address of a 68HC12 indexed operand.
 546    Pre and post modifications are handled on the source register.  */
 547 extern uint16 cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
 548
 549 extern void cpu_return (sim_cpu *cpu);
 550 extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
 551 extern int cpu_reset (sim_cpu *cpu);
 552 extern int cpu_restart (sim_cpu *cpu);
 553 extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
 554                               uint16 addr, const char *message, ...);
 555 extern void emul_os (int op, sim_cpu *cpu);
 556 extern void cpu_interp_m6811 (sim_cpu *cpu);
 557 extern void cpu_interp_m6812 (sim_cpu *cpu);
 558
 559 extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
 560                                       double ton, double toff,
 561                                       signed64 repeat);
 562 extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
 563 extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
 564                                  unsigned addr, uint8 val);
 565
 566 /* The current state of the processor; registers, memory, etc.  */
 567
 568 struct sim_state {
 569   sim_cpu        *cpu[MAX_NR_PROCESSORS];
 570   sim_state_base base;
 571 };
 572
 573 extern void sim_board_reset (SIM_DESC sd);
 574
 575 #define PRINT_TIME  0x01
 576 #define PRINT_CYCLE 0x02
 577 extern const char *cycle_to_string (sim_cpu *cpu, signed64 t, int flags);
 578
 579 #endif
 580
 581