1 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
3 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
4 bit mips16 igen simulator.
5 * configure: Re-generate.
7 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
9 * vr.igen: Mark all instructions as 64 bit only.
11 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
13 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
17 Mon Nov 23 16:51:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
19 * configure.in (tx19): Reconize target mips-tx19-elf.
20 * configure: Re-generate.
23 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
25 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
26 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
27 * configure: Re-generate.
29 * m16.igen (BREAK): Define breakpoint instruction.
30 (JALX32): Mark instruction as mips16 and not r3900.
31 * mips.igen (C.cond.fmt): Fix typo in instruction format.
33 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
36 Mon Nov 16 11:44:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
38 * r5900.igen (CVT.W.S): Always round towards zero.
41 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
43 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
44 insn as a debug breakpoint.
46 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
48 (PENDING_SCHED): Clean up trace statement.
49 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
50 (PENDING_FILL): Delay write by only one cycle.
51 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
53 * sim-main.c (pending_tick): Clean up trace statements. Add trace
55 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
57 (pending_tick): Move incrementing of index to FOR statement.
58 (pending_tick): Only update PENDING_OUT after a write has occured.
60 * configure.in: Add explicit mips-lsi-* target. Use gencode to
62 * configure: Re-generate.
64 * interp.c (sim_engine_run OLD): Delete explicit call to
65 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
68 Wed Nov 11 16:53:57 1998 Andrew Cagney <cagney@b1.cygnus.com>
70 * r5900.igen (RSQRT): Set both I/SI and D/SD when div-0.
72 Thu Nov 5 10:29:42 EST 1998 Frank Ch. Eigler <fche@cygnus.com>
74 * r5900.igen (r59fp_opdiv): Correct erroneous FGR[FD] reference.
76 Thu Nov 5 19:40:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
78 * r5900.igen (DIV): Do not clear clear SO/SU when already set.
80 * r5900.igen (RSQRT.S): Do not compute 1/srqt(abs(T)) when T
81 negative, compute S/sqrt(abs(T)) instead. Correctly set FCSR
84 * r5900.igen (RSQRT.S): Handle overflow/underflow better. Check
86 (r59fp_store): Clarify "bad value" abort messages.
90 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
92 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
93 interrupt level number to match changed SignalExceptionInterrupt
98 Thu Oct 29 12:47:46 1998 Frank Ch. Eigler <fche@cygnus.com>
100 * sim-main.c (tlb_try_match): Include physical address in
101 scratchpad non-mapping warning.
105 Thu Oct 29 11:06:30 EST 1998 Frank Ch. Eigler <fche@cygnus.com>
107 * r5900.igen: Fix PSRLVW, MULTU1, PADSBH instructions,
108 as per customer patch.
111 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
113 * interp.c: #include "itable.h" if WITH_IGEN.
114 (get_insn_name): New function.
115 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
116 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
119 Tue Sep 22 10:35:37 1998 Frank Ch. Eigler <fche@cygnus.com>
121 * sim-main.c (tlb_try_match): Specially match virtual
122 pages mapped to scratchpad RAM, an unimplemented feature.
126 Fri Sep 18 11:31:16 1998 Frank Ch. Eigler <fche@cygnus.com>
128 * r5900.igen (prot3w): Correct rotation sequence; patch
132 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
134 * configure: Rebuilt to inhale new common/aclocal.m4.
137 Thu Sep 10 11:50:54 1998 Doug Evans <devans@canuck.cygnus.com>
139 * r5900.igen (plzcw): Make `i' signed.
141 Wed Sep 9 15:02:10 1998 Doug Evans <devans@canuck.cygnus.com>
143 * sim-main.h (COP0_COUNT,COP0_COMPARE,status_IM7): New macros.
144 * sky-engine.c (cpu_issue): Increment COP0_COUNT and signal an
145 interrupt if == COP0_COMPARE and interrupt masks/enables allow it.
146 * interp.c (signal_exception, sky version): Handle INT 2.
148 Wed Sep 9 11:28:20 1998 Ron Unrau <runrau@cygnus.com>
150 * sim-main.h: track COP0 registers
151 * interp.c (sim_{fetch,store}_register): read/write COP0 registers
153 Fri Sep 4 10:37:57 1998 Frank Ch. Eigler <fche@cygnus.com>
155 * r5900.igen (mtsab): Correct typo in input register.
157 * sim-main.h (TMP_*): New macros for accessing local 128-bit
158 temporary for multimedia instructions.
159 * r5900.igen (*): Convert most instructions to use new TMP
160 macros to store output result during computation.
163 start-sanitize-tx3904
164 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
166 * dv-tx3904sio.c: Include sim-assert.h.
168 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
170 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
171 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
172 Reorganize target-specific sim-hardware checks.
173 * configure: rebuilt.
174 * interp.c (sim_open): For tx39 target boards, set
175 OPERATING_ENVIRONMENT, add tx3904sio devices.
176 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
177 ROM executables. Install dv-sockser into sim-modules list.
179 * dv-tx3904irc.c: Compiler warning clean-up.
180 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
181 frequent hw-trace messages.
185 Tue Aug 11 13:52:16 1998 Frank Ch. Eigler <fche@cygnus.com>
187 * interp.c (signal_exception): Set IP3 bit in CAUSE on
191 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
193 * vr.igen (MulAcc): Identify as a vr4100 specific function.
195 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
197 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
200 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
201 * mips.igen: Define vr4100 model. Include vr.igen.
202 start-sanitize-cygnus
203 * vr5400.igen: Move instructions to vr.igen
204 * Makefile.in (IGEN_INCLUDE): Remove vr5400.igen.
206 start-sanitize-vr4320
207 * vr4320.igen: Move instructions to vr.igen.
208 * Makefile.in (IGEN_INCLUDE): Remove vr5320.igen.
212 Fri Jul 24 16:01:03 1998 Ian Carmichael <iancarm@cygnus.com>
214 * interp.c (MONITOR_SIZE): Make 1MB monitor for SKY.
215 * mips.igen (BREAK): Fix 0xffff2 monitor call. Slightly less
216 confusing message if not enough --load-next options appear.
218 * sky-pke.h (VUx_MEMx_SRCADDR_START): Move to 0x19800000 range.
219 * sim-main.c (GDB_COMM_AREA): Move to 0x19810000.
220 * sky-gdb.c (init_fifo_bp_cache): Use VIO_BASE when reading GDB area.
221 (resume_handler): Same.
222 (suspend_handler): Same.
224 Wed Jul 22 13:04:13 1998 Frank Ch. Eigler <fche@cygnus.com>
226 * mips.igen (break): Implement LOAD_INSTRUCTION ("break 0xffff1")
227 to trigger multi-phase load.
229 * sim-main.c: Include sim-assert.h for ASSERT macro.
230 * sim-main.h (PRINTF_INSTRUCTION): Correct bit pattern for
233 Tue Jul 21 18:37:36 1998 Ian Carmichael <iancarm@cygnus.com>
236 * interp.c (sim_open): Initialize TLB.
237 * interp.c (signal_exceptions): New 5900 handling.
238 * r5900.igen (TLBWR, TLBWI, TLBR, TLBP): Make these work.
239 * sim-main.c (tlb_try_match, tlb_lookup): New functions.
240 (address_translation): Use the TLB.
241 * sim-main.h (r4000_tlb_entry_t): New type.
242 (TLB_*): New constants.
243 (COP0_*): New register names.
245 Sky character I/O device.
246 * sky-psio.c: New file.
247 * sky-psio.h: New file.
248 * Makefile.in: Add sky-psio.o.
252 Tue Jul 14 16:10:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
254 * r5900.igen (r59fp_overflow): Replace argument ANS with argument
257 (r59fp_store): Update calls.
258 (DIV.S): Compute 0/0 sign from inputs. Ditto for X/0.
261 start-sanitize-branchbug4011
262 Mon Jun 29 09:31:27 1998 Gavin Koch <gavin@cygnus.com>
264 * interp.c (OPTION_BRANCH_BUG_4011): Add.
265 (mips_option_handler): Handle OPTION_BRANCH_BUG_4011.
266 (mips_options): Define the option.
267 * mips.igen (check_4011_branch_bug): New.
268 (mark_4011_branch_bug): New.
269 (all branch insn): Call mark_branch_bug, and check_branch_bug.
270 * sim-main.h (branchbug4011_option, branchbug4011_last_target,
271 branchbug4011_last_cia, BRANCHBUG4011_OPTION,
272 BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA,
273 check_branch_bug, mark_branch_bug): Define.
275 end-sanitize-branchbug4011
276 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
278 * mips.igen (check_mf_hilo): Correct check.
281 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
283 * sim-main.h (NR_COP0_GPR, COP0_GPR, cop0_gpr, NR_COP0_BP,
284 COP0_BP, cop0_bp, NR_COP0_P, COP0_P, cop0_p): Add 32 COP0 general
285 purpose registers, add 8 COP0 break-point registers, add 64 COP0
286 performance registers.
288 * interp.c (decode_coproc): Accept any MTC0/MFC0, MTBP/MFBP, MTP*
289 MFP* instructions. Just transfer value to/from corresponding
292 * r5900.igen (BC0F, BC0FL, BC0T, BC0TL): Implement, assume COP0
293 status is always true.
294 (CACHE, TLBP, TPGWI, TLBWR): Treat as NOP.
295 (EI, DI): Set/clear Status-EIE bit.
299 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
301 * mips.igen (BC0F, BC0FL, BC0T, BC0TL): Move to sky code to
305 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
308 * sky-vu.c (vu0_read_cop2_register, vu0_write_cop2_register): Call
310 * sky-gdb.c: Include "sim-assert.h".
313 * sim-main.h (interrupt_event): Add prototype.
315 start-sanitize-tx3904
316 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
317 register_ptr, register_value.
318 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
321 * sim-main.h (tracefh): Make extern.
323 start-sanitize-tx3904
324 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
326 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
327 Reduce unnecessarily high timer event frequency.
328 * dv-tx3904cpu.c: Ditto for interrupt event.
332 Tue Jun 16 14:12:09 1998 Frank Ch. Eigler <fche@cygnus.com>
334 * interp.c (decode_coproc): Removed COP2 branches.
335 * r5900.igen: Moved COP2 branch instructions here.
336 * mips.igen: Restricted COPz == COP2 bit pattern to
337 exclude COP2 branches.
340 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
342 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
344 (interrupt_event): Made non-static.
345 start-sanitize-tx3904
347 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
348 interchange of configuration values for external vs. internal
352 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
354 * mips.igen (BREAK): Moved code to here for
355 simulator-reserved break instructions.
356 * gencode.c (build_instruction): Ditto.
357 * interp.c (signal_exception): Code moved from here. Non-
358 reserved instructions now use exception vector, rather
360 * sim-main.h: Moved magic constants to here.
362 start-sanitize-tx3904
363 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
365 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
366 register upon non-zero interrupt event level, clear upon zero
368 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
369 by passing zero event value.
370 (*_io_{read,write}_buffer): Endianness fixes.
371 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
372 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
374 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
375 serial I/O and timer module at base address 0xFFFF0000.
378 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
380 * mips.igen (SWC1) : Correct the handling of ReverseEndian
383 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
385 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
389 start-sanitize-tx3904
390 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
392 * dv-tx3904tmr.c: New file - implements tx3904 timer.
393 * dv-tx3904{irc,cpu}.c: Mild reformatting.
394 * configure.in: Include tx3904tmr in hw_device list.
395 * configure: Rebuilt.
396 * interp.c (sim_open): Instantiate three timer instances.
397 Fix address typo of tx3904irc instance.
401 Thu Jun 4 16:47:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
403 * mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO.
404 Select corresponding check_mt_hilo function.
405 (check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo):
408 * r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark
412 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
414 * interp.c (signal_exception): SystemCall exception now uses
415 the exception vector.
417 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
419 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
423 Mon Jun 1 10:28:25 1998 Jeffrey A Law (law@cygnus.com)
425 * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1.
429 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
431 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
433 start-sanitize-tx3904
434 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
436 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
438 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
439 sim-main.h. Declare a struct hw_descriptor instead of struct
440 hw_device_descriptor.
443 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
445 * mips.igen (do_store_left, do_load_left): Compute nr of left and
446 right bits and then re-align left hand bytes to correct byte
447 lanes. Fix incorrect computation in do_store_left when loading
448 bytes from second word.
450 start-sanitize-tx3904
451 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
453 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
454 * interp.c (sim_open): Only create a device tree when HW is
457 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
458 * interp.c (signal_exception): Ditto.
461 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
463 * gencode.c: Mark BEGEZALL as LIKELY.
465 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
467 * sim-main.h (ALU32_END): Sign extend 32 bit results.
468 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
471 Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
473 * interp.c (sim_fetch_register): Convert internal r5900 regs to
477 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
479 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
480 modules. Recognize TX39 target with "mips*tx39" pattern.
481 * configure: Rebuilt.
482 * sim-main.h (*): Added many macros defining bits in
483 TX39 control registers.
484 (SignalInterrupt): Send actual PC instead of NULL.
485 (SignalNMIReset): New exception type.
486 * interp.c (board): New variable for future use to identify
487 a particular board being simulated.
488 (mips_option_handler,mips_options): Added "--board" option.
489 (interrupt_event): Send actual PC.
490 (sim_open): Make memory layout conditional on board setting.
491 (signal_exception): Initial implementation of hardware interrupt
492 handling. Accept another break instruction variant for simulator
494 (decode_coproc): Implement RFE instruction for TX39.
495 (mips.igen): Decode RFE instruction as such.
496 start-sanitize-tx3904
497 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
498 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
499 bbegin to implement memory map.
500 * dv-tx3904cpu.c: New file.
501 * dv-tx3904irc.c: New file.
504 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
506 * mips.igen (check_mt_hilo): Create a separate r3900 version.
509 Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
511 * r5900.igen: Replace the calls and the definition of the
512 function check_op_hilo_hi1lo1 with the pair
513 check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
516 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
518 * tx.igen (madd,maddu): Replace calls to check_op_hilo
519 with calls to check_div_hilo.
521 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
523 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
524 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
525 Add special r3900 version of do_mult_hilo.
526 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
527 with calls to check_mult_hilo.
528 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
529 with calls to check_div_hilo.
531 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
533 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
534 Document a replacement.
536 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
538 * interp.c (sim_monitor): Make mon_printf work.
540 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
542 * sim-main.h (INSN_NAME): New arg `cpu'.
545 Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com>
547 * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
552 Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
554 * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
555 * r5900.igen (r59fp_overflow): Use.
557 * r5900.igen (r59fp_op3): Rename to
558 (r59fp_mula): This, delete opm argument.
559 (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
560 (r59fp_mula): Overflowing product propogates through to result.
561 (r59fp_mula): ACC to the MAX propogates to result.
562 (r59fp_mula): Underflow during multiply only sets SU.
565 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
567 * configure: Regenerated to track ../common/aclocal.m4 changes.
569 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
571 * configure: Regenerated to track ../common/aclocal.m4 changes.
574 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
576 * acconfig.h: New file.
577 * configure.in: Reverted change of Apr 24; use sinclude again.
579 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
581 * configure: Regenerated to track ../common/aclocal.m4 changes.
584 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
586 * configure.in: Don't call sinclude.
588 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
590 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
592 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
594 * mips.igen (ERET): Implement.
596 * interp.c (decode_coproc): Return sign-extended EPC.
598 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
600 * interp.c (signal_exception): Do not ignore Trap.
601 (signal_exception): On TRAP, restart at exception address.
602 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
603 (signal_exception): Update.
604 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
605 so that TRAP instructions are caught.
607 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
609 * sim-main.h (struct hilo_access, struct hilo_history): Define,
610 contains HI/LO access history.
611 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
612 (HIACCESS, LOACCESS): Delete, replace with
613 (HIHISTORY, LOHISTORY): New macros.
614 (start-sanitize-r5900):
615 (struct sim_5900_cpu): Make hi1access, lo1access of type
617 (HI1ACCESS, LO1ACCESS): Delete, replace with
618 (HI1HISTORY, LO1HISTORY): New macros.
619 (end-sanitize-r5900):
620 (CHECKHILO): Delete all, moved to mips.igen
622 * gencode.c (build_instruction): Do not generate checks for
623 correct HI/LO register usage.
625 * interp.c (old_engine_run): Delete checks for correct HI/LO
628 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
629 check_mf_cycles): New functions.
630 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
631 do_divu, domultx, do_mult, do_multu): Use.
633 * tx.igen ("madd", "maddu"): Use.
634 (start-sanitize-r5900):
636 r5900.igen: Update all HI/LO checks.
637 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
638 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
639 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
640 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
641 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
643 (end-sanitize-r5900):
646 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
648 * interp.c (decode_coproc): Correct CMFC2/QMTC2
651 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
652 instead of a single 128-bit access.
656 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
658 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
659 * interp.c (cop_[ls]q): Fixes corresponding to above.
663 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
665 * interp.c (decode_coproc): Adapt COP2 micro interlock to
666 clarified specs. Reset "M" bit; exit also on "E" bit.
670 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
672 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
673 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
675 * r5900.igen (r59fp_unpack): New function.
676 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
677 RSQRT.S, SQRT.S): Use.
678 (r59fp_zero): New function.
679 (r59fp_overflow): Generate r5900 specific overflow value.
680 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
682 (CVT.S.W, CVT.W.S): Exchange implementations.
684 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
688 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
690 * configure.in (tx19, sim_use_gen): Switch to igen.
691 * configure: Re-build.
695 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
697 * interp.c (decode_coproc): Make COP2 branch code compile after
698 igen signature changes.
701 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
703 * mips.igen (DSRAV): Use function do_dsrav.
704 (SRAV): Use new function do_srav.
706 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
707 (B): Sign extend 11 bit immediate.
708 (EXT-B*): Shift 16 bit immediate left by 1.
709 (ADDIU*): Don't sign extend immediate value.
711 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
713 * m16run.c (sim_engine_run): Restore CIA after handling an event.
716 * mips.igen (mtc0): Valid tx19 instruction.
719 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
722 * mips.igen (delayslot32, nullify_next_insn): New functions.
723 (m16.igen): Always include.
724 (do_*): Add more tracing.
726 * m16.igen (delayslot16): Add NIA argument, could be called by a
727 32 bit MIPS16 instruction.
729 * interp.c (ifetch16): Move function from here.
730 * sim-main.c (ifetch16): To here.
732 * sim-main.c (ifetch16, ifetch32): Update to match current
733 implementations of LH, LW.
734 (signal_exception): Don't print out incorrect hex value of illegal
737 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
739 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
742 * m16.igen: Implement MIPS16 instructions.
744 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
745 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
746 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
747 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
748 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
749 bodies of corresponding code from 32 bit insn to these. Also used
750 by MIPS16 versions of functions.
752 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
753 (IMEM16): Drop NR argument from macro.
756 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
758 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
759 of VU lower instruction.
763 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
765 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
768 * sim-main.h: Removed attempt at allowing 128-bit access.
772 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
774 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
776 * interp.c (decode_coproc): Refer to VU CIA as a "special"
777 register, not as a "misc" register. Aha. Add activity
778 assertions after VCALLMS* instructions.
782 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
784 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
785 to upper code of generated VU instruction.
789 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
791 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
793 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
796 * r5900.igen (SQC2): Thinko.
800 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
802 * interp.c (*): Adapt code to merged VU device & state structs.
803 (decode_coproc): Execute COP2 each macroinstruction without
804 pipelining, by stepping VU to completion state. Adapted to
805 read_vu_*_reg style of register access.
807 * mips.igen ([SL]QC2): Removed these COP2 instructions.
809 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
811 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
814 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
816 * Makefile.in (SIM_OBJS): Add sim-main.o.
818 * sim-main.h (address_translation, load_memory, store_memory,
819 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
821 (pr_addr, pr_uword64): Declare.
822 (sim-main.c): Include when H_REVEALS_MODULE_P.
824 * interp.c (address_translation, load_memory, store_memory,
825 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
827 * sim-main.c: To here. Fix compilation problems.
829 * configure.in: Enable inlining.
830 * configure: Re-config.
832 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
834 * configure: Regenerated to track ../common/aclocal.m4 changes.
836 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
838 * mips.igen: Include tx.igen.
839 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
840 * tx.igen: New file, contains MADD and MADDU.
842 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
843 the hardwired constant `7'.
844 (store_memory): Ditto.
845 (LOADDRMASK): Move definition to sim-main.h.
847 mips.igen (MTC0): Enable for r3900.
850 mips.igen (do_load_byte): Delete.
851 (do_load, do_store, do_load_left, do_load_write, do_store_left,
852 do_store_right): New functions.
853 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
855 configure.in: Let the tx39 use igen again.
858 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
860 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
861 not an address sized quantity. Return zero for cache sizes.
863 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
865 * mips.igen (r3900): r3900 does not support 64 bit integer
869 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
871 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
875 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
877 * interp.c (decode_coproc): Continuing COP2 work.
878 (cop_[ls]q): Make sky-target-only.
880 * sim-main.h (COP_[LS]Q): Make sky-target-only.
882 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
884 * configure.in (mipstx39*-*-*): Use gencode simulator rather
886 * configure : Rebuild.
889 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
891 * interp.c (decode_coproc): Added a missing TARGET_SKY check
892 around COP2 implementation skeleton.
896 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
898 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
900 * interp.c (sim_{load,store}_register): Use new vu[01]_device
901 static to access VU registers.
902 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
903 decoding. Work in progress.
905 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
906 overlapping/redundant bit pattern.
907 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
910 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
913 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
914 access to coprocessor registers.
916 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
918 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
920 * configure: Regenerated to track ../common/aclocal.m4 changes.
922 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
924 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
926 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
928 * configure: Regenerated to track ../common/aclocal.m4 changes.
929 * config.in: Regenerated to track ../common/aclocal.m4 changes.
931 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
933 * configure: Regenerated to track ../common/aclocal.m4 changes.
935 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
937 * interp.c (Max, Min): Comment out functions. Not yet used.
939 start-sanitize-vr4320
940 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
942 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
945 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
947 * configure: Regenerated to track ../common/aclocal.m4 changes.
949 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
951 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
952 configurable settings for stand-alone simulator.
955 * configure.in: Added --with-sim-gpu2 option to specify path of
956 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
957 links/compiles stand-alone simulator with this library.
959 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
961 * configure.in: Added X11 search, just in case.
963 * configure: Regenerated.
965 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
967 * interp.c (sim_write, sim_read, load_memory, store_memory):
968 Replace sim_core_*_map with read_map, write_map, exec_map resp.
970 start-sanitize-vr4320
971 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
973 * vr4320.igen (clz,dclz) : Added.
974 (dmac): Replaced 99, with LO.
977 start-sanitize-cygnus
978 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
980 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
983 start-sanitize-vr4320
984 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
986 * vr4320.igen: New file.
987 * Makefile.in (vr4320.igen) : Added.
988 * configure.in (mips64vr4320-*-*): Added.
989 * configure : Rebuilt.
990 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
991 Add the vr4320 model entry and mark the vr4320 insn as necessary.
994 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
996 * sim-main.h (GETFCC): Return an unsigned value.
999 * r5900.igen: Use an unsigned array index variable `i'.
1000 (QFSRV): Ditto for variable bytes.
1003 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1005 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1006 (DADD): Result destination is RD not RT.
1008 start-sanitize-r5900
1009 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
1010 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
1014 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1016 * sim-main.h (HIACCESS, LOACCESS): Always define.
1018 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1020 * interp.c (sim_info): Delete.
1022 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1024 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1025 (mips_option_handler): New argument `cpu'.
1026 (sim_open): Update call to sim_add_option_table.
1028 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1030 * mips.igen (CxC1): Add tracing.
1032 start-sanitize-r5900
1033 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1035 * r5900.igen (StoreFP): Delete.
1036 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
1038 (rsqrt.s, sqrt.s): Implement.
1039 (r59cond): New function.
1040 (C.COND.S): Call r59cond in assembler line.
1041 (cvt.w.s, cvt.s.w): Implement.
1043 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
1046 * sim-main.h: Define an enum of r5900 FCSR bit fields.
1049 start-sanitize-r5900
1050 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
1052 * r5900.igen: Add tracing to all p* instructions.
1054 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
1056 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
1057 to get gdb talking to re-aranged sim_cpu register structure.
1060 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1062 * sim-main.h (Max, Min): Declare.
1064 * interp.c (Max, Min): New functions.
1066 * mips.igen (BC1): Add tracing.
1068 start-sanitize-cygnus
1069 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
1071 * mdmx.igen: Tag all functions as requiring either with mdmx or
1075 start-sanitize-r5900
1076 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1078 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
1080 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
1082 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
1084 * r5900.igen: Rewrite.
1086 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
1088 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
1089 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
1092 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1094 * interp.c Added memory map for stack in vr4100
1096 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1098 * interp.c (load_memory): Add missing "break"'s.
1100 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1102 * interp.c (sim_store_register, sim_fetch_register): Pass in
1103 length parameter. Return -1.
1105 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1107 * interp.c: Added hardware init hook, fixed warnings.
1109 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1111 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1113 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1115 * interp.c (ifetch16): New function.
1117 * sim-main.h (IMEM32): Rename IMEM.
1118 (IMEM16_IMMED): Define.
1120 (DELAY_SLOT): Update.
1122 * m16run.c (sim_engine_run): New file.
1124 * m16.igen: All instructions except LB.
1125 (LB): Call do_load_byte.
1126 * mips.igen (do_load_byte): New function.
1127 (LB): Call do_load_byte.
1129 * mips.igen: Move spec for insn bit size and high bit from here.
1130 * Makefile.in (tmp-igen, tmp-m16): To here.
1132 * m16.dc: New file, decode mips16 instructions.
1134 * Makefile.in (SIM_NO_ALL): Define.
1135 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1138 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
1142 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1144 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1145 point unit to 32 bit registers.
1146 * configure: Re-generate.
1148 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1150 * configure.in (sim_use_gen): Make IGEN the default simulator
1151 generator for generic 32 and 64 bit mips targets.
1152 * configure: Re-generate.
1154 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1156 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1159 * interp.c (sim_fetch_register, sim_store_register): Read/write
1160 FGR from correct location.
1161 (sim_open): Set size of FGR's according to
1162 WITH_TARGET_FLOATING_POINT_BITSIZE.
1164 * sim-main.h (FGR): Store floating point registers in a separate
1167 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1169 * configure: Regenerated to track ../common/aclocal.m4 changes.
1171 start-sanitize-cygnus
1172 * mdmx.igen: Mark all instructions as 64bit/fp specific.
1175 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1177 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1179 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1181 * interp.c (pending_tick): New function. Deliver pending writes.
1183 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1184 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1185 it can handle mixed sized quantites and single bits.
1187 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1189 * interp.c (oengine.h): Do not include when building with IGEN.
1190 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1191 (sim_info): Ditto for PROCESSOR_64BIT.
1192 (sim_monitor): Replace ut_reg with unsigned_word.
1193 (*): Ditto for t_reg.
1194 (LOADDRMASK): Define.
1195 (sim_open): Remove defunct check that host FP is IEEE compliant,
1196 using software to emulate floating point.
1197 (value_fpr, ...): Always compile, was conditional on HASFPU.
1199 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1201 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1204 * interp.c (SD, CPU): Define.
1205 (mips_option_handler): Set flags in each CPU.
1206 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1207 (sim_close): Do not clear STATE, deleted anyway.
1208 (sim_write, sim_read): Assume CPU zero's vm should be used for
1210 (sim_create_inferior): Set the PC for all processors.
1211 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1213 (mips16_entry): Pass correct nr of args to store_word, load_word.
1214 (ColdReset): Cold reset all cpu's.
1215 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1216 (sim_monitor, load_memory, store_memory, signal_exception): Use
1217 `CPU' instead of STATE_CPU.
1220 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1223 * sim-main.h (signal_exception): Add sim_cpu arg.
1224 (SignalException*): Pass both SD and CPU to signal_exception.
1225 * interp.c (signal_exception): Update.
1227 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1229 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1230 address_translation): Ditto
1231 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1233 start-sanitize-cygnus
1234 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
1236 (ByteAlign): Use StoreFPR, pass args in correct order.
1239 start-sanitize-r5900
1240 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1242 * configure.in (sim_igen_filter): For r5900, configure as SMP.
1245 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1247 * configure: Regenerated to track ../common/aclocal.m4 changes.
1249 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1251 start-sanitize-r5900
1252 * configure.in (sim_igen_filter): For r5900, use igen.
1253 * configure: Re-generate.
1256 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1258 * mips.igen (model): Map processor names onto BFD name.
1260 * sim-main.h (CPU_CIA): Delete.
1261 (SET_CIA, GET_CIA): Define
1263 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1265 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1268 * configure.in (default_endian): Configure a big-endian simulator
1270 * configure: Re-generate.
1272 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1274 * configure: Regenerated to track ../common/aclocal.m4 changes.
1276 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1278 * interp.c (sim_monitor): Handle Densan monitor outbyte
1279 and inbyte functions.
1281 1997-12-29 Felix Lee <flee@cygnus.com>
1283 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1285 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1287 * Makefile.in (tmp-igen): Arrange for $zero to always be
1288 reset to zero after every instruction.
1290 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1292 * configure: Regenerated to track ../common/aclocal.m4 changes.
1295 start-sanitize-cygnus
1296 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1298 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
1301 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
1303 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
1304 vr5400 with the vr5000 as the default.
1307 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1309 * mips.igen (MSUB): Fix to work like MADD.
1310 * gencode.c (MSUB): Similarly.
1312 start-sanitize-cygnus
1313 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
1315 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
1319 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1321 * configure: Regenerated to track ../common/aclocal.m4 changes.
1323 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1325 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1327 start-sanitize-cygnus
1328 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
1329 (value_cc, store_cc): Implement.
1331 * sim-main.h: Add 8*3*8 bit accumulator.
1333 * vr5400.igen: Move mdmx instructins from here
1334 * mdmx.igen: To here - new file. Add/fix missing instructions.
1335 * mips.igen: Include mdmx.igen.
1336 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1339 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1341 * sim-main.h (sim-fpu.h): Include.
1343 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1344 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1345 using host independant sim_fpu module.
1347 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1349 * interp.c (signal_exception): Report internal errors with SIGABRT
1352 * sim-main.h (C0_CONFIG): New register.
1353 (signal.h): No longer include.
1355 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1357 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1359 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1361 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1363 * mips.igen: Tag vr5000 instructions.
1364 (ANDI): Was missing mipsIV model, fix assembler syntax.
1365 (do_c_cond_fmt): New function.
1366 (C.cond.fmt): Handle mips I-III which do not support CC field
1368 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1369 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1371 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1372 vr5000 which saves LO in a GPR separatly.
1374 * configure.in (enable-sim-igen): For vr5000, select vr5000
1375 specific instructions.
1376 * configure: Re-generate.
1378 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1380 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1382 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1383 fmt_uninterpreted_64 bit cases to switch. Convert to
1386 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1388 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1389 as specified in IV3.2 spec.
1390 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1392 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1394 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1395 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1396 (start-sanitize-r5900):
1397 (LWXC1, SWXC1): Delete from r5900 instruction set.
1398 (end-sanitize-r5900):
1399 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1400 PENDING_FILL versions of instructions. Simplify.
1402 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1404 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1406 (MTHI, MFHI): Disable code checking HI-LO.
1408 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1410 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1412 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1414 * gencode.c (build_mips16_operands): Replace IPC with cia.
1416 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1417 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1419 (UndefinedResult): Replace function with macro/function
1421 (sim_engine_run): Don't save PC in IPC.
1423 * sim-main.h (IPC): Delete.
1425 start-sanitize-cygnus
1426 * vr5400.igen (vr): Add missing cia argument to value_fpr.
1427 (do_select): Rename function select.
1430 * interp.c (signal_exception, store_word, load_word,
1431 address_translation, load_memory, store_memory, cache_op,
1432 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1433 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1434 current instruction address - cia - argument.
1435 (sim_read, sim_write): Call address_translation directly.
1436 (sim_engine_run): Rename variable vaddr to cia.
1437 (signal_exception): Pass cia to sim_monitor
1439 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1440 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1441 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1443 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1444 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1447 * interp.c (signal_exception): Pass restart address to
1450 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1451 idecode.o): Add dependency.
1453 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1455 (DELAY_SLOT): Update NIA not PC with branch address.
1456 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1458 * mips.igen: Use CIA not PC in branch calculations.
1459 (illegal): Call SignalException.
1460 (BEQ, ADDIU): Fix assembler.
1462 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1464 * m16.igen (JALX): Was missing.
1466 * configure.in (enable-sim-igen): New configuration option.
1467 * configure: Re-generate.
1469 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1471 * interp.c (load_memory, store_memory): Delete parameter RAW.
1472 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1473 bypassing {load,store}_memory.
1475 * sim-main.h (ByteSwapMem): Delete definition.
1477 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1479 * interp.c (sim_do_command, sim_commands): Delete mips specific
1480 commands. Handled by module sim-options.
1482 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1483 (WITH_MODULO_MEMORY): Define.
1485 * interp.c (sim_info): Delete code printing memory size.
1487 * interp.c (mips_size): Nee sim_size, delete function.
1489 (monitor, monitor_base, monitor_size): Delete global variables.
1490 (sim_open, sim_close): Delete code creating monitor and other
1491 memory regions. Use sim-memopts module, via sim_do_commandf, to
1492 manage memory regions.
1493 (load_memory, store_memory): Use sim-core for memory model.
1495 * interp.c (address_translation): Delete all memory map code
1496 except line forcing 32 bit addresses.
1498 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1500 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1503 * interp.c (logfh, logfile): Delete globals.
1504 (sim_open, sim_close): Delete code opening & closing log file.
1505 (mips_option_handler): Delete -l and -n options.
1506 (OPTION mips_options): Ditto.
1508 * interp.c (OPTION mips_options): Rename option trace to dinero.
1509 (mips_option_handler): Update.
1511 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1513 * interp.c (fetch_str): New function.
1514 (sim_monitor): Rewrite using sim_read & sim_write.
1515 (sim_open): Check magic number.
1516 (sim_open): Write monitor vectors into memory using sim_write.
1517 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1518 (sim_read, sim_write): Simplify - transfer data one byte at a
1520 (load_memory, store_memory): Clarify meaning of parameter RAW.
1522 * sim-main.h (isHOST): Defete definition.
1523 (isTARGET): Mark as depreciated.
1524 (address_translation): Delete parameter HOST.
1526 * interp.c (address_translation): Delete parameter HOST.
1529 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
1531 * gencode.c: Add tx49 configury and insns.
1532 * configure.in: Add tx49 configury.
1533 * configure: Update.
1536 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1540 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1541 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1543 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1545 * mips.igen: Add model filter field to records.
1547 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1549 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1551 interp.c (sim_engine_run): Do not compile function sim_engine_run
1552 when WITH_IGEN == 1.
1554 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1555 target architecture.
1557 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1558 igen. Replace with configuration variables sim_igen_flags /
1561 start-sanitize-r5900
1562 * r5900.igen: New file. Copy r5900 insns here.
1564 start-sanitize-cygnus
1565 * vr5400.igen: New file.
1567 * m16.igen: New file. Copy mips16 insns here.
1568 * mips.igen: From here.
1570 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1572 start-sanitize-cygnus
1573 * mips.igen: Tag all mipsIV instructions with vr5400 model.
1575 * configure.in: Add mips64vr5400 target.
1576 * configure: Re-generate.
1579 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1581 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1583 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1585 * gencode.c (build_instruction): Follow sim_write's lead in using
1586 BigEndianMem instead of !ByteSwapMem.
1588 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1590 * configure.in (sim_gen): Dependent on target, select type of
1591 generator. Always select old style generator.
1593 configure: Re-generate.
1595 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1597 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1598 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1599 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1600 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1601 SIM_@sim_gen@_*, set by autoconf.
1603 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1605 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1607 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1608 CURRENT_FLOATING_POINT instead.
1610 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1611 (address_translation): Raise exception InstructionFetch when
1612 translation fails and isINSTRUCTION.
1614 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1615 sim_engine_run): Change type of of vaddr and paddr to
1617 (address_translation, prefetch, load_memory, store_memory,
1618 cache_op): Change type of vAddr and pAddr to address_word.
1620 * gencode.c (build_instruction): Change type of vaddr and paddr to
1623 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1625 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1626 macro to obtain result of ALU op.
1628 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1630 * interp.c (sim_info): Call profile_print.
1632 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1634 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1636 * sim-main.h (WITH_PROFILE): Do not define, defined in
1637 common/sim-config.h. Use sim-profile module.
1638 (simPROFILE): Delete defintion.
1640 * interp.c (PROFILE): Delete definition.
1641 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1642 (sim_close): Delete code writing profile histogram.
1643 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1645 (sim_engine_run): Delete code profiling the PC.
1647 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1649 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1651 * interp.c (sim_monitor): Make register pointers of type
1654 * sim-main.h: Make registers of type unsigned_word not
1657 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1659 start-sanitize-r5900
1660 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1661 ...): Move to sim-main.h
1664 * interp.c (sync_operation): Rename from SyncOperation, make
1665 global, add SD argument.
1666 (prefetch): Rename from Prefetch, make global, add SD argument.
1667 (decode_coproc): Make global.
1669 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1671 * gencode.c (build_instruction): Generate DecodeCoproc not
1672 decode_coproc calls.
1674 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1675 (SizeFGR): Move to sim-main.h
1676 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1677 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1678 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1680 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1681 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1682 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1683 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1684 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1685 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1687 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1689 (sim-alu.h): Include.
1690 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1691 (sim_cia): Typedef to instruction_address.
1693 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1695 * Makefile.in (interp.o): Rename generated file engine.c to
1700 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1702 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1704 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1706 * gencode.c (build_instruction): For "FPSQRT", output correct
1707 number of arguments to Recip.
1709 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1711 * Makefile.in (interp.o): Depends on sim-main.h
1713 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1715 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1716 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1717 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1718 STATE, DSSTATE): Define
1719 (GPR, FGRIDX, ..): Define.
1721 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1722 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1723 (GPR, FGRIDX, ...): Delete macros.
1725 * interp.c: Update names to match defines from sim-main.h
1727 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1729 * interp.c (sim_monitor): Add SD argument.
1730 (sim_warning): Delete. Replace calls with calls to
1732 (sim_error): Delete. Replace calls with sim_io_error.
1733 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1734 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1735 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1737 (mips_size): Rename from sim_size. Add SD argument.
1739 * interp.c (simulator): Delete global variable.
1740 (callback): Delete global variable.
1741 (mips_option_handler, sim_open, sim_write, sim_read,
1742 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1743 sim_size,sim_monitor): Use sim_io_* not callback->*.
1744 (sim_open): ZALLOC simulator struct.
1745 (PROFILE): Do not define.
1747 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1749 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1750 support.h with corresponding code.
1752 * sim-main.h (word64, uword64), support.h: Move definition to
1754 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1757 * Makefile.in: Update dependencies
1758 * interp.c: Do not include.
1760 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1762 * interp.c (address_translation, load_memory, store_memory,
1763 cache_op): Rename to from AddressTranslation et.al., make global,
1766 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1769 * interp.c (SignalException): Rename to signal_exception, make
1772 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1774 * sim-main.h (SignalException, SignalExceptionInterrupt,
1775 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1776 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1777 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1780 * interp.c, support.h: Use.
1782 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1784 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1785 to value_fpr / store_fpr. Add SD argument.
1786 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1787 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1789 * sim-main.h (ValueFPR, StoreFPR): Define.
1791 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1793 * interp.c (sim_engine_run): Check consistency between configure
1794 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1797 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1798 (mips_fpu): Configure WITH_FLOATING_POINT.
1799 (mips_endian): Configure WITH_TARGET_ENDIAN.
1800 * configure: Update.
1802 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1804 * configure: Regenerated to track ../common/aclocal.m4 changes.
1806 start-sanitize-r5900
1807 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1809 * interp.c (MAX_REG): Allow up-to 128 registers.
1810 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1811 (REGISTER_SA): Ditto.
1812 (sim_open): Initialize register_widths for r5900 specific
1814 (sim_fetch_register, sim_store_register): Check for request of
1815 r5900 specific SA register. Check for request for hi 64 bits of
1816 r5900 specific registers.
1819 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1821 * configure: Regenerated.
1823 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1825 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1827 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1829 * gencode.c (print_igen_insn_models): Assume certain architectures
1830 include all mips* instructions.
1831 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1834 * Makefile.in (tmp.igen): Add target. Generate igen input from
1837 * gencode.c (FEATURE_IGEN): Define.
1838 (main): Add --igen option. Generate output in igen format.
1839 (process_instructions): Format output according to igen option.
1840 (print_igen_insn_format): New function.
1841 (print_igen_insn_models): New function.
1842 (process_instructions): Only issue warnings and ignore
1843 instructions when no FEATURE_IGEN.
1845 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1847 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1850 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1852 * configure: Regenerated to track ../common/aclocal.m4 changes.
1854 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1856 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1857 SIM_RESERVED_BITS): Delete, moved to common.
1858 (SIM_EXTRA_CFLAGS): Update.
1860 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1862 * configure.in: Configure non-strict memory alignment.
1863 * configure: Regenerated to track ../common/aclocal.m4 changes.
1865 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1867 * configure: Regenerated to track ../common/aclocal.m4 changes.
1869 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1871 * gencode.c (SDBBP,DERET): Added (3900) insns.
1872 (RFE): Turn on for 3900.
1873 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1874 (dsstate): Made global.
1875 (SUBTARGET_R3900): Added.
1876 (CANCELDELAYSLOT): New.
1877 (SignalException): Ignore SystemCall rather than ignore and
1878 terminate. Add DebugBreakPoint handling.
1879 (decode_coproc): New insns RFE, DERET; and new registers Debug
1880 and DEPC protected by SUBTARGET_R3900.
1881 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1883 * Makefile.in,configure.in: Add mips subtarget option.
1884 * configure: Update.
1886 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1888 * gencode.c: Add r3900 (tx39).
1891 * gencode.c: Fix some configuration problems by improving
1892 the relationship between tx19 and tx39.
1895 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1897 * gencode.c (build_instruction): Don't need to subtract 4 for
1900 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1902 * interp.c: Correct some HASFPU problems.
1904 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1906 * configure: Regenerated to track ../common/aclocal.m4 changes.
1908 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1910 * interp.c (mips_options): Fix samples option short form, should
1913 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1915 * interp.c (sim_info): Enable info code. Was just returning.
1917 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1919 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1922 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1924 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1926 (build_instruction): Ditto for LL.
1929 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1931 * mips/configure.in, mips/gencode: Add tx19/r1900.
1934 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1936 * configure: Regenerated to track ../common/aclocal.m4 changes.
1938 start-sanitize-r5900
1939 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1941 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1942 for overflow due to ABS of MININT, set result to MAXINT.
1943 (build_instruction): For "psrlvw", signextend bit 31.
1946 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1948 * configure: Regenerated to track ../common/aclocal.m4 changes.
1951 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1953 * interp.c (sim_open): Add call to sim_analyze_program, update
1956 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1958 * interp.c (sim_kill): Delete.
1959 (sim_create_inferior): Add ABFD argument. Set PC from same.
1960 (sim_load): Move code initializing trap handlers from here.
1961 (sim_open): To here.
1962 (sim_load): Delete, use sim-hload.c.
1964 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1966 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1968 * configure: Regenerated to track ../common/aclocal.m4 changes.
1971 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1973 * interp.c (sim_open): Add ABFD argument.
1974 (sim_load): Move call to sim_config from here.
1975 (sim_open): To here. Check return status.
1977 start-sanitize-r5900
1978 * gencode.c (build_instruction): Do not define x8000000000000000,
1979 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1982 start-sanitize-r5900
1983 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1985 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1986 "pdivuw" check for overflow due to signed divide by -1.
1989 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1991 * gencode.c (build_instruction): Two arg MADD should
1992 not assign result to $0.
1994 start-sanitize-r5900
1995 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1997 * gencode.c (build_instruction): For "ppac5" use unsigned
1998 arrithmetic so that the sign bit doesn't smear when right shifted.
1999 (build_instruction): For "pdiv" perform sign extension when
2000 storing results in HI and LO.
2001 (build_instructions): For "pdiv" and "pdivbw" check for
2003 (build_instruction): For "pmfhl.slw" update hi part of dest
2004 register as well as low part.
2005 (build_instruction): For "pmfhl" portably handle long long values.
2006 (build_instruction): For "pmfhl.sh" correctly negative values.
2007 Store half words 2 and three in the correct place.
2008 (build_instruction): For "psllvw", sign extend value after shift.
2011 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2013 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2014 * sim/mips/configure.in: Regenerate.
2016 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2018 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2019 signed8, unsigned8 et.al. types.
2021 start-sanitize-r5900
2022 * gencode.c (build_instruction): For PMULTU* do not sign extend
2023 registers. Make generated code easier to debug.
2026 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2027 hosts when selecting subreg.
2029 start-sanitize-r5900
2030 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
2032 * gencode.c (type_for_data_len): For 32bit operations concerned
2033 with overflow, perform op using 64bits.
2034 (build_instruction): For PADD, always compute operation using type
2035 returned by type_for_data_len.
2036 (build_instruction): For PSUBU, when overflow, saturate to zero as
2040 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2042 start-sanitize-r5900
2043 * gencode.c (build_instruction): Handle "pext5" according to
2044 version 1.95 of the r5900 ISA.
2046 * gencode.c (build_instruction): Handle "ppac5" according to
2047 version 1.95 of the r5900 ISA.
2050 * interp.c (sim_engine_run): Reset the ZERO register to zero
2051 regardless of FEATURE_WARN_ZERO.
2052 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2054 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2056 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2057 (SignalException): For BreakPoints ignore any mode bits and just
2059 (SignalException): Always set the CAUSE register.
2061 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2063 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2064 exception has been taken.
2066 * interp.c: Implement the ERET and mt/f sr instructions.
2068 start-sanitize-r5900
2069 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
2071 * gencode.c (build_instruction): For paddu, extract unsigned
2074 * gencode.c (build_instruction): Saturate padds instead of padd
2078 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2080 * interp.c (SignalException): Don't bother restarting an
2083 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2085 * interp.c (SignalException): Really take an interrupt.
2086 (interrupt_event): Only deliver interrupts when enabled.
2088 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2090 * interp.c (sim_info): Only print info when verbose.
2091 (sim_info) Use sim_io_printf for output.
2093 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2095 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2098 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2100 * interp.c (sim_do_command): Check for common commands if a
2101 simulator specific command fails.
2103 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2105 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2106 and simBE when DEBUG is defined.
2108 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2110 * interp.c (interrupt_event): New function. Pass exception event
2111 onto exception handler.
2113 * configure.in: Check for stdlib.h.
2114 * configure: Regenerate.
2116 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2117 variable declaration.
2118 (build_instruction): Initialize memval1.
2119 (build_instruction): Add UNUSED attribute to byte, bigend,
2121 (build_operands): Ditto.
2123 * interp.c: Fix GCC warnings.
2124 (sim_get_quit_code): Delete.
2126 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2127 * Makefile.in: Ditto.
2128 * configure: Re-generate.
2130 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2132 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2134 * interp.c (mips_option_handler): New function parse argumes using
2136 (myname): Replace with STATE_MY_NAME.
2137 (sim_open): Delete check for host endianness - performed by
2139 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2140 (sim_open): Move much of the initialization from here.
2141 (sim_load): To here. After the image has been loaded and
2143 (sim_open): Move ColdReset from here.
2144 (sim_create_inferior): To here.
2145 (sim_open): Make FP check less dependant on host endianness.
2147 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2149 * interp.c (sim_set_callbacks): Delete.
2151 * interp.c (membank, membank_base, membank_size): Replace with
2152 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2153 (sim_open): Remove call to callback->init. gdb/run do this.
2157 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2159 * interp.c (big_endian_p): Delete, replaced by
2160 current_target_byte_order.
2162 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2164 * interp.c (host_read_long, host_read_word, host_swap_word,
2165 host_swap_long): Delete. Using common sim-endian.
2166 (sim_fetch_register, sim_store_register): Use H2T.
2167 (pipeline_ticks): Delete. Handled by sim-events.
2169 (sim_engine_run): Update.
2171 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2173 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2175 (SignalException): To here. Signal using sim_engine_halt.
2176 (sim_stop_reason): Delete, moved to common.
2178 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2180 * interp.c (sim_open): Add callback argument.
2181 (sim_set_callbacks): Delete SIM_DESC argument.
2184 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2186 * Makefile.in (SIM_OBJS): Add common modules.
2188 * interp.c (sim_set_callbacks): Also set SD callback.
2189 (set_endianness, xfer_*, swap_*): Delete.
2190 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2191 Change to functions using sim-endian macros.
2192 (control_c, sim_stop): Delete, use common version.
2193 (simulate): Convert into.
2194 (sim_engine_run): This function.
2195 (sim_resume): Delete.
2197 * interp.c (simulation): New variable - the simulator object.
2198 (sim_kind): Delete global - merged into simulation.
2199 (sim_load): Cleanup. Move PC assignment from here.
2200 (sim_create_inferior): To here.
2202 * sim-main.h: New file.
2203 * interp.c (sim-main.h): Include.
2205 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2207 * configure: Regenerated to track ../common/aclocal.m4 changes.
2209 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2211 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2213 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2215 * gencode.c (build_instruction): DIV instructions: check
2216 for division by zero and integer overflow before using
2217 host's division operation.
2219 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2221 * Makefile.in (SIM_OBJS): Add sim-load.o.
2222 * interp.c: #include bfd.h.
2223 (target_byte_order): Delete.
2224 (sim_kind, myname, big_endian_p): New static locals.
2225 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2226 after argument parsing. Recognize -E arg, set endianness accordingly.
2227 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2228 load file into simulator. Set PC from bfd.
2229 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2230 (set_endianness): Use big_endian_p instead of target_byte_order.
2232 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2234 * interp.c (sim_size): Delete prototype - conflicts with
2235 definition in remote-sim.h. Correct definition.
2237 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2239 * configure: Regenerated to track ../common/aclocal.m4 changes.
2242 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2244 * interp.c (sim_open): New arg `kind'.
2246 * configure: Regenerated to track ../common/aclocal.m4 changes.
2248 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2250 * configure: Regenerated to track ../common/aclocal.m4 changes.
2252 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2254 * interp.c (sim_open): Set optind to 0 before calling getopt.
2256 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2258 * configure: Regenerated to track ../common/aclocal.m4 changes.
2260 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2262 * interp.c : Replace uses of pr_addr with pr_uword64
2263 where the bit length is always 64 independent of SIM_ADDR.
2264 (pr_uword64) : added.
2266 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2268 * configure: Re-generate.
2270 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2272 * configure: Regenerate to track ../common/aclocal.m4 changes.
2274 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2276 * interp.c (sim_open): New SIM_DESC result. Argument is now
2278 (other sim_*): New SIM_DESC argument.
2280 start-sanitize-r5900
2281 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
2283 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
2284 Change values to avoid overloading DOUBLEWORD which is tested
2286 * gencode.c: reinstate "offending code".
2289 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2291 * interp.c: Fix printing of addresses for non-64-bit targets.
2292 (pr_addr): Add function to print address based on size.
2293 start-sanitize-r5900
2294 * gencode.c: #ifdef out offending code until a permanent fix
2295 can be added. Code is causing build errors for non-5900 mips targets.
2298 start-sanitize-r5900
2299 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
2301 * gencode.c (process_instructions): Correct test for ISA dependent
2302 architecture bits in isa field of MIPS_DECODE.
2305 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2307 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2309 start-sanitize-r5900
2310 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
2312 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
2316 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2318 * gencode.c (build_mips16_operands): Correct computation of base
2319 address for extended PC relative instruction.
2321 start-sanitize-r5900
2322 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
2324 * Makefile.in, configure, configure.in, gencode.c,
2325 interp.c, support.h: add r5900.
2328 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2330 * interp.c (mips16_entry): Add support for floating point cases.
2331 (SignalException): Pass floating point cases to mips16_entry.
2332 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2334 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2336 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2337 and then set the state to fmt_uninterpreted.
2338 (COP_SW): Temporarily set the state to fmt_word while calling
2341 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2343 * gencode.c (build_instruction): The high order may be set in the
2344 comparison flags at any ISA level, not just ISA 4.
2346 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2348 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2349 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2350 * configure.in: sinclude ../common/aclocal.m4.
2351 * configure: Regenerated.
2353 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2355 * configure: Rebuild after change to aclocal.m4.
2357 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2359 * configure configure.in Makefile.in: Update to new configure
2360 scheme which is more compatible with WinGDB builds.
2361 * configure.in: Improve comment on how to run autoconf.
2362 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2363 * Makefile.in: Use autoconf substitution to install common
2366 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2368 * gencode.c (build_instruction): Use BigEndianCPU instead of
2371 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2373 * interp.c (sim_monitor): Make output to stdout visible in
2374 wingdb's I/O log window.
2376 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2378 * support.h: Undo previous change to SIGTRAP
2381 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2383 * interp.c (store_word, load_word): New static functions.
2384 (mips16_entry): New static function.
2385 (SignalException): Look for mips16 entry and exit instructions.
2386 (simulate): Use the correct index when setting fpr_state after
2387 doing a pending move.
2389 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2391 * interp.c: Fix byte-swapping code throughout to work on
2392 both little- and big-endian hosts.
2394 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2396 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2397 with gdb/config/i386/xm-windows.h.
2399 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2401 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2402 that messes up arithmetic shifts.
2404 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2406 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2407 SIGTRAP and SIGQUIT for _WIN32.
2409 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2411 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2412 force a 64 bit multiplication.
2413 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2414 destination register is 0, since that is the default mips16 nop
2417 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2419 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2420 (build_endian_shift): Don't check proc64.
2421 (build_instruction): Always set memval to uword64. Cast op2 to
2422 uword64 when shifting it left in memory instructions. Always use
2423 the same code for stores--don't special case proc64.
2425 * gencode.c (build_mips16_operands): Fix base PC value for PC
2427 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2429 * interp.c (simJALDELAYSLOT): Define.
2430 (JALDELAYSLOT): Define.
2431 (INDELAYSLOT, INJALDELAYSLOT): Define.
2432 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2434 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2436 * interp.c (sim_open): add flush_cache as a PMON routine
2437 (sim_monitor): handle flush_cache by ignoring it
2439 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2441 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2443 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2444 (BigEndianMem): Rename to ByteSwapMem and change sense.
2445 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2446 BigEndianMem references to !ByteSwapMem.
2447 (set_endianness): New function, with prototype.
2448 (sim_open): Call set_endianness.
2449 (sim_info): Use simBE instead of BigEndianMem.
2450 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2451 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2452 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2453 ifdefs, keeping the prototype declaration.
2454 (swap_word): Rewrite correctly.
2455 (ColdReset): Delete references to CONFIG. Delete endianness related
2456 code; moved to set_endianness.
2458 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2460 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2461 * interp.c (CHECKHILO): Define away.
2462 (simSIGINT): New macro.
2463 (membank_size): Increase from 1MB to 2MB.
2464 (control_c): New function.
2465 (sim_resume): Rename parameter signal to signal_number. Add local
2466 variable prev. Call signal before and after simulate.
2467 (sim_stop_reason): Add simSIGINT support.
2468 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2470 (sim_warning): Delete call to SignalException. Do call printf_filtered
2472 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2473 a call to sim_warning.
2475 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2477 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2478 16 bit instructions.
2480 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2482 Add support for mips16 (16 bit MIPS implementation):
2483 * gencode.c (inst_type): Add mips16 instruction encoding types.
2484 (GETDATASIZEINSN): Define.
2485 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2486 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2488 (MIPS16_DECODE): New table, for mips16 instructions.
2489 (bitmap_val): New static function.
2490 (struct mips16_op): Define.
2491 (mips16_op_table): New table, for mips16 operands.
2492 (build_mips16_operands): New static function.
2493 (process_instructions): If PC is odd, decode a mips16
2494 instruction. Break out instruction handling into new
2495 build_instruction function.
2496 (build_instruction): New static function, broken out of
2497 process_instructions. Check modifiers rather than flags for SHIFT
2498 bit count and m[ft]{hi,lo} direction.
2499 (usage): Pass program name to fprintf.
2500 (main): Remove unused variable this_option_optind. Change
2501 ``*loptarg++'' to ``loptarg++''.
2502 (my_strtoul): Parenthesize && within ||.
2503 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2504 (simulate): If PC is odd, fetch a 16 bit instruction, and
2505 increment PC by 2 rather than 4.
2506 * configure.in: Add case for mips16*-*-*.
2507 * configure: Rebuild.
2509 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2511 * interp.c: Allow -t to enable tracing in standalone simulator.
2512 Fix garbage output in trace file and error messages.
2514 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2516 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2517 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2518 * configure.in: Simplify using macros in ../common/aclocal.m4.
2519 * configure: Regenerated.
2520 * tconfig.in: New file.
2522 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2524 * interp.c: Fix bugs in 64-bit port.
2525 Use ansi function declarations for msvc compiler.
2526 Initialize and test file pointer in trace code.
2527 Prevent duplicate definition of LAST_EMED_REGNUM.
2529 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2531 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2533 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2535 * interp.c (SignalException): Check for explicit terminating
2537 * gencode.c: Pass instruction value through SignalException()
2538 calls for Trap, Breakpoint and Syscall.
2540 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2542 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2543 only used on those hosts that provide it.
2544 * configure.in: Add sqrt() to list of functions to be checked for.
2545 * config.in: Re-generated.
2546 * configure: Re-generated.
2548 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2550 * gencode.c (process_instructions): Call build_endian_shift when
2551 expanding STORE RIGHT, to fix swr.
2552 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2553 clear the high bits.
2554 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2555 Fix float to int conversions to produce signed values.
2557 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2559 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2560 (process_instructions): Correct handling of nor instruction.
2561 Correct shift count for 32 bit shift instructions. Correct sign
2562 extension for arithmetic shifts to not shift the number of bits in
2563 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2564 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2566 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2567 It's OK to have a mult follow a mult. What's not OK is to have a
2568 mult follow an mfhi.
2569 (Convert): Comment out incorrect rounding code.
2571 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2573 * interp.c (sim_monitor): Improved monitor printf
2574 simulation. Tidied up simulator warnings, and added "--log" option
2575 for directing warning message output.
2576 * gencode.c: Use sim_warning() rather than WARNING macro.
2578 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2580 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2581 getopt1.o, rather than on gencode.c. Link objects together.
2582 Don't link against -liberty.
2583 (gencode.o, getopt.o, getopt1.o): New targets.
2584 * gencode.c: Include <ctype.h> and "ansidecl.h".
2585 (AND): Undefine after including "ansidecl.h".
2586 (ULONG_MAX): Define if not defined.
2587 (OP_*): Don't define macros; now defined in opcode/mips.h.
2588 (main): Call my_strtoul rather than strtoul.
2589 (my_strtoul): New static function.
2591 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2593 * gencode.c (process_instructions): Generate word64 and uword64
2594 instead of `long long' and `unsigned long long' data types.
2595 * interp.c: #include sysdep.h to get signals, and define default
2597 * (Convert): Work around for Visual-C++ compiler bug with type
2599 * support.h: Make things compile under Visual-C++ by using
2600 __int64 instead of `long long'. Change many refs to long long
2601 into word64/uword64 typedefs.
2603 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2605 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2606 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2608 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2609 (AC_PROG_INSTALL): Added.
2610 (AC_PROG_CC): Moved to before configure.host call.
2611 * configure: Rebuilt.
2613 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2615 * configure.in: Define @SIMCONF@ depending on mips target.
2616 * configure: Rebuild.
2617 * Makefile.in (run): Add @SIMCONF@ to control simulator
2619 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2620 * interp.c: Remove some debugging, provide more detailed error
2621 messages, update memory accesses to use LOADDRMASK.
2623 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2625 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2626 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2628 * configure: Rebuild.
2629 * config.in: New file, generated by autoheader.
2630 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2631 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2632 HAVE_ANINT and HAVE_AINT, as appropriate.
2633 * Makefile.in (run): Use @LIBS@ rather than -lm.
2634 (interp.o): Depend upon config.h.
2635 (Makefile): Just rebuild Makefile.
2636 (clean): Remove stamp-h.
2637 (mostlyclean): Make the same as clean, not as distclean.
2638 (config.h, stamp-h): New targets.
2640 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2642 * interp.c (ColdReset): Fix boolean test. Make all simulator
2645 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2647 * interp.c (xfer_direct_word, xfer_direct_long,
2648 swap_direct_word, swap_direct_long, xfer_big_word,
2649 xfer_big_long, xfer_little_word, xfer_little_long,
2650 swap_word,swap_long): Added.
2651 * interp.c (ColdReset): Provide function indirection to
2652 host<->simulated_target transfer routines.
2653 * interp.c (sim_store_register, sim_fetch_register): Updated to
2654 make use of indirected transfer routines.
2656 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2658 * gencode.c (process_instructions): Ensure FP ABS instruction
2660 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2661 system call support.
2663 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2665 * interp.c (sim_do_command): Complain if callback structure not
2668 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2670 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2671 support for Sun hosts.
2672 * Makefile.in (gencode): Ensure the host compiler and libraries
2673 used for cross-hosted build.
2675 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2677 * interp.c, gencode.c: Some more (TODO) tidying.
2679 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2681 * gencode.c, interp.c: Replaced explicit long long references with
2682 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2683 * support.h (SET64LO, SET64HI): Macros added.
2685 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2687 * configure: Regenerate with autoconf 2.7.
2689 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2691 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2692 * support.h: Remove superfluous "1" from #if.
2693 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2695 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2697 * interp.c (StoreFPR): Control UndefinedResult() call on
2698 WARN_RESULT manifest.
2700 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2702 * gencode.c: Tidied instruction decoding, and added FP instruction
2705 * interp.c: Added dineroIII, and BSD profiling support. Also
2706 run-time FP handling.
2708 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2710 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2711 gencode.c, interp.c, support.h: created.