1 2012-06-15 Joel Brobecker <brobecker@adacore.com>
3 * config.in, configure: Regenerate.
5 2012-05-18 Nick Clifton <nickc@redhat.com>
8 * interp.c: Include config.h before system header files.
10 2012-03-24 Mike Frysinger <vapier@gentoo.org>
12 * aclocal.m4, config.in, configure: Regenerate.
14 2011-12-03 Mike Frysinger <vapier@gentoo.org>
16 * aclocal.m4: New file.
17 * configure: Regenerate.
19 2011-10-19 Mike Frysinger <vapier@gentoo.org>
21 * configure: Regenerate after common/acinclude.m4 update.
23 2011-10-17 Mike Frysinger <vapier@gentoo.org>
25 * configure.ac: Change include to common/acinclude.m4.
27 2011-10-17 Mike Frysinger <vapier@gentoo.org>
29 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
30 call. Replace common.m4 include with SIM_AC_COMMON.
31 * configure: Regenerate.
33 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
35 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
37 (tmp-mach-multi): Exit early when igen fails.
39 2011-07-05 Mike Frysinger <vapier@gentoo.org>
41 * interp.c (sim_do_command): Delete.
43 2011-02-14 Mike Frysinger <vapier@gentoo.org>
45 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
46 (tx3904sio_fifo_reset): Likewise.
47 * interp.c (sim_monitor): Likewise.
49 2010-04-14 Mike Frysinger <vapier@gentoo.org>
51 * interp.c (sim_write): Add const to buffer arg.
53 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
55 * interp.c: Don't include sysdep.h
57 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
59 * configure: Regenerate.
61 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
63 * config.in: Regenerate.
64 * configure: Likewise.
66 * configure: Regenerate.
68 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
70 * configure: Regenerate to track ../common/common.m4 changes.
73 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
74 Daniel Jacobowitz <dan@codesourcery.com>
75 Joseph Myers <joseph@codesourcery.com>
77 * configure: Regenerate.
79 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
81 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
82 that unconditionally allows fmt_ps.
83 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
84 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
85 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
86 filter from 64,f to 32,f.
87 (PREFX): Change filter from 64 to 32.
88 (LDXC1, LUXC1): Provide separate mips32r2 implementations
89 that use do_load_double instead of do_load. Make both LUXC1
90 versions unpredictable if SizeFGR () != 64.
91 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
92 instead of do_store. Remove unused variable. Make both SUXC1
93 versions unpredictable if SizeFGR () != 64.
95 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
97 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
98 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
101 2007-09-04 Nick Clifton <nickc@redhat.com>
103 * interp.c (options enum): Add OPTION_INFO_MEMORY.
104 (display_mem_info): New static variable.
105 (mips_option_handler): Handle OPTION_INFO_MEMORY.
106 (mips_options): Add info-memory and memory-info.
107 (sim_open): After processing the command line and board
108 specification, check display_mem_info. If it is set then
109 call the real handler for the --memory-info command line
112 2007-08-24 Joel Brobecker <brobecker@adacore.com>
114 * configure.ac: Change license of multi-run.c to GPL version 3.
115 * configure: Regenerate.
117 2007-06-28 Richard Sandiford <richard@codesourcery.com>
119 * configure.ac, configure: Revert last patch.
121 2007-06-26 Richard Sandiford <richard@codesourcery.com>
123 * configure.ac (sim_mipsisa3264_configs): New variable.
124 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
125 every configuration support all four targets, using the triplet to
126 determine the default.
127 * configure: Regenerate.
129 2007-06-25 Richard Sandiford <richard@codesourcery.com>
131 * Makefile.in (m16run.o): New rule.
133 2007-05-15 Thiemo Seufer <ths@mips.com>
135 * mips3264r2.igen (DSHD): Fix compile warning.
137 2007-05-14 Thiemo Seufer <ths@mips.com>
139 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
140 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
141 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
142 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
145 2007-03-01 Thiemo Seufer <ths@mips.com>
147 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
150 2007-02-20 Thiemo Seufer <ths@mips.com>
152 * dsp.igen: Update copyright notice.
153 * dsp2.igen: Fix copyright notice.
155 2007-02-20 Thiemo Seufer <ths@mips.com>
156 Chao-Ying Fu <fu@mips.com>
158 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
159 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
160 Add dsp2 to sim_igen_machine.
161 * configure: Regenerate.
162 * dsp.igen (do_ph_op): Add MUL support when op = 2.
163 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
164 (mulq_rs.ph): Use do_ph_mulq.
165 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
166 * mips.igen: Add dsp2 model and include dsp2.igen.
167 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
168 for *mips32r2, *mips64r2, *dsp.
169 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
170 for *mips32r2, *mips64r2, *dsp2.
171 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
173 2007-02-19 Thiemo Seufer <ths@mips.com>
174 Nigel Stephens <nigel@mips.com>
176 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
177 jumps with hazard barrier.
179 2007-02-19 Thiemo Seufer <ths@mips.com>
180 Nigel Stephens <nigel@mips.com>
182 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
183 after each call to sim_io_write.
185 2007-02-19 Thiemo Seufer <ths@mips.com>
186 Nigel Stephens <nigel@mips.com>
188 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
189 supported by this simulator.
190 (decode_coproc): Recognise additional CP0 Config registers
193 2007-02-19 Thiemo Seufer <ths@mips.com>
194 Nigel Stephens <nigel@mips.com>
195 David Ung <davidu@mips.com>
197 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
198 uninterpreted formats. If fmt is one of the uninterpreted types
199 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
200 fmt_word, and fmt_uninterpreted_64 like fmt_long.
201 (store_fpr): When writing an invalid odd register, set the
202 matching even register to fmt_unknown, not the following register.
203 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
204 the the memory window at offset 0 set by --memory-size command
206 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
208 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
210 (sim_monitor): When returning the memory size to the MIPS
211 application, use the value in STATE_MEM_SIZE, not an arbitrary
213 (cop_lw): Don' mess around with FPR_STATE, just pass
214 fmt_uninterpreted_32 to StoreFPR.
216 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
218 * mips.igen (not_word_value): Single version for mips32, mips64
221 2007-02-19 Thiemo Seufer <ths@mips.com>
222 Nigel Stephens <nigel@mips.com>
224 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
227 2007-02-17 Thiemo Seufer <ths@mips.com>
229 * configure.ac (mips*-sde-elf*): Move in front of generic machine
231 * configure: Regenerate.
233 2007-02-17 Thiemo Seufer <ths@mips.com>
235 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
236 Add mdmx to sim_igen_machine.
237 (mipsisa64*-*-*): Likewise. Remove dsp.
238 (mipsisa32*-*-*): Remove dsp.
239 * configure: Regenerate.
241 2007-02-13 Thiemo Seufer <ths@mips.com>
243 * configure.ac: Add mips*-sde-elf* target.
244 * configure: Regenerate.
246 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
248 * acconfig.h: Remove.
249 * config.in, configure: Regenerate.
251 2006-11-07 Thiemo Seufer <ths@mips.com>
253 * dsp.igen (do_w_op): Fix compiler warning.
255 2006-08-29 Thiemo Seufer <ths@mips.com>
256 David Ung <davidu@mips.com>
258 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
260 * configure: Regenerate.
261 * mips.igen (model): Add smartmips.
262 (MADDU): Increment ACX if carry.
263 (do_mult): Clear ACX.
264 (ROR,RORV): Add smartmips.
265 (include): Include smartmips.igen.
266 * sim-main.h (ACX): Set to REGISTERS[89].
267 * smartmips.igen: New file.
269 2006-08-29 Thiemo Seufer <ths@mips.com>
270 David Ung <davidu@mips.com>
272 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
273 mips3264r2.igen. Add missing dependency rules.
274 * m16e.igen: Support for mips16e save/restore instructions.
276 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
278 * configure: Regenerated.
280 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
282 * configure: Regenerated.
284 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
286 * configure: Regenerated.
288 2006-05-15 Chao-ying Fu <fu@mips.com>
290 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
292 2006-04-18 Nick Clifton <nickc@redhat.com>
294 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
297 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
299 * configure: Regenerate.
301 2005-12-14 Chao-ying Fu <fu@mips.com>
303 * Makefile.in (SIM_OBJS): Add dsp.o.
304 (dsp.o): New dependency.
305 (IGEN_INCLUDE): Add dsp.igen.
306 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
307 mipsisa64*-*-*): Add dsp to sim_igen_machine.
308 * configure: Regenerate.
309 * mips.igen: Add dsp model and include dsp.igen.
310 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
311 because these instructions are extended in DSP ASE.
312 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
313 adding 6 DSP accumulator registers and 1 DSP control register.
314 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
315 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
316 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
317 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
318 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
319 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
320 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
321 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
322 DSPCR_CCOND_SMASK): New define.
323 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
324 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
326 2005-07-08 Ian Lance Taylor <ian@airs.com>
328 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
330 2005-06-16 David Ung <davidu@mips.com>
331 Nigel Stephens <nigel@mips.com>
333 * mips.igen: New mips16e model and include m16e.igen.
334 (check_u64): Add mips16e tag.
335 * m16e.igen: New file for MIPS16e instructions.
336 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
337 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
339 * configure: Regenerate.
341 2005-05-26 David Ung <davidu@mips.com>
343 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
344 tags to all instructions which are applicable to the new ISAs.
345 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
347 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
349 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
351 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
352 * configure: Regenerate.
354 2005-03-23 Mark Kettenis <kettenis@gnu.org>
356 * configure: Regenerate.
358 2005-01-14 Andrew Cagney <cagney@gnu.org>
360 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
361 explicit call to AC_CONFIG_HEADER.
362 * configure: Regenerate.
364 2005-01-12 Andrew Cagney <cagney@gnu.org>
366 * configure.ac: Update to use ../common/common.m4.
367 * configure: Re-generate.
369 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
371 * configure: Regenerated to track ../common/aclocal.m4 changes.
373 2005-01-07 Andrew Cagney <cagney@gnu.org>
375 * configure.ac: Rename configure.in, require autoconf 2.59.
376 * configure: Re-generate.
378 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
380 * configure: Regenerate for ../common/aclocal.m4 update.
382 2004-09-24 Monika Chaddha <monika@acmet.com>
384 Committed by Andrew Cagney.
385 * m16.igen (CMP, CMPI): Fix assembler.
387 2004-08-18 Chris Demetriou <cgd@broadcom.com>
389 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
390 * configure: Regenerate.
392 2004-06-25 Chris Demetriou <cgd@broadcom.com>
394 * configure.in (sim_m16_machine): Include mipsIII.
395 * configure: Regenerate.
397 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
399 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
401 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
403 2004-04-10 Chris Demetriou <cgd@broadcom.com>
405 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
407 2004-04-09 Chris Demetriou <cgd@broadcom.com>
409 * mips.igen (check_fmt): Remove.
410 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
411 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
412 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
413 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
414 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
415 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
416 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
417 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
418 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
419 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
421 2004-04-09 Chris Demetriou <cgd@broadcom.com>
423 * sb1.igen (check_sbx): New function.
424 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
426 2004-03-29 Chris Demetriou <cgd@broadcom.com>
427 Richard Sandiford <rsandifo@redhat.com>
429 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
430 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
431 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
432 separate implementations for mipsIV and mipsV. Use new macros to
433 determine whether the restrictions apply.
435 2004-01-19 Chris Demetriou <cgd@broadcom.com>
437 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
438 (check_mult_hilo): Improve comments.
439 (check_div_hilo): Likewise. Also, fork off a new version
440 to handle mips32/mips64 (since there are no hazards to check
443 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
445 * mips.igen (do_dmultx): Fix check for negative operands.
447 2003-05-16 Ian Lance Taylor <ian@airs.com>
449 * Makefile.in (SHELL): Make sure this is defined.
450 (various): Use $(SHELL) whenever we invoke move-if-change.
452 2003-05-03 Chris Demetriou <cgd@broadcom.com>
454 * cp1.c: Tweak attribution slightly.
457 * mdmx.igen: Likewise.
458 * mips3d.igen: Likewise.
459 * sb1.igen: Likewise.
461 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
463 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
466 2003-02-27 Andrew Cagney <cagney@redhat.com>
468 * interp.c (sim_open): Rename _bfd to bfd.
469 (sim_create_inferior): Ditto.
471 2003-01-14 Chris Demetriou <cgd@broadcom.com>
473 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
475 2003-01-14 Chris Demetriou <cgd@broadcom.com>
477 * mips.igen (EI, DI): Remove.
479 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
481 * Makefile.in (tmp-run-multi): Fix mips16 filter.
483 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
484 Andrew Cagney <ac131313@redhat.com>
485 Gavin Romig-Koch <gavin@redhat.com>
486 Graydon Hoare <graydon@redhat.com>
487 Aldy Hernandez <aldyh@redhat.com>
488 Dave Brolley <brolley@redhat.com>
489 Chris Demetriou <cgd@broadcom.com>
491 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
492 (sim_mach_default): New variable.
493 (mips64vr-*-*, mips64vrel-*-*): New configurations.
494 Add a new simulator generator, MULTI.
495 * configure: Regenerate.
496 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
497 (multi-run.o): New dependency.
498 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
499 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
500 (tmp-multi): Combine them.
501 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
502 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
503 (distclean-extra): New rule.
504 * sim-main.h: Include bfd.h.
505 (MIPS_MACH): New macro.
506 * mips.igen (vr4120, vr5400, vr5500): New models.
507 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
508 * vr.igen: Replace with new version.
510 2003-01-04 Chris Demetriou <cgd@broadcom.com>
512 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
513 * configure: Regenerate.
515 2002-12-31 Chris Demetriou <cgd@broadcom.com>
517 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
518 * mips.igen: Remove all invocations of check_branch_bug and
521 2002-12-16 Chris Demetriou <cgd@broadcom.com>
523 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
525 2002-07-30 Chris Demetriou <cgd@broadcom.com>
527 * mips.igen (do_load_double, do_store_double): New functions.
528 (LDC1, SDC1): Rename to...
529 (LDC1b, SDC1b): respectively.
530 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
532 2002-07-29 Michael Snyder <msnyder@redhat.com>
534 * cp1.c (fp_recip2): Modify initialization expression so that
535 GCC will recognize it as constant.
537 2002-06-18 Chris Demetriou <cgd@broadcom.com>
539 * mdmx.c (SD_): Delete.
540 (Unpredictable): Re-define, for now, to directly invoke
541 unpredictable_action().
542 (mdmx_acc_op): Fix error in .ob immediate handling.
544 2002-06-18 Andrew Cagney <cagney@redhat.com>
546 * interp.c (sim_firmware_command): Initialize `address'.
548 2002-06-16 Andrew Cagney <ac131313@redhat.com>
550 * configure: Regenerated to track ../common/aclocal.m4 changes.
552 2002-06-14 Chris Demetriou <cgd@broadcom.com>
553 Ed Satterthwaite <ehs@broadcom.com>
555 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
556 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
557 * mips.igen: Include mips3d.igen.
558 (mips3d): New model name for MIPS-3D ASE instructions.
559 (CVT.W.fmt): Don't use this instruction for word (source) format
561 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
562 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
563 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
564 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
565 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
566 (RSquareRoot1, RSquareRoot2): New macros.
567 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
568 (fp_rsqrt2): New functions.
569 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
570 * configure: Regenerate.
572 2002-06-13 Chris Demetriou <cgd@broadcom.com>
573 Ed Satterthwaite <ehs@broadcom.com>
575 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
576 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
577 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
578 (convert): Note that this function is not used for paired-single
580 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
581 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
582 (check_fmt_p): Enable paired-single support.
583 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
584 (PUU.PS): New instructions.
585 (CVT.S.fmt): Don't use this instruction for paired-single format
587 * sim-main.h (FP_formats): New value 'fmt_ps.'
588 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
589 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
591 2002-06-12 Chris Demetriou <cgd@broadcom.com>
593 * mips.igen: Fix formatting of function calls in
596 2002-06-12 Chris Demetriou <cgd@broadcom.com>
598 * mips.igen (MOVN, MOVZ): Trace result.
599 (TNEI): Print "tnei" as the opcode name in traces.
600 (CEIL.W): Add disassembly string for traces.
601 (RSQRT.fmt): Make location of disassembly string consistent
602 with other instructions.
604 2002-06-12 Chris Demetriou <cgd@broadcom.com>
606 * mips.igen (X): Delete unused function.
608 2002-06-08 Andrew Cagney <cagney@redhat.com>
610 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
612 2002-06-07 Chris Demetriou <cgd@broadcom.com>
613 Ed Satterthwaite <ehs@broadcom.com>
615 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
616 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
617 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
618 (fp_nmsub): New prototypes.
619 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
620 (NegMultiplySub): New defines.
621 * mips.igen (RSQRT.fmt): Use RSquareRoot().
622 (MADD.D, MADD.S): Replace with...
623 (MADD.fmt): New instruction.
624 (MSUB.D, MSUB.S): Replace with...
625 (MSUB.fmt): New instruction.
626 (NMADD.D, NMADD.S): Replace with...
627 (NMADD.fmt): New instruction.
628 (NMSUB.D, MSUB.S): Replace with...
629 (NMSUB.fmt): New instruction.
631 2002-06-07 Chris Demetriou <cgd@broadcom.com>
632 Ed Satterthwaite <ehs@broadcom.com>
634 * cp1.c: Fix more comment spelling and formatting.
635 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
636 (denorm_mode): New function.
637 (fpu_unary, fpu_binary): Round results after operation, collect
638 status from rounding operations, and update the FCSR.
639 (convert): Collect status from integer conversions and rounding
640 operations, and update the FCSR. Adjust NaN values that result
641 from conversions. Convert to use sim_io_eprintf rather than
642 fprintf, and remove some debugging code.
643 * cp1.h (fenr_FS): New define.
645 2002-06-07 Chris Demetriou <cgd@broadcom.com>
647 * cp1.c (convert): Remove unusable debugging code, and move MIPS
648 rounding mode to sim FP rounding mode flag conversion code into...
649 (rounding_mode): New function.
651 2002-06-07 Chris Demetriou <cgd@broadcom.com>
653 * cp1.c: Clean up formatting of a few comments.
654 (value_fpr): Reformat switch statement.
656 2002-06-06 Chris Demetriou <cgd@broadcom.com>
657 Ed Satterthwaite <ehs@broadcom.com>
660 * sim-main.h: Include cp1.h.
661 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
662 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
663 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
664 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
665 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
666 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
667 * cp1.c: Don't include sim-fpu.h; already included by
668 sim-main.h. Clean up formatting of some comments.
669 (NaN, Equal, Less): Remove.
670 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
671 (fp_cmp): New functions.
672 * mips.igen (do_c_cond_fmt): Remove.
673 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
674 Compare. Add result tracing.
675 (CxC1): Remove, replace with...
676 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
677 (DMxC1): Remove, replace with...
678 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
679 (MxC1): Remove, replace with...
680 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
682 2002-06-04 Chris Demetriou <cgd@broadcom.com>
684 * sim-main.h (FGRIDX): Remove, replace all uses with...
685 (FGR_BASE): New macro.
686 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
687 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
688 (NR_FGR, FGR): Likewise.
689 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
690 * mips.igen: Likewise.
692 2002-06-04 Chris Demetriou <cgd@broadcom.com>
694 * cp1.c: Add an FSF Copyright notice to this file.
696 2002-06-04 Chris Demetriou <cgd@broadcom.com>
697 Ed Satterthwaite <ehs@broadcom.com>
699 * cp1.c (Infinity): Remove.
700 * sim-main.h (Infinity): Likewise.
702 * cp1.c (fp_unary, fp_binary): New functions.
703 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
704 (fp_sqrt): New functions, implemented in terms of the above.
705 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
706 (Recip, SquareRoot): Remove (replaced by functions above).
707 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
708 (fp_recip, fp_sqrt): New prototypes.
709 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
710 (Recip, SquareRoot): Replace prototypes with #defines which
711 invoke the functions above.
713 2002-06-03 Chris Demetriou <cgd@broadcom.com>
715 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
716 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
717 file, remove PARAMS from prototypes.
718 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
719 simulator state arguments.
720 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
721 pass simulator state arguments.
722 * cp1.c (SD): Redefine as CPU_STATE(cpu).
723 (store_fpr, convert): Remove 'sd' argument.
724 (value_fpr): Likewise. Convert to use 'SD' instead.
726 2002-06-03 Chris Demetriou <cgd@broadcom.com>
728 * cp1.c (Min, Max): Remove #if 0'd functions.
729 * sim-main.h (Min, Max): Remove.
731 2002-06-03 Chris Demetriou <cgd@broadcom.com>
733 * cp1.c: fix formatting of switch case and default labels.
734 * interp.c: Likewise.
735 * sim-main.c: Likewise.
737 2002-06-03 Chris Demetriou <cgd@broadcom.com>
739 * cp1.c: Clean up comments which describe FP formats.
740 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
742 2002-06-03 Chris Demetriou <cgd@broadcom.com>
743 Ed Satterthwaite <ehs@broadcom.com>
745 * configure.in (mipsisa64sb1*-*-*): New target for supporting
746 Broadcom SiByte SB-1 processor configurations.
747 * configure: Regenerate.
748 * sb1.igen: New file.
749 * mips.igen: Include sb1.igen.
751 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
752 * mdmx.igen: Add "sb1" model to all appropriate functions and
754 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
755 (ob_func, ob_acc): Reference the above.
756 (qh_acc): Adjust to keep the same size as ob_acc.
757 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
758 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
760 2002-06-03 Chris Demetriou <cgd@broadcom.com>
762 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
764 2002-06-02 Chris Demetriou <cgd@broadcom.com>
765 Ed Satterthwaite <ehs@broadcom.com>
767 * mips.igen (mdmx): New (pseudo-)model.
768 * mdmx.c, mdmx.igen: New files.
769 * Makefile.in (SIM_OBJS): Add mdmx.o.
770 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
772 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
773 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
774 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
775 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
776 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
777 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
778 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
779 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
780 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
781 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
782 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
783 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
784 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
785 (qh_fmtsel): New macros.
786 (_sim_cpu): New member "acc".
787 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
788 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
790 2002-05-01 Chris Demetriou <cgd@broadcom.com>
792 * interp.c: Use 'deprecated' rather than 'depreciated.'
793 * sim-main.h: Likewise.
795 2002-05-01 Chris Demetriou <cgd@broadcom.com>
797 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
798 which wouldn't compile anyway.
799 * sim-main.h (unpredictable_action): New function prototype.
800 (Unpredictable): Define to call igen function unpredictable().
801 (NotWordValue): New macro to call igen function not_word_value().
802 (UndefinedResult): Remove.
803 * interp.c (undefined_result): Remove.
804 (unpredictable_action): New function.
805 * mips.igen (not_word_value, unpredictable): New functions.
806 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
807 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
808 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
809 NotWordValue() to check for unpredictable inputs, then
810 Unpredictable() to handle them.
812 2002-02-24 Chris Demetriou <cgd@broadcom.com>
814 * mips.igen: Fix formatting of calls to Unpredictable().
816 2002-04-20 Andrew Cagney <ac131313@redhat.com>
818 * interp.c (sim_open): Revert previous change.
820 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
822 * interp.c (sim_open): Disable chunk of code that wrote code in
823 vector table entries.
825 2002-03-19 Chris Demetriou <cgd@broadcom.com>
827 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
828 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
831 2002-03-19 Chris Demetriou <cgd@broadcom.com>
833 * cp1.c: Fix many formatting issues.
835 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
837 * cp1.c (fpu_format_name): New function to replace...
838 (DOFMT): This. Delete, and update all callers.
839 (fpu_rounding_mode_name): New function to replace...
840 (RMMODE): This. Delete, and update all callers.
842 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
844 * interp.c: Move FPU support routines from here to...
845 * cp1.c: Here. New file.
846 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
849 2002-03-12 Chris Demetriou <cgd@broadcom.com>
851 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
852 * mips.igen (mips32, mips64): New models, add to all instructions
853 and functions as appropriate.
854 (loadstore_ea, check_u64): New variant for model mips64.
855 (check_fmt_p): New variant for models mipsV and mips64, remove
856 mipsV model marking fro other variant.
859 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
860 for mips32 and mips64.
861 (DCLO, DCLZ): New instructions for mips64.
863 2002-03-07 Chris Demetriou <cgd@broadcom.com>
865 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
866 immediate or code as a hex value with the "%#lx" format.
867 (ANDI): Likewise, and fix printed instruction name.
869 2002-03-05 Chris Demetriou <cgd@broadcom.com>
871 * sim-main.h (UndefinedResult, Unpredictable): New macros
872 which currently do nothing.
874 2002-03-05 Chris Demetriou <cgd@broadcom.com>
876 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
877 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
878 (status_CU3): New definitions.
880 * sim-main.h (ExceptionCause): Add new values for MIPS32
881 and MIPS64: MDMX, MCheck, CacheErr. Update comments
882 for DebugBreakPoint and NMIReset to note their status in
884 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
885 (SignalExceptionCacheErr): New exception macros.
887 2002-03-05 Chris Demetriou <cgd@broadcom.com>
889 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
890 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
892 (SignalExceptionCoProcessorUnusable): Take as argument the
893 unusable coprocessor number.
895 2002-03-05 Chris Demetriou <cgd@broadcom.com>
897 * mips.igen: Fix formatting of all SignalException calls.
899 2002-03-05 Chris Demetriou <cgd@broadcom.com>
901 * sim-main.h (SIGNEXTEND): Remove.
903 2002-03-04 Chris Demetriou <cgd@broadcom.com>
905 * mips.igen: Remove gencode comment from top of file, fix
906 spelling in another comment.
908 2002-03-04 Chris Demetriou <cgd@broadcom.com>
910 * mips.igen (check_fmt, check_fmt_p): New functions to check
911 whether specific floating point formats are usable.
912 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
913 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
914 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
915 Use the new functions.
916 (do_c_cond_fmt): Remove format checks...
917 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
919 2002-03-03 Chris Demetriou <cgd@broadcom.com>
921 * mips.igen: Fix formatting of check_fpu calls.
923 2002-03-03 Chris Demetriou <cgd@broadcom.com>
925 * mips.igen (FLOOR.L.fmt): Store correct destination register.
927 2002-03-03 Chris Demetriou <cgd@broadcom.com>
929 * mips.igen: Remove whitespace at end of lines.
931 2002-03-02 Chris Demetriou <cgd@broadcom.com>
933 * mips.igen (loadstore_ea): New function to do effective
934 address calculations.
935 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
936 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
937 CACHE): Use loadstore_ea to do effective address computations.
939 2002-03-02 Chris Demetriou <cgd@broadcom.com>
941 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
942 * mips.igen (LL, CxC1, MxC1): Likewise.
944 2002-03-02 Chris Demetriou <cgd@broadcom.com>
946 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
947 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
948 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
949 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
950 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
951 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
952 Don't split opcode fields by hand, use the opcode field values
955 2002-03-01 Chris Demetriou <cgd@broadcom.com>
957 * mips.igen (do_divu): Fix spacing.
959 * mips.igen (do_dsllv): Move to be right before DSLLV,
960 to match the rest of the do_<shift> functions.
962 2002-03-01 Chris Demetriou <cgd@broadcom.com>
964 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
965 DSRL32, do_dsrlv): Trace inputs and results.
967 2002-03-01 Chris Demetriou <cgd@broadcom.com>
969 * mips.igen (CACHE): Provide instruction-printing string.
971 * interp.c (signal_exception): Comment tokens after #endif.
973 2002-02-28 Chris Demetriou <cgd@broadcom.com>
975 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
976 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
977 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
978 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
979 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
980 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
981 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
982 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
984 2002-02-28 Chris Demetriou <cgd@broadcom.com>
986 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
987 instruction-printing string.
988 (LWU): Use '64' as the filter flag.
990 2002-02-28 Chris Demetriou <cgd@broadcom.com>
992 * mips.igen (SDXC1): Fix instruction-printing string.
994 2002-02-28 Chris Demetriou <cgd@broadcom.com>
996 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
999 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1001 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1004 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1006 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1007 add a comma) so that it more closely match the MIPS ISA
1008 documentation opcode partitioning.
1009 (PREF): Put useful names on opcode fields, and include
1010 instruction-printing string.
1012 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1014 * mips.igen (check_u64): New function which in the future will
1015 check whether 64-bit instructions are usable and signal an
1016 exception if not. Currently a no-op.
1017 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1018 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1019 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1020 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1022 * mips.igen (check_fpu): New function which in the future will
1023 check whether FPU instructions are usable and signal an exception
1024 if not. Currently a no-op.
1025 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1026 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1027 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1028 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1029 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1030 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1031 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1032 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1034 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1036 * mips.igen (do_load_left, do_load_right): Move to be immediately
1038 (do_store_left, do_store_right): Move to be immediately following
1041 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1043 * mips.igen (mipsV): New model name. Also, add it to
1044 all instructions and functions where it is appropriate.
1046 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1048 * mips.igen: For all functions and instructions, list model
1049 names that support that instruction one per line.
1051 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1053 * mips.igen: Add some additional comments about supported
1054 models, and about which instructions go where.
1055 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1056 order as is used in the rest of the file.
1058 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1060 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1061 indicating that ALU32_END or ALU64_END are there to check
1063 (DADD): Likewise, but also remove previous comment about
1066 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1068 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1069 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1070 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1071 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1072 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1073 fields (i.e., add and move commas) so that they more closely
1074 match the MIPS ISA documentation opcode partitioning.
1076 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1078 * mips.igen (ADDI): Print immediate value.
1079 (BREAK): Print code.
1080 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1081 (SLL): Print "nop" specially, and don't run the code
1082 that does the shift for the "nop" case.
1084 2001-11-17 Fred Fish <fnf@redhat.com>
1086 * sim-main.h (float_operation): Move enum declaration outside
1087 of _sim_cpu struct declaration.
1089 2001-04-12 Jim Blandy <jimb@redhat.com>
1091 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1092 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1094 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1095 PENDING_FILL, and you can get the intended effect gracefully by
1096 calling PENDING_SCHED directly.
1098 2001-02-23 Ben Elliston <bje@redhat.com>
1100 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1101 already defined elsewhere.
1103 2001-02-19 Ben Elliston <bje@redhat.com>
1105 * sim-main.h (sim_monitor): Return an int.
1106 * interp.c (sim_monitor): Add return values.
1107 (signal_exception): Handle error conditions from sim_monitor.
1109 2001-02-08 Ben Elliston <bje@redhat.com>
1111 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1112 (store_memory): Likewise, pass cia to sim_core_write*.
1114 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1116 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1117 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1119 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1121 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1122 * Makefile.in: Don't delete *.igen when cleaning directory.
1124 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1126 * m16.igen (break): Call SignalException not sim_engine_halt.
1128 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1130 From Jason Eckhardt:
1131 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1133 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1135 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1137 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1139 * mips.igen (do_dmultx): Fix typo.
1141 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1143 * configure: Regenerated to track ../common/aclocal.m4 changes.
1145 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1147 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1149 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1151 * sim-main.h (GPR_CLEAR): Define macro.
1153 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1155 * interp.c (decode_coproc): Output long using %lx and not %s.
1157 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1159 * interp.c (sim_open): Sort & extend dummy memory regions for
1160 --board=jmr3904 for eCos.
1162 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1164 * configure: Regenerated.
1166 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1168 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1169 calls, conditional on the simulator being in verbose mode.
1171 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1173 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1174 cache don't get ReservedInstruction traps.
1176 1999-11-29 Mark Salter <msalter@cygnus.com>
1178 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1179 to clear status bits in sdisr register. This is how the hardware works.
1181 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1182 being used by cygmon.
1184 1999-11-11 Andrew Haley <aph@cygnus.com>
1186 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1189 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1191 * mips.igen (MULT): Correct previous mis-applied patch.
1193 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1195 * mips.igen (delayslot32): Handle sequence like
1196 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1197 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1198 (MULT): Actually pass the third register...
1200 1999-09-03 Mark Salter <msalter@cygnus.com>
1202 * interp.c (sim_open): Added more memory aliases for additional
1203 hardware being touched by cygmon on jmr3904 board.
1205 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1207 * configure: Regenerated to track ../common/aclocal.m4 changes.
1209 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1211 * interp.c (sim_store_register): Handle case where client - GDB -
1212 specifies that a 4 byte register is 8 bytes in size.
1213 (sim_fetch_register): Ditto.
1215 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1217 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1218 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1219 (idt_monitor_base): Base address for IDT monitor traps.
1220 (pmon_monitor_base): Ditto for PMON.
1221 (lsipmon_monitor_base): Ditto for LSI PMON.
1222 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1223 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1224 (sim_firmware_command): New function.
1225 (mips_option_handler): Call it for OPTION_FIRMWARE.
1226 (sim_open): Allocate memory for idt_monitor region. If "--board"
1227 option was given, add no monitor by default. Add BREAK hooks only if
1228 monitors are also there.
1230 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1232 * interp.c (sim_monitor): Flush output before reading input.
1234 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1236 * tconfig.in (SIM_HANDLES_LMA): Always define.
1238 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1240 From Mark Salter <msalter@cygnus.com>:
1241 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1242 (sim_open): Add setup for BSP board.
1244 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1246 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1247 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1248 them as unimplemented.
1250 1999-05-08 Felix Lee <flee@cygnus.com>
1252 * configure: Regenerated to track ../common/aclocal.m4 changes.
1254 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1256 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1258 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1260 * configure.in: Any mips64vr5*-*-* target should have
1261 -DTARGET_ENABLE_FR=1.
1262 (default_endian): Any mips64vr*el-*-* target should default to
1264 * configure: Re-generate.
1266 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1268 * mips.igen (ldl): Extend from _16_, not 32.
1270 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1272 * interp.c (sim_store_register): Force registers written to by GDB
1273 into an un-interpreted state.
1275 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1277 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1278 CPU, start periodic background I/O polls.
1279 (tx3904sio_poll): New function: periodic I/O poller.
1281 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1283 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1285 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1287 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1290 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1292 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1293 (load_word): Call SIM_CORE_SIGNAL hook on error.
1294 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1295 starting. For exception dispatching, pass PC instead of NULL_CIA.
1296 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1297 * sim-main.h (COP0_BADVADDR): Define.
1298 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1299 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1300 (_sim_cpu): Add exc_* fields to store register value snapshots.
1301 * mips.igen (*): Replace memory-related SignalException* calls
1302 with references to SIM_CORE_SIGNAL hook.
1304 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1306 * sim-main.c (*): Minor warning cleanups.
1308 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1310 * m16.igen (DADDIU5): Correct type-o.
1312 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1314 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1317 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1319 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1321 (interp.o): Add dependency on itable.h
1322 (oengine.c, gencode): Delete remaining references.
1323 (BUILT_SRC_FROM_GEN): Clean up.
1325 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1328 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1329 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1330 tmp-run-hack) : New.
1331 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1332 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1333 Drop the "64" qualifier to get the HACK generator working.
1334 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1335 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1336 qualifier to get the hack generator working.
1337 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1338 (DSLL): Use do_dsll.
1339 (DSLLV): Use do_dsllv.
1340 (DSRA): Use do_dsra.
1341 (DSRL): Use do_dsrl.
1342 (DSRLV): Use do_dsrlv.
1343 (BC1): Move *vr4100 to get the HACK generator working.
1344 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1345 get the HACK generator working.
1346 (MACC) Rename to get the HACK generator working.
1347 (DMACC,MACCS,DMACCS): Add the 64.
1349 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1351 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1352 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1354 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1356 * mips/interp.c (DEBUG): Cleanups.
1358 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1360 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1361 (tx3904sio_tickle): fflush after a stdout character output.
1363 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1365 * interp.c (sim_close): Uninstall modules.
1367 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1369 * sim-main.h, interp.c (sim_monitor): Change to global
1372 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1374 * configure.in (vr4100): Only include vr4100 instructions in
1376 * configure: Re-generate.
1377 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1379 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1381 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1382 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1385 * configure.in (sim_default_gen, sim_use_gen): Replace with
1387 (--enable-sim-igen): Delete config option. Always using IGEN.
1388 * configure: Re-generate.
1390 * Makefile.in (gencode): Kill, kill, kill.
1393 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1395 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1396 bit mips16 igen simulator.
1397 * configure: Re-generate.
1399 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1400 as part of vr4100 ISA.
1401 * vr.igen: Mark all instructions as 64 bit only.
1403 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1405 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1408 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1410 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1411 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1412 * configure: Re-generate.
1414 * m16.igen (BREAK): Define breakpoint instruction.
1415 (JALX32): Mark instruction as mips16 and not r3900.
1416 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1418 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1420 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1422 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1423 insn as a debug breakpoint.
1425 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1427 (PENDING_SCHED): Clean up trace statement.
1428 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1429 (PENDING_FILL): Delay write by only one cycle.
1430 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1432 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1434 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1436 (pending_tick): Move incrementing of index to FOR statement.
1437 (pending_tick): Only update PENDING_OUT after a write has occured.
1439 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1441 * configure: Re-generate.
1443 * interp.c (sim_engine_run OLD): Delete explicit call to
1444 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1446 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1448 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1449 interrupt level number to match changed SignalExceptionInterrupt
1452 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1454 * interp.c: #include "itable.h" if WITH_IGEN.
1455 (get_insn_name): New function.
1456 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1457 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1459 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1461 * configure: Rebuilt to inhale new common/aclocal.m4.
1463 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1465 * dv-tx3904sio.c: Include sim-assert.h.
1467 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1469 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1470 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1471 Reorganize target-specific sim-hardware checks.
1472 * configure: rebuilt.
1473 * interp.c (sim_open): For tx39 target boards, set
1474 OPERATING_ENVIRONMENT, add tx3904sio devices.
1475 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1476 ROM executables. Install dv-sockser into sim-modules list.
1478 * dv-tx3904irc.c: Compiler warning clean-up.
1479 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1480 frequent hw-trace messages.
1482 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1484 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1486 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1488 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1490 * vr.igen: New file.
1491 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1492 * mips.igen: Define vr4100 model. Include vr.igen.
1493 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1495 * mips.igen (check_mf_hilo): Correct check.
1497 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1499 * sim-main.h (interrupt_event): Add prototype.
1501 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1502 register_ptr, register_value.
1503 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1505 * sim-main.h (tracefh): Make extern.
1507 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1509 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1510 Reduce unnecessarily high timer event frequency.
1511 * dv-tx3904cpu.c: Ditto for interrupt event.
1513 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1515 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1517 (interrupt_event): Made non-static.
1519 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1520 interchange of configuration values for external vs. internal
1523 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1525 * mips.igen (BREAK): Moved code to here for
1526 simulator-reserved break instructions.
1527 * gencode.c (build_instruction): Ditto.
1528 * interp.c (signal_exception): Code moved from here. Non-
1529 reserved instructions now use exception vector, rather
1531 * sim-main.h: Moved magic constants to here.
1533 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1535 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1536 register upon non-zero interrupt event level, clear upon zero
1538 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1539 by passing zero event value.
1540 (*_io_{read,write}_buffer): Endianness fixes.
1541 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1542 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1544 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1545 serial I/O and timer module at base address 0xFFFF0000.
1547 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1549 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1552 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1554 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1556 * configure: Update.
1558 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1560 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1561 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1562 * configure.in: Include tx3904tmr in hw_device list.
1563 * configure: Rebuilt.
1564 * interp.c (sim_open): Instantiate three timer instances.
1565 Fix address typo of tx3904irc instance.
1567 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1569 * interp.c (signal_exception): SystemCall exception now uses
1570 the exception vector.
1572 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1574 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1577 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1579 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1581 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1583 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1585 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1586 sim-main.h. Declare a struct hw_descriptor instead of struct
1587 hw_device_descriptor.
1589 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1591 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1592 right bits and then re-align left hand bytes to correct byte
1593 lanes. Fix incorrect computation in do_store_left when loading
1594 bytes from second word.
1596 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1598 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1599 * interp.c (sim_open): Only create a device tree when HW is
1602 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1603 * interp.c (signal_exception): Ditto.
1605 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1607 * gencode.c: Mark BEGEZALL as LIKELY.
1609 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1611 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1612 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1614 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1616 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1617 modules. Recognize TX39 target with "mips*tx39" pattern.
1618 * configure: Rebuilt.
1619 * sim-main.h (*): Added many macros defining bits in
1620 TX39 control registers.
1621 (SignalInterrupt): Send actual PC instead of NULL.
1622 (SignalNMIReset): New exception type.
1623 * interp.c (board): New variable for future use to identify
1624 a particular board being simulated.
1625 (mips_option_handler,mips_options): Added "--board" option.
1626 (interrupt_event): Send actual PC.
1627 (sim_open): Make memory layout conditional on board setting.
1628 (signal_exception): Initial implementation of hardware interrupt
1629 handling. Accept another break instruction variant for simulator
1631 (decode_coproc): Implement RFE instruction for TX39.
1632 (mips.igen): Decode RFE instruction as such.
1633 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1634 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1635 bbegin to implement memory map.
1636 * dv-tx3904cpu.c: New file.
1637 * dv-tx3904irc.c: New file.
1639 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1641 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1643 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1645 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1646 with calls to check_div_hilo.
1648 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1650 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1651 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1652 Add special r3900 version of do_mult_hilo.
1653 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1654 with calls to check_mult_hilo.
1655 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1656 with calls to check_div_hilo.
1658 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1660 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1661 Document a replacement.
1663 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1665 * interp.c (sim_monitor): Make mon_printf work.
1667 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1669 * sim-main.h (INSN_NAME): New arg `cpu'.
1671 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1673 * configure: Regenerated to track ../common/aclocal.m4 changes.
1675 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1677 * configure: Regenerated to track ../common/aclocal.m4 changes.
1680 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1682 * acconfig.h: New file.
1683 * configure.in: Reverted change of Apr 24; use sinclude again.
1685 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1687 * configure: Regenerated to track ../common/aclocal.m4 changes.
1690 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1692 * configure.in: Don't call sinclude.
1694 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1696 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1698 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1700 * mips.igen (ERET): Implement.
1702 * interp.c (decode_coproc): Return sign-extended EPC.
1704 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1706 * interp.c (signal_exception): Do not ignore Trap.
1707 (signal_exception): On TRAP, restart at exception address.
1708 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1709 (signal_exception): Update.
1710 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1711 so that TRAP instructions are caught.
1713 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1715 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1716 contains HI/LO access history.
1717 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1718 (HIACCESS, LOACCESS): Delete, replace with
1719 (HIHISTORY, LOHISTORY): New macros.
1720 (CHECKHILO): Delete all, moved to mips.igen
1722 * gencode.c (build_instruction): Do not generate checks for
1723 correct HI/LO register usage.
1725 * interp.c (old_engine_run): Delete checks for correct HI/LO
1728 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1729 check_mf_cycles): New functions.
1730 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1731 do_divu, domultx, do_mult, do_multu): Use.
1733 * tx.igen ("madd", "maddu"): Use.
1735 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1737 * mips.igen (DSRAV): Use function do_dsrav.
1738 (SRAV): Use new function do_srav.
1740 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1741 (B): Sign extend 11 bit immediate.
1742 (EXT-B*): Shift 16 bit immediate left by 1.
1743 (ADDIU*): Don't sign extend immediate value.
1745 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1747 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1749 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1752 * mips.igen (delayslot32, nullify_next_insn): New functions.
1753 (m16.igen): Always include.
1754 (do_*): Add more tracing.
1756 * m16.igen (delayslot16): Add NIA argument, could be called by a
1757 32 bit MIPS16 instruction.
1759 * interp.c (ifetch16): Move function from here.
1760 * sim-main.c (ifetch16): To here.
1762 * sim-main.c (ifetch16, ifetch32): Update to match current
1763 implementations of LH, LW.
1764 (signal_exception): Don't print out incorrect hex value of illegal
1767 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1769 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1772 * m16.igen: Implement MIPS16 instructions.
1774 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1775 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1776 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1777 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1778 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1779 bodies of corresponding code from 32 bit insn to these. Also used
1780 by MIPS16 versions of functions.
1782 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1783 (IMEM16): Drop NR argument from macro.
1785 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1787 * Makefile.in (SIM_OBJS): Add sim-main.o.
1789 * sim-main.h (address_translation, load_memory, store_memory,
1790 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1792 (pr_addr, pr_uword64): Declare.
1793 (sim-main.c): Include when H_REVEALS_MODULE_P.
1795 * interp.c (address_translation, load_memory, store_memory,
1796 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1798 * sim-main.c: To here. Fix compilation problems.
1800 * configure.in: Enable inlining.
1801 * configure: Re-config.
1803 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1805 * configure: Regenerated to track ../common/aclocal.m4 changes.
1807 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1809 * mips.igen: Include tx.igen.
1810 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1811 * tx.igen: New file, contains MADD and MADDU.
1813 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1814 the hardwired constant `7'.
1815 (store_memory): Ditto.
1816 (LOADDRMASK): Move definition to sim-main.h.
1818 mips.igen (MTC0): Enable for r3900.
1821 mips.igen (do_load_byte): Delete.
1822 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1823 do_store_right): New functions.
1824 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1826 configure.in: Let the tx39 use igen again.
1829 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1831 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1832 not an address sized quantity. Return zero for cache sizes.
1834 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1836 * mips.igen (r3900): r3900 does not support 64 bit integer
1839 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1841 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1843 * configure : Rebuild.
1845 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1847 * configure: Regenerated to track ../common/aclocal.m4 changes.
1849 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1851 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1853 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1855 * configure: Regenerated to track ../common/aclocal.m4 changes.
1856 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1858 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1860 * configure: Regenerated to track ../common/aclocal.m4 changes.
1862 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1864 * interp.c (Max, Min): Comment out functions. Not yet used.
1866 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1868 * configure: Regenerated to track ../common/aclocal.m4 changes.
1870 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1872 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1873 configurable settings for stand-alone simulator.
1875 * configure.in: Added X11 search, just in case.
1877 * configure: Regenerated.
1879 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1881 * interp.c (sim_write, sim_read, load_memory, store_memory):
1882 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1884 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1886 * sim-main.h (GETFCC): Return an unsigned value.
1888 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1890 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1891 (DADD): Result destination is RD not RT.
1893 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1895 * sim-main.h (HIACCESS, LOACCESS): Always define.
1897 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1899 * interp.c (sim_info): Delete.
1901 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1903 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1904 (mips_option_handler): New argument `cpu'.
1905 (sim_open): Update call to sim_add_option_table.
1907 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1909 * mips.igen (CxC1): Add tracing.
1911 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1913 * sim-main.h (Max, Min): Declare.
1915 * interp.c (Max, Min): New functions.
1917 * mips.igen (BC1): Add tracing.
1919 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1921 * interp.c Added memory map for stack in vr4100
1923 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1925 * interp.c (load_memory): Add missing "break"'s.
1927 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1929 * interp.c (sim_store_register, sim_fetch_register): Pass in
1930 length parameter. Return -1.
1932 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1934 * interp.c: Added hardware init hook, fixed warnings.
1936 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1938 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1940 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1942 * interp.c (ifetch16): New function.
1944 * sim-main.h (IMEM32): Rename IMEM.
1945 (IMEM16_IMMED): Define.
1947 (DELAY_SLOT): Update.
1949 * m16run.c (sim_engine_run): New file.
1951 * m16.igen: All instructions except LB.
1952 (LB): Call do_load_byte.
1953 * mips.igen (do_load_byte): New function.
1954 (LB): Call do_load_byte.
1956 * mips.igen: Move spec for insn bit size and high bit from here.
1957 * Makefile.in (tmp-igen, tmp-m16): To here.
1959 * m16.dc: New file, decode mips16 instructions.
1961 * Makefile.in (SIM_NO_ALL): Define.
1962 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1964 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1966 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1967 point unit to 32 bit registers.
1968 * configure: Re-generate.
1970 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1972 * configure.in (sim_use_gen): Make IGEN the default simulator
1973 generator for generic 32 and 64 bit mips targets.
1974 * configure: Re-generate.
1976 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1978 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1981 * interp.c (sim_fetch_register, sim_store_register): Read/write
1982 FGR from correct location.
1983 (sim_open): Set size of FGR's according to
1984 WITH_TARGET_FLOATING_POINT_BITSIZE.
1986 * sim-main.h (FGR): Store floating point registers in a separate
1989 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1991 * configure: Regenerated to track ../common/aclocal.m4 changes.
1993 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1995 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1997 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1999 * interp.c (pending_tick): New function. Deliver pending writes.
2001 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2002 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2003 it can handle mixed sized quantites and single bits.
2005 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2007 * interp.c (oengine.h): Do not include when building with IGEN.
2008 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2009 (sim_info): Ditto for PROCESSOR_64BIT.
2010 (sim_monitor): Replace ut_reg with unsigned_word.
2011 (*): Ditto for t_reg.
2012 (LOADDRMASK): Define.
2013 (sim_open): Remove defunct check that host FP is IEEE compliant,
2014 using software to emulate floating point.
2015 (value_fpr, ...): Always compile, was conditional on HASFPU.
2017 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2019 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2022 * interp.c (SD, CPU): Define.
2023 (mips_option_handler): Set flags in each CPU.
2024 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2025 (sim_close): Do not clear STATE, deleted anyway.
2026 (sim_write, sim_read): Assume CPU zero's vm should be used for
2028 (sim_create_inferior): Set the PC for all processors.
2029 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2031 (mips16_entry): Pass correct nr of args to store_word, load_word.
2032 (ColdReset): Cold reset all cpu's.
2033 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2034 (sim_monitor, load_memory, store_memory, signal_exception): Use
2035 `CPU' instead of STATE_CPU.
2038 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2041 * sim-main.h (signal_exception): Add sim_cpu arg.
2042 (SignalException*): Pass both SD and CPU to signal_exception.
2043 * interp.c (signal_exception): Update.
2045 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2047 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2048 address_translation): Ditto
2049 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2051 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2053 * configure: Regenerated to track ../common/aclocal.m4 changes.
2055 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2057 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2059 * mips.igen (model): Map processor names onto BFD name.
2061 * sim-main.h (CPU_CIA): Delete.
2062 (SET_CIA, GET_CIA): Define
2064 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2066 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2069 * configure.in (default_endian): Configure a big-endian simulator
2071 * configure: Re-generate.
2073 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2075 * configure: Regenerated to track ../common/aclocal.m4 changes.
2077 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2079 * interp.c (sim_monitor): Handle Densan monitor outbyte
2080 and inbyte functions.
2082 1997-12-29 Felix Lee <flee@cygnus.com>
2084 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2086 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2088 * Makefile.in (tmp-igen): Arrange for $zero to always be
2089 reset to zero after every instruction.
2091 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2093 * configure: Regenerated to track ../common/aclocal.m4 changes.
2096 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2098 * mips.igen (MSUB): Fix to work like MADD.
2099 * gencode.c (MSUB): Similarly.
2101 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2103 * configure: Regenerated to track ../common/aclocal.m4 changes.
2105 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2107 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2109 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2111 * sim-main.h (sim-fpu.h): Include.
2113 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2114 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2115 using host independant sim_fpu module.
2117 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2119 * interp.c (signal_exception): Report internal errors with SIGABRT
2122 * sim-main.h (C0_CONFIG): New register.
2123 (signal.h): No longer include.
2125 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2127 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2129 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2131 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2133 * mips.igen: Tag vr5000 instructions.
2134 (ANDI): Was missing mipsIV model, fix assembler syntax.
2135 (do_c_cond_fmt): New function.
2136 (C.cond.fmt): Handle mips I-III which do not support CC field
2138 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2139 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2141 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2142 vr5000 which saves LO in a GPR separatly.
2144 * configure.in (enable-sim-igen): For vr5000, select vr5000
2145 specific instructions.
2146 * configure: Re-generate.
2148 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2150 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2152 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2153 fmt_uninterpreted_64 bit cases to switch. Convert to
2156 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2158 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2159 as specified in IV3.2 spec.
2160 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2162 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2164 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2165 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2166 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2167 PENDING_FILL versions of instructions. Simplify.
2169 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2171 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2173 (MTHI, MFHI): Disable code checking HI-LO.
2175 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2177 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2179 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2181 * gencode.c (build_mips16_operands): Replace IPC with cia.
2183 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2184 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2186 (UndefinedResult): Replace function with macro/function
2188 (sim_engine_run): Don't save PC in IPC.
2190 * sim-main.h (IPC): Delete.
2193 * interp.c (signal_exception, store_word, load_word,
2194 address_translation, load_memory, store_memory, cache_op,
2195 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2196 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2197 current instruction address - cia - argument.
2198 (sim_read, sim_write): Call address_translation directly.
2199 (sim_engine_run): Rename variable vaddr to cia.
2200 (signal_exception): Pass cia to sim_monitor
2202 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2203 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2204 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2206 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2207 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2210 * interp.c (signal_exception): Pass restart address to
2213 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2214 idecode.o): Add dependency.
2216 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2218 (DELAY_SLOT): Update NIA not PC with branch address.
2219 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2221 * mips.igen: Use CIA not PC in branch calculations.
2222 (illegal): Call SignalException.
2223 (BEQ, ADDIU): Fix assembler.
2225 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2227 * m16.igen (JALX): Was missing.
2229 * configure.in (enable-sim-igen): New configuration option.
2230 * configure: Re-generate.
2232 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2234 * interp.c (load_memory, store_memory): Delete parameter RAW.
2235 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2236 bypassing {load,store}_memory.
2238 * sim-main.h (ByteSwapMem): Delete definition.
2240 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2242 * interp.c (sim_do_command, sim_commands): Delete mips specific
2243 commands. Handled by module sim-options.
2245 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2246 (WITH_MODULO_MEMORY): Define.
2248 * interp.c (sim_info): Delete code printing memory size.
2250 * interp.c (mips_size): Nee sim_size, delete function.
2252 (monitor, monitor_base, monitor_size): Delete global variables.
2253 (sim_open, sim_close): Delete code creating monitor and other
2254 memory regions. Use sim-memopts module, via sim_do_commandf, to
2255 manage memory regions.
2256 (load_memory, store_memory): Use sim-core for memory model.
2258 * interp.c (address_translation): Delete all memory map code
2259 except line forcing 32 bit addresses.
2261 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2263 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2266 * interp.c (logfh, logfile): Delete globals.
2267 (sim_open, sim_close): Delete code opening & closing log file.
2268 (mips_option_handler): Delete -l and -n options.
2269 (OPTION mips_options): Ditto.
2271 * interp.c (OPTION mips_options): Rename option trace to dinero.
2272 (mips_option_handler): Update.
2274 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2276 * interp.c (fetch_str): New function.
2277 (sim_monitor): Rewrite using sim_read & sim_write.
2278 (sim_open): Check magic number.
2279 (sim_open): Write monitor vectors into memory using sim_write.
2280 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2281 (sim_read, sim_write): Simplify - transfer data one byte at a
2283 (load_memory, store_memory): Clarify meaning of parameter RAW.
2285 * sim-main.h (isHOST): Defete definition.
2286 (isTARGET): Mark as depreciated.
2287 (address_translation): Delete parameter HOST.
2289 * interp.c (address_translation): Delete parameter HOST.
2291 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2295 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2296 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2298 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2300 * mips.igen: Add model filter field to records.
2302 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2304 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2306 interp.c (sim_engine_run): Do not compile function sim_engine_run
2307 when WITH_IGEN == 1.
2309 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2310 target architecture.
2312 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2313 igen. Replace with configuration variables sim_igen_flags /
2316 * m16.igen: New file. Copy mips16 insns here.
2317 * mips.igen: From here.
2319 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2321 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2323 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2325 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2327 * gencode.c (build_instruction): Follow sim_write's lead in using
2328 BigEndianMem instead of !ByteSwapMem.
2330 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2332 * configure.in (sim_gen): Dependent on target, select type of
2333 generator. Always select old style generator.
2335 configure: Re-generate.
2337 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2339 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2340 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2341 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2342 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2343 SIM_@sim_gen@_*, set by autoconf.
2345 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2347 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2349 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2350 CURRENT_FLOATING_POINT instead.
2352 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2353 (address_translation): Raise exception InstructionFetch when
2354 translation fails and isINSTRUCTION.
2356 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2357 sim_engine_run): Change type of of vaddr and paddr to
2359 (address_translation, prefetch, load_memory, store_memory,
2360 cache_op): Change type of vAddr and pAddr to address_word.
2362 * gencode.c (build_instruction): Change type of vaddr and paddr to
2365 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2367 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2368 macro to obtain result of ALU op.
2370 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2372 * interp.c (sim_info): Call profile_print.
2374 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2376 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2378 * sim-main.h (WITH_PROFILE): Do not define, defined in
2379 common/sim-config.h. Use sim-profile module.
2380 (simPROFILE): Delete defintion.
2382 * interp.c (PROFILE): Delete definition.
2383 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2384 (sim_close): Delete code writing profile histogram.
2385 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2387 (sim_engine_run): Delete code profiling the PC.
2389 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2391 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2393 * interp.c (sim_monitor): Make register pointers of type
2396 * sim-main.h: Make registers of type unsigned_word not
2399 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2401 * interp.c (sync_operation): Rename from SyncOperation, make
2402 global, add SD argument.
2403 (prefetch): Rename from Prefetch, make global, add SD argument.
2404 (decode_coproc): Make global.
2406 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2408 * gencode.c (build_instruction): Generate DecodeCoproc not
2409 decode_coproc calls.
2411 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2412 (SizeFGR): Move to sim-main.h
2413 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2414 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2415 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2417 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2418 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2419 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2420 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2421 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2422 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2424 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2426 (sim-alu.h): Include.
2427 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2428 (sim_cia): Typedef to instruction_address.
2430 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2432 * Makefile.in (interp.o): Rename generated file engine.c to
2437 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2439 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2441 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2443 * gencode.c (build_instruction): For "FPSQRT", output correct
2444 number of arguments to Recip.
2446 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2448 * Makefile.in (interp.o): Depends on sim-main.h
2450 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2452 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2453 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2454 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2455 STATE, DSSTATE): Define
2456 (GPR, FGRIDX, ..): Define.
2458 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2459 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2460 (GPR, FGRIDX, ...): Delete macros.
2462 * interp.c: Update names to match defines from sim-main.h
2464 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2466 * interp.c (sim_monitor): Add SD argument.
2467 (sim_warning): Delete. Replace calls with calls to
2469 (sim_error): Delete. Replace calls with sim_io_error.
2470 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2471 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2472 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2474 (mips_size): Rename from sim_size. Add SD argument.
2476 * interp.c (simulator): Delete global variable.
2477 (callback): Delete global variable.
2478 (mips_option_handler, sim_open, sim_write, sim_read,
2479 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2480 sim_size,sim_monitor): Use sim_io_* not callback->*.
2481 (sim_open): ZALLOC simulator struct.
2482 (PROFILE): Do not define.
2484 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2486 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2487 support.h with corresponding code.
2489 * sim-main.h (word64, uword64), support.h: Move definition to
2491 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2494 * Makefile.in: Update dependencies
2495 * interp.c: Do not include.
2497 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2499 * interp.c (address_translation, load_memory, store_memory,
2500 cache_op): Rename to from AddressTranslation et.al., make global,
2503 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2506 * interp.c (SignalException): Rename to signal_exception, make
2509 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2511 * sim-main.h (SignalException, SignalExceptionInterrupt,
2512 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2513 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2514 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2517 * interp.c, support.h: Use.
2519 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2521 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2522 to value_fpr / store_fpr. Add SD argument.
2523 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2524 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2526 * sim-main.h (ValueFPR, StoreFPR): Define.
2528 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2530 * interp.c (sim_engine_run): Check consistency between configure
2531 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2534 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2535 (mips_fpu): Configure WITH_FLOATING_POINT.
2536 (mips_endian): Configure WITH_TARGET_ENDIAN.
2537 * configure: Update.
2539 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2541 * configure: Regenerated to track ../common/aclocal.m4 changes.
2543 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2545 * configure: Regenerated.
2547 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2549 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2551 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2553 * gencode.c (print_igen_insn_models): Assume certain architectures
2554 include all mips* instructions.
2555 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2558 * Makefile.in (tmp.igen): Add target. Generate igen input from
2561 * gencode.c (FEATURE_IGEN): Define.
2562 (main): Add --igen option. Generate output in igen format.
2563 (process_instructions): Format output according to igen option.
2564 (print_igen_insn_format): New function.
2565 (print_igen_insn_models): New function.
2566 (process_instructions): Only issue warnings and ignore
2567 instructions when no FEATURE_IGEN.
2569 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2571 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2574 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2576 * configure: Regenerated to track ../common/aclocal.m4 changes.
2578 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2580 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2581 SIM_RESERVED_BITS): Delete, moved to common.
2582 (SIM_EXTRA_CFLAGS): Update.
2584 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2586 * configure.in: Configure non-strict memory alignment.
2587 * configure: Regenerated to track ../common/aclocal.m4 changes.
2589 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2591 * configure: Regenerated to track ../common/aclocal.m4 changes.
2593 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2595 * gencode.c (SDBBP,DERET): Added (3900) insns.
2596 (RFE): Turn on for 3900.
2597 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2598 (dsstate): Made global.
2599 (SUBTARGET_R3900): Added.
2600 (CANCELDELAYSLOT): New.
2601 (SignalException): Ignore SystemCall rather than ignore and
2602 terminate. Add DebugBreakPoint handling.
2603 (decode_coproc): New insns RFE, DERET; and new registers Debug
2604 and DEPC protected by SUBTARGET_R3900.
2605 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2607 * Makefile.in,configure.in: Add mips subtarget option.
2608 * configure: Update.
2610 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2612 * gencode.c: Add r3900 (tx39).
2615 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2617 * gencode.c (build_instruction): Don't need to subtract 4 for
2620 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2622 * interp.c: Correct some HASFPU problems.
2624 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2626 * configure: Regenerated to track ../common/aclocal.m4 changes.
2628 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2630 * interp.c (mips_options): Fix samples option short form, should
2633 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2635 * interp.c (sim_info): Enable info code. Was just returning.
2637 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2639 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2642 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2644 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2646 (build_instruction): Ditto for LL.
2648 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2650 * configure: Regenerated to track ../common/aclocal.m4 changes.
2652 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2654 * configure: Regenerated to track ../common/aclocal.m4 changes.
2657 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2659 * interp.c (sim_open): Add call to sim_analyze_program, update
2662 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2664 * interp.c (sim_kill): Delete.
2665 (sim_create_inferior): Add ABFD argument. Set PC from same.
2666 (sim_load): Move code initializing trap handlers from here.
2667 (sim_open): To here.
2668 (sim_load): Delete, use sim-hload.c.
2670 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2672 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2674 * configure: Regenerated to track ../common/aclocal.m4 changes.
2677 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2679 * interp.c (sim_open): Add ABFD argument.
2680 (sim_load): Move call to sim_config from here.
2681 (sim_open): To here. Check return status.
2683 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2685 * gencode.c (build_instruction): Two arg MADD should
2686 not assign result to $0.
2688 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2690 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2691 * sim/mips/configure.in: Regenerate.
2693 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2695 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2696 signed8, unsigned8 et.al. types.
2698 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2699 hosts when selecting subreg.
2701 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2703 * interp.c (sim_engine_run): Reset the ZERO register to zero
2704 regardless of FEATURE_WARN_ZERO.
2705 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2707 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2709 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2710 (SignalException): For BreakPoints ignore any mode bits and just
2712 (SignalException): Always set the CAUSE register.
2714 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2716 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2717 exception has been taken.
2719 * interp.c: Implement the ERET and mt/f sr instructions.
2721 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2723 * interp.c (SignalException): Don't bother restarting an
2726 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2728 * interp.c (SignalException): Really take an interrupt.
2729 (interrupt_event): Only deliver interrupts when enabled.
2731 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2733 * interp.c (sim_info): Only print info when verbose.
2734 (sim_info) Use sim_io_printf for output.
2736 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2738 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2741 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2743 * interp.c (sim_do_command): Check for common commands if a
2744 simulator specific command fails.
2746 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2748 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2749 and simBE when DEBUG is defined.
2751 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2753 * interp.c (interrupt_event): New function. Pass exception event
2754 onto exception handler.
2756 * configure.in: Check for stdlib.h.
2757 * configure: Regenerate.
2759 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2760 variable declaration.
2761 (build_instruction): Initialize memval1.
2762 (build_instruction): Add UNUSED attribute to byte, bigend,
2764 (build_operands): Ditto.
2766 * interp.c: Fix GCC warnings.
2767 (sim_get_quit_code): Delete.
2769 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2770 * Makefile.in: Ditto.
2771 * configure: Re-generate.
2773 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2775 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2777 * interp.c (mips_option_handler): New function parse argumes using
2779 (myname): Replace with STATE_MY_NAME.
2780 (sim_open): Delete check for host endianness - performed by
2782 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2783 (sim_open): Move much of the initialization from here.
2784 (sim_load): To here. After the image has been loaded and
2786 (sim_open): Move ColdReset from here.
2787 (sim_create_inferior): To here.
2788 (sim_open): Make FP check less dependant on host endianness.
2790 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2792 * interp.c (sim_set_callbacks): Delete.
2794 * interp.c (membank, membank_base, membank_size): Replace with
2795 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2796 (sim_open): Remove call to callback->init. gdb/run do this.
2800 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2802 * interp.c (big_endian_p): Delete, replaced by
2803 current_target_byte_order.
2805 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2807 * interp.c (host_read_long, host_read_word, host_swap_word,
2808 host_swap_long): Delete. Using common sim-endian.
2809 (sim_fetch_register, sim_store_register): Use H2T.
2810 (pipeline_ticks): Delete. Handled by sim-events.
2812 (sim_engine_run): Update.
2814 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2816 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2818 (SignalException): To here. Signal using sim_engine_halt.
2819 (sim_stop_reason): Delete, moved to common.
2821 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2823 * interp.c (sim_open): Add callback argument.
2824 (sim_set_callbacks): Delete SIM_DESC argument.
2827 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2829 * Makefile.in (SIM_OBJS): Add common modules.
2831 * interp.c (sim_set_callbacks): Also set SD callback.
2832 (set_endianness, xfer_*, swap_*): Delete.
2833 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2834 Change to functions using sim-endian macros.
2835 (control_c, sim_stop): Delete, use common version.
2836 (simulate): Convert into.
2837 (sim_engine_run): This function.
2838 (sim_resume): Delete.
2840 * interp.c (simulation): New variable - the simulator object.
2841 (sim_kind): Delete global - merged into simulation.
2842 (sim_load): Cleanup. Move PC assignment from here.
2843 (sim_create_inferior): To here.
2845 * sim-main.h: New file.
2846 * interp.c (sim-main.h): Include.
2848 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2850 * configure: Regenerated to track ../common/aclocal.m4 changes.
2852 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2854 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2856 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2858 * gencode.c (build_instruction): DIV instructions: check
2859 for division by zero and integer overflow before using
2860 host's division operation.
2862 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2864 * Makefile.in (SIM_OBJS): Add sim-load.o.
2865 * interp.c: #include bfd.h.
2866 (target_byte_order): Delete.
2867 (sim_kind, myname, big_endian_p): New static locals.
2868 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2869 after argument parsing. Recognize -E arg, set endianness accordingly.
2870 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2871 load file into simulator. Set PC from bfd.
2872 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2873 (set_endianness): Use big_endian_p instead of target_byte_order.
2875 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2877 * interp.c (sim_size): Delete prototype - conflicts with
2878 definition in remote-sim.h. Correct definition.
2880 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2882 * configure: Regenerated to track ../common/aclocal.m4 changes.
2885 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2887 * interp.c (sim_open): New arg `kind'.
2889 * configure: Regenerated to track ../common/aclocal.m4 changes.
2891 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2893 * configure: Regenerated to track ../common/aclocal.m4 changes.
2895 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2897 * interp.c (sim_open): Set optind to 0 before calling getopt.
2899 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2901 * configure: Regenerated to track ../common/aclocal.m4 changes.
2903 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2905 * interp.c : Replace uses of pr_addr with pr_uword64
2906 where the bit length is always 64 independent of SIM_ADDR.
2907 (pr_uword64) : added.
2909 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2911 * configure: Re-generate.
2913 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2915 * configure: Regenerate to track ../common/aclocal.m4 changes.
2917 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2919 * interp.c (sim_open): New SIM_DESC result. Argument is now
2921 (other sim_*): New SIM_DESC argument.
2923 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2925 * interp.c: Fix printing of addresses for non-64-bit targets.
2926 (pr_addr): Add function to print address based on size.
2928 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2930 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2932 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2934 * gencode.c (build_mips16_operands): Correct computation of base
2935 address for extended PC relative instruction.
2937 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2939 * interp.c (mips16_entry): Add support for floating point cases.
2940 (SignalException): Pass floating point cases to mips16_entry.
2941 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2943 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2945 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2946 and then set the state to fmt_uninterpreted.
2947 (COP_SW): Temporarily set the state to fmt_word while calling
2950 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2952 * gencode.c (build_instruction): The high order may be set in the
2953 comparison flags at any ISA level, not just ISA 4.
2955 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2957 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2958 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2959 * configure.in: sinclude ../common/aclocal.m4.
2960 * configure: Regenerated.
2962 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2964 * configure: Rebuild after change to aclocal.m4.
2966 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2968 * configure configure.in Makefile.in: Update to new configure
2969 scheme which is more compatible with WinGDB builds.
2970 * configure.in: Improve comment on how to run autoconf.
2971 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2972 * Makefile.in: Use autoconf substitution to install common
2975 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2977 * gencode.c (build_instruction): Use BigEndianCPU instead of
2980 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2982 * interp.c (sim_monitor): Make output to stdout visible in
2983 wingdb's I/O log window.
2985 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2987 * support.h: Undo previous change to SIGTRAP
2990 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2992 * interp.c (store_word, load_word): New static functions.
2993 (mips16_entry): New static function.
2994 (SignalException): Look for mips16 entry and exit instructions.
2995 (simulate): Use the correct index when setting fpr_state after
2996 doing a pending move.
2998 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3000 * interp.c: Fix byte-swapping code throughout to work on
3001 both little- and big-endian hosts.
3003 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3005 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3006 with gdb/config/i386/xm-windows.h.
3008 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3010 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3011 that messes up arithmetic shifts.
3013 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3015 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3016 SIGTRAP and SIGQUIT for _WIN32.
3018 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3020 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3021 force a 64 bit multiplication.
3022 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3023 destination register is 0, since that is the default mips16 nop
3026 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3028 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3029 (build_endian_shift): Don't check proc64.
3030 (build_instruction): Always set memval to uword64. Cast op2 to
3031 uword64 when shifting it left in memory instructions. Always use
3032 the same code for stores--don't special case proc64.
3034 * gencode.c (build_mips16_operands): Fix base PC value for PC
3036 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3038 * interp.c (simJALDELAYSLOT): Define.
3039 (JALDELAYSLOT): Define.
3040 (INDELAYSLOT, INJALDELAYSLOT): Define.
3041 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3043 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3045 * interp.c (sim_open): add flush_cache as a PMON routine
3046 (sim_monitor): handle flush_cache by ignoring it
3048 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3050 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3052 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3053 (BigEndianMem): Rename to ByteSwapMem and change sense.
3054 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3055 BigEndianMem references to !ByteSwapMem.
3056 (set_endianness): New function, with prototype.
3057 (sim_open): Call set_endianness.
3058 (sim_info): Use simBE instead of BigEndianMem.
3059 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3060 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3061 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3062 ifdefs, keeping the prototype declaration.
3063 (swap_word): Rewrite correctly.
3064 (ColdReset): Delete references to CONFIG. Delete endianness related
3065 code; moved to set_endianness.
3067 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3069 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3070 * interp.c (CHECKHILO): Define away.
3071 (simSIGINT): New macro.
3072 (membank_size): Increase from 1MB to 2MB.
3073 (control_c): New function.
3074 (sim_resume): Rename parameter signal to signal_number. Add local
3075 variable prev. Call signal before and after simulate.
3076 (sim_stop_reason): Add simSIGINT support.
3077 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3079 (sim_warning): Delete call to SignalException. Do call printf_filtered
3081 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3082 a call to sim_warning.
3084 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3086 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3087 16 bit instructions.
3089 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3091 Add support for mips16 (16 bit MIPS implementation):
3092 * gencode.c (inst_type): Add mips16 instruction encoding types.
3093 (GETDATASIZEINSN): Define.
3094 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3095 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3097 (MIPS16_DECODE): New table, for mips16 instructions.
3098 (bitmap_val): New static function.
3099 (struct mips16_op): Define.
3100 (mips16_op_table): New table, for mips16 operands.
3101 (build_mips16_operands): New static function.
3102 (process_instructions): If PC is odd, decode a mips16
3103 instruction. Break out instruction handling into new
3104 build_instruction function.
3105 (build_instruction): New static function, broken out of
3106 process_instructions. Check modifiers rather than flags for SHIFT
3107 bit count and m[ft]{hi,lo} direction.
3108 (usage): Pass program name to fprintf.
3109 (main): Remove unused variable this_option_optind. Change
3110 ``*loptarg++'' to ``loptarg++''.
3111 (my_strtoul): Parenthesize && within ||.
3112 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3113 (simulate): If PC is odd, fetch a 16 bit instruction, and
3114 increment PC by 2 rather than 4.
3115 * configure.in: Add case for mips16*-*-*.
3116 * configure: Rebuild.
3118 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3120 * interp.c: Allow -t to enable tracing in standalone simulator.
3121 Fix garbage output in trace file and error messages.
3123 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3125 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3126 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3127 * configure.in: Simplify using macros in ../common/aclocal.m4.
3128 * configure: Regenerated.
3129 * tconfig.in: New file.
3131 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3133 * interp.c: Fix bugs in 64-bit port.
3134 Use ansi function declarations for msvc compiler.
3135 Initialize and test file pointer in trace code.
3136 Prevent duplicate definition of LAST_EMED_REGNUM.
3138 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3140 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3142 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3144 * interp.c (SignalException): Check for explicit terminating
3146 * gencode.c: Pass instruction value through SignalException()
3147 calls for Trap, Breakpoint and Syscall.
3149 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3151 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3152 only used on those hosts that provide it.
3153 * configure.in: Add sqrt() to list of functions to be checked for.
3154 * config.in: Re-generated.
3155 * configure: Re-generated.
3157 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3159 * gencode.c (process_instructions): Call build_endian_shift when
3160 expanding STORE RIGHT, to fix swr.
3161 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3162 clear the high bits.
3163 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3164 Fix float to int conversions to produce signed values.
3166 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3168 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3169 (process_instructions): Correct handling of nor instruction.
3170 Correct shift count for 32 bit shift instructions. Correct sign
3171 extension for arithmetic shifts to not shift the number of bits in
3172 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3173 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3175 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3176 It's OK to have a mult follow a mult. What's not OK is to have a
3177 mult follow an mfhi.
3178 (Convert): Comment out incorrect rounding code.
3180 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3182 * interp.c (sim_monitor): Improved monitor printf
3183 simulation. Tidied up simulator warnings, and added "--log" option
3184 for directing warning message output.
3185 * gencode.c: Use sim_warning() rather than WARNING macro.
3187 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3189 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3190 getopt1.o, rather than on gencode.c. Link objects together.
3191 Don't link against -liberty.
3192 (gencode.o, getopt.o, getopt1.o): New targets.
3193 * gencode.c: Include <ctype.h> and "ansidecl.h".
3194 (AND): Undefine after including "ansidecl.h".
3195 (ULONG_MAX): Define if not defined.
3196 (OP_*): Don't define macros; now defined in opcode/mips.h.
3197 (main): Call my_strtoul rather than strtoul.
3198 (my_strtoul): New static function.
3200 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3202 * gencode.c (process_instructions): Generate word64 and uword64
3203 instead of `long long' and `unsigned long long' data types.
3204 * interp.c: #include sysdep.h to get signals, and define default
3206 * (Convert): Work around for Visual-C++ compiler bug with type
3208 * support.h: Make things compile under Visual-C++ by using
3209 __int64 instead of `long long'. Change many refs to long long
3210 into word64/uword64 typedefs.
3212 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3214 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3215 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3217 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3218 (AC_PROG_INSTALL): Added.
3219 (AC_PROG_CC): Moved to before configure.host call.
3220 * configure: Rebuilt.
3222 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3224 * configure.in: Define @SIMCONF@ depending on mips target.
3225 * configure: Rebuild.
3226 * Makefile.in (run): Add @SIMCONF@ to control simulator
3228 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3229 * interp.c: Remove some debugging, provide more detailed error
3230 messages, update memory accesses to use LOADDRMASK.
3232 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3234 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3235 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3237 * configure: Rebuild.
3238 * config.in: New file, generated by autoheader.
3239 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3240 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3241 HAVE_ANINT and HAVE_AINT, as appropriate.
3242 * Makefile.in (run): Use @LIBS@ rather than -lm.
3243 (interp.o): Depend upon config.h.
3244 (Makefile): Just rebuild Makefile.
3245 (clean): Remove stamp-h.
3246 (mostlyclean): Make the same as clean, not as distclean.
3247 (config.h, stamp-h): New targets.
3249 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3251 * interp.c (ColdReset): Fix boolean test. Make all simulator
3254 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3256 * interp.c (xfer_direct_word, xfer_direct_long,
3257 swap_direct_word, swap_direct_long, xfer_big_word,
3258 xfer_big_long, xfer_little_word, xfer_little_long,
3259 swap_word,swap_long): Added.
3260 * interp.c (ColdReset): Provide function indirection to
3261 host<->simulated_target transfer routines.
3262 * interp.c (sim_store_register, sim_fetch_register): Updated to
3263 make use of indirected transfer routines.
3265 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3267 * gencode.c (process_instructions): Ensure FP ABS instruction
3269 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3270 system call support.
3272 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3274 * interp.c (sim_do_command): Complain if callback structure not
3277 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3279 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3280 support for Sun hosts.
3281 * Makefile.in (gencode): Ensure the host compiler and libraries
3282 used for cross-hosted build.
3284 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3286 * interp.c, gencode.c: Some more (TODO) tidying.
3288 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3290 * gencode.c, interp.c: Replaced explicit long long references with
3291 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3292 * support.h (SET64LO, SET64HI): Macros added.
3294 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3296 * configure: Regenerate with autoconf 2.7.
3298 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3300 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3301 * support.h: Remove superfluous "1" from #if.
3302 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3304 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3306 * interp.c (StoreFPR): Control UndefinedResult() call on
3307 WARN_RESULT manifest.
3309 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3311 * gencode.c: Tidied instruction decoding, and added FP instruction
3314 * interp.c: Added dineroIII, and BSD profiling support. Also
3315 run-time FP handling.
3317 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3319 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3320 gencode.c, interp.c, support.h: created.