1 2007-02-19 Thiemo Seufer <ths@mips.com>
2 Nigel Stephens <nigel@mips.com>
4 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
7 2007-02-17 Thiemo Seufer <ths@mips.com>
9 * configure.ac (mips*-sde-elf*): Move in front of generic machine
11 * configure: Regenerate.
13 2007-02-17 Thiemo Seufer <ths@mips.com>
15 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
16 Add mdmx to sim_igen_machine.
17 (mipsisa64*-*-*): Likewise. Remove dsp.
18 (mipsisa32*-*-*): Remove dsp.
19 * configure: Regenerate.
21 2007-02-13 Thiemo Seufer <ths@mips.com>
23 * configure.ac: Add mips*-sde-elf* target.
24 * configure: Regenerate.
26 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
29 * config.in, configure: Regenerate.
31 2006-11-07 Thiemo Seufer <ths@mips.com>
33 * dsp.igen (do_w_op): Fix compiler warning.
35 2006-08-29 Thiemo Seufer <ths@mips.com>
36 David Ung <davidu@mips.com>
38 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
40 * configure: Regenerate.
41 * mips.igen (model): Add smartmips.
42 (MADDU): Increment ACX if carry.
44 (ROR,RORV): Add smartmips.
45 (include): Include smartmips.igen.
46 * sim-main.h (ACX): Set to REGISTERS[89].
47 * smartmips.igen: New file.
49 2006-08-29 Thiemo Seufer <ths@mips.com>
50 David Ung <davidu@mips.com>
52 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
53 mips3264r2.igen. Add missing dependency rules.
54 * m16e.igen: Support for mips16e save/restore instructions.
56 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
58 * configure: Regenerated.
60 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
62 * configure: Regenerated.
64 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
66 * configure: Regenerated.
68 2006-05-15 Chao-ying Fu <fu@mips.com>
70 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
72 2006-04-18 Nick Clifton <nickc@redhat.com>
74 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
77 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
79 * configure: Regenerate.
81 2005-12-14 Chao-ying Fu <fu@mips.com>
83 * Makefile.in (SIM_OBJS): Add dsp.o.
84 (dsp.o): New dependency.
85 (IGEN_INCLUDE): Add dsp.igen.
86 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
87 mipsisa64*-*-*): Add dsp to sim_igen_machine.
88 * configure: Regenerate.
89 * mips.igen: Add dsp model and include dsp.igen.
90 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
91 because these instructions are extended in DSP ASE.
92 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
93 adding 6 DSP accumulator registers and 1 DSP control register.
94 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
95 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
96 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
97 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
98 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
99 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
100 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
101 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
102 DSPCR_CCOND_SMASK): New define.
103 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
104 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
106 2005-07-08 Ian Lance Taylor <ian@airs.com>
108 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
110 2005-06-16 David Ung <davidu@mips.com>
111 Nigel Stephens <nigel@mips.com>
113 * mips.igen: New mips16e model and include m16e.igen.
114 (check_u64): Add mips16e tag.
115 * m16e.igen: New file for MIPS16e instructions.
116 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
117 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
119 * configure: Regenerate.
121 2005-05-26 David Ung <davidu@mips.com>
123 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
124 tags to all instructions which are applicable to the new ISAs.
125 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
127 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
129 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
131 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
132 * configure: Regenerate.
134 2005-03-23 Mark Kettenis <kettenis@gnu.org>
136 * configure: Regenerate.
138 2005-01-14 Andrew Cagney <cagney@gnu.org>
140 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
141 explicit call to AC_CONFIG_HEADER.
142 * configure: Regenerate.
144 2005-01-12 Andrew Cagney <cagney@gnu.org>
146 * configure.ac: Update to use ../common/common.m4.
147 * configure: Re-generate.
149 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
151 * configure: Regenerated to track ../common/aclocal.m4 changes.
153 2005-01-07 Andrew Cagney <cagney@gnu.org>
155 * configure.ac: Rename configure.in, require autoconf 2.59.
156 * configure: Re-generate.
158 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
160 * configure: Regenerate for ../common/aclocal.m4 update.
162 2004-09-24 Monika Chaddha <monika@acmet.com>
164 Committed by Andrew Cagney.
165 * m16.igen (CMP, CMPI): Fix assembler.
167 2004-08-18 Chris Demetriou <cgd@broadcom.com>
169 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
170 * configure: Regenerate.
172 2004-06-25 Chris Demetriou <cgd@broadcom.com>
174 * configure.in (sim_m16_machine): Include mipsIII.
175 * configure: Regenerate.
177 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
179 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
181 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
183 2004-04-10 Chris Demetriou <cgd@broadcom.com>
185 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
187 2004-04-09 Chris Demetriou <cgd@broadcom.com>
189 * mips.igen (check_fmt): Remove.
190 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
191 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
192 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
193 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
194 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
195 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
196 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
197 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
198 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
199 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
201 2004-04-09 Chris Demetriou <cgd@broadcom.com>
203 * sb1.igen (check_sbx): New function.
204 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
206 2004-03-29 Chris Demetriou <cgd@broadcom.com>
207 Richard Sandiford <rsandifo@redhat.com>
209 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
210 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
211 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
212 separate implementations for mipsIV and mipsV. Use new macros to
213 determine whether the restrictions apply.
215 2004-01-19 Chris Demetriou <cgd@broadcom.com>
217 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
218 (check_mult_hilo): Improve comments.
219 (check_div_hilo): Likewise. Also, fork off a new version
220 to handle mips32/mips64 (since there are no hazards to check
223 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
225 * mips.igen (do_dmultx): Fix check for negative operands.
227 2003-05-16 Ian Lance Taylor <ian@airs.com>
229 * Makefile.in (SHELL): Make sure this is defined.
230 (various): Use $(SHELL) whenever we invoke move-if-change.
232 2003-05-03 Chris Demetriou <cgd@broadcom.com>
234 * cp1.c: Tweak attribution slightly.
237 * mdmx.igen: Likewise.
238 * mips3d.igen: Likewise.
239 * sb1.igen: Likewise.
241 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
243 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
246 2003-02-27 Andrew Cagney <cagney@redhat.com>
248 * interp.c (sim_open): Rename _bfd to bfd.
249 (sim_create_inferior): Ditto.
251 2003-01-14 Chris Demetriou <cgd@broadcom.com>
253 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
255 2003-01-14 Chris Demetriou <cgd@broadcom.com>
257 * mips.igen (EI, DI): Remove.
259 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
261 * Makefile.in (tmp-run-multi): Fix mips16 filter.
263 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
264 Andrew Cagney <ac131313@redhat.com>
265 Gavin Romig-Koch <gavin@redhat.com>
266 Graydon Hoare <graydon@redhat.com>
267 Aldy Hernandez <aldyh@redhat.com>
268 Dave Brolley <brolley@redhat.com>
269 Chris Demetriou <cgd@broadcom.com>
271 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
272 (sim_mach_default): New variable.
273 (mips64vr-*-*, mips64vrel-*-*): New configurations.
274 Add a new simulator generator, MULTI.
275 * configure: Regenerate.
276 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
277 (multi-run.o): New dependency.
278 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
279 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
280 (tmp-multi): Combine them.
281 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
282 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
283 (distclean-extra): New rule.
284 * sim-main.h: Include bfd.h.
285 (MIPS_MACH): New macro.
286 * mips.igen (vr4120, vr5400, vr5500): New models.
287 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
288 * vr.igen: Replace with new version.
290 2003-01-04 Chris Demetriou <cgd@broadcom.com>
292 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
293 * configure: Regenerate.
295 2002-12-31 Chris Demetriou <cgd@broadcom.com>
297 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
298 * mips.igen: Remove all invocations of check_branch_bug and
301 2002-12-16 Chris Demetriou <cgd@broadcom.com>
303 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
305 2002-07-30 Chris Demetriou <cgd@broadcom.com>
307 * mips.igen (do_load_double, do_store_double): New functions.
308 (LDC1, SDC1): Rename to...
309 (LDC1b, SDC1b): respectively.
310 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
312 2002-07-29 Michael Snyder <msnyder@redhat.com>
314 * cp1.c (fp_recip2): Modify initialization expression so that
315 GCC will recognize it as constant.
317 2002-06-18 Chris Demetriou <cgd@broadcom.com>
319 * mdmx.c (SD_): Delete.
320 (Unpredictable): Re-define, for now, to directly invoke
321 unpredictable_action().
322 (mdmx_acc_op): Fix error in .ob immediate handling.
324 2002-06-18 Andrew Cagney <cagney@redhat.com>
326 * interp.c (sim_firmware_command): Initialize `address'.
328 2002-06-16 Andrew Cagney <ac131313@redhat.com>
330 * configure: Regenerated to track ../common/aclocal.m4 changes.
332 2002-06-14 Chris Demetriou <cgd@broadcom.com>
333 Ed Satterthwaite <ehs@broadcom.com>
335 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
336 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
337 * mips.igen: Include mips3d.igen.
338 (mips3d): New model name for MIPS-3D ASE instructions.
339 (CVT.W.fmt): Don't use this instruction for word (source) format
341 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
342 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
343 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
344 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
345 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
346 (RSquareRoot1, RSquareRoot2): New macros.
347 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
348 (fp_rsqrt2): New functions.
349 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
350 * configure: Regenerate.
352 2002-06-13 Chris Demetriou <cgd@broadcom.com>
353 Ed Satterthwaite <ehs@broadcom.com>
355 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
356 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
357 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
358 (convert): Note that this function is not used for paired-single
360 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
361 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
362 (check_fmt_p): Enable paired-single support.
363 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
364 (PUU.PS): New instructions.
365 (CVT.S.fmt): Don't use this instruction for paired-single format
367 * sim-main.h (FP_formats): New value 'fmt_ps.'
368 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
369 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
371 2002-06-12 Chris Demetriou <cgd@broadcom.com>
373 * mips.igen: Fix formatting of function calls in
376 2002-06-12 Chris Demetriou <cgd@broadcom.com>
378 * mips.igen (MOVN, MOVZ): Trace result.
379 (TNEI): Print "tnei" as the opcode name in traces.
380 (CEIL.W): Add disassembly string for traces.
381 (RSQRT.fmt): Make location of disassembly string consistent
382 with other instructions.
384 2002-06-12 Chris Demetriou <cgd@broadcom.com>
386 * mips.igen (X): Delete unused function.
388 2002-06-08 Andrew Cagney <cagney@redhat.com>
390 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
392 2002-06-07 Chris Demetriou <cgd@broadcom.com>
393 Ed Satterthwaite <ehs@broadcom.com>
395 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
396 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
397 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
398 (fp_nmsub): New prototypes.
399 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
400 (NegMultiplySub): New defines.
401 * mips.igen (RSQRT.fmt): Use RSquareRoot().
402 (MADD.D, MADD.S): Replace with...
403 (MADD.fmt): New instruction.
404 (MSUB.D, MSUB.S): Replace with...
405 (MSUB.fmt): New instruction.
406 (NMADD.D, NMADD.S): Replace with...
407 (NMADD.fmt): New instruction.
408 (NMSUB.D, MSUB.S): Replace with...
409 (NMSUB.fmt): New instruction.
411 2002-06-07 Chris Demetriou <cgd@broadcom.com>
412 Ed Satterthwaite <ehs@broadcom.com>
414 * cp1.c: Fix more comment spelling and formatting.
415 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
416 (denorm_mode): New function.
417 (fpu_unary, fpu_binary): Round results after operation, collect
418 status from rounding operations, and update the FCSR.
419 (convert): Collect status from integer conversions and rounding
420 operations, and update the FCSR. Adjust NaN values that result
421 from conversions. Convert to use sim_io_eprintf rather than
422 fprintf, and remove some debugging code.
423 * cp1.h (fenr_FS): New define.
425 2002-06-07 Chris Demetriou <cgd@broadcom.com>
427 * cp1.c (convert): Remove unusable debugging code, and move MIPS
428 rounding mode to sim FP rounding mode flag conversion code into...
429 (rounding_mode): New function.
431 2002-06-07 Chris Demetriou <cgd@broadcom.com>
433 * cp1.c: Clean up formatting of a few comments.
434 (value_fpr): Reformat switch statement.
436 2002-06-06 Chris Demetriou <cgd@broadcom.com>
437 Ed Satterthwaite <ehs@broadcom.com>
440 * sim-main.h: Include cp1.h.
441 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
442 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
443 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
444 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
445 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
446 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
447 * cp1.c: Don't include sim-fpu.h; already included by
448 sim-main.h. Clean up formatting of some comments.
449 (NaN, Equal, Less): Remove.
450 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
451 (fp_cmp): New functions.
452 * mips.igen (do_c_cond_fmt): Remove.
453 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
454 Compare. Add result tracing.
455 (CxC1): Remove, replace with...
456 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
457 (DMxC1): Remove, replace with...
458 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
459 (MxC1): Remove, replace with...
460 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
462 2002-06-04 Chris Demetriou <cgd@broadcom.com>
464 * sim-main.h (FGRIDX): Remove, replace all uses with...
465 (FGR_BASE): New macro.
466 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
467 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
468 (NR_FGR, FGR): Likewise.
469 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
470 * mips.igen: Likewise.
472 2002-06-04 Chris Demetriou <cgd@broadcom.com>
474 * cp1.c: Add an FSF Copyright notice to this file.
476 2002-06-04 Chris Demetriou <cgd@broadcom.com>
477 Ed Satterthwaite <ehs@broadcom.com>
479 * cp1.c (Infinity): Remove.
480 * sim-main.h (Infinity): Likewise.
482 * cp1.c (fp_unary, fp_binary): New functions.
483 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
484 (fp_sqrt): New functions, implemented in terms of the above.
485 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
486 (Recip, SquareRoot): Remove (replaced by functions above).
487 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
488 (fp_recip, fp_sqrt): New prototypes.
489 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
490 (Recip, SquareRoot): Replace prototypes with #defines which
491 invoke the functions above.
493 2002-06-03 Chris Demetriou <cgd@broadcom.com>
495 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
496 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
497 file, remove PARAMS from prototypes.
498 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
499 simulator state arguments.
500 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
501 pass simulator state arguments.
502 * cp1.c (SD): Redefine as CPU_STATE(cpu).
503 (store_fpr, convert): Remove 'sd' argument.
504 (value_fpr): Likewise. Convert to use 'SD' instead.
506 2002-06-03 Chris Demetriou <cgd@broadcom.com>
508 * cp1.c (Min, Max): Remove #if 0'd functions.
509 * sim-main.h (Min, Max): Remove.
511 2002-06-03 Chris Demetriou <cgd@broadcom.com>
513 * cp1.c: fix formatting of switch case and default labels.
514 * interp.c: Likewise.
515 * sim-main.c: Likewise.
517 2002-06-03 Chris Demetriou <cgd@broadcom.com>
519 * cp1.c: Clean up comments which describe FP formats.
520 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
522 2002-06-03 Chris Demetriou <cgd@broadcom.com>
523 Ed Satterthwaite <ehs@broadcom.com>
525 * configure.in (mipsisa64sb1*-*-*): New target for supporting
526 Broadcom SiByte SB-1 processor configurations.
527 * configure: Regenerate.
528 * sb1.igen: New file.
529 * mips.igen: Include sb1.igen.
531 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
532 * mdmx.igen: Add "sb1" model to all appropriate functions and
534 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
535 (ob_func, ob_acc): Reference the above.
536 (qh_acc): Adjust to keep the same size as ob_acc.
537 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
538 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
540 2002-06-03 Chris Demetriou <cgd@broadcom.com>
542 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
544 2002-06-02 Chris Demetriou <cgd@broadcom.com>
545 Ed Satterthwaite <ehs@broadcom.com>
547 * mips.igen (mdmx): New (pseudo-)model.
548 * mdmx.c, mdmx.igen: New files.
549 * Makefile.in (SIM_OBJS): Add mdmx.o.
550 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
552 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
553 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
554 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
555 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
556 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
557 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
558 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
559 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
560 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
561 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
562 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
563 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
564 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
565 (qh_fmtsel): New macros.
566 (_sim_cpu): New member "acc".
567 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
568 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
570 2002-05-01 Chris Demetriou <cgd@broadcom.com>
572 * interp.c: Use 'deprecated' rather than 'depreciated.'
573 * sim-main.h: Likewise.
575 2002-05-01 Chris Demetriou <cgd@broadcom.com>
577 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
578 which wouldn't compile anyway.
579 * sim-main.h (unpredictable_action): New function prototype.
580 (Unpredictable): Define to call igen function unpredictable().
581 (NotWordValue): New macro to call igen function not_word_value().
582 (UndefinedResult): Remove.
583 * interp.c (undefined_result): Remove.
584 (unpredictable_action): New function.
585 * mips.igen (not_word_value, unpredictable): New functions.
586 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
587 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
588 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
589 NotWordValue() to check for unpredictable inputs, then
590 Unpredictable() to handle them.
592 2002-02-24 Chris Demetriou <cgd@broadcom.com>
594 * mips.igen: Fix formatting of calls to Unpredictable().
596 2002-04-20 Andrew Cagney <ac131313@redhat.com>
598 * interp.c (sim_open): Revert previous change.
600 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
602 * interp.c (sim_open): Disable chunk of code that wrote code in
603 vector table entries.
605 2002-03-19 Chris Demetriou <cgd@broadcom.com>
607 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
608 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
611 2002-03-19 Chris Demetriou <cgd@broadcom.com>
613 * cp1.c: Fix many formatting issues.
615 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
617 * cp1.c (fpu_format_name): New function to replace...
618 (DOFMT): This. Delete, and update all callers.
619 (fpu_rounding_mode_name): New function to replace...
620 (RMMODE): This. Delete, and update all callers.
622 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
624 * interp.c: Move FPU support routines from here to...
625 * cp1.c: Here. New file.
626 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
629 2002-03-12 Chris Demetriou <cgd@broadcom.com>
631 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
632 * mips.igen (mips32, mips64): New models, add to all instructions
633 and functions as appropriate.
634 (loadstore_ea, check_u64): New variant for model mips64.
635 (check_fmt_p): New variant for models mipsV and mips64, remove
636 mipsV model marking fro other variant.
639 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
640 for mips32 and mips64.
641 (DCLO, DCLZ): New instructions for mips64.
643 2002-03-07 Chris Demetriou <cgd@broadcom.com>
645 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
646 immediate or code as a hex value with the "%#lx" format.
647 (ANDI): Likewise, and fix printed instruction name.
649 2002-03-05 Chris Demetriou <cgd@broadcom.com>
651 * sim-main.h (UndefinedResult, Unpredictable): New macros
652 which currently do nothing.
654 2002-03-05 Chris Demetriou <cgd@broadcom.com>
656 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
657 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
658 (status_CU3): New definitions.
660 * sim-main.h (ExceptionCause): Add new values for MIPS32
661 and MIPS64: MDMX, MCheck, CacheErr. Update comments
662 for DebugBreakPoint and NMIReset to note their status in
664 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
665 (SignalExceptionCacheErr): New exception macros.
667 2002-03-05 Chris Demetriou <cgd@broadcom.com>
669 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
670 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
672 (SignalExceptionCoProcessorUnusable): Take as argument the
673 unusable coprocessor number.
675 2002-03-05 Chris Demetriou <cgd@broadcom.com>
677 * mips.igen: Fix formatting of all SignalException calls.
679 2002-03-05 Chris Demetriou <cgd@broadcom.com>
681 * sim-main.h (SIGNEXTEND): Remove.
683 2002-03-04 Chris Demetriou <cgd@broadcom.com>
685 * mips.igen: Remove gencode comment from top of file, fix
686 spelling in another comment.
688 2002-03-04 Chris Demetriou <cgd@broadcom.com>
690 * mips.igen (check_fmt, check_fmt_p): New functions to check
691 whether specific floating point formats are usable.
692 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
693 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
694 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
695 Use the new functions.
696 (do_c_cond_fmt): Remove format checks...
697 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
699 2002-03-03 Chris Demetriou <cgd@broadcom.com>
701 * mips.igen: Fix formatting of check_fpu calls.
703 2002-03-03 Chris Demetriou <cgd@broadcom.com>
705 * mips.igen (FLOOR.L.fmt): Store correct destination register.
707 2002-03-03 Chris Demetriou <cgd@broadcom.com>
709 * mips.igen: Remove whitespace at end of lines.
711 2002-03-02 Chris Demetriou <cgd@broadcom.com>
713 * mips.igen (loadstore_ea): New function to do effective
714 address calculations.
715 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
716 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
717 CACHE): Use loadstore_ea to do effective address computations.
719 2002-03-02 Chris Demetriou <cgd@broadcom.com>
721 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
722 * mips.igen (LL, CxC1, MxC1): Likewise.
724 2002-03-02 Chris Demetriou <cgd@broadcom.com>
726 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
727 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
728 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
729 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
730 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
731 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
732 Don't split opcode fields by hand, use the opcode field values
735 2002-03-01 Chris Demetriou <cgd@broadcom.com>
737 * mips.igen (do_divu): Fix spacing.
739 * mips.igen (do_dsllv): Move to be right before DSLLV,
740 to match the rest of the do_<shift> functions.
742 2002-03-01 Chris Demetriou <cgd@broadcom.com>
744 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
745 DSRL32, do_dsrlv): Trace inputs and results.
747 2002-03-01 Chris Demetriou <cgd@broadcom.com>
749 * mips.igen (CACHE): Provide instruction-printing string.
751 * interp.c (signal_exception): Comment tokens after #endif.
753 2002-02-28 Chris Demetriou <cgd@broadcom.com>
755 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
756 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
757 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
758 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
759 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
760 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
761 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
762 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
764 2002-02-28 Chris Demetriou <cgd@broadcom.com>
766 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
767 instruction-printing string.
768 (LWU): Use '64' as the filter flag.
770 2002-02-28 Chris Demetriou <cgd@broadcom.com>
772 * mips.igen (SDXC1): Fix instruction-printing string.
774 2002-02-28 Chris Demetriou <cgd@broadcom.com>
776 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
779 2002-02-27 Chris Demetriou <cgd@broadcom.com>
781 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
784 2002-02-27 Chris Demetriou <cgd@broadcom.com>
786 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
787 add a comma) so that it more closely match the MIPS ISA
788 documentation opcode partitioning.
789 (PREF): Put useful names on opcode fields, and include
790 instruction-printing string.
792 2002-02-27 Chris Demetriou <cgd@broadcom.com>
794 * mips.igen (check_u64): New function which in the future will
795 check whether 64-bit instructions are usable and signal an
796 exception if not. Currently a no-op.
797 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
798 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
799 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
800 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
802 * mips.igen (check_fpu): New function which in the future will
803 check whether FPU instructions are usable and signal an exception
804 if not. Currently a no-op.
805 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
806 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
807 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
808 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
809 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
810 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
811 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
812 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
814 2002-02-27 Chris Demetriou <cgd@broadcom.com>
816 * mips.igen (do_load_left, do_load_right): Move to be immediately
818 (do_store_left, do_store_right): Move to be immediately following
821 2002-02-27 Chris Demetriou <cgd@broadcom.com>
823 * mips.igen (mipsV): New model name. Also, add it to
824 all instructions and functions where it is appropriate.
826 2002-02-18 Chris Demetriou <cgd@broadcom.com>
828 * mips.igen: For all functions and instructions, list model
829 names that support that instruction one per line.
831 2002-02-11 Chris Demetriou <cgd@broadcom.com>
833 * mips.igen: Add some additional comments about supported
834 models, and about which instructions go where.
835 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
836 order as is used in the rest of the file.
838 2002-02-11 Chris Demetriou <cgd@broadcom.com>
840 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
841 indicating that ALU32_END or ALU64_END are there to check
843 (DADD): Likewise, but also remove previous comment about
846 2002-02-10 Chris Demetriou <cgd@broadcom.com>
848 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
849 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
850 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
851 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
852 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
853 fields (i.e., add and move commas) so that they more closely
854 match the MIPS ISA documentation opcode partitioning.
856 2002-02-10 Chris Demetriou <cgd@broadcom.com>
858 * mips.igen (ADDI): Print immediate value.
860 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
861 (SLL): Print "nop" specially, and don't run the code
862 that does the shift for the "nop" case.
864 2001-11-17 Fred Fish <fnf@redhat.com>
866 * sim-main.h (float_operation): Move enum declaration outside
867 of _sim_cpu struct declaration.
869 2001-04-12 Jim Blandy <jimb@redhat.com>
871 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
872 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
874 * sim-main.h (COCIDX): Remove definition; this isn't supported by
875 PENDING_FILL, and you can get the intended effect gracefully by
876 calling PENDING_SCHED directly.
878 2001-02-23 Ben Elliston <bje@redhat.com>
880 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
881 already defined elsewhere.
883 2001-02-19 Ben Elliston <bje@redhat.com>
885 * sim-main.h (sim_monitor): Return an int.
886 * interp.c (sim_monitor): Add return values.
887 (signal_exception): Handle error conditions from sim_monitor.
889 2001-02-08 Ben Elliston <bje@redhat.com>
891 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
892 (store_memory): Likewise, pass cia to sim_core_write*.
894 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
896 On advice from Chris G. Demetriou <cgd@sibyte.com>:
897 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
899 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
901 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
902 * Makefile.in: Don't delete *.igen when cleaning directory.
904 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
906 * m16.igen (break): Call SignalException not sim_engine_halt.
908 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
911 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
913 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
915 * mips.igen (MxC1, DMxC1): Fix printf formatting.
917 2000-05-24 Michael Hayes <mhayes@cygnus.com>
919 * mips.igen (do_dmultx): Fix typo.
921 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
923 * configure: Regenerated to track ../common/aclocal.m4 changes.
925 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
927 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
929 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
931 * sim-main.h (GPR_CLEAR): Define macro.
933 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
935 * interp.c (decode_coproc): Output long using %lx and not %s.
937 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
939 * interp.c (sim_open): Sort & extend dummy memory regions for
940 --board=jmr3904 for eCos.
942 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
944 * configure: Regenerated.
946 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
948 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
949 calls, conditional on the simulator being in verbose mode.
951 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
953 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
954 cache don't get ReservedInstruction traps.
956 1999-11-29 Mark Salter <msalter@cygnus.com>
958 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
959 to clear status bits in sdisr register. This is how the hardware works.
961 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
962 being used by cygmon.
964 1999-11-11 Andrew Haley <aph@cygnus.com>
966 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
969 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
971 * mips.igen (MULT): Correct previous mis-applied patch.
973 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
975 * mips.igen (delayslot32): Handle sequence like
976 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
977 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
978 (MULT): Actually pass the third register...
980 1999-09-03 Mark Salter <msalter@cygnus.com>
982 * interp.c (sim_open): Added more memory aliases for additional
983 hardware being touched by cygmon on jmr3904 board.
985 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
987 * configure: Regenerated to track ../common/aclocal.m4 changes.
989 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
991 * interp.c (sim_store_register): Handle case where client - GDB -
992 specifies that a 4 byte register is 8 bytes in size.
993 (sim_fetch_register): Ditto.
995 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
997 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
998 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
999 (idt_monitor_base): Base address for IDT monitor traps.
1000 (pmon_monitor_base): Ditto for PMON.
1001 (lsipmon_monitor_base): Ditto for LSI PMON.
1002 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1003 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1004 (sim_firmware_command): New function.
1005 (mips_option_handler): Call it for OPTION_FIRMWARE.
1006 (sim_open): Allocate memory for idt_monitor region. If "--board"
1007 option was given, add no monitor by default. Add BREAK hooks only if
1008 monitors are also there.
1010 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1012 * interp.c (sim_monitor): Flush output before reading input.
1014 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1016 * tconfig.in (SIM_HANDLES_LMA): Always define.
1018 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1020 From Mark Salter <msalter@cygnus.com>:
1021 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1022 (sim_open): Add setup for BSP board.
1024 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1026 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1027 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1028 them as unimplemented.
1030 1999-05-08 Felix Lee <flee@cygnus.com>
1032 * configure: Regenerated to track ../common/aclocal.m4 changes.
1034 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1036 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1038 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1040 * configure.in: Any mips64vr5*-*-* target should have
1041 -DTARGET_ENABLE_FR=1.
1042 (default_endian): Any mips64vr*el-*-* target should default to
1044 * configure: Re-generate.
1046 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1048 * mips.igen (ldl): Extend from _16_, not 32.
1050 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1052 * interp.c (sim_store_register): Force registers written to by GDB
1053 into an un-interpreted state.
1055 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1057 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1058 CPU, start periodic background I/O polls.
1059 (tx3904sio_poll): New function: periodic I/O poller.
1061 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1063 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1065 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1067 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1070 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1072 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1073 (load_word): Call SIM_CORE_SIGNAL hook on error.
1074 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1075 starting. For exception dispatching, pass PC instead of NULL_CIA.
1076 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1077 * sim-main.h (COP0_BADVADDR): Define.
1078 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1079 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1080 (_sim_cpu): Add exc_* fields to store register value snapshots.
1081 * mips.igen (*): Replace memory-related SignalException* calls
1082 with references to SIM_CORE_SIGNAL hook.
1084 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1086 * sim-main.c (*): Minor warning cleanups.
1088 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1090 * m16.igen (DADDIU5): Correct type-o.
1092 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1094 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1097 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1099 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1101 (interp.o): Add dependency on itable.h
1102 (oengine.c, gencode): Delete remaining references.
1103 (BUILT_SRC_FROM_GEN): Clean up.
1105 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1108 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1109 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1110 tmp-run-hack) : New.
1111 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1112 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1113 Drop the "64" qualifier to get the HACK generator working.
1114 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1115 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1116 qualifier to get the hack generator working.
1117 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1118 (DSLL): Use do_dsll.
1119 (DSLLV): Use do_dsllv.
1120 (DSRA): Use do_dsra.
1121 (DSRL): Use do_dsrl.
1122 (DSRLV): Use do_dsrlv.
1123 (BC1): Move *vr4100 to get the HACK generator working.
1124 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1125 get the HACK generator working.
1126 (MACC) Rename to get the HACK generator working.
1127 (DMACC,MACCS,DMACCS): Add the 64.
1129 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1131 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1132 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1134 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1136 * mips/interp.c (DEBUG): Cleanups.
1138 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1140 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1141 (tx3904sio_tickle): fflush after a stdout character output.
1143 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1145 * interp.c (sim_close): Uninstall modules.
1147 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1149 * sim-main.h, interp.c (sim_monitor): Change to global
1152 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1154 * configure.in (vr4100): Only include vr4100 instructions in
1156 * configure: Re-generate.
1157 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1159 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1161 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1162 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1165 * configure.in (sim_default_gen, sim_use_gen): Replace with
1167 (--enable-sim-igen): Delete config option. Always using IGEN.
1168 * configure: Re-generate.
1170 * Makefile.in (gencode): Kill, kill, kill.
1173 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1175 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1176 bit mips16 igen simulator.
1177 * configure: Re-generate.
1179 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1180 as part of vr4100 ISA.
1181 * vr.igen: Mark all instructions as 64 bit only.
1183 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1185 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1188 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1190 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1191 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1192 * configure: Re-generate.
1194 * m16.igen (BREAK): Define breakpoint instruction.
1195 (JALX32): Mark instruction as mips16 and not r3900.
1196 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1198 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1200 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1202 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1203 insn as a debug breakpoint.
1205 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1207 (PENDING_SCHED): Clean up trace statement.
1208 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1209 (PENDING_FILL): Delay write by only one cycle.
1210 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1212 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1214 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1216 (pending_tick): Move incrementing of index to FOR statement.
1217 (pending_tick): Only update PENDING_OUT after a write has occured.
1219 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1221 * configure: Re-generate.
1223 * interp.c (sim_engine_run OLD): Delete explicit call to
1224 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1226 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1228 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1229 interrupt level number to match changed SignalExceptionInterrupt
1232 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1234 * interp.c: #include "itable.h" if WITH_IGEN.
1235 (get_insn_name): New function.
1236 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1237 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1239 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1241 * configure: Rebuilt to inhale new common/aclocal.m4.
1243 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1245 * dv-tx3904sio.c: Include sim-assert.h.
1247 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1249 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1250 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1251 Reorganize target-specific sim-hardware checks.
1252 * configure: rebuilt.
1253 * interp.c (sim_open): For tx39 target boards, set
1254 OPERATING_ENVIRONMENT, add tx3904sio devices.
1255 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1256 ROM executables. Install dv-sockser into sim-modules list.
1258 * dv-tx3904irc.c: Compiler warning clean-up.
1259 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1260 frequent hw-trace messages.
1262 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1264 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1266 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1268 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1270 * vr.igen: New file.
1271 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1272 * mips.igen: Define vr4100 model. Include vr.igen.
1273 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1275 * mips.igen (check_mf_hilo): Correct check.
1277 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1279 * sim-main.h (interrupt_event): Add prototype.
1281 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1282 register_ptr, register_value.
1283 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1285 * sim-main.h (tracefh): Make extern.
1287 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1289 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1290 Reduce unnecessarily high timer event frequency.
1291 * dv-tx3904cpu.c: Ditto for interrupt event.
1293 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1295 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1297 (interrupt_event): Made non-static.
1299 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1300 interchange of configuration values for external vs. internal
1303 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1305 * mips.igen (BREAK): Moved code to here for
1306 simulator-reserved break instructions.
1307 * gencode.c (build_instruction): Ditto.
1308 * interp.c (signal_exception): Code moved from here. Non-
1309 reserved instructions now use exception vector, rather
1311 * sim-main.h: Moved magic constants to here.
1313 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1315 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1316 register upon non-zero interrupt event level, clear upon zero
1318 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1319 by passing zero event value.
1320 (*_io_{read,write}_buffer): Endianness fixes.
1321 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1322 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1324 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1325 serial I/O and timer module at base address 0xFFFF0000.
1327 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1329 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1332 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1334 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1336 * configure: Update.
1338 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1340 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1341 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1342 * configure.in: Include tx3904tmr in hw_device list.
1343 * configure: Rebuilt.
1344 * interp.c (sim_open): Instantiate three timer instances.
1345 Fix address typo of tx3904irc instance.
1347 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1349 * interp.c (signal_exception): SystemCall exception now uses
1350 the exception vector.
1352 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1354 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1357 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1359 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1361 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1363 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1365 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1366 sim-main.h. Declare a struct hw_descriptor instead of struct
1367 hw_device_descriptor.
1369 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1371 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1372 right bits and then re-align left hand bytes to correct byte
1373 lanes. Fix incorrect computation in do_store_left when loading
1374 bytes from second word.
1376 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1378 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1379 * interp.c (sim_open): Only create a device tree when HW is
1382 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1383 * interp.c (signal_exception): Ditto.
1385 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1387 * gencode.c: Mark BEGEZALL as LIKELY.
1389 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1391 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1392 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1394 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1396 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1397 modules. Recognize TX39 target with "mips*tx39" pattern.
1398 * configure: Rebuilt.
1399 * sim-main.h (*): Added many macros defining bits in
1400 TX39 control registers.
1401 (SignalInterrupt): Send actual PC instead of NULL.
1402 (SignalNMIReset): New exception type.
1403 * interp.c (board): New variable for future use to identify
1404 a particular board being simulated.
1405 (mips_option_handler,mips_options): Added "--board" option.
1406 (interrupt_event): Send actual PC.
1407 (sim_open): Make memory layout conditional on board setting.
1408 (signal_exception): Initial implementation of hardware interrupt
1409 handling. Accept another break instruction variant for simulator
1411 (decode_coproc): Implement RFE instruction for TX39.
1412 (mips.igen): Decode RFE instruction as such.
1413 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1414 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1415 bbegin to implement memory map.
1416 * dv-tx3904cpu.c: New file.
1417 * dv-tx3904irc.c: New file.
1419 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1421 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1423 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1425 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1426 with calls to check_div_hilo.
1428 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1430 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1431 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1432 Add special r3900 version of do_mult_hilo.
1433 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1434 with calls to check_mult_hilo.
1435 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1436 with calls to check_div_hilo.
1438 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1440 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1441 Document a replacement.
1443 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1445 * interp.c (sim_monitor): Make mon_printf work.
1447 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1449 * sim-main.h (INSN_NAME): New arg `cpu'.
1451 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1453 * configure: Regenerated to track ../common/aclocal.m4 changes.
1455 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1457 * configure: Regenerated to track ../common/aclocal.m4 changes.
1460 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1462 * acconfig.h: New file.
1463 * configure.in: Reverted change of Apr 24; use sinclude again.
1465 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1467 * configure: Regenerated to track ../common/aclocal.m4 changes.
1470 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1472 * configure.in: Don't call sinclude.
1474 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1476 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1478 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1480 * mips.igen (ERET): Implement.
1482 * interp.c (decode_coproc): Return sign-extended EPC.
1484 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1486 * interp.c (signal_exception): Do not ignore Trap.
1487 (signal_exception): On TRAP, restart at exception address.
1488 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1489 (signal_exception): Update.
1490 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1491 so that TRAP instructions are caught.
1493 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1495 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1496 contains HI/LO access history.
1497 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1498 (HIACCESS, LOACCESS): Delete, replace with
1499 (HIHISTORY, LOHISTORY): New macros.
1500 (CHECKHILO): Delete all, moved to mips.igen
1502 * gencode.c (build_instruction): Do not generate checks for
1503 correct HI/LO register usage.
1505 * interp.c (old_engine_run): Delete checks for correct HI/LO
1508 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1509 check_mf_cycles): New functions.
1510 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1511 do_divu, domultx, do_mult, do_multu): Use.
1513 * tx.igen ("madd", "maddu"): Use.
1515 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1517 * mips.igen (DSRAV): Use function do_dsrav.
1518 (SRAV): Use new function do_srav.
1520 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1521 (B): Sign extend 11 bit immediate.
1522 (EXT-B*): Shift 16 bit immediate left by 1.
1523 (ADDIU*): Don't sign extend immediate value.
1525 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1527 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1529 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1532 * mips.igen (delayslot32, nullify_next_insn): New functions.
1533 (m16.igen): Always include.
1534 (do_*): Add more tracing.
1536 * m16.igen (delayslot16): Add NIA argument, could be called by a
1537 32 bit MIPS16 instruction.
1539 * interp.c (ifetch16): Move function from here.
1540 * sim-main.c (ifetch16): To here.
1542 * sim-main.c (ifetch16, ifetch32): Update to match current
1543 implementations of LH, LW.
1544 (signal_exception): Don't print out incorrect hex value of illegal
1547 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1549 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1552 * m16.igen: Implement MIPS16 instructions.
1554 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1555 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1556 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1557 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1558 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1559 bodies of corresponding code from 32 bit insn to these. Also used
1560 by MIPS16 versions of functions.
1562 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1563 (IMEM16): Drop NR argument from macro.
1565 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1567 * Makefile.in (SIM_OBJS): Add sim-main.o.
1569 * sim-main.h (address_translation, load_memory, store_memory,
1570 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1572 (pr_addr, pr_uword64): Declare.
1573 (sim-main.c): Include when H_REVEALS_MODULE_P.
1575 * interp.c (address_translation, load_memory, store_memory,
1576 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1578 * sim-main.c: To here. Fix compilation problems.
1580 * configure.in: Enable inlining.
1581 * configure: Re-config.
1583 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1585 * configure: Regenerated to track ../common/aclocal.m4 changes.
1587 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1589 * mips.igen: Include tx.igen.
1590 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1591 * tx.igen: New file, contains MADD and MADDU.
1593 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1594 the hardwired constant `7'.
1595 (store_memory): Ditto.
1596 (LOADDRMASK): Move definition to sim-main.h.
1598 mips.igen (MTC0): Enable for r3900.
1601 mips.igen (do_load_byte): Delete.
1602 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1603 do_store_right): New functions.
1604 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1606 configure.in: Let the tx39 use igen again.
1609 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1611 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1612 not an address sized quantity. Return zero for cache sizes.
1614 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1616 * mips.igen (r3900): r3900 does not support 64 bit integer
1619 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1621 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1623 * configure : Rebuild.
1625 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1627 * configure: Regenerated to track ../common/aclocal.m4 changes.
1629 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1631 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1633 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1635 * configure: Regenerated to track ../common/aclocal.m4 changes.
1636 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1638 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1640 * configure: Regenerated to track ../common/aclocal.m4 changes.
1642 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1644 * interp.c (Max, Min): Comment out functions. Not yet used.
1646 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1648 * configure: Regenerated to track ../common/aclocal.m4 changes.
1650 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1652 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1653 configurable settings for stand-alone simulator.
1655 * configure.in: Added X11 search, just in case.
1657 * configure: Regenerated.
1659 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1661 * interp.c (sim_write, sim_read, load_memory, store_memory):
1662 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1664 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1666 * sim-main.h (GETFCC): Return an unsigned value.
1668 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1670 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1671 (DADD): Result destination is RD not RT.
1673 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1675 * sim-main.h (HIACCESS, LOACCESS): Always define.
1677 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1679 * interp.c (sim_info): Delete.
1681 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1683 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1684 (mips_option_handler): New argument `cpu'.
1685 (sim_open): Update call to sim_add_option_table.
1687 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1689 * mips.igen (CxC1): Add tracing.
1691 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1693 * sim-main.h (Max, Min): Declare.
1695 * interp.c (Max, Min): New functions.
1697 * mips.igen (BC1): Add tracing.
1699 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1701 * interp.c Added memory map for stack in vr4100
1703 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1705 * interp.c (load_memory): Add missing "break"'s.
1707 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1709 * interp.c (sim_store_register, sim_fetch_register): Pass in
1710 length parameter. Return -1.
1712 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1714 * interp.c: Added hardware init hook, fixed warnings.
1716 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1718 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1720 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1722 * interp.c (ifetch16): New function.
1724 * sim-main.h (IMEM32): Rename IMEM.
1725 (IMEM16_IMMED): Define.
1727 (DELAY_SLOT): Update.
1729 * m16run.c (sim_engine_run): New file.
1731 * m16.igen: All instructions except LB.
1732 (LB): Call do_load_byte.
1733 * mips.igen (do_load_byte): New function.
1734 (LB): Call do_load_byte.
1736 * mips.igen: Move spec for insn bit size and high bit from here.
1737 * Makefile.in (tmp-igen, tmp-m16): To here.
1739 * m16.dc: New file, decode mips16 instructions.
1741 * Makefile.in (SIM_NO_ALL): Define.
1742 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1744 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1746 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1747 point unit to 32 bit registers.
1748 * configure: Re-generate.
1750 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1752 * configure.in (sim_use_gen): Make IGEN the default simulator
1753 generator for generic 32 and 64 bit mips targets.
1754 * configure: Re-generate.
1756 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1758 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1761 * interp.c (sim_fetch_register, sim_store_register): Read/write
1762 FGR from correct location.
1763 (sim_open): Set size of FGR's according to
1764 WITH_TARGET_FLOATING_POINT_BITSIZE.
1766 * sim-main.h (FGR): Store floating point registers in a separate
1769 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1771 * configure: Regenerated to track ../common/aclocal.m4 changes.
1773 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1775 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1777 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1779 * interp.c (pending_tick): New function. Deliver pending writes.
1781 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1782 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1783 it can handle mixed sized quantites and single bits.
1785 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1787 * interp.c (oengine.h): Do not include when building with IGEN.
1788 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1789 (sim_info): Ditto for PROCESSOR_64BIT.
1790 (sim_monitor): Replace ut_reg with unsigned_word.
1791 (*): Ditto for t_reg.
1792 (LOADDRMASK): Define.
1793 (sim_open): Remove defunct check that host FP is IEEE compliant,
1794 using software to emulate floating point.
1795 (value_fpr, ...): Always compile, was conditional on HASFPU.
1797 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1799 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1802 * interp.c (SD, CPU): Define.
1803 (mips_option_handler): Set flags in each CPU.
1804 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1805 (sim_close): Do not clear STATE, deleted anyway.
1806 (sim_write, sim_read): Assume CPU zero's vm should be used for
1808 (sim_create_inferior): Set the PC for all processors.
1809 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1811 (mips16_entry): Pass correct nr of args to store_word, load_word.
1812 (ColdReset): Cold reset all cpu's.
1813 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1814 (sim_monitor, load_memory, store_memory, signal_exception): Use
1815 `CPU' instead of STATE_CPU.
1818 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1821 * sim-main.h (signal_exception): Add sim_cpu arg.
1822 (SignalException*): Pass both SD and CPU to signal_exception.
1823 * interp.c (signal_exception): Update.
1825 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1827 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1828 address_translation): Ditto
1829 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1831 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1833 * configure: Regenerated to track ../common/aclocal.m4 changes.
1835 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1837 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1839 * mips.igen (model): Map processor names onto BFD name.
1841 * sim-main.h (CPU_CIA): Delete.
1842 (SET_CIA, GET_CIA): Define
1844 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1846 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1849 * configure.in (default_endian): Configure a big-endian simulator
1851 * configure: Re-generate.
1853 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1855 * configure: Regenerated to track ../common/aclocal.m4 changes.
1857 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1859 * interp.c (sim_monitor): Handle Densan monitor outbyte
1860 and inbyte functions.
1862 1997-12-29 Felix Lee <flee@cygnus.com>
1864 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1866 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1868 * Makefile.in (tmp-igen): Arrange for $zero to always be
1869 reset to zero after every instruction.
1871 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1873 * configure: Regenerated to track ../common/aclocal.m4 changes.
1876 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1878 * mips.igen (MSUB): Fix to work like MADD.
1879 * gencode.c (MSUB): Similarly.
1881 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1883 * configure: Regenerated to track ../common/aclocal.m4 changes.
1885 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1887 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1889 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1891 * sim-main.h (sim-fpu.h): Include.
1893 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1894 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1895 using host independant sim_fpu module.
1897 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1899 * interp.c (signal_exception): Report internal errors with SIGABRT
1902 * sim-main.h (C0_CONFIG): New register.
1903 (signal.h): No longer include.
1905 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1907 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1909 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1911 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1913 * mips.igen: Tag vr5000 instructions.
1914 (ANDI): Was missing mipsIV model, fix assembler syntax.
1915 (do_c_cond_fmt): New function.
1916 (C.cond.fmt): Handle mips I-III which do not support CC field
1918 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1919 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1921 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1922 vr5000 which saves LO in a GPR separatly.
1924 * configure.in (enable-sim-igen): For vr5000, select vr5000
1925 specific instructions.
1926 * configure: Re-generate.
1928 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1930 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1932 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1933 fmt_uninterpreted_64 bit cases to switch. Convert to
1936 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1938 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1939 as specified in IV3.2 spec.
1940 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1942 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1944 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1945 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1946 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1947 PENDING_FILL versions of instructions. Simplify.
1949 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1951 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1953 (MTHI, MFHI): Disable code checking HI-LO.
1955 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1957 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1959 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1961 * gencode.c (build_mips16_operands): Replace IPC with cia.
1963 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1964 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1966 (UndefinedResult): Replace function with macro/function
1968 (sim_engine_run): Don't save PC in IPC.
1970 * sim-main.h (IPC): Delete.
1973 * interp.c (signal_exception, store_word, load_word,
1974 address_translation, load_memory, store_memory, cache_op,
1975 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1976 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1977 current instruction address - cia - argument.
1978 (sim_read, sim_write): Call address_translation directly.
1979 (sim_engine_run): Rename variable vaddr to cia.
1980 (signal_exception): Pass cia to sim_monitor
1982 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1983 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1984 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1986 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1987 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1990 * interp.c (signal_exception): Pass restart address to
1993 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1994 idecode.o): Add dependency.
1996 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1998 (DELAY_SLOT): Update NIA not PC with branch address.
1999 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2001 * mips.igen: Use CIA not PC in branch calculations.
2002 (illegal): Call SignalException.
2003 (BEQ, ADDIU): Fix assembler.
2005 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2007 * m16.igen (JALX): Was missing.
2009 * configure.in (enable-sim-igen): New configuration option.
2010 * configure: Re-generate.
2012 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2014 * interp.c (load_memory, store_memory): Delete parameter RAW.
2015 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2016 bypassing {load,store}_memory.
2018 * sim-main.h (ByteSwapMem): Delete definition.
2020 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2022 * interp.c (sim_do_command, sim_commands): Delete mips specific
2023 commands. Handled by module sim-options.
2025 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2026 (WITH_MODULO_MEMORY): Define.
2028 * interp.c (sim_info): Delete code printing memory size.
2030 * interp.c (mips_size): Nee sim_size, delete function.
2032 (monitor, monitor_base, monitor_size): Delete global variables.
2033 (sim_open, sim_close): Delete code creating monitor and other
2034 memory regions. Use sim-memopts module, via sim_do_commandf, to
2035 manage memory regions.
2036 (load_memory, store_memory): Use sim-core for memory model.
2038 * interp.c (address_translation): Delete all memory map code
2039 except line forcing 32 bit addresses.
2041 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2043 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2046 * interp.c (logfh, logfile): Delete globals.
2047 (sim_open, sim_close): Delete code opening & closing log file.
2048 (mips_option_handler): Delete -l and -n options.
2049 (OPTION mips_options): Ditto.
2051 * interp.c (OPTION mips_options): Rename option trace to dinero.
2052 (mips_option_handler): Update.
2054 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2056 * interp.c (fetch_str): New function.
2057 (sim_monitor): Rewrite using sim_read & sim_write.
2058 (sim_open): Check magic number.
2059 (sim_open): Write monitor vectors into memory using sim_write.
2060 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2061 (sim_read, sim_write): Simplify - transfer data one byte at a
2063 (load_memory, store_memory): Clarify meaning of parameter RAW.
2065 * sim-main.h (isHOST): Defete definition.
2066 (isTARGET): Mark as depreciated.
2067 (address_translation): Delete parameter HOST.
2069 * interp.c (address_translation): Delete parameter HOST.
2071 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2075 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2076 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2078 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2080 * mips.igen: Add model filter field to records.
2082 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2084 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2086 interp.c (sim_engine_run): Do not compile function sim_engine_run
2087 when WITH_IGEN == 1.
2089 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2090 target architecture.
2092 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2093 igen. Replace with configuration variables sim_igen_flags /
2096 * m16.igen: New file. Copy mips16 insns here.
2097 * mips.igen: From here.
2099 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2101 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2103 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2105 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2107 * gencode.c (build_instruction): Follow sim_write's lead in using
2108 BigEndianMem instead of !ByteSwapMem.
2110 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2112 * configure.in (sim_gen): Dependent on target, select type of
2113 generator. Always select old style generator.
2115 configure: Re-generate.
2117 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2119 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2120 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2121 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2122 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2123 SIM_@sim_gen@_*, set by autoconf.
2125 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2127 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2129 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2130 CURRENT_FLOATING_POINT instead.
2132 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2133 (address_translation): Raise exception InstructionFetch when
2134 translation fails and isINSTRUCTION.
2136 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2137 sim_engine_run): Change type of of vaddr and paddr to
2139 (address_translation, prefetch, load_memory, store_memory,
2140 cache_op): Change type of vAddr and pAddr to address_word.
2142 * gencode.c (build_instruction): Change type of vaddr and paddr to
2145 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2147 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2148 macro to obtain result of ALU op.
2150 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2152 * interp.c (sim_info): Call profile_print.
2154 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2156 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2158 * sim-main.h (WITH_PROFILE): Do not define, defined in
2159 common/sim-config.h. Use sim-profile module.
2160 (simPROFILE): Delete defintion.
2162 * interp.c (PROFILE): Delete definition.
2163 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2164 (sim_close): Delete code writing profile histogram.
2165 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2167 (sim_engine_run): Delete code profiling the PC.
2169 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2171 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2173 * interp.c (sim_monitor): Make register pointers of type
2176 * sim-main.h: Make registers of type unsigned_word not
2179 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2181 * interp.c (sync_operation): Rename from SyncOperation, make
2182 global, add SD argument.
2183 (prefetch): Rename from Prefetch, make global, add SD argument.
2184 (decode_coproc): Make global.
2186 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2188 * gencode.c (build_instruction): Generate DecodeCoproc not
2189 decode_coproc calls.
2191 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2192 (SizeFGR): Move to sim-main.h
2193 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2194 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2195 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2197 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2198 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2199 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2200 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2201 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2202 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2204 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2206 (sim-alu.h): Include.
2207 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2208 (sim_cia): Typedef to instruction_address.
2210 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2212 * Makefile.in (interp.o): Rename generated file engine.c to
2217 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2219 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2221 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2223 * gencode.c (build_instruction): For "FPSQRT", output correct
2224 number of arguments to Recip.
2226 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2228 * Makefile.in (interp.o): Depends on sim-main.h
2230 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2232 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2233 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2234 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2235 STATE, DSSTATE): Define
2236 (GPR, FGRIDX, ..): Define.
2238 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2239 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2240 (GPR, FGRIDX, ...): Delete macros.
2242 * interp.c: Update names to match defines from sim-main.h
2244 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2246 * interp.c (sim_monitor): Add SD argument.
2247 (sim_warning): Delete. Replace calls with calls to
2249 (sim_error): Delete. Replace calls with sim_io_error.
2250 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2251 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2252 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2254 (mips_size): Rename from sim_size. Add SD argument.
2256 * interp.c (simulator): Delete global variable.
2257 (callback): Delete global variable.
2258 (mips_option_handler, sim_open, sim_write, sim_read,
2259 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2260 sim_size,sim_monitor): Use sim_io_* not callback->*.
2261 (sim_open): ZALLOC simulator struct.
2262 (PROFILE): Do not define.
2264 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2266 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2267 support.h with corresponding code.
2269 * sim-main.h (word64, uword64), support.h: Move definition to
2271 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2274 * Makefile.in: Update dependencies
2275 * interp.c: Do not include.
2277 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2279 * interp.c (address_translation, load_memory, store_memory,
2280 cache_op): Rename to from AddressTranslation et.al., make global,
2283 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2286 * interp.c (SignalException): Rename to signal_exception, make
2289 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2291 * sim-main.h (SignalException, SignalExceptionInterrupt,
2292 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2293 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2294 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2297 * interp.c, support.h: Use.
2299 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2301 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2302 to value_fpr / store_fpr. Add SD argument.
2303 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2304 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2306 * sim-main.h (ValueFPR, StoreFPR): Define.
2308 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2310 * interp.c (sim_engine_run): Check consistency between configure
2311 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2314 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2315 (mips_fpu): Configure WITH_FLOATING_POINT.
2316 (mips_endian): Configure WITH_TARGET_ENDIAN.
2317 * configure: Update.
2319 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2321 * configure: Regenerated to track ../common/aclocal.m4 changes.
2323 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2325 * configure: Regenerated.
2327 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2329 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2331 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2333 * gencode.c (print_igen_insn_models): Assume certain architectures
2334 include all mips* instructions.
2335 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2338 * Makefile.in (tmp.igen): Add target. Generate igen input from
2341 * gencode.c (FEATURE_IGEN): Define.
2342 (main): Add --igen option. Generate output in igen format.
2343 (process_instructions): Format output according to igen option.
2344 (print_igen_insn_format): New function.
2345 (print_igen_insn_models): New function.
2346 (process_instructions): Only issue warnings and ignore
2347 instructions when no FEATURE_IGEN.
2349 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2351 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2354 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2356 * configure: Regenerated to track ../common/aclocal.m4 changes.
2358 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2360 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2361 SIM_RESERVED_BITS): Delete, moved to common.
2362 (SIM_EXTRA_CFLAGS): Update.
2364 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2366 * configure.in: Configure non-strict memory alignment.
2367 * configure: Regenerated to track ../common/aclocal.m4 changes.
2369 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2371 * configure: Regenerated to track ../common/aclocal.m4 changes.
2373 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2375 * gencode.c (SDBBP,DERET): Added (3900) insns.
2376 (RFE): Turn on for 3900.
2377 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2378 (dsstate): Made global.
2379 (SUBTARGET_R3900): Added.
2380 (CANCELDELAYSLOT): New.
2381 (SignalException): Ignore SystemCall rather than ignore and
2382 terminate. Add DebugBreakPoint handling.
2383 (decode_coproc): New insns RFE, DERET; and new registers Debug
2384 and DEPC protected by SUBTARGET_R3900.
2385 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2387 * Makefile.in,configure.in: Add mips subtarget option.
2388 * configure: Update.
2390 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2392 * gencode.c: Add r3900 (tx39).
2395 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2397 * gencode.c (build_instruction): Don't need to subtract 4 for
2400 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2402 * interp.c: Correct some HASFPU problems.
2404 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2406 * configure: Regenerated to track ../common/aclocal.m4 changes.
2408 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2410 * interp.c (mips_options): Fix samples option short form, should
2413 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2415 * interp.c (sim_info): Enable info code. Was just returning.
2417 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2419 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2422 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2424 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2426 (build_instruction): Ditto for LL.
2428 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2430 * configure: Regenerated to track ../common/aclocal.m4 changes.
2432 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2434 * configure: Regenerated to track ../common/aclocal.m4 changes.
2437 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2439 * interp.c (sim_open): Add call to sim_analyze_program, update
2442 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2444 * interp.c (sim_kill): Delete.
2445 (sim_create_inferior): Add ABFD argument. Set PC from same.
2446 (sim_load): Move code initializing trap handlers from here.
2447 (sim_open): To here.
2448 (sim_load): Delete, use sim-hload.c.
2450 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2452 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2454 * configure: Regenerated to track ../common/aclocal.m4 changes.
2457 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2459 * interp.c (sim_open): Add ABFD argument.
2460 (sim_load): Move call to sim_config from here.
2461 (sim_open): To here. Check return status.
2463 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2465 * gencode.c (build_instruction): Two arg MADD should
2466 not assign result to $0.
2468 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2470 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2471 * sim/mips/configure.in: Regenerate.
2473 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2475 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2476 signed8, unsigned8 et.al. types.
2478 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2479 hosts when selecting subreg.
2481 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2483 * interp.c (sim_engine_run): Reset the ZERO register to zero
2484 regardless of FEATURE_WARN_ZERO.
2485 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2487 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2489 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2490 (SignalException): For BreakPoints ignore any mode bits and just
2492 (SignalException): Always set the CAUSE register.
2494 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2496 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2497 exception has been taken.
2499 * interp.c: Implement the ERET and mt/f sr instructions.
2501 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2503 * interp.c (SignalException): Don't bother restarting an
2506 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2508 * interp.c (SignalException): Really take an interrupt.
2509 (interrupt_event): Only deliver interrupts when enabled.
2511 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2513 * interp.c (sim_info): Only print info when verbose.
2514 (sim_info) Use sim_io_printf for output.
2516 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2518 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2521 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2523 * interp.c (sim_do_command): Check for common commands if a
2524 simulator specific command fails.
2526 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2528 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2529 and simBE when DEBUG is defined.
2531 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2533 * interp.c (interrupt_event): New function. Pass exception event
2534 onto exception handler.
2536 * configure.in: Check for stdlib.h.
2537 * configure: Regenerate.
2539 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2540 variable declaration.
2541 (build_instruction): Initialize memval1.
2542 (build_instruction): Add UNUSED attribute to byte, bigend,
2544 (build_operands): Ditto.
2546 * interp.c: Fix GCC warnings.
2547 (sim_get_quit_code): Delete.
2549 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2550 * Makefile.in: Ditto.
2551 * configure: Re-generate.
2553 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2555 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2557 * interp.c (mips_option_handler): New function parse argumes using
2559 (myname): Replace with STATE_MY_NAME.
2560 (sim_open): Delete check for host endianness - performed by
2562 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2563 (sim_open): Move much of the initialization from here.
2564 (sim_load): To here. After the image has been loaded and
2566 (sim_open): Move ColdReset from here.
2567 (sim_create_inferior): To here.
2568 (sim_open): Make FP check less dependant on host endianness.
2570 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2572 * interp.c (sim_set_callbacks): Delete.
2574 * interp.c (membank, membank_base, membank_size): Replace with
2575 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2576 (sim_open): Remove call to callback->init. gdb/run do this.
2580 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2582 * interp.c (big_endian_p): Delete, replaced by
2583 current_target_byte_order.
2585 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2587 * interp.c (host_read_long, host_read_word, host_swap_word,
2588 host_swap_long): Delete. Using common sim-endian.
2589 (sim_fetch_register, sim_store_register): Use H2T.
2590 (pipeline_ticks): Delete. Handled by sim-events.
2592 (sim_engine_run): Update.
2594 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2596 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2598 (SignalException): To here. Signal using sim_engine_halt.
2599 (sim_stop_reason): Delete, moved to common.
2601 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2603 * interp.c (sim_open): Add callback argument.
2604 (sim_set_callbacks): Delete SIM_DESC argument.
2607 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2609 * Makefile.in (SIM_OBJS): Add common modules.
2611 * interp.c (sim_set_callbacks): Also set SD callback.
2612 (set_endianness, xfer_*, swap_*): Delete.
2613 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2614 Change to functions using sim-endian macros.
2615 (control_c, sim_stop): Delete, use common version.
2616 (simulate): Convert into.
2617 (sim_engine_run): This function.
2618 (sim_resume): Delete.
2620 * interp.c (simulation): New variable - the simulator object.
2621 (sim_kind): Delete global - merged into simulation.
2622 (sim_load): Cleanup. Move PC assignment from here.
2623 (sim_create_inferior): To here.
2625 * sim-main.h: New file.
2626 * interp.c (sim-main.h): Include.
2628 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2630 * configure: Regenerated to track ../common/aclocal.m4 changes.
2632 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2634 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2636 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2638 * gencode.c (build_instruction): DIV instructions: check
2639 for division by zero and integer overflow before using
2640 host's division operation.
2642 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2644 * Makefile.in (SIM_OBJS): Add sim-load.o.
2645 * interp.c: #include bfd.h.
2646 (target_byte_order): Delete.
2647 (sim_kind, myname, big_endian_p): New static locals.
2648 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2649 after argument parsing. Recognize -E arg, set endianness accordingly.
2650 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2651 load file into simulator. Set PC from bfd.
2652 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2653 (set_endianness): Use big_endian_p instead of target_byte_order.
2655 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2657 * interp.c (sim_size): Delete prototype - conflicts with
2658 definition in remote-sim.h. Correct definition.
2660 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2662 * configure: Regenerated to track ../common/aclocal.m4 changes.
2665 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2667 * interp.c (sim_open): New arg `kind'.
2669 * configure: Regenerated to track ../common/aclocal.m4 changes.
2671 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2673 * configure: Regenerated to track ../common/aclocal.m4 changes.
2675 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2677 * interp.c (sim_open): Set optind to 0 before calling getopt.
2679 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2681 * configure: Regenerated to track ../common/aclocal.m4 changes.
2683 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2685 * interp.c : Replace uses of pr_addr with pr_uword64
2686 where the bit length is always 64 independent of SIM_ADDR.
2687 (pr_uword64) : added.
2689 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2691 * configure: Re-generate.
2693 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2695 * configure: Regenerate to track ../common/aclocal.m4 changes.
2697 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2699 * interp.c (sim_open): New SIM_DESC result. Argument is now
2701 (other sim_*): New SIM_DESC argument.
2703 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2705 * interp.c: Fix printing of addresses for non-64-bit targets.
2706 (pr_addr): Add function to print address based on size.
2708 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2710 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2712 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2714 * gencode.c (build_mips16_operands): Correct computation of base
2715 address for extended PC relative instruction.
2717 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2719 * interp.c (mips16_entry): Add support for floating point cases.
2720 (SignalException): Pass floating point cases to mips16_entry.
2721 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2723 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2725 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2726 and then set the state to fmt_uninterpreted.
2727 (COP_SW): Temporarily set the state to fmt_word while calling
2730 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2732 * gencode.c (build_instruction): The high order may be set in the
2733 comparison flags at any ISA level, not just ISA 4.
2735 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2737 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2738 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2739 * configure.in: sinclude ../common/aclocal.m4.
2740 * configure: Regenerated.
2742 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2744 * configure: Rebuild after change to aclocal.m4.
2746 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2748 * configure configure.in Makefile.in: Update to new configure
2749 scheme which is more compatible with WinGDB builds.
2750 * configure.in: Improve comment on how to run autoconf.
2751 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2752 * Makefile.in: Use autoconf substitution to install common
2755 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2757 * gencode.c (build_instruction): Use BigEndianCPU instead of
2760 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2762 * interp.c (sim_monitor): Make output to stdout visible in
2763 wingdb's I/O log window.
2765 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2767 * support.h: Undo previous change to SIGTRAP
2770 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2772 * interp.c (store_word, load_word): New static functions.
2773 (mips16_entry): New static function.
2774 (SignalException): Look for mips16 entry and exit instructions.
2775 (simulate): Use the correct index when setting fpr_state after
2776 doing a pending move.
2778 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2780 * interp.c: Fix byte-swapping code throughout to work on
2781 both little- and big-endian hosts.
2783 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2785 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2786 with gdb/config/i386/xm-windows.h.
2788 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2790 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2791 that messes up arithmetic shifts.
2793 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2795 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2796 SIGTRAP and SIGQUIT for _WIN32.
2798 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2800 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2801 force a 64 bit multiplication.
2802 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2803 destination register is 0, since that is the default mips16 nop
2806 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2808 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2809 (build_endian_shift): Don't check proc64.
2810 (build_instruction): Always set memval to uword64. Cast op2 to
2811 uword64 when shifting it left in memory instructions. Always use
2812 the same code for stores--don't special case proc64.
2814 * gencode.c (build_mips16_operands): Fix base PC value for PC
2816 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2818 * interp.c (simJALDELAYSLOT): Define.
2819 (JALDELAYSLOT): Define.
2820 (INDELAYSLOT, INJALDELAYSLOT): Define.
2821 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2823 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2825 * interp.c (sim_open): add flush_cache as a PMON routine
2826 (sim_monitor): handle flush_cache by ignoring it
2828 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2830 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2832 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2833 (BigEndianMem): Rename to ByteSwapMem and change sense.
2834 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2835 BigEndianMem references to !ByteSwapMem.
2836 (set_endianness): New function, with prototype.
2837 (sim_open): Call set_endianness.
2838 (sim_info): Use simBE instead of BigEndianMem.
2839 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2840 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2841 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2842 ifdefs, keeping the prototype declaration.
2843 (swap_word): Rewrite correctly.
2844 (ColdReset): Delete references to CONFIG. Delete endianness related
2845 code; moved to set_endianness.
2847 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2849 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2850 * interp.c (CHECKHILO): Define away.
2851 (simSIGINT): New macro.
2852 (membank_size): Increase from 1MB to 2MB.
2853 (control_c): New function.
2854 (sim_resume): Rename parameter signal to signal_number. Add local
2855 variable prev. Call signal before and after simulate.
2856 (sim_stop_reason): Add simSIGINT support.
2857 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2859 (sim_warning): Delete call to SignalException. Do call printf_filtered
2861 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2862 a call to sim_warning.
2864 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2866 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2867 16 bit instructions.
2869 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2871 Add support for mips16 (16 bit MIPS implementation):
2872 * gencode.c (inst_type): Add mips16 instruction encoding types.
2873 (GETDATASIZEINSN): Define.
2874 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2875 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2877 (MIPS16_DECODE): New table, for mips16 instructions.
2878 (bitmap_val): New static function.
2879 (struct mips16_op): Define.
2880 (mips16_op_table): New table, for mips16 operands.
2881 (build_mips16_operands): New static function.
2882 (process_instructions): If PC is odd, decode a mips16
2883 instruction. Break out instruction handling into new
2884 build_instruction function.
2885 (build_instruction): New static function, broken out of
2886 process_instructions. Check modifiers rather than flags for SHIFT
2887 bit count and m[ft]{hi,lo} direction.
2888 (usage): Pass program name to fprintf.
2889 (main): Remove unused variable this_option_optind. Change
2890 ``*loptarg++'' to ``loptarg++''.
2891 (my_strtoul): Parenthesize && within ||.
2892 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2893 (simulate): If PC is odd, fetch a 16 bit instruction, and
2894 increment PC by 2 rather than 4.
2895 * configure.in: Add case for mips16*-*-*.
2896 * configure: Rebuild.
2898 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2900 * interp.c: Allow -t to enable tracing in standalone simulator.
2901 Fix garbage output in trace file and error messages.
2903 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2905 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2906 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2907 * configure.in: Simplify using macros in ../common/aclocal.m4.
2908 * configure: Regenerated.
2909 * tconfig.in: New file.
2911 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2913 * interp.c: Fix bugs in 64-bit port.
2914 Use ansi function declarations for msvc compiler.
2915 Initialize and test file pointer in trace code.
2916 Prevent duplicate definition of LAST_EMED_REGNUM.
2918 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2920 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2922 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2924 * interp.c (SignalException): Check for explicit terminating
2926 * gencode.c: Pass instruction value through SignalException()
2927 calls for Trap, Breakpoint and Syscall.
2929 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2931 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2932 only used on those hosts that provide it.
2933 * configure.in: Add sqrt() to list of functions to be checked for.
2934 * config.in: Re-generated.
2935 * configure: Re-generated.
2937 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2939 * gencode.c (process_instructions): Call build_endian_shift when
2940 expanding STORE RIGHT, to fix swr.
2941 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2942 clear the high bits.
2943 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2944 Fix float to int conversions to produce signed values.
2946 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2948 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2949 (process_instructions): Correct handling of nor instruction.
2950 Correct shift count for 32 bit shift instructions. Correct sign
2951 extension for arithmetic shifts to not shift the number of bits in
2952 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2953 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2955 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2956 It's OK to have a mult follow a mult. What's not OK is to have a
2957 mult follow an mfhi.
2958 (Convert): Comment out incorrect rounding code.
2960 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2962 * interp.c (sim_monitor): Improved monitor printf
2963 simulation. Tidied up simulator warnings, and added "--log" option
2964 for directing warning message output.
2965 * gencode.c: Use sim_warning() rather than WARNING macro.
2967 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2969 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2970 getopt1.o, rather than on gencode.c. Link objects together.
2971 Don't link against -liberty.
2972 (gencode.o, getopt.o, getopt1.o): New targets.
2973 * gencode.c: Include <ctype.h> and "ansidecl.h".
2974 (AND): Undefine after including "ansidecl.h".
2975 (ULONG_MAX): Define if not defined.
2976 (OP_*): Don't define macros; now defined in opcode/mips.h.
2977 (main): Call my_strtoul rather than strtoul.
2978 (my_strtoul): New static function.
2980 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2982 * gencode.c (process_instructions): Generate word64 and uword64
2983 instead of `long long' and `unsigned long long' data types.
2984 * interp.c: #include sysdep.h to get signals, and define default
2986 * (Convert): Work around for Visual-C++ compiler bug with type
2988 * support.h: Make things compile under Visual-C++ by using
2989 __int64 instead of `long long'. Change many refs to long long
2990 into word64/uword64 typedefs.
2992 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2994 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2995 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2997 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2998 (AC_PROG_INSTALL): Added.
2999 (AC_PROG_CC): Moved to before configure.host call.
3000 * configure: Rebuilt.
3002 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3004 * configure.in: Define @SIMCONF@ depending on mips target.
3005 * configure: Rebuild.
3006 * Makefile.in (run): Add @SIMCONF@ to control simulator
3008 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3009 * interp.c: Remove some debugging, provide more detailed error
3010 messages, update memory accesses to use LOADDRMASK.
3012 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3014 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3015 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3017 * configure: Rebuild.
3018 * config.in: New file, generated by autoheader.
3019 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3020 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3021 HAVE_ANINT and HAVE_AINT, as appropriate.
3022 * Makefile.in (run): Use @LIBS@ rather than -lm.
3023 (interp.o): Depend upon config.h.
3024 (Makefile): Just rebuild Makefile.
3025 (clean): Remove stamp-h.
3026 (mostlyclean): Make the same as clean, not as distclean.
3027 (config.h, stamp-h): New targets.
3029 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3031 * interp.c (ColdReset): Fix boolean test. Make all simulator
3034 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3036 * interp.c (xfer_direct_word, xfer_direct_long,
3037 swap_direct_word, swap_direct_long, xfer_big_word,
3038 xfer_big_long, xfer_little_word, xfer_little_long,
3039 swap_word,swap_long): Added.
3040 * interp.c (ColdReset): Provide function indirection to
3041 host<->simulated_target transfer routines.
3042 * interp.c (sim_store_register, sim_fetch_register): Updated to
3043 make use of indirected transfer routines.
3045 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3047 * gencode.c (process_instructions): Ensure FP ABS instruction
3049 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3050 system call support.
3052 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3054 * interp.c (sim_do_command): Complain if callback structure not
3057 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3059 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3060 support for Sun hosts.
3061 * Makefile.in (gencode): Ensure the host compiler and libraries
3062 used for cross-hosted build.
3064 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3066 * interp.c, gencode.c: Some more (TODO) tidying.
3068 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3070 * gencode.c, interp.c: Replaced explicit long long references with
3071 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3072 * support.h (SET64LO, SET64HI): Macros added.
3074 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3076 * configure: Regenerate with autoconf 2.7.
3078 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3080 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3081 * support.h: Remove superfluous "1" from #if.
3082 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3084 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3086 * interp.c (StoreFPR): Control UndefinedResult() call on
3087 WARN_RESULT manifest.
3089 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3091 * gencode.c: Tidied instruction decoding, and added FP instruction
3094 * interp.c: Added dineroIII, and BSD profiling support. Also
3095 run-time FP handling.
3097 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3099 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3100 gencode.c, interp.c, support.h: created.