sim/mips/ChangeLog

   1 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
   2
   3         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
   4
   5 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
   6
   7         * mips.igen (check_fmt): Remove.
   8         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
   9         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
  10         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
  11         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
  12         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
  13         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
  14         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
  15         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
  16         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
  17         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
  18
  19 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
  20
  21         * sb1.igen (check_sbx): New function.
  22         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
  23
  24 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
  25             Richard Sandiford  <rsandifo@redhat.com>
  26
  27         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
  28         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
  29         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
  30         separate implementations for mipsIV and mipsV.  Use new macros to
  31         determine whether the restrictions apply.
  32
  33 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
  34
  35         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
  36         (check_mult_hilo): Improve comments.
  37         (check_div_hilo): Likewise.  Also, fork off a new version
  38         to handle mips32/mips64 (since there are no hazards to check
  39         in MIPS32/MIPS64).
  40
  41 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
  42
  43         * mips.igen (do_dmultx): Fix check for negative operands.
  44
  45 2003-05-16  Ian Lance Taylor  <ian@airs.com>
  46
  47         * Makefile.in (SHELL): Make sure this is defined.
  48         (various): Use $(SHELL) whenever we invoke move-if-change.
  49
  50 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
  51
  52         * cp1.c: Tweak attribution slightly.
  53         * cp1.h: Likewise.
  54         * mdmx.c: Likewise.
  55         * mdmx.igen: Likewise.
  56         * mips3d.igen: Likewise.
  57         * sb1.igen: Likewise.
  58
  59 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
  60
  61         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
  62         unsigned operands.
  63
  64 2003-02-27  Andrew Cagney  <cagney@redhat.com>
  65
  66         * interp.c (sim_open): Rename _bfd to bfd.
  67         (sim_create_inferior): Ditto.
  68
  69 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
  70
  71         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
  72
  73 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
  74
  75         * mips.igen (EI, DI): Remove.
  76
  77 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
  78
  79         * Makefile.in (tmp-run-multi): Fix mips16 filter.
  80
  81 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
  82             Andrew Cagney  <ac131313@redhat.com>
  83             Gavin Romig-Koch  <gavin@redhat.com>
  84             Graydon Hoare  <graydon@redhat.com>
  85             Aldy Hernandez  <aldyh@redhat.com>
  86             Dave Brolley  <brolley@redhat.com>
  87             Chris Demetriou  <cgd@broadcom.com>
  88
  89         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
  90         (sim_mach_default): New variable.
  91         (mips64vr-*-*, mips64vrel-*-*): New configurations.
  92         Add a new simulator generator, MULTI.
  93         * configure: Regenerate.
  94         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
  95         (multi-run.o): New dependency.
  96         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
  97         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
  98         (tmp-multi): Combine them.
  99         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 100         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 101         (distclean-extra): New rule.
 102         * sim-main.h: Include bfd.h.
 103         (MIPS_MACH): New macro.
 104         * mips.igen (vr4120, vr5400, vr5500): New models.
 105         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 106         * vr.igen: Replace with new version.
 107
 108 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 109
 110         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 111         * configure: Regenerate.
 112
 113 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 114
 115         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 116         * mips.igen: Remove all invocations of check_branch_bug and
 117         mark_branch_bug.
 118
 119 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 120
 121         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 122
 123 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 124
 125         * mips.igen (do_load_double, do_store_double): New functions.
 126         (LDC1, SDC1): Rename to...
 127         (LDC1b, SDC1b): respectively.
 128         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 129
 130 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 131
 132         * cp1.c (fp_recip2): Modify initialization expression so that
 133         GCC will recognize it as constant.
 134
 135 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 136
 137         * mdmx.c (SD_): Delete.
 138         (Unpredictable): Re-define, for now, to directly invoke
 139         unpredictable_action().
 140         (mdmx_acc_op): Fix error in .ob immediate handling.
 141
 142 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 143
 144         * interp.c (sim_firmware_command): Initialize `address'.
 145
 146 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 147
 148         * configure: Regenerated to track ../common/aclocal.m4 changes.
 149
 150 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 151             Ed Satterthwaite  <ehs@broadcom.com>
 152
 153         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 154         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 155         * mips.igen: Include mips3d.igen.
 156         (mips3d): New model name for MIPS-3D ASE instructions.
 157         (CVT.W.fmt): Don't use this instruction for word (source) format
 158         instructions.
 159         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 160         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 161         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 162         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 163         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 164         (RSquareRoot1, RSquareRoot2): New macros.
 165         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 166         (fp_rsqrt2): New functions.
 167         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 168         * configure: Regenerate.
 169
 170 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 171             Ed Satterthwaite  <ehs@broadcom.com>
 172
 173         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 174         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 175         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 176         (convert): Note that this function is not used for paired-single
 177         format conversions.
 178         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 179         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 180         (check_fmt_p): Enable paired-single support.
 181         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 182         (PUU.PS): New instructions.
 183         (CVT.S.fmt): Don't use this instruction for paired-single format
 184         destinations.
 185         * sim-main.h (FP_formats): New value 'fmt_ps.'
 186         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 187         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 188
 189 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 190
 191         * mips.igen: Fix formatting of function calls in
 192         many FP operations.
 193
 194 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 195
 196         * mips.igen (MOVN, MOVZ): Trace result.
 197         (TNEI): Print "tnei" as the opcode name in traces.
 198         (CEIL.W): Add disassembly string for traces.
 199         (RSQRT.fmt): Make location of disassembly string consistent
 200         with other instructions.
 201
 202 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 203
 204         * mips.igen (X): Delete unused function.
 205
 206 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 207
 208         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 209
 210 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 211             Ed Satterthwaite  <ehs@broadcom.com>
 212
 213         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 214         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 215         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 216         (fp_nmsub): New prototypes.
 217         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 218         (NegMultiplySub): New defines.
 219         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 220         (MADD.D, MADD.S): Replace with...
 221         (MADD.fmt): New instruction.
 222         (MSUB.D, MSUB.S): Replace with...
 223         (MSUB.fmt): New instruction.
 224         (NMADD.D, NMADD.S): Replace with...
 225         (NMADD.fmt): New instruction.
 226         (NMSUB.D, MSUB.S): Replace with...
 227         (NMSUB.fmt): New instruction.
 228
 229 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 230             Ed Satterthwaite  <ehs@broadcom.com>
 231
 232         * cp1.c: Fix more comment spelling and formatting.
 233         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 234         (denorm_mode): New function.
 235         (fpu_unary, fpu_binary): Round results after operation, collect
 236         status from rounding operations, and update the FCSR.
 237         (convert): Collect status from integer conversions and rounding
 238         operations, and update the FCSR.  Adjust NaN values that result
 239         from conversions.  Convert to use sim_io_eprintf rather than
 240         fprintf, and remove some debugging code.
 241         * cp1.h (fenr_FS): New define.
 242
 243 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 244
 245         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 246         rounding mode to sim FP rounding mode flag conversion code into...
 247         (rounding_mode): New function.
 248
 249 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 250
 251         * cp1.c: Clean up formatting of a few comments.
 252         (value_fpr): Reformat switch statement.
 253
 254 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 255             Ed Satterthwaite  <ehs@broadcom.com>
 256
 257         * cp1.h: New file.
 258         * sim-main.h: Include cp1.h.
 259         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 260         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 261         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 262         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 263         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 264         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 265         * cp1.c: Don't include sim-fpu.h; already included by
 266         sim-main.h.  Clean up formatting of some comments.
 267         (NaN, Equal, Less): Remove.
 268         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 269         (fp_cmp): New functions.
 270         * mips.igen (do_c_cond_fmt): Remove.
 271         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 272         Compare.  Add result tracing.
 273         (CxC1): Remove, replace with...
 274         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 275         (DMxC1): Remove, replace with...
 276         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 277         (MxC1): Remove, replace with...
 278         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 279
 280 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 281
 282         * sim-main.h (FGRIDX): Remove, replace all uses with...
 283         (FGR_BASE): New macro.
 284         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 285         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 286         (NR_FGR, FGR): Likewise.
 287         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 288         * mips.igen: Likewise.
 289
 290 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 291
 292         * cp1.c: Add an FSF Copyright notice to this file.
 293
 294 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 295             Ed Satterthwaite  <ehs@broadcom.com>
 296
 297         * cp1.c (Infinity): Remove.
 298         * sim-main.h (Infinity): Likewise.
 299
 300         * cp1.c (fp_unary, fp_binary): New functions.
 301         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 302         (fp_sqrt): New functions, implemented in terms of the above.
 303         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 304         (Recip, SquareRoot): Remove (replaced by functions above).
 305         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 306         (fp_recip, fp_sqrt): New prototypes.
 307         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 308         (Recip, SquareRoot): Replace prototypes with #defines which
 309         invoke the functions above.
 310
 311 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 312
 313         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 314         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 315         file, remove PARAMS from prototypes.
 316         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 317         simulator state arguments.
 318         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 319         pass simulator state arguments.
 320         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 321         (store_fpr, convert): Remove 'sd' argument.
 322         (value_fpr): Likewise.  Convert to use 'SD' instead.
 323
 324 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 325
 326         * cp1.c (Min, Max): Remove #if 0'd functions.
 327         * sim-main.h (Min, Max): Remove.
 328
 329 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 330
 331         * cp1.c: fix formatting of switch case and default labels.
 332         * interp.c: Likewise.
 333         * sim-main.c: Likewise.
 334
 335 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 336
 337         * cp1.c: Clean up comments which describe FP formats.
 338          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 339
 340 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 341             Ed Satterthwaite  <ehs@broadcom.com>
 342
 343         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 344         Broadcom SiByte SB-1 processor configurations.
 345         * configure: Regenerate.
 346         * sb1.igen: New file.
 347         * mips.igen: Include sb1.igen.
 348         (sb1): New model.
 349         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 350         * mdmx.igen: Add "sb1" model to all appropriate functions and
 351         instructions.
 352         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 353         (ob_func, ob_acc): Reference the above.
 354         (qh_acc): Adjust to keep the same size as ob_acc.
 355         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 356         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 357
 358 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 359
 360         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 361
 362 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 363             Ed Satterthwaite  <ehs@broadcom.com>
 364
 365         * mips.igen (mdmx): New (pseudo-)model.
 366         * mdmx.c, mdmx.igen: New files.
 367         * Makefile.in (SIM_OBJS): Add mdmx.o.
 368         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 369         New typedefs.
 370         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 371         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 372         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 373         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 374         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 375         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 376         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 377         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 378         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 379         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 380         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 381         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 382         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 383         (qh_fmtsel): New macros.
 384         (_sim_cpu): New member "acc".
 385         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 386         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 387
 388 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 389
 390         * interp.c: Use 'deprecated' rather than 'depreciated.'
 391         * sim-main.h: Likewise.
 392
 393 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 394
 395         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 396         which wouldn't compile anyway.
 397         * sim-main.h (unpredictable_action): New function prototype.
 398         (Unpredictable): Define to call igen function unpredictable().
 399         (NotWordValue): New macro to call igen function not_word_value().
 400         (UndefinedResult): Remove.
 401         * interp.c (undefined_result): Remove.
 402         (unpredictable_action): New function.
 403         * mips.igen (not_word_value, unpredictable): New functions.
 404         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 405         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 406         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 407         NotWordValue() to check for unpredictable inputs, then
 408         Unpredictable() to handle them.
 409
 410 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 411
 412         * mips.igen: Fix formatting of calls to Unpredictable().
 413
 414 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 415
 416         * interp.c (sim_open): Revert previous change.
 417
 418 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 419
 420         * interp.c (sim_open): Disable chunk of code that wrote code in
 421         vector table entries.
 422
 423 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 424
 425         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 426         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 427         unused definitions.
 428
 429 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 430
 431         * cp1.c: Fix many formatting issues.
 432
 433 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 434
 435         * cp1.c (fpu_format_name): New function to replace...
 436         (DOFMT): This.  Delete, and update all callers.
 437         (fpu_rounding_mode_name): New function to replace...
 438         (RMMODE): This.  Delete, and update all callers.
 439
 440 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 441
 442         * interp.c: Move FPU support routines from here to...
 443         * cp1.c: Here.  New file.
 444         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 445         (cp1.o): New target.
 446
 447 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 448
 449         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 450         * mips.igen (mips32, mips64): New models, add to all instructions
 451         and functions as appropriate.
 452         (loadstore_ea, check_u64): New variant for model mips64.
 453         (check_fmt_p): New variant for models mipsV and mips64, remove
 454         mipsV model marking fro other variant.
 455         (SLL) Rename to...
 456         (SLLa) this.
 457         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 458         for mips32 and mips64.
 459         (DCLO, DCLZ): New instructions for mips64.
 460
 461 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 462
 463         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 464         immediate or code as a hex value with the "%#lx" format.
 465         (ANDI): Likewise, and fix printed instruction name.
 466
 467 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 468
 469         * sim-main.h (UndefinedResult, Unpredictable): New macros
 470         which currently do nothing.
 471
 472 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 473
 474         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 475         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 476         (status_CU3): New definitions.
 477
 478         * sim-main.h (ExceptionCause): Add new values for MIPS32
 479         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 480         for DebugBreakPoint and NMIReset to note their status in
 481         MIPS32 and MIPS64.
 482         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 483         (SignalExceptionCacheErr): New exception macros.
 484
 485 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 486
 487         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 488         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 489         is always enabled.
 490         (SignalExceptionCoProcessorUnusable): Take as argument the
 491         unusable coprocessor number.
 492
 493 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 494
 495         * mips.igen: Fix formatting of all SignalException calls.
 496
 497 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 498
 499         * sim-main.h (SIGNEXTEND): Remove.
 500
 501 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 502
 503         * mips.igen: Remove gencode comment from top of file, fix
 504         spelling in another comment.
 505
 506 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 507
 508         * mips.igen (check_fmt, check_fmt_p): New functions to check
 509         whether specific floating point formats are usable.
 510         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 511         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 512         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 513         Use the new functions.
 514         (do_c_cond_fmt): Remove format checks...
 515         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 516
 517 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 518
 519         * mips.igen: Fix formatting of check_fpu calls.
 520
 521 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 522
 523         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 524
 525 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 526
 527         * mips.igen: Remove whitespace at end of lines.
 528
 529 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 530
 531         * mips.igen (loadstore_ea): New function to do effective
 532         address calculations.
 533         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 534         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 535         CACHE): Use loadstore_ea to do effective address computations.
 536
 537 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 538
 539         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 540         * mips.igen (LL, CxC1, MxC1): Likewise.
 541
 542 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 543
 544         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 545         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 546         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 547         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 548         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 549         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 550         Don't split opcode fields by hand, use the opcode field values
 551         provided by igen.
 552
 553 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 554
 555         * mips.igen (do_divu): Fix spacing.
 556
 557         * mips.igen (do_dsllv): Move to be right before DSLLV,
 558         to match the rest of the do_<shift> functions.
 559
 560 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 561
 562         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 563         DSRL32, do_dsrlv): Trace inputs and results.
 564
 565 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 566
 567         * mips.igen (CACHE): Provide instruction-printing string.
 568
 569         * interp.c (signal_exception): Comment tokens after #endif.
 570
 571 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 572
 573         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 574         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 575         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 576         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 577         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 578         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 579         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 580         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 581
 582 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 583
 584         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 585         instruction-printing string.
 586         (LWU): Use '64' as the filter flag.
 587
 588 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 589
 590         * mips.igen (SDXC1): Fix instruction-printing string.
 591
 592 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 593
 594         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 595         filter flags "32,f".
 596
 597 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 598
 599         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 600         as the filter flag.
 601
 602 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 603
 604         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 605         add a comma) so that it more closely match the MIPS ISA
 606         documentation opcode partitioning.
 607         (PREF): Put useful names on opcode fields, and include
 608         instruction-printing string.
 609
 610 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 611
 612         * mips.igen (check_u64): New function which in the future will
 613         check whether 64-bit instructions are usable and signal an
 614         exception if not.  Currently a no-op.
 615         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 616         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 617         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 618         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 619
 620         * mips.igen (check_fpu): New function which in the future will
 621         check whether FPU instructions are usable and signal an exception
 622         if not.  Currently a no-op.
 623         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 624         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 625         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 626         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 627         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 628         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 629         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 630         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 631
 632 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 633
 634         * mips.igen (do_load_left, do_load_right): Move to be immediately
 635         following do_load.
 636         (do_store_left, do_store_right): Move to be immediately following
 637         do_store.
 638
 639 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 640
 641         * mips.igen (mipsV): New model name.  Also, add it to
 642         all instructions and functions where it is appropriate.
 643
 644 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 645
 646         * mips.igen: For all functions and instructions, list model
 647         names that support that instruction one per line.
 648
 649 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 650
 651         * mips.igen: Add some additional comments about supported
 652         models, and about which instructions go where.
 653         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 654         order as is used in the rest of the file.
 655
 656 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 657
 658         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 659         indicating that ALU32_END or ALU64_END are there to check
 660         for overflow.
 661         (DADD): Likewise, but also remove previous comment about
 662         overflow checking.
 663
 664 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 665
 666         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 667         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 668         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 669         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 670         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 671         fields (i.e., add and move commas) so that they more closely
 672         match the MIPS ISA documentation opcode partitioning.
 673
 674 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 675
 676         * mips.igen (ADDI): Print immediate value.
 677         (BREAK): Print code.
 678         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 679         (SLL): Print "nop" specially, and don't run the code
 680         that does the shift for the "nop" case.
 681
 682 2001-11-17  Fred Fish  <fnf@redhat.com>
 683
 684         * sim-main.h (float_operation): Move enum declaration outside
 685         of _sim_cpu struct declaration.
 686
 687 2001-04-12  Jim Blandy  <jimb@redhat.com>
 688
 689         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 690         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 691         set of the FCSR.
 692         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 693         PENDING_FILL, and you can get the intended effect gracefully by
 694         calling PENDING_SCHED directly.
 695
 696 2001-02-23  Ben Elliston  <bje@redhat.com>
 697
 698         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 699         already defined elsewhere.
 700
 701 2001-02-19  Ben Elliston  <bje@redhat.com>
 702
 703         * sim-main.h (sim_monitor): Return an int.
 704         * interp.c (sim_monitor): Add return values.
 705         (signal_exception): Handle error conditions from sim_monitor.
 706
 707 2001-02-08  Ben Elliston  <bje@redhat.com>
 708
 709         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 710         (store_memory): Likewise, pass cia to sim_core_write*.
 711
 712 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 713
 714         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 715         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 716
 717 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 718
 719         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 720         * Makefile.in: Don't delete *.igen when cleaning directory.
 721
 722 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 723
 724         * m16.igen (break): Call SignalException not sim_engine_halt.
 725
 726 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 727
 728         From Jason Eckhardt:
 729         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 730
 731 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 732
 733         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 734
 735 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 736
 737         * mips.igen (do_dmultx): Fix typo.
 738
 739 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 740
 741         * configure: Regenerated to track ../common/aclocal.m4 changes.
 742
 743 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 744
 745         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 746
 747 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 748
 749         * sim-main.h (GPR_CLEAR): Define macro.
 750
 751 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 752
 753         * interp.c (decode_coproc): Output long using %lx and not %s.
 754
 755 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 756
 757         * interp.c (sim_open): Sort & extend dummy memory regions for
 758         --board=jmr3904 for eCos.
 759
 760 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 761
 762         * configure: Regenerated.
 763
 764 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 765
 766         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 767         calls, conditional on the simulator being in verbose mode.
 768
 769 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 770
 771         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 772         cache don't get ReservedInstruction traps.
 773
 774 1999-11-29  Mark Salter  <msalter@cygnus.com>
 775
 776         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 777         to clear status bits in sdisr register. This is how the hardware works.
 778
 779         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 780         being used by cygmon.
 781
 782 1999-11-11  Andrew Haley  <aph@cygnus.com>
 783
 784         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 785         instructions.
 786
 787 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 788
 789         * mips.igen (MULT): Correct previous mis-applied patch.
 790
 791 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 792
 793         * mips.igen (delayslot32): Handle sequence like
 794         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 795         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 796         (MULT): Actually pass the third register...
 797
 798 1999-09-03  Mark Salter  <msalter@cygnus.com>
 799
 800         * interp.c (sim_open): Added more memory aliases for additional
 801         hardware being touched by cygmon on jmr3904 board.
 802
 803 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 804
 805         * configure: Regenerated to track ../common/aclocal.m4 changes.
 806
 807 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 808
 809         * interp.c (sim_store_register): Handle case where client - GDB -
 810         specifies that a 4 byte register is 8 bytes in size.
 811         (sim_fetch_register): Ditto.
 812
 813 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 814
 815         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 816         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 817         (idt_monitor_base): Base address for IDT monitor traps.
 818         (pmon_monitor_base): Ditto for PMON.
 819         (lsipmon_monitor_base): Ditto for LSI PMON.
 820         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 821         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 822         (sim_firmware_command): New function.
 823         (mips_option_handler): Call it for OPTION_FIRMWARE.
 824         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 825         option was given, add no monitor by default.  Add BREAK hooks only if
 826         monitors are also there.
 827
 828 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 829
 830         * interp.c (sim_monitor): Flush output before reading input.
 831
 832 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 833
 834         * tconfig.in (SIM_HANDLES_LMA): Always define.
 835
 836 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 837
 838         From Mark Salter <msalter@cygnus.com>:
 839         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 840         (sim_open): Add setup for BSP board.
 841
 842 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 843
 844         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 845         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 846         them as unimplemented.
 847
 848 1999-05-08  Felix Lee  <flee@cygnus.com>
 849
 850         * configure: Regenerated to track ../common/aclocal.m4 changes.
 851
 852 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 853
 854         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 855
 856 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 857
 858         * configure.in: Any mips64vr5*-*-* target should have
 859         -DTARGET_ENABLE_FR=1.
 860         (default_endian): Any mips64vr*el-*-* target should default to
 861         LITTLE_ENDIAN.
 862         * configure: Re-generate.
 863
 864 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 865
 866         * mips.igen (ldl): Extend from _16_, not 32.
 867
 868 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 869
 870         * interp.c (sim_store_register): Force registers written to by GDB
 871         into an un-interpreted state.
 872
 873 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 874
 875         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 876         CPU, start periodic background I/O polls.
 877         (tx3904sio_poll): New function: periodic I/O poller.
 878
 879 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 880
 881         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 882
 883 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 884
 885         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 886         case statement.
 887
 888 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 889
 890         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 891         (load_word): Call SIM_CORE_SIGNAL hook on error.
 892         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 893         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 894         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 895         * sim-main.h (COP0_BADVADDR): Define.
 896         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 897         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 898         (_sim_cpu): Add exc_* fields to store register value snapshots.
 899         * mips.igen (*): Replace memory-related SignalException* calls
 900         with references to SIM_CORE_SIGNAL hook.
 901
 902         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 903         fix.
 904         * sim-main.c (*): Minor warning cleanups.
 905
 906 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 907
 908         * m16.igen (DADDIU5): Correct type-o.
 909
 910 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 911
 912         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 913         variables.
 914
 915 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 916
 917         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 918         to include path.
 919         (interp.o): Add dependency on itable.h
 920         (oengine.c, gencode): Delete remaining references.
 921         (BUILT_SRC_FROM_GEN): Clean up.
 922
 923 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 924
 925         * vr4run.c: New.
 926         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 927         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 928         tmp-run-hack) : New.
 929         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 930         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 931         Drop the "64" qualifier to get the HACK generator working.
 932         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 933         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 934         qualifier to get the hack generator working.
 935         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 936         (DSLL): Use do_dsll.
 937         (DSLLV): Use do_dsllv.
 938         (DSRA): Use do_dsra.
 939         (DSRL): Use do_dsrl.
 940         (DSRLV): Use do_dsrlv.
 941         (BC1): Move *vr4100 to get the HACK generator working.
 942         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 943         get the HACK generator working.
 944         (MACC) Rename to get the HACK generator working.
 945         (DMACC,MACCS,DMACCS): Add the 64.
 946
 947 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 948
 949         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 950         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 951
 952 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 953
 954     * mips/interp.c (DEBUG): Cleanups.
 955
 956 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 957
 958         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 959         (tx3904sio_tickle): fflush after a stdout character output.
 960
 961 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 962
 963         * interp.c (sim_close): Uninstall modules.
 964
 965 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 966
 967         * sim-main.h, interp.c (sim_monitor): Change to global
 968         function.
 969
 970 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 971
 972         * configure.in (vr4100): Only include vr4100 instructions in
 973         simulator.
 974         * configure: Re-generate.
 975         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 976
 977 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 978
 979         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 980         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 981         true alternative.
 982
 983         * configure.in (sim_default_gen, sim_use_gen): Replace with
 984         sim_gen.
 985         (--enable-sim-igen): Delete config option. Always using IGEN.
 986         * configure: Re-generate.
 987
 988         * Makefile.in (gencode): Kill, kill, kill.
 989         * gencode.c: Ditto.
 990
 991 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 992
 993         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 994         bit mips16 igen simulator.
 995         * configure: Re-generate.
 996
 997         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 998         as part of vr4100 ISA.
 999         * vr.igen: Mark all instructions as 64 bit only.
1000
1001 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1002
1003         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1004         Pacify GCC.
1005
1006 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1007
1008         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1009         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1010         * configure: Re-generate.
1011
1012         * m16.igen (BREAK): Define breakpoint instruction.
1013         (JALX32): Mark instruction as mips16 and not r3900.
1014         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1015
1016         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1017
1018 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1019
1020         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1021         insn as a debug breakpoint.
1022
1023         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1024         pending.slot_size.
1025         (PENDING_SCHED): Clean up trace statement.
1026         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1027         (PENDING_FILL): Delay write by only one cycle.
1028         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1029
1030         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1031         of pending writes.
1032         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1033         32 & 64.
1034         (pending_tick): Move incrementing of index to FOR statement.
1035         (pending_tick): Only update PENDING_OUT after a write has occured.
1036
1037         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1038         build simulator.
1039         * configure: Re-generate.
1040
1041         * interp.c (sim_engine_run OLD): Delete explicit call to
1042         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1043
1044 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1045
1046         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1047         interrupt level number to match changed SignalExceptionInterrupt
1048         macro.
1049
1050 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1051
1052         * interp.c: #include "itable.h" if WITH_IGEN.
1053         (get_insn_name): New function.
1054         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1055         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1056
1057 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1058
1059         * configure: Rebuilt to inhale new common/aclocal.m4.
1060
1061 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1062
1063         * dv-tx3904sio.c: Include sim-assert.h.
1064
1065 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1066
1067         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1068         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1069         Reorganize target-specific sim-hardware checks.
1070         * configure: rebuilt.
1071         * interp.c (sim_open): For tx39 target boards, set
1072         OPERATING_ENVIRONMENT, add tx3904sio devices.
1073         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1074         ROM executables.  Install dv-sockser into sim-modules list.
1075
1076         * dv-tx3904irc.c: Compiler warning clean-up.
1077         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1078         frequent hw-trace messages.
1079
1080 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1081
1082         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1083
1084 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1085
1086         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1087
1088         * vr.igen: New file.
1089         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1090         * mips.igen: Define vr4100 model. Include vr.igen.
1091 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1092
1093         * mips.igen (check_mf_hilo): Correct check.
1094
1095 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1096
1097         * sim-main.h (interrupt_event): Add prototype.
1098
1099         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1100         register_ptr, register_value.
1101         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1102
1103         * sim-main.h (tracefh): Make extern.
1104
1105 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1106
1107         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1108         Reduce unnecessarily high timer event frequency.
1109         * dv-tx3904cpu.c: Ditto for interrupt event.
1110
1111 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1112
1113         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1114         to allay warnings.
1115         (interrupt_event): Made non-static.
1116
1117         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1118         interchange of configuration values for external vs. internal
1119         clock dividers.
1120
1121 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1122
1123         * mips.igen (BREAK): Moved code to here for
1124         simulator-reserved break instructions.
1125         * gencode.c (build_instruction): Ditto.
1126         * interp.c (signal_exception): Code moved from here.  Non-
1127         reserved instructions now use exception vector, rather
1128         than halting sim.
1129         * sim-main.h: Moved magic constants to here.
1130
1131 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1132
1133         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1134         register upon non-zero interrupt event level, clear upon zero
1135         event value.
1136         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1137         by passing zero event value.
1138         (*_io_{read,write}_buffer): Endianness fixes.
1139         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1140         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1141
1142         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1143         serial I/O and timer module at base address 0xFFFF0000.
1144
1145 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1146
1147         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1148         and BigEndianCPU.
1149
1150 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1151
1152         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1153         parts.
1154         * configure: Update.
1155
1156 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1157
1158         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1159         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1160         * configure.in: Include tx3904tmr in hw_device list.
1161         * configure: Rebuilt.
1162         * interp.c (sim_open): Instantiate three timer instances.
1163         Fix address typo of tx3904irc instance.
1164
1165 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1166
1167         * interp.c (signal_exception): SystemCall exception now uses
1168         the exception vector.
1169
1170 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1171
1172         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1173         to allay warnings.
1174
1175 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1176
1177         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1178
1179 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1180
1181         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1182
1183         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1184         sim-main.h. Declare a struct hw_descriptor instead of struct
1185         hw_device_descriptor.
1186
1187 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1188
1189         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1190         right bits and then re-align left hand bytes to correct byte
1191         lanes.  Fix incorrect computation in do_store_left when loading
1192         bytes from second word.
1193
1194 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1195
1196         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1197         * interp.c (sim_open): Only create a device tree when HW is
1198         enabled.
1199
1200         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1201         * interp.c (signal_exception): Ditto.
1202
1203 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1204
1205         * gencode.c: Mark BEGEZALL as LIKELY.
1206
1207 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1208
1209         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1210         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1211
1212 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1213
1214         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1215         modules.  Recognize TX39 target with "mips*tx39" pattern.
1216         * configure: Rebuilt.
1217         * sim-main.h (*): Added many macros defining bits in
1218         TX39 control registers.
1219         (SignalInterrupt): Send actual PC instead of NULL.
1220         (SignalNMIReset): New exception type.
1221         * interp.c (board): New variable for future use to identify
1222         a particular board being simulated.
1223         (mips_option_handler,mips_options): Added "--board" option.
1224         (interrupt_event): Send actual PC.
1225         (sim_open): Make memory layout conditional on board setting.
1226         (signal_exception): Initial implementation of hardware interrupt
1227         handling.  Accept another break instruction variant for simulator
1228         exit.
1229         (decode_coproc): Implement RFE instruction for TX39.
1230         (mips.igen): Decode RFE instruction as such.
1231         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1232         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1233         bbegin to implement memory map.
1234         * dv-tx3904cpu.c: New file.
1235         * dv-tx3904irc.c: New file.
1236
1237 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1238
1239         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1240
1241 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1242
1243         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1244         with calls to check_div_hilo.
1245
1246 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1247
1248         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1249         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1250         Add special r3900 version of do_mult_hilo.
1251         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1252         with calls to check_mult_hilo.
1253         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1254         with calls to check_div_hilo.
1255
1256 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1257
1258         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1259         Document a replacement.
1260
1261 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1262
1263         * interp.c (sim_monitor): Make mon_printf work.
1264
1265 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1266
1267         * sim-main.h (INSN_NAME): New arg `cpu'.
1268
1269 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1270
1271         * configure: Regenerated to track ../common/aclocal.m4 changes.
1272
1273 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1274
1275         * configure: Regenerated to track ../common/aclocal.m4 changes.
1276         * config.in: Ditto.
1277
1278 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1279
1280         * acconfig.h: New file.
1281         * configure.in: Reverted change of Apr 24; use sinclude again.
1282
1283 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1284
1285         * configure: Regenerated to track ../common/aclocal.m4 changes.
1286         * config.in: Ditto.
1287
1288 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1289
1290         * configure.in: Don't call sinclude.
1291
1292 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1293
1294         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1295
1296 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1297
1298         * mips.igen (ERET): Implement.
1299
1300         * interp.c (decode_coproc): Return sign-extended EPC.
1301
1302         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1303
1304         * interp.c (signal_exception): Do not ignore Trap.
1305         (signal_exception): On TRAP, restart at exception address.
1306         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1307         (signal_exception): Update.
1308         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1309         so that TRAP instructions are caught.
1310
1311 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1312
1313         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1314         contains HI/LO access history.
1315         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1316         (HIACCESS, LOACCESS): Delete, replace with
1317         (HIHISTORY, LOHISTORY): New macros.
1318         (CHECKHILO): Delete all, moved to mips.igen
1319
1320         * gencode.c (build_instruction): Do not generate checks for
1321         correct HI/LO register usage.
1322
1323         * interp.c (old_engine_run): Delete checks for correct HI/LO
1324         register usage.
1325
1326         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1327         check_mf_cycles): New functions.
1328         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1329         do_divu, domultx, do_mult, do_multu): Use.
1330
1331         * tx.igen ("madd", "maddu"): Use.
1332
1333 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1334
1335         * mips.igen (DSRAV): Use function do_dsrav.
1336         (SRAV): Use new function do_srav.
1337
1338         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1339         (B): Sign extend 11 bit immediate.
1340         (EXT-B*): Shift 16 bit immediate left by 1.
1341         (ADDIU*): Don't sign extend immediate value.
1342
1343 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1344
1345         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1346
1347         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1348         functions.
1349
1350         * mips.igen (delayslot32, nullify_next_insn): New functions.
1351         (m16.igen): Always include.
1352         (do_*): Add more tracing.
1353
1354         * m16.igen (delayslot16): Add NIA argument, could be called by a
1355         32 bit MIPS16 instruction.
1356
1357         * interp.c (ifetch16): Move function from here.
1358         * sim-main.c (ifetch16): To here.
1359
1360         * sim-main.c (ifetch16, ifetch32): Update to match current
1361         implementations of LH, LW.
1362         (signal_exception): Don't print out incorrect hex value of illegal
1363         instruction.
1364
1365 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1366
1367         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1368         instruction.
1369
1370         * m16.igen: Implement MIPS16 instructions.
1371
1372         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1373         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1374         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1375         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1376         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1377         bodies of corresponding code from 32 bit insn to these.  Also used
1378         by MIPS16 versions of functions.
1379
1380         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1381         (IMEM16): Drop NR argument from macro.
1382
1383 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1384
1385         * Makefile.in (SIM_OBJS): Add sim-main.o.
1386
1387         * sim-main.h (address_translation, load_memory, store_memory,
1388         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1389         as INLINE_SIM_MAIN.
1390         (pr_addr, pr_uword64): Declare.
1391         (sim-main.c): Include when H_REVEALS_MODULE_P.
1392
1393         * interp.c (address_translation, load_memory, store_memory,
1394         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1395         from here.
1396         * sim-main.c: To here. Fix compilation problems.
1397
1398         * configure.in: Enable inlining.
1399         * configure: Re-config.
1400
1401 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1402
1403         * configure: Regenerated to track ../common/aclocal.m4 changes.
1404
1405 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1406
1407         * mips.igen: Include tx.igen.
1408         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1409         * tx.igen: New file, contains MADD and MADDU.
1410
1411         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1412         the hardwired constant `7'.
1413         (store_memory): Ditto.
1414         (LOADDRMASK): Move definition to sim-main.h.
1415
1416         mips.igen (MTC0): Enable for r3900.
1417         (ADDU): Add trace.
1418
1419         mips.igen (do_load_byte): Delete.
1420         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1421         do_store_right): New functions.
1422         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1423
1424         configure.in: Let the tx39 use igen again.
1425         configure: Update.
1426
1427 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1428
1429         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1430         not an address sized quantity.  Return zero for cache sizes.
1431
1432 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1433
1434         * mips.igen (r3900): r3900 does not support 64 bit integer
1435         operations.
1436
1437 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1438
1439         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1440         than igen one.
1441         * configure : Rebuild.
1442
1443 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1444
1445         * configure: Regenerated to track ../common/aclocal.m4 changes.
1446
1447 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1448
1449         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1450
1451 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1452
1453         * configure: Regenerated to track ../common/aclocal.m4 changes.
1454         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1455
1456 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1457
1458         * configure: Regenerated to track ../common/aclocal.m4 changes.
1459
1460 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1461
1462         * interp.c (Max, Min): Comment out functions. Not yet used.
1463
1464 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1465
1466         * configure: Regenerated to track ../common/aclocal.m4 changes.
1467
1468 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1469
1470         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1471         configurable settings for stand-alone simulator.
1472
1473         * configure.in: Added X11 search, just in case.
1474
1475         * configure: Regenerated.
1476
1477 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1478
1479         * interp.c (sim_write, sim_read, load_memory, store_memory):
1480         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1481
1482 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1483
1484         * sim-main.h (GETFCC): Return an unsigned value.
1485
1486 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1487
1488         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1489         (DADD): Result destination is RD not RT.
1490
1491 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1492
1493         * sim-main.h (HIACCESS, LOACCESS): Always define.
1494
1495         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1496
1497         * interp.c (sim_info): Delete.
1498
1499 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1500
1501         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1502         (mips_option_handler): New argument `cpu'.
1503         (sim_open): Update call to sim_add_option_table.
1504
1505 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1506
1507         * mips.igen (CxC1): Add tracing.
1508
1509 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1510
1511         * sim-main.h (Max, Min): Declare.
1512
1513         * interp.c (Max, Min): New functions.
1514
1515         * mips.igen (BC1): Add tracing.
1516
1517 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1518
1519         * interp.c Added memory map for stack in vr4100
1520
1521 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1522
1523         * interp.c (load_memory): Add missing "break"'s.
1524
1525 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1526
1527         * interp.c (sim_store_register, sim_fetch_register): Pass in
1528         length parameter.  Return -1.
1529
1530 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1531
1532         * interp.c: Added hardware init hook, fixed warnings.
1533
1534 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1535
1536         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1537
1538 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1539
1540         * interp.c (ifetch16): New function.
1541
1542         * sim-main.h (IMEM32): Rename IMEM.
1543         (IMEM16_IMMED): Define.
1544         (IMEM16): Define.
1545         (DELAY_SLOT): Update.
1546
1547         * m16run.c (sim_engine_run): New file.
1548
1549         * m16.igen: All instructions except LB.
1550         (LB): Call do_load_byte.
1551         * mips.igen (do_load_byte): New function.
1552         (LB): Call do_load_byte.
1553
1554         * mips.igen: Move spec for insn bit size and high bit from here.
1555         * Makefile.in (tmp-igen, tmp-m16): To here.
1556
1557         * m16.dc: New file, decode mips16 instructions.
1558
1559         * Makefile.in (SIM_NO_ALL): Define.
1560         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1561
1562 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1563
1564         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1565         point unit to 32 bit registers.
1566         * configure: Re-generate.
1567
1568 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1569
1570         * configure.in (sim_use_gen): Make IGEN the default simulator
1571         generator for generic 32 and 64 bit mips targets.
1572         * configure: Re-generate.
1573
1574 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1575
1576         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1577         bitsize.
1578
1579         * interp.c (sim_fetch_register, sim_store_register): Read/write
1580         FGR from correct location.
1581         (sim_open): Set size of FGR's according to
1582         WITH_TARGET_FLOATING_POINT_BITSIZE.
1583
1584         * sim-main.h (FGR): Store floating point registers in a separate
1585         array.
1586
1587 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1588
1589         * configure: Regenerated to track ../common/aclocal.m4 changes.
1590
1591 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1592
1593         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1594
1595         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1596
1597         * interp.c (pending_tick): New function.  Deliver pending writes.
1598
1599         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1600         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1601         it can handle mixed sized quantites and single bits.
1602
1603 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1604
1605         * interp.c (oengine.h): Do not include when building with IGEN.
1606         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1607         (sim_info): Ditto for PROCESSOR_64BIT.
1608         (sim_monitor): Replace ut_reg with unsigned_word.
1609         (*): Ditto for t_reg.
1610         (LOADDRMASK): Define.
1611         (sim_open): Remove defunct check that host FP is IEEE compliant,
1612         using software to emulate floating point.
1613         (value_fpr, ...): Always compile, was conditional on HASFPU.
1614
1615 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1616
1617         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1618         size.
1619
1620         * interp.c (SD, CPU): Define.
1621         (mips_option_handler): Set flags in each CPU.
1622         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1623         (sim_close): Do not clear STATE, deleted anyway.
1624         (sim_write, sim_read): Assume CPU zero's vm should be used for
1625         data transfers.
1626         (sim_create_inferior): Set the PC for all processors.
1627         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1628         argument.
1629         (mips16_entry): Pass correct nr of args to store_word, load_word.
1630         (ColdReset): Cold reset all cpu's.
1631         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1632         (sim_monitor, load_memory, store_memory, signal_exception): Use
1633         `CPU' instead of STATE_CPU.
1634
1635
1636         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1637         SD or CPU_.
1638
1639         * sim-main.h (signal_exception): Add sim_cpu arg.
1640         (SignalException*): Pass both SD and CPU to signal_exception.
1641         * interp.c (signal_exception): Update.
1642
1643         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1644         Ditto
1645         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1646         address_translation): Ditto
1647         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1648
1649 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1650
1651         * configure: Regenerated to track ../common/aclocal.m4 changes.
1652
1653 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1654
1655         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1656
1657         * mips.igen (model): Map processor names onto BFD name.
1658
1659         * sim-main.h (CPU_CIA): Delete.
1660         (SET_CIA, GET_CIA): Define
1661
1662 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1663
1664         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1665         regiser.
1666
1667         * configure.in (default_endian): Configure a big-endian simulator
1668         by default.
1669         * configure: Re-generate.
1670
1671 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1672
1673         * configure: Regenerated to track ../common/aclocal.m4 changes.
1674
1675 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1676
1677         * interp.c (sim_monitor): Handle Densan monitor outbyte
1678         and inbyte functions.
1679
1680 1997-12-29  Felix Lee  <flee@cygnus.com>
1681
1682         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1683
1684 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1685
1686         * Makefile.in (tmp-igen): Arrange for $zero to always be
1687         reset to zero after every instruction.
1688
1689 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1690
1691         * configure: Regenerated to track ../common/aclocal.m4 changes.
1692         * config.in: Ditto.
1693
1694 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1695
1696         * mips.igen (MSUB): Fix to work like MADD.
1697         * gencode.c (MSUB): Similarly.
1698
1699 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1700
1701         * configure: Regenerated to track ../common/aclocal.m4 changes.
1702
1703 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1704
1705         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1706
1707 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1708
1709         * sim-main.h (sim-fpu.h): Include.
1710
1711         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1712         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1713         using host independant sim_fpu module.
1714
1715 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1716
1717         * interp.c (signal_exception): Report internal errors with SIGABRT
1718         not SIGQUIT.
1719
1720         * sim-main.h (C0_CONFIG): New register.
1721         (signal.h): No longer include.
1722
1723         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1724
1725 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1726
1727         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1728
1729 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1730
1731         * mips.igen: Tag vr5000 instructions.
1732         (ANDI): Was missing mipsIV model, fix assembler syntax.
1733         (do_c_cond_fmt): New function.
1734         (C.cond.fmt): Handle mips I-III which do not support CC field
1735         separatly.
1736         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1737         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1738         in IV3.2 spec.
1739         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1740         vr5000 which saves LO in a GPR separatly.
1741
1742         * configure.in (enable-sim-igen): For vr5000, select vr5000
1743         specific instructions.
1744         * configure: Re-generate.
1745
1746 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1747
1748         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1749
1750         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1751         fmt_uninterpreted_64 bit cases to switch.  Convert to
1752         fmt_formatted,
1753
1754         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1755
1756         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1757         as specified in IV3.2 spec.
1758         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1759
1760 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1761
1762         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1763         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1764         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1765         PENDING_FILL versions of instructions.  Simplify.
1766         (X): New function.
1767         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1768         instructions.
1769         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1770         a signed value.
1771         (MTHI, MFHI): Disable code checking HI-LO.
1772
1773         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1774         global.
1775         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1776
1777 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1778
1779         * gencode.c (build_mips16_operands): Replace IPC with cia.
1780
1781         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1782         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1783         IPC to `cia'.
1784         (UndefinedResult): Replace function with macro/function
1785         combination.
1786         (sim_engine_run): Don't save PC in IPC.
1787
1788         * sim-main.h (IPC): Delete.
1789
1790
1791         * interp.c (signal_exception, store_word, load_word,
1792         address_translation, load_memory, store_memory, cache_op,
1793         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1794         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1795         current instruction address - cia - argument.
1796         (sim_read, sim_write): Call address_translation directly.
1797         (sim_engine_run): Rename variable vaddr to cia.
1798         (signal_exception): Pass cia to sim_monitor
1799
1800         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1801         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1802         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1803
1804         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1805         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1806         SIM_ASSERT.
1807
1808         * interp.c (signal_exception): Pass restart address to
1809         sim_engine_restart.
1810
1811         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1812         idecode.o): Add dependency.
1813
1814         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1815         Delete definitions
1816         (DELAY_SLOT): Update NIA not PC with branch address.
1817         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1818
1819         * mips.igen: Use CIA not PC in branch calculations.
1820         (illegal): Call SignalException.
1821         (BEQ, ADDIU): Fix assembler.
1822
1823 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1824
1825         * m16.igen (JALX): Was missing.
1826
1827         * configure.in (enable-sim-igen): New configuration option.
1828         * configure: Re-generate.
1829
1830         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1831
1832         * interp.c (load_memory, store_memory): Delete parameter RAW.
1833         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1834         bypassing {load,store}_memory.
1835
1836         * sim-main.h (ByteSwapMem): Delete definition.
1837
1838         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1839
1840         * interp.c (sim_do_command, sim_commands): Delete mips specific
1841         commands.  Handled by module sim-options.
1842
1843         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1844         (WITH_MODULO_MEMORY): Define.
1845
1846         * interp.c (sim_info): Delete code printing memory size.
1847
1848         * interp.c (mips_size): Nee sim_size, delete function.
1849         (power2): Delete.
1850         (monitor, monitor_base, monitor_size): Delete global variables.
1851         (sim_open, sim_close): Delete code creating monitor and other
1852         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1853         manage memory regions.
1854         (load_memory, store_memory): Use sim-core for memory model.
1855
1856         * interp.c (address_translation): Delete all memory map code
1857         except line forcing 32 bit addresses.
1858
1859 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1860
1861         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1862         trace options.
1863
1864         * interp.c (logfh, logfile): Delete globals.
1865         (sim_open, sim_close): Delete code opening & closing log file.
1866         (mips_option_handler): Delete -l and -n options.
1867         (OPTION mips_options): Ditto.
1868
1869         * interp.c (OPTION mips_options): Rename option trace to dinero.
1870         (mips_option_handler): Update.
1871
1872 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1873
1874         * interp.c (fetch_str): New function.
1875         (sim_monitor): Rewrite using sim_read & sim_write.
1876         (sim_open): Check magic number.
1877         (sim_open): Write monitor vectors into memory using sim_write.
1878         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1879         (sim_read, sim_write): Simplify - transfer data one byte at a
1880         time.
1881         (load_memory, store_memory): Clarify meaning of parameter RAW.
1882
1883         * sim-main.h (isHOST): Defete definition.
1884         (isTARGET): Mark as depreciated.
1885         (address_translation): Delete parameter HOST.
1886
1887         * interp.c (address_translation): Delete parameter HOST.
1888
1889 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1890
1891         * mips.igen:
1892
1893         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1894         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1895
1896 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1897
1898         * mips.igen: Add model filter field to records.
1899
1900 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1901
1902         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1903
1904         interp.c (sim_engine_run): Do not compile function sim_engine_run
1905         when WITH_IGEN == 1.
1906
1907         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1908         target architecture.
1909
1910         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1911         igen. Replace with configuration variables sim_igen_flags /
1912         sim_m16_flags.
1913
1914         * m16.igen: New file.  Copy mips16 insns here.
1915         * mips.igen: From here.
1916
1917 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1918
1919         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1920         to top.
1921         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1922
1923 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1924
1925         * gencode.c (build_instruction): Follow sim_write's lead in using
1926         BigEndianMem instead of !ByteSwapMem.
1927
1928 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1929
1930         * configure.in (sim_gen): Dependent on target, select type of
1931         generator.  Always select old style generator.
1932
1933         configure: Re-generate.
1934
1935         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1936         targets.
1937         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1938         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1939         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1940         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1941         SIM_@sim_gen@_*, set by autoconf.
1942
1943 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1944
1945         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1946
1947         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1948         CURRENT_FLOATING_POINT instead.
1949
1950         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1951         (address_translation): Raise exception InstructionFetch when
1952         translation fails and isINSTRUCTION.
1953
1954         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1955         sim_engine_run): Change type of of vaddr and paddr to
1956         address_word.
1957         (address_translation, prefetch, load_memory, store_memory,
1958         cache_op): Change type of vAddr and pAddr to address_word.
1959
1960         * gencode.c (build_instruction): Change type of vaddr and paddr to
1961         address_word.
1962
1963 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1964
1965         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1966         macro to obtain result of ALU op.
1967
1968 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1969
1970         * interp.c (sim_info): Call profile_print.
1971
1972 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1973
1974         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1975
1976         * sim-main.h (WITH_PROFILE): Do not define, defined in
1977         common/sim-config.h.  Use sim-profile module.
1978         (simPROFILE): Delete defintion.
1979
1980         * interp.c (PROFILE): Delete definition.
1981         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1982         (sim_close): Delete code writing profile histogram.
1983         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1984         Delete.
1985         (sim_engine_run): Delete code profiling the PC.
1986
1987 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1988
1989         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1990
1991         * interp.c (sim_monitor): Make register pointers of type
1992         unsigned_word*.
1993
1994         * sim-main.h: Make registers of type unsigned_word not
1995         signed_word.
1996
1997 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1998
1999         * interp.c (sync_operation): Rename from SyncOperation, make
2000         global, add SD argument.
2001         (prefetch): Rename from Prefetch, make global, add SD argument.
2002         (decode_coproc): Make global.
2003
2004         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2005
2006         * gencode.c (build_instruction): Generate DecodeCoproc not
2007         decode_coproc calls.
2008
2009         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2010         (SizeFGR): Move to sim-main.h
2011         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2012         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2013         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2014         sim-main.h.
2015         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2016         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2017         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2018         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2019         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2020         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2021
2022         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2023         exception.
2024         (sim-alu.h): Include.
2025         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2026         (sim_cia): Typedef to instruction_address.
2027
2028 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2029
2030         * Makefile.in (interp.o): Rename generated file engine.c to
2031         oengine.c.
2032
2033         * interp.c: Update.
2034
2035 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2036
2037         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2038
2039 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2040
2041         * gencode.c (build_instruction): For "FPSQRT", output correct
2042         number of arguments to Recip.
2043
2044 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2045
2046         * Makefile.in (interp.o): Depends on sim-main.h
2047
2048         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2049
2050         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2051         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2052         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2053         STATE, DSSTATE): Define
2054         (GPR, FGRIDX, ..): Define.
2055
2056         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2057         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2058         (GPR, FGRIDX, ...): Delete macros.
2059
2060         * interp.c: Update names to match defines from sim-main.h
2061
2062 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2063
2064         * interp.c (sim_monitor): Add SD argument.
2065         (sim_warning): Delete.  Replace calls with calls to
2066         sim_io_eprintf.
2067         (sim_error): Delete. Replace calls with sim_io_error.
2068         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2069         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2070         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2071         argument.
2072         (mips_size): Rename from sim_size. Add SD argument.
2073
2074         * interp.c (simulator): Delete global variable.
2075         (callback): Delete global variable.
2076         (mips_option_handler, sim_open, sim_write, sim_read,
2077         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2078         sim_size,sim_monitor): Use sim_io_* not callback->*.
2079         (sim_open): ZALLOC simulator struct.
2080         (PROFILE): Do not define.
2081
2082 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2083
2084         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2085         support.h with corresponding code.
2086
2087         * sim-main.h (word64, uword64), support.h: Move definition to
2088         sim-main.h.
2089         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2090
2091         * support.h: Delete
2092         * Makefile.in: Update dependencies
2093         * interp.c: Do not include.
2094
2095 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2096
2097         * interp.c (address_translation, load_memory, store_memory,
2098         cache_op): Rename to from AddressTranslation et.al., make global,
2099         add SD argument
2100
2101         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2102         CacheOp): Define.
2103
2104         * interp.c (SignalException): Rename to signal_exception, make
2105         global.
2106
2107         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2108
2109         * sim-main.h (SignalException, SignalExceptionInterrupt,
2110         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2111         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2112         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2113         Define.
2114
2115         * interp.c, support.h: Use.
2116
2117 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2118
2119         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2120         to value_fpr / store_fpr. Add SD argument.
2121         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2122         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2123
2124         * sim-main.h (ValueFPR, StoreFPR): Define.
2125
2126 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2127
2128         * interp.c (sim_engine_run): Check consistency between configure
2129         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2130         and HASFPU.
2131
2132         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2133         (mips_fpu): Configure WITH_FLOATING_POINT.
2134         (mips_endian): Configure WITH_TARGET_ENDIAN.
2135         * configure: Update.
2136
2137 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2138
2139         * configure: Regenerated to track ../common/aclocal.m4 changes.
2140
2141 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2142
2143         * configure: Regenerated.
2144
2145 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2146
2147         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2148
2149 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2150
2151         * gencode.c (print_igen_insn_models): Assume certain architectures
2152         include all mips* instructions.
2153         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2154         instruction.
2155
2156         * Makefile.in (tmp.igen): Add target. Generate igen input from
2157         gencode file.
2158
2159         * gencode.c (FEATURE_IGEN): Define.
2160         (main): Add --igen option.  Generate output in igen format.
2161         (process_instructions): Format output according to igen option.
2162         (print_igen_insn_format): New function.
2163         (print_igen_insn_models): New function.
2164         (process_instructions): Only issue warnings and ignore
2165         instructions when no FEATURE_IGEN.
2166
2167 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2168
2169         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2170         MIPS targets.
2171
2172 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2173
2174         * configure: Regenerated to track ../common/aclocal.m4 changes.
2175
2176 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2177
2178         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2179         SIM_RESERVED_BITS): Delete, moved to common.
2180         (SIM_EXTRA_CFLAGS): Update.
2181
2182 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2183
2184         * configure.in: Configure non-strict memory alignment.
2185         * configure: Regenerated to track ../common/aclocal.m4 changes.
2186
2187 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2188
2189         * configure: Regenerated to track ../common/aclocal.m4 changes.
2190
2191 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2192
2193         * gencode.c (SDBBP,DERET): Added (3900) insns.
2194         (RFE): Turn on for 3900.
2195         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2196         (dsstate): Made global.
2197         (SUBTARGET_R3900): Added.
2198         (CANCELDELAYSLOT): New.
2199         (SignalException): Ignore SystemCall rather than ignore and
2200         terminate.  Add DebugBreakPoint handling.
2201         (decode_coproc): New insns RFE, DERET; and new registers Debug
2202         and DEPC protected by SUBTARGET_R3900.
2203         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2204         bits explicitly.
2205         * Makefile.in,configure.in: Add mips subtarget option.
2206         * configure: Update.
2207
2208 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2209
2210         * gencode.c: Add r3900 (tx39).
2211
2212
2213 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2214
2215         * gencode.c (build_instruction): Don't need to subtract 4 for
2216         JALR, just 2.
2217
2218 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2219
2220         * interp.c: Correct some HASFPU problems.
2221
2222 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2223
2224         * configure: Regenerated to track ../common/aclocal.m4 changes.
2225
2226 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2227
2228         * interp.c (mips_options): Fix samples option short form, should
2229         be `x'.
2230
2231 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2232
2233         * interp.c (sim_info): Enable info code.  Was just returning.
2234
2235 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2236
2237         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2238         MFC0.
2239
2240 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2241
2242         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2243         constants.
2244         (build_instruction): Ditto for LL.
2245
2246 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2247
2248         * configure: Regenerated to track ../common/aclocal.m4 changes.
2249
2250 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2251
2252         * configure: Regenerated to track ../common/aclocal.m4 changes.
2253         * config.in: Ditto.
2254
2255 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2256
2257         * interp.c (sim_open): Add call to sim_analyze_program, update
2258         call to sim_config.
2259
2260 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2261
2262         * interp.c (sim_kill): Delete.
2263         (sim_create_inferior): Add ABFD argument. Set PC from same.
2264         (sim_load): Move code initializing trap handlers from here.
2265         (sim_open): To here.
2266         (sim_load): Delete, use sim-hload.c.
2267
2268         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2269
2270 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2271
2272         * configure: Regenerated to track ../common/aclocal.m4 changes.
2273         * config.in: Ditto.
2274
2275 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2276
2277         * interp.c (sim_open): Add ABFD argument.
2278         (sim_load): Move call to sim_config from here.
2279         (sim_open): To here.  Check return status.
2280
2281 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2282
2283         * gencode.c (build_instruction): Two arg MADD should
2284         not assign result to $0.
2285
2286 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2287
2288         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2289         * sim/mips/configure.in: Regenerate.
2290
2291 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2292
2293         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2294         signed8, unsigned8 et.al. types.
2295
2296         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2297         hosts when selecting subreg.
2298
2299 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2300
2301         * interp.c (sim_engine_run): Reset the ZERO register to zero
2302         regardless of FEATURE_WARN_ZERO.
2303         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2304
2305 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2306
2307         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2308         (SignalException): For BreakPoints ignore any mode bits and just
2309         save the PC.
2310         (SignalException): Always set the CAUSE register.
2311
2312 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2313
2314         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2315         exception has been taken.
2316
2317         * interp.c: Implement the ERET and mt/f sr instructions.
2318
2319 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2320
2321         * interp.c (SignalException): Don't bother restarting an
2322         interrupt.
2323
2324 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2325
2326         * interp.c (SignalException): Really take an interrupt.
2327         (interrupt_event): Only deliver interrupts when enabled.
2328
2329 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2330
2331         * interp.c (sim_info): Only print info when verbose.
2332         (sim_info) Use sim_io_printf for output.
2333
2334 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2335
2336         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2337         mips architectures.
2338
2339 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2340
2341         * interp.c (sim_do_command): Check for common commands if a
2342         simulator specific command fails.
2343
2344 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2345
2346         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2347         and simBE when DEBUG is defined.
2348
2349 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2350
2351         * interp.c (interrupt_event): New function.  Pass exception event
2352         onto exception handler.
2353
2354         * configure.in: Check for stdlib.h.
2355         * configure: Regenerate.
2356
2357         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2358         variable declaration.
2359         (build_instruction): Initialize memval1.
2360         (build_instruction): Add UNUSED attribute to byte, bigend,
2361         reverse.
2362         (build_operands): Ditto.
2363
2364         * interp.c: Fix GCC warnings.
2365         (sim_get_quit_code): Delete.
2366
2367         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2368         * Makefile.in: Ditto.
2369         * configure: Re-generate.
2370
2371         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2372
2373 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2374
2375         * interp.c (mips_option_handler): New function parse argumes using
2376         sim-options.
2377         (myname): Replace with STATE_MY_NAME.
2378         (sim_open): Delete check for host endianness - performed by
2379         sim_config.
2380         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2381         (sim_open): Move much of the initialization from here.
2382         (sim_load): To here.  After the image has been loaded and
2383         endianness set.
2384         (sim_open): Move ColdReset from here.
2385         (sim_create_inferior): To here.
2386         (sim_open): Make FP check less dependant on host endianness.
2387
2388         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2389         run.
2390         * interp.c (sim_set_callbacks): Delete.
2391
2392         * interp.c (membank, membank_base, membank_size): Replace with
2393         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2394         (sim_open): Remove call to callback->init. gdb/run do this.
2395
2396         * interp.c: Update
2397
2398         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2399
2400         * interp.c (big_endian_p): Delete, replaced by
2401         current_target_byte_order.
2402
2403 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2404
2405         * interp.c (host_read_long, host_read_word, host_swap_word,
2406         host_swap_long): Delete. Using common sim-endian.
2407         (sim_fetch_register, sim_store_register): Use H2T.
2408         (pipeline_ticks): Delete.  Handled by sim-events.
2409         (sim_info): Update.
2410         (sim_engine_run): Update.
2411
2412 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2413
2414         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2415         reason from here.
2416         (SignalException): To here. Signal using sim_engine_halt.
2417         (sim_stop_reason): Delete, moved to common.
2418
2419 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2420
2421         * interp.c (sim_open): Add callback argument.
2422         (sim_set_callbacks): Delete SIM_DESC argument.
2423         (sim_size): Ditto.
2424
2425 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2426
2427         * Makefile.in (SIM_OBJS): Add common modules.
2428
2429         * interp.c (sim_set_callbacks): Also set SD callback.
2430         (set_endianness, xfer_*, swap_*): Delete.
2431         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2432         Change to functions using sim-endian macros.
2433         (control_c, sim_stop): Delete, use common version.
2434         (simulate): Convert into.
2435         (sim_engine_run): This function.
2436         (sim_resume): Delete.
2437
2438         * interp.c (simulation): New variable - the simulator object.
2439         (sim_kind): Delete global - merged into simulation.
2440         (sim_load): Cleanup.  Move PC assignment from here.
2441         (sim_create_inferior): To here.
2442
2443         * sim-main.h: New file.
2444         * interp.c (sim-main.h): Include.
2445
2446 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2447
2448         * configure: Regenerated to track ../common/aclocal.m4 changes.
2449
2450 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2451
2452         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2453
2454 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2455
2456         * gencode.c (build_instruction): DIV instructions: check
2457         for division by zero and integer overflow before using
2458         host's division operation.
2459
2460 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2461
2462         * Makefile.in (SIM_OBJS): Add sim-load.o.
2463         * interp.c: #include bfd.h.
2464         (target_byte_order): Delete.
2465         (sim_kind, myname, big_endian_p): New static locals.
2466         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2467         after argument parsing.  Recognize -E arg, set endianness accordingly.
2468         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2469         load file into simulator.  Set PC from bfd.
2470         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2471         (set_endianness): Use big_endian_p instead of target_byte_order.
2472
2473 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2474
2475         * interp.c (sim_size): Delete prototype - conflicts with
2476         definition in remote-sim.h.  Correct definition.
2477
2478 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2479
2480         * configure: Regenerated to track ../common/aclocal.m4 changes.
2481         * config.in: Ditto.
2482
2483 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2484
2485         * interp.c (sim_open): New arg `kind'.
2486
2487         * configure: Regenerated to track ../common/aclocal.m4 changes.
2488
2489 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2490
2491         * configure: Regenerated to track ../common/aclocal.m4 changes.
2492
2493 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2494
2495         * interp.c (sim_open): Set optind to 0 before calling getopt.
2496
2497 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2498
2499         * configure: Regenerated to track ../common/aclocal.m4 changes.
2500
2501 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2502
2503         * interp.c : Replace uses of pr_addr with pr_uword64
2504         where the bit length is always 64 independent of SIM_ADDR.
2505         (pr_uword64) : added.
2506
2507 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2508
2509         * configure: Re-generate.
2510
2511 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2512
2513         * configure: Regenerate to track ../common/aclocal.m4 changes.
2514
2515 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2516
2517         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2518         in argv form.
2519         (other sim_*): New SIM_DESC argument.
2520
2521 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2522
2523         * interp.c: Fix printing of addresses for non-64-bit targets.
2524         (pr_addr): Add function to print address based on size.
2525
2526 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2527
2528         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2529
2530 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2531
2532         * gencode.c (build_mips16_operands): Correct computation of base
2533         address for extended PC relative instruction.
2534
2535 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2536
2537         * interp.c (mips16_entry): Add support for floating point cases.
2538         (SignalException): Pass floating point cases to mips16_entry.
2539         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2540         registers.
2541         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2542         or fmt_word.
2543         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2544         and then set the state to fmt_uninterpreted.
2545         (COP_SW): Temporarily set the state to fmt_word while calling
2546         ValueFPR.
2547
2548 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2549
2550         * gencode.c (build_instruction): The high order may be set in the
2551         comparison flags at any ISA level, not just ISA 4.
2552
2553 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2554
2555         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2556         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2557         * configure.in: sinclude ../common/aclocal.m4.
2558         * configure: Regenerated.
2559
2560 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2561
2562         * configure: Rebuild after change to aclocal.m4.
2563
2564 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2565
2566         * configure configure.in Makefile.in:  Update to new configure
2567         scheme which is more compatible with WinGDB builds.
2568         * configure.in:  Improve comment on how to run autoconf.
2569         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2570         * Makefile.in:  Use autoconf substitution to install common
2571         makefile fragment.
2572
2573 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2574
2575         * gencode.c (build_instruction): Use BigEndianCPU instead of
2576         ByteSwapMem.
2577
2578 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2579
2580         * interp.c (sim_monitor): Make output to stdout visible in
2581         wingdb's I/O log window.
2582
2583 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2584
2585         * support.h: Undo previous change to SIGTRAP
2586         and SIGQUIT values.
2587
2588 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2589
2590         * interp.c (store_word, load_word): New static functions.
2591         (mips16_entry): New static function.
2592         (SignalException): Look for mips16 entry and exit instructions.
2593         (simulate): Use the correct index when setting fpr_state after
2594         doing a pending move.
2595
2596 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2597
2598         * interp.c: Fix byte-swapping code throughout to work on
2599         both little- and big-endian hosts.
2600
2601 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2602
2603         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2604         with gdb/config/i386/xm-windows.h.
2605
2606 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2607
2608         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2609         that messes up arithmetic shifts.
2610
2611 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2612
2613         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2614         SIGTRAP and SIGQUIT for _WIN32.
2615
2616 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2617
2618         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2619         force a 64 bit multiplication.
2620         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2621         destination register is 0, since that is the default mips16 nop
2622         instruction.
2623
2624 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2625
2626         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2627         (build_endian_shift): Don't check proc64.
2628         (build_instruction): Always set memval to uword64.  Cast op2 to
2629         uword64 when shifting it left in memory instructions.  Always use
2630         the same code for stores--don't special case proc64.
2631
2632         * gencode.c (build_mips16_operands): Fix base PC value for PC
2633         relative operands.
2634         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2635         jal instruction.
2636         * interp.c (simJALDELAYSLOT): Define.
2637         (JALDELAYSLOT): Define.
2638         (INDELAYSLOT, INJALDELAYSLOT): Define.
2639         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2640
2641 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2642
2643         * interp.c (sim_open): add flush_cache as a PMON routine
2644         (sim_monitor): handle flush_cache by ignoring it
2645
2646 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2647
2648         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2649         BigEndianMem.
2650         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2651         (BigEndianMem): Rename to ByteSwapMem and change sense.
2652         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2653         BigEndianMem references to !ByteSwapMem.
2654         (set_endianness): New function, with prototype.
2655         (sim_open): Call set_endianness.
2656         (sim_info): Use simBE instead of BigEndianMem.
2657         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2658         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2659         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2660         ifdefs, keeping the prototype declaration.
2661         (swap_word): Rewrite correctly.
2662         (ColdReset): Delete references to CONFIG.  Delete endianness related
2663         code; moved to set_endianness.
2664
2665 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2666
2667         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2668         * interp.c (CHECKHILO): Define away.
2669         (simSIGINT): New macro.
2670         (membank_size): Increase from 1MB to 2MB.
2671         (control_c): New function.
2672         (sim_resume): Rename parameter signal to signal_number.  Add local
2673         variable prev.  Call signal before and after simulate.
2674         (sim_stop_reason): Add simSIGINT support.
2675         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2676         functions always.
2677         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2678         if logfh is NULL.
2679         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2680         a call to sim_warning.
2681
2682 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2683
2684         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2685         16 bit instructions.
2686
2687 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2688
2689         Add support for mips16 (16 bit MIPS implementation):
2690         * gencode.c (inst_type): Add mips16 instruction encoding types.
2691         (GETDATASIZEINSN): Define.
2692         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2693         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2694         mtlo.
2695         (MIPS16_DECODE): New table, for mips16 instructions.
2696         (bitmap_val): New static function.
2697         (struct mips16_op): Define.
2698         (mips16_op_table): New table, for mips16 operands.
2699         (build_mips16_operands): New static function.
2700         (process_instructions): If PC is odd, decode a mips16
2701         instruction.  Break out instruction handling into new
2702         build_instruction function.
2703         (build_instruction): New static function, broken out of
2704         process_instructions.  Check modifiers rather than flags for SHIFT
2705         bit count and m[ft]{hi,lo} direction.
2706         (usage): Pass program name to fprintf.
2707         (main): Remove unused variable this_option_optind.  Change
2708         ``*loptarg++'' to ``loptarg++''.
2709         (my_strtoul): Parenthesize && within ||.
2710         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2711         (simulate): If PC is odd, fetch a 16 bit instruction, and
2712         increment PC by 2 rather than 4.
2713         * configure.in: Add case for mips16*-*-*.
2714         * configure: Rebuild.
2715
2716 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2717
2718         * interp.c: Allow -t to enable tracing in standalone simulator.
2719         Fix garbage output in trace file and error messages.
2720
2721 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2722
2723         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2724         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2725         * configure.in: Simplify using macros in ../common/aclocal.m4.
2726         * configure: Regenerated.
2727         * tconfig.in: New file.
2728
2729 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2730
2731         * interp.c: Fix bugs in 64-bit port.
2732         Use ansi function declarations for msvc compiler.
2733         Initialize and test file pointer in trace code.
2734         Prevent duplicate definition of LAST_EMED_REGNUM.
2735
2736 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2737
2738         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2739
2740 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2741
2742         * interp.c (SignalException): Check for explicit terminating
2743         breakpoint value.
2744         * gencode.c: Pass instruction value through SignalException()
2745         calls for Trap, Breakpoint and Syscall.
2746
2747 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2748
2749         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2750         only used on those hosts that provide it.
2751         * configure.in: Add sqrt() to list of functions to be checked for.
2752         * config.in: Re-generated.
2753         * configure: Re-generated.
2754
2755 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2756
2757         * gencode.c (process_instructions): Call build_endian_shift when
2758         expanding STORE RIGHT, to fix swr.
2759         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2760         clear the high bits.
2761         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2762         Fix float to int conversions to produce signed values.
2763
2764 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2765
2766         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2767         (process_instructions): Correct handling of nor instruction.
2768         Correct shift count for 32 bit shift instructions. Correct sign
2769         extension for arithmetic shifts to not shift the number of bits in
2770         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2771         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2772         Fix madd.
2773         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2774         It's OK to have a mult follow a mult.  What's not OK is to have a
2775         mult follow an mfhi.
2776         (Convert): Comment out incorrect rounding code.
2777
2778 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2779
2780         * interp.c (sim_monitor): Improved monitor printf
2781         simulation. Tidied up simulator warnings, and added "--log" option
2782         for directing warning message output.
2783         * gencode.c: Use sim_warning() rather than WARNING macro.
2784
2785 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2786
2787         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2788         getopt1.o, rather than on gencode.c.  Link objects together.
2789         Don't link against -liberty.
2790         (gencode.o, getopt.o, getopt1.o): New targets.
2791         * gencode.c: Include <ctype.h> and "ansidecl.h".
2792         (AND): Undefine after including "ansidecl.h".
2793         (ULONG_MAX): Define if not defined.
2794         (OP_*): Don't define macros; now defined in opcode/mips.h.
2795         (main): Call my_strtoul rather than strtoul.
2796         (my_strtoul): New static function.
2797
2798 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2799
2800         * gencode.c (process_instructions):  Generate word64 and uword64
2801         instead of `long long' and `unsigned long long' data types.
2802         * interp.c:  #include sysdep.h to get signals, and define default
2803         for SIGBUS.
2804         * (Convert):  Work around for Visual-C++ compiler bug with type
2805         conversion.
2806         * support.h:  Make things compile under Visual-C++ by using
2807         __int64 instead of `long long'.  Change many refs to long long
2808         into word64/uword64 typedefs.
2809
2810 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2811
2812         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2813         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2814         (docdir): Removed.
2815         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2816         (AC_PROG_INSTALL): Added.
2817         (AC_PROG_CC): Moved to before configure.host call.
2818         * configure: Rebuilt.
2819
2820 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2821
2822         * configure.in: Define @SIMCONF@ depending on mips target.
2823         * configure: Rebuild.
2824         * Makefile.in (run): Add @SIMCONF@ to control simulator
2825         construction.
2826         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2827         * interp.c: Remove some debugging, provide more detailed error
2828         messages, update memory accesses to use LOADDRMASK.
2829
2830 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2831
2832         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2833         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2834         stamp-h.
2835         * configure: Rebuild.
2836         * config.in: New file, generated by autoheader.
2837         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2838         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2839         HAVE_ANINT and HAVE_AINT, as appropriate.
2840         * Makefile.in (run): Use @LIBS@ rather than -lm.
2841         (interp.o): Depend upon config.h.
2842         (Makefile): Just rebuild Makefile.
2843         (clean): Remove stamp-h.
2844         (mostlyclean): Make the same as clean, not as distclean.
2845         (config.h, stamp-h): New targets.
2846
2847 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2848
2849         * interp.c (ColdReset): Fix boolean test. Make all simulator
2850         globals static.
2851
2852 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2853
2854         * interp.c (xfer_direct_word, xfer_direct_long,
2855         swap_direct_word, swap_direct_long, xfer_big_word,
2856         xfer_big_long, xfer_little_word, xfer_little_long,
2857         swap_word,swap_long): Added.
2858         * interp.c (ColdReset): Provide function indirection to
2859         host<->simulated_target transfer routines.
2860         * interp.c (sim_store_register, sim_fetch_register): Updated to
2861         make use of indirected transfer routines.
2862
2863 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2864
2865         * gencode.c (process_instructions): Ensure FP ABS instruction
2866         recognised.
2867         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2868         system call support.
2869
2870 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2871
2872         * interp.c (sim_do_command): Complain if callback structure not
2873         initialised.
2874
2875 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2876
2877         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2878         support for Sun hosts.
2879         * Makefile.in (gencode): Ensure the host compiler and libraries
2880         used for cross-hosted build.
2881
2882 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2883
2884         * interp.c, gencode.c: Some more (TODO) tidying.
2885
2886 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2887
2888         * gencode.c, interp.c: Replaced explicit long long references with
2889         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2890         * support.h (SET64LO, SET64HI): Macros added.
2891
2892 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2893
2894         * configure: Regenerate with autoconf 2.7.
2895
2896 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2897
2898         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2899         * support.h: Remove superfluous "1" from #if.
2900         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2901
2902 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2903
2904         * interp.c (StoreFPR): Control UndefinedResult() call on
2905         WARN_RESULT manifest.
2906
2907 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2908
2909         * gencode.c: Tidied instruction decoding, and added FP instruction
2910         support.
2911
2912         * interp.c: Added dineroIII, and BSD profiling support. Also
2913         run-time FP handling.
2914
2915 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2916
2917         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2918         gencode.c, interp.c, support.h: created.