1 2016-01-12 Mike Frysinger <vapier@gentoo.org>
3 * interp.c: Include elf-bfd.h.
4 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
7 2016-01-10 Mike Frysinger <vapier@gentoo.org>
9 * config.in, configure: Regenerate.
11 2016-01-10 Mike Frysinger <vapier@gentoo.org>
13 * configure: Regenerate.
15 2016-01-10 Mike Frysinger <vapier@gentoo.org>
17 * configure: Regenerate.
19 2016-01-10 Mike Frysinger <vapier@gentoo.org>
21 * configure: Regenerate.
23 2016-01-10 Mike Frysinger <vapier@gentoo.org>
25 * configure: Regenerate.
27 2016-01-10 Mike Frysinger <vapier@gentoo.org>
29 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
30 * configure: Regenerate.
32 2016-01-10 Mike Frysinger <vapier@gentoo.org>
34 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
35 * configure: Regenerate.
37 2016-01-10 Mike Frysinger <vapier@gentoo.org>
39 * configure: Regenerate.
41 2016-01-10 Mike Frysinger <vapier@gentoo.org>
43 * configure: Regenerate.
45 2016-01-09 Mike Frysinger <vapier@gentoo.org>
47 * config.in, configure: Regenerate.
49 2016-01-06 Mike Frysinger <vapier@gentoo.org>
51 * interp.c (sim_open): Mark argv const.
52 (sim_create_inferior): Mark argv and env const.
54 2016-01-04 Mike Frysinger <vapier@gentoo.org>
56 * configure: Regenerate.
58 2016-01-03 Mike Frysinger <vapier@gentoo.org>
60 * interp.c (sim_open): Update sim_parse_args comment.
62 2016-01-03 Mike Frysinger <vapier@gentoo.org>
64 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
65 * configure: Regenerate.
67 2016-01-02 Mike Frysinger <vapier@gentoo.org>
69 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
70 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
71 * configure: Regenerate.
72 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
74 2016-01-02 Mike Frysinger <vapier@gentoo.org>
76 * dv-tx3904cpu.c (CPU, SD): Delete.
78 2015-12-30 Mike Frysinger <vapier@gentoo.org>
80 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
81 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
82 (sim_store_register): Rename to ...
83 (mips_reg_store): ... this. Delete local cpu var.
84 Update sim_io_eprintf calls.
85 (sim_fetch_register): Rename to ...
86 (mips_reg_fetch): ... this. Delete local cpu var.
87 Update sim_io_eprintf calls.
89 2015-12-27 Mike Frysinger <vapier@gentoo.org>
91 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
93 2015-12-26 Mike Frysinger <vapier@gentoo.org>
95 * config.in, configure: Regenerate.
97 2015-12-26 Mike Frysinger <vapier@gentoo.org>
99 * interp.c (sim_write, sim_read): Delete.
100 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
101 (load_word): Likewise.
102 * micromips.igen (cache): Likewise.
103 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
104 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
105 do_store_left, do_store_right, do_load_double, do_store_double):
107 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
108 (do_prefx): Likewise.
109 * sim-main.c (address_translation, prefetch): Delete.
110 (ifetch32, ifetch16): Delete call to AddressTranslation and set
112 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
113 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
114 (LoadMemory, StoreMemory): Delete CCA arg.
116 2015-12-24 Mike Frysinger <vapier@gentoo.org>
118 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
119 * configure: Regenerated.
121 2015-12-24 Mike Frysinger <vapier@gentoo.org>
123 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
126 2015-12-24 Mike Frysinger <vapier@gentoo.org>
128 * tconfig.h (SIM_HANDLES_LMA): Delete.
130 2015-12-24 Mike Frysinger <vapier@gentoo.org>
132 * sim-main.h (WITH_WATCHPOINTS): Delete.
134 2015-12-24 Mike Frysinger <vapier@gentoo.org>
136 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
138 2015-12-24 Mike Frysinger <vapier@gentoo.org>
140 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
142 2015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
144 * micromips.igen (process_isa_mode): Fix left shift of negative
147 2015-11-17 Mike Frysinger <vapier@gentoo.org>
149 * sim-main.h (WITH_MODULO_MEMORY): Delete.
151 2015-11-15 Mike Frysinger <vapier@gentoo.org>
153 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
155 2015-11-14 Mike Frysinger <vapier@gentoo.org>
157 * interp.c (sim_close): Rename to ...
158 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
160 * sim-main.h (mips_sim_close): Declare.
161 (SIM_CLOSE_HOOK): Define.
163 2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
164 Ali Lown <ali.lown@imgtec.com>
166 * Makefile.in (tmp-micromips): New rule.
167 (tmp-mach-multi): Add support for micromips.
168 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
169 that works for both mips64 and micromips64.
170 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
172 Add build support for micromips.
173 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
174 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
175 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
176 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
177 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
178 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
179 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
180 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
181 Refactored instruction code to use these functions.
182 * dsp2.igen: Refactored instruction code to use the new functions.
183 * interp.c (decode_coproc): Refactored to work with any instruction
185 (isa_mode): New variable
186 (RSVD_INSTRUCTION): Changed to 0x00000039.
187 * m16.igen (BREAK16): Refactored instruction to use do_break16.
188 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
189 * micromips.dc: New file.
190 * micromips.igen: New file.
191 * micromips16.dc: New file.
192 * micromipsdsp.igen: New file.
193 * micromipsrun.c: New file.
194 * mips.igen (do_swc1): Changed to work with any instruction encoding.
195 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
196 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
197 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
198 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
199 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
200 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
201 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
202 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
203 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
204 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
205 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
206 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
207 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
208 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
209 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
210 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
211 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
212 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
214 Refactored instruction code to use these functions.
215 (RSVD): Changed to use new reserved instruction.
216 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
217 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
218 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
219 do_store_double): Added micromips32 and micromips64 models.
220 Added include for micromips.igen and micromipsdsp.igen
221 Add micromips32 and micromips64 models.
222 (DecodeCoproc): Updated to use new macro definition.
223 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
224 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
225 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
226 Refactored instruction code to use these functions.
227 * sim-main.h (CP0_operation): New enum.
228 (DecodeCoproc): Updated macro.
229 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
230 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
231 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
232 ISA_MODE_MICROMIPS): New defines.
233 (sim_state): Add isa_mode field.
235 2015-06-23 Mike Frysinger <vapier@gentoo.org>
237 * configure: Regenerate.
239 2015-06-12 Mike Frysinger <vapier@gentoo.org>
241 * configure.ac: Change configure.in to configure.ac.
242 * configure: Regenerate.
244 2015-06-12 Mike Frysinger <vapier@gentoo.org>
246 * configure: Regenerate.
248 2015-06-12 Mike Frysinger <vapier@gentoo.org>
250 * interp.c [TRACE]: Delete.
251 (TRACE): Change to WITH_TRACE_ANY_P.
252 [!WITH_TRACE_ANY_P] (open_trace): Define.
253 (mips_option_handler, open_trace, sim_close, dotrace):
254 Change defined(TRACE) to WITH_TRACE_ANY_P.
255 (sim_open): Delete TRACE ifdef check.
256 * sim-main.c (load_memory): Delete TRACE ifdef check.
257 (store_memory): Likewise.
258 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
259 [!WITH_TRACE_ANY_P] (dotrace): Define.
261 2015-04-18 Mike Frysinger <vapier@gentoo.org>
263 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
266 2015-04-18 Mike Frysinger <vapier@gentoo.org>
268 * sim-main.h (SIM_CPU): Delete.
270 2015-04-18 Mike Frysinger <vapier@gentoo.org>
272 * sim-main.h (sim_cia): Delete.
274 2015-04-17 Mike Frysinger <vapier@gentoo.org>
276 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
278 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
279 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
280 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
281 CIA_SET to CPU_PC_SET.
282 * sim-main.h (CIA_GET, CIA_SET): Delete.
284 2015-04-15 Mike Frysinger <vapier@gentoo.org>
286 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
287 * sim-main.h (STATE_CPU): Delete.
289 2015-04-13 Mike Frysinger <vapier@gentoo.org>
291 * configure: Regenerate.
293 2015-04-13 Mike Frysinger <vapier@gentoo.org>
295 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
296 * interp.c (mips_pc_get, mips_pc_set): New functions.
297 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
298 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
299 (sim_pc_get): Delete.
300 * sim-main.h (SIM_CPU): Define.
301 (struct sim_state): Change cpu to an array of pointers.
304 2015-04-13 Mike Frysinger <vapier@gentoo.org>
306 * interp.c (mips_option_handler, open_trace, sim_close,
307 sim_write, sim_read, sim_store_register, sim_fetch_register,
308 sim_create_inferior, pr_addr, pr_uword64): Convert old style
310 (sim_open): Convert old style prototype. Change casts with
311 sim_write to unsigned char *.
312 (fetch_str): Change null to unsigned char, and change cast to
314 (sim_monitor): Change c & ch to unsigned char. Change cast to
317 2015-04-12 Mike Frysinger <vapier@gentoo.org>
319 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
321 2015-04-06 Mike Frysinger <vapier@gentoo.org>
323 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
325 2015-04-01 Mike Frysinger <vapier@gentoo.org>
327 * tconfig.h (SIM_HAVE_PROFILE): Delete.
329 2015-03-31 Mike Frysinger <vapier@gentoo.org>
331 * config.in, configure: Regenerate.
333 2015-03-24 Mike Frysinger <vapier@gentoo.org>
335 * interp.c (sim_pc_get): New function.
337 2015-03-24 Mike Frysinger <vapier@gentoo.org>
339 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
340 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
342 2015-03-24 Mike Frysinger <vapier@gentoo.org>
344 * configure: Regenerate.
346 2015-03-23 Mike Frysinger <vapier@gentoo.org>
348 * configure: Regenerate.
350 2015-03-23 Mike Frysinger <vapier@gentoo.org>
352 * configure: Regenerate.
353 * configure.ac (mips_extra_objs): Delete.
354 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
355 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
357 2015-03-23 Mike Frysinger <vapier@gentoo.org>
359 * configure: Regenerate.
360 * configure.ac: Delete sim_hw checks for dv-sockser.
362 2015-03-16 Mike Frysinger <vapier@gentoo.org>
364 * config.in, configure: Regenerate.
365 * tconfig.in: Rename file ...
366 * tconfig.h: ... here.
368 2015-03-15 Mike Frysinger <vapier@gentoo.org>
370 * tconfig.in: Delete includes.
371 [HAVE_DV_SOCKSER]: Delete.
373 2015-03-14 Mike Frysinger <vapier@gentoo.org>
375 * Makefile.in (SIM_RUN_OBJS): Delete.
377 2015-03-14 Mike Frysinger <vapier@gentoo.org>
379 * configure.ac (AC_CHECK_HEADERS): Delete.
380 * aclocal.m4, configure: Regenerate.
382 2014-08-19 Alan Modra <amodra@gmail.com>
384 * configure: Regenerate.
386 2014-08-15 Roland McGrath <mcgrathr@google.com>
388 * configure: Regenerate.
389 * config.in: Regenerate.
391 2014-03-04 Mike Frysinger <vapier@gentoo.org>
393 * configure: Regenerate.
395 2013-09-23 Alan Modra <amodra@gmail.com>
397 * configure: Regenerate.
399 2013-06-03 Mike Frysinger <vapier@gentoo.org>
401 * aclocal.m4, configure: Regenerate.
403 2013-05-10 Freddie Chopin <freddie_chopin@op.pl>
405 * configure: Rebuild.
407 2013-03-26 Mike Frysinger <vapier@gentoo.org>
409 * configure: Regenerate.
411 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
413 * configure.ac: Address use of dv-sockser.o.
414 * tconfig.in: Conditionalize use of dv_sockser_install.
415 * configure: Regenerated.
416 * config.in: Regenerated.
418 2012-10-04 Chao-ying Fu <fu@mips.com>
419 Steve Ellcey <sellcey@mips.com>
421 * mips/mips3264r2.igen (rdhwr): New.
423 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
425 * configure.ac: Always link against dv-sockser.o.
426 * configure: Regenerate.
428 2012-06-15 Joel Brobecker <brobecker@adacore.com>
430 * config.in, configure: Regenerate.
432 2012-05-18 Nick Clifton <nickc@redhat.com>
435 * interp.c: Include config.h before system header files.
437 2012-03-24 Mike Frysinger <vapier@gentoo.org>
439 * aclocal.m4, config.in, configure: Regenerate.
441 2011-12-03 Mike Frysinger <vapier@gentoo.org>
443 * aclocal.m4: New file.
444 * configure: Regenerate.
446 2011-10-19 Mike Frysinger <vapier@gentoo.org>
448 * configure: Regenerate after common/acinclude.m4 update.
450 2011-10-17 Mike Frysinger <vapier@gentoo.org>
452 * configure.ac: Change include to common/acinclude.m4.
454 2011-10-17 Mike Frysinger <vapier@gentoo.org>
456 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
457 call. Replace common.m4 include with SIM_AC_COMMON.
458 * configure: Regenerate.
460 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
462 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
464 (tmp-mach-multi): Exit early when igen fails.
466 2011-07-05 Mike Frysinger <vapier@gentoo.org>
468 * interp.c (sim_do_command): Delete.
470 2011-02-14 Mike Frysinger <vapier@gentoo.org>
472 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
473 (tx3904sio_fifo_reset): Likewise.
474 * interp.c (sim_monitor): Likewise.
476 2010-04-14 Mike Frysinger <vapier@gentoo.org>
478 * interp.c (sim_write): Add const to buffer arg.
480 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
482 * interp.c: Don't include sysdep.h
484 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
486 * configure: Regenerate.
488 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
490 * config.in: Regenerate.
491 * configure: Likewise.
493 * configure: Regenerate.
495 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
497 * configure: Regenerate to track ../common/common.m4 changes.
500 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
501 Daniel Jacobowitz <dan@codesourcery.com>
502 Joseph Myers <joseph@codesourcery.com>
504 * configure: Regenerate.
506 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
508 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
509 that unconditionally allows fmt_ps.
510 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
511 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
512 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
513 filter from 64,f to 32,f.
514 (PREFX): Change filter from 64 to 32.
515 (LDXC1, LUXC1): Provide separate mips32r2 implementations
516 that use do_load_double instead of do_load. Make both LUXC1
517 versions unpredictable if SizeFGR () != 64.
518 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
519 instead of do_store. Remove unused variable. Make both SUXC1
520 versions unpredictable if SizeFGR () != 64.
522 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
524 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
525 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
526 shifts for that case.
528 2007-09-04 Nick Clifton <nickc@redhat.com>
530 * interp.c (options enum): Add OPTION_INFO_MEMORY.
531 (display_mem_info): New static variable.
532 (mips_option_handler): Handle OPTION_INFO_MEMORY.
533 (mips_options): Add info-memory and memory-info.
534 (sim_open): After processing the command line and board
535 specification, check display_mem_info. If it is set then
536 call the real handler for the --memory-info command line
539 2007-08-24 Joel Brobecker <brobecker@adacore.com>
541 * configure.ac: Change license of multi-run.c to GPL version 3.
542 * configure: Regenerate.
544 2007-06-28 Richard Sandiford <richard@codesourcery.com>
546 * configure.ac, configure: Revert last patch.
548 2007-06-26 Richard Sandiford <richard@codesourcery.com>
550 * configure.ac (sim_mipsisa3264_configs): New variable.
551 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
552 every configuration support all four targets, using the triplet to
553 determine the default.
554 * configure: Regenerate.
556 2007-06-25 Richard Sandiford <richard@codesourcery.com>
558 * Makefile.in (m16run.o): New rule.
560 2007-05-15 Thiemo Seufer <ths@mips.com>
562 * mips3264r2.igen (DSHD): Fix compile warning.
564 2007-05-14 Thiemo Seufer <ths@mips.com>
566 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
567 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
568 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
569 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
572 2007-03-01 Thiemo Seufer <ths@mips.com>
574 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
577 2007-02-20 Thiemo Seufer <ths@mips.com>
579 * dsp.igen: Update copyright notice.
580 * dsp2.igen: Fix copyright notice.
582 2007-02-20 Thiemo Seufer <ths@mips.com>
583 Chao-Ying Fu <fu@mips.com>
585 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
586 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
587 Add dsp2 to sim_igen_machine.
588 * configure: Regenerate.
589 * dsp.igen (do_ph_op): Add MUL support when op = 2.
590 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
591 (mulq_rs.ph): Use do_ph_mulq.
592 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
593 * mips.igen: Add dsp2 model and include dsp2.igen.
594 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
595 for *mips32r2, *mips64r2, *dsp.
596 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
597 for *mips32r2, *mips64r2, *dsp2.
598 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
600 2007-02-19 Thiemo Seufer <ths@mips.com>
601 Nigel Stephens <nigel@mips.com>
603 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
604 jumps with hazard barrier.
606 2007-02-19 Thiemo Seufer <ths@mips.com>
607 Nigel Stephens <nigel@mips.com>
609 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
610 after each call to sim_io_write.
612 2007-02-19 Thiemo Seufer <ths@mips.com>
613 Nigel Stephens <nigel@mips.com>
615 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
616 supported by this simulator.
617 (decode_coproc): Recognise additional CP0 Config registers
620 2007-02-19 Thiemo Seufer <ths@mips.com>
621 Nigel Stephens <nigel@mips.com>
622 David Ung <davidu@mips.com>
624 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
625 uninterpreted formats. If fmt is one of the uninterpreted types
626 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
627 fmt_word, and fmt_uninterpreted_64 like fmt_long.
628 (store_fpr): When writing an invalid odd register, set the
629 matching even register to fmt_unknown, not the following register.
630 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
631 the the memory window at offset 0 set by --memory-size command
633 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
635 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
637 (sim_monitor): When returning the memory size to the MIPS
638 application, use the value in STATE_MEM_SIZE, not an arbitrary
640 (cop_lw): Don' mess around with FPR_STATE, just pass
641 fmt_uninterpreted_32 to StoreFPR.
643 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
645 * mips.igen (not_word_value): Single version for mips32, mips64
648 2007-02-19 Thiemo Seufer <ths@mips.com>
649 Nigel Stephens <nigel@mips.com>
651 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
654 2007-02-17 Thiemo Seufer <ths@mips.com>
656 * configure.ac (mips*-sde-elf*): Move in front of generic machine
658 * configure: Regenerate.
660 2007-02-17 Thiemo Seufer <ths@mips.com>
662 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
663 Add mdmx to sim_igen_machine.
664 (mipsisa64*-*-*): Likewise. Remove dsp.
665 (mipsisa32*-*-*): Remove dsp.
666 * configure: Regenerate.
668 2007-02-13 Thiemo Seufer <ths@mips.com>
670 * configure.ac: Add mips*-sde-elf* target.
671 * configure: Regenerate.
673 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
675 * acconfig.h: Remove.
676 * config.in, configure: Regenerate.
678 2006-11-07 Thiemo Seufer <ths@mips.com>
680 * dsp.igen (do_w_op): Fix compiler warning.
682 2006-08-29 Thiemo Seufer <ths@mips.com>
683 David Ung <davidu@mips.com>
685 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
687 * configure: Regenerate.
688 * mips.igen (model): Add smartmips.
689 (MADDU): Increment ACX if carry.
690 (do_mult): Clear ACX.
691 (ROR,RORV): Add smartmips.
692 (include): Include smartmips.igen.
693 * sim-main.h (ACX): Set to REGISTERS[89].
694 * smartmips.igen: New file.
696 2006-08-29 Thiemo Seufer <ths@mips.com>
697 David Ung <davidu@mips.com>
699 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
700 mips3264r2.igen. Add missing dependency rules.
701 * m16e.igen: Support for mips16e save/restore instructions.
703 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
705 * configure: Regenerated.
707 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
709 * configure: Regenerated.
711 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
713 * configure: Regenerated.
715 2006-05-15 Chao-ying Fu <fu@mips.com>
717 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
719 2006-04-18 Nick Clifton <nickc@redhat.com>
721 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
724 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
726 * configure: Regenerate.
728 2005-12-14 Chao-ying Fu <fu@mips.com>
730 * Makefile.in (SIM_OBJS): Add dsp.o.
731 (dsp.o): New dependency.
732 (IGEN_INCLUDE): Add dsp.igen.
733 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
734 mipsisa64*-*-*): Add dsp to sim_igen_machine.
735 * configure: Regenerate.
736 * mips.igen: Add dsp model and include dsp.igen.
737 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
738 because these instructions are extended in DSP ASE.
739 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
740 adding 6 DSP accumulator registers and 1 DSP control register.
741 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
742 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
743 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
744 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
745 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
746 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
747 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
748 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
749 DSPCR_CCOND_SMASK): New define.
750 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
751 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
753 2005-07-08 Ian Lance Taylor <ian@airs.com>
755 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
757 2005-06-16 David Ung <davidu@mips.com>
758 Nigel Stephens <nigel@mips.com>
760 * mips.igen: New mips16e model and include m16e.igen.
761 (check_u64): Add mips16e tag.
762 * m16e.igen: New file for MIPS16e instructions.
763 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
764 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
766 * configure: Regenerate.
768 2005-05-26 David Ung <davidu@mips.com>
770 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
771 tags to all instructions which are applicable to the new ISAs.
772 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
774 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
776 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
778 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
779 * configure: Regenerate.
781 2005-03-23 Mark Kettenis <kettenis@gnu.org>
783 * configure: Regenerate.
785 2005-01-14 Andrew Cagney <cagney@gnu.org>
787 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
788 explicit call to AC_CONFIG_HEADER.
789 * configure: Regenerate.
791 2005-01-12 Andrew Cagney <cagney@gnu.org>
793 * configure.ac: Update to use ../common/common.m4.
794 * configure: Re-generate.
796 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
798 * configure: Regenerated to track ../common/aclocal.m4 changes.
800 2005-01-07 Andrew Cagney <cagney@gnu.org>
802 * configure.ac: Rename configure.in, require autoconf 2.59.
803 * configure: Re-generate.
805 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
807 * configure: Regenerate for ../common/aclocal.m4 update.
809 2004-09-24 Monika Chaddha <monika@acmet.com>
811 Committed by Andrew Cagney.
812 * m16.igen (CMP, CMPI): Fix assembler.
814 2004-08-18 Chris Demetriou <cgd@broadcom.com>
816 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
817 * configure: Regenerate.
819 2004-06-25 Chris Demetriou <cgd@broadcom.com>
821 * configure.in (sim_m16_machine): Include mipsIII.
822 * configure: Regenerate.
824 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
826 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
828 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
830 2004-04-10 Chris Demetriou <cgd@broadcom.com>
832 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
834 2004-04-09 Chris Demetriou <cgd@broadcom.com>
836 * mips.igen (check_fmt): Remove.
837 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
838 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
839 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
840 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
841 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
842 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
843 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
844 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
845 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
846 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
848 2004-04-09 Chris Demetriou <cgd@broadcom.com>
850 * sb1.igen (check_sbx): New function.
851 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
853 2004-03-29 Chris Demetriou <cgd@broadcom.com>
854 Richard Sandiford <rsandifo@redhat.com>
856 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
857 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
858 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
859 separate implementations for mipsIV and mipsV. Use new macros to
860 determine whether the restrictions apply.
862 2004-01-19 Chris Demetriou <cgd@broadcom.com>
864 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
865 (check_mult_hilo): Improve comments.
866 (check_div_hilo): Likewise. Also, fork off a new version
867 to handle mips32/mips64 (since there are no hazards to check
870 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
872 * mips.igen (do_dmultx): Fix check for negative operands.
874 2003-05-16 Ian Lance Taylor <ian@airs.com>
876 * Makefile.in (SHELL): Make sure this is defined.
877 (various): Use $(SHELL) whenever we invoke move-if-change.
879 2003-05-03 Chris Demetriou <cgd@broadcom.com>
881 * cp1.c: Tweak attribution slightly.
884 * mdmx.igen: Likewise.
885 * mips3d.igen: Likewise.
886 * sb1.igen: Likewise.
888 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
890 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
893 2003-02-27 Andrew Cagney <cagney@redhat.com>
895 * interp.c (sim_open): Rename _bfd to bfd.
896 (sim_create_inferior): Ditto.
898 2003-01-14 Chris Demetriou <cgd@broadcom.com>
900 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
902 2003-01-14 Chris Demetriou <cgd@broadcom.com>
904 * mips.igen (EI, DI): Remove.
906 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
908 * Makefile.in (tmp-run-multi): Fix mips16 filter.
910 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
911 Andrew Cagney <ac131313@redhat.com>
912 Gavin Romig-Koch <gavin@redhat.com>
913 Graydon Hoare <graydon@redhat.com>
914 Aldy Hernandez <aldyh@redhat.com>
915 Dave Brolley <brolley@redhat.com>
916 Chris Demetriou <cgd@broadcom.com>
918 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
919 (sim_mach_default): New variable.
920 (mips64vr-*-*, mips64vrel-*-*): New configurations.
921 Add a new simulator generator, MULTI.
922 * configure: Regenerate.
923 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
924 (multi-run.o): New dependency.
925 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
926 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
927 (tmp-multi): Combine them.
928 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
929 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
930 (distclean-extra): New rule.
931 * sim-main.h: Include bfd.h.
932 (MIPS_MACH): New macro.
933 * mips.igen (vr4120, vr5400, vr5500): New models.
934 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
935 * vr.igen: Replace with new version.
937 2003-01-04 Chris Demetriou <cgd@broadcom.com>
939 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
940 * configure: Regenerate.
942 2002-12-31 Chris Demetriou <cgd@broadcom.com>
944 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
945 * mips.igen: Remove all invocations of check_branch_bug and
948 2002-12-16 Chris Demetriou <cgd@broadcom.com>
950 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
952 2002-07-30 Chris Demetriou <cgd@broadcom.com>
954 * mips.igen (do_load_double, do_store_double): New functions.
955 (LDC1, SDC1): Rename to...
956 (LDC1b, SDC1b): respectively.
957 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
959 2002-07-29 Michael Snyder <msnyder@redhat.com>
961 * cp1.c (fp_recip2): Modify initialization expression so that
962 GCC will recognize it as constant.
964 2002-06-18 Chris Demetriou <cgd@broadcom.com>
966 * mdmx.c (SD_): Delete.
967 (Unpredictable): Re-define, for now, to directly invoke
968 unpredictable_action().
969 (mdmx_acc_op): Fix error in .ob immediate handling.
971 2002-06-18 Andrew Cagney <cagney@redhat.com>
973 * interp.c (sim_firmware_command): Initialize `address'.
975 2002-06-16 Andrew Cagney <ac131313@redhat.com>
977 * configure: Regenerated to track ../common/aclocal.m4 changes.
979 2002-06-14 Chris Demetriou <cgd@broadcom.com>
980 Ed Satterthwaite <ehs@broadcom.com>
982 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
983 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
984 * mips.igen: Include mips3d.igen.
985 (mips3d): New model name for MIPS-3D ASE instructions.
986 (CVT.W.fmt): Don't use this instruction for word (source) format
988 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
989 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
990 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
991 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
992 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
993 (RSquareRoot1, RSquareRoot2): New macros.
994 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
995 (fp_rsqrt2): New functions.
996 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
997 * configure: Regenerate.
999 2002-06-13 Chris Demetriou <cgd@broadcom.com>
1000 Ed Satterthwaite <ehs@broadcom.com>
1002 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1003 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1004 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1005 (convert): Note that this function is not used for paired-single
1007 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1008 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1009 (check_fmt_p): Enable paired-single support.
1010 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1011 (PUU.PS): New instructions.
1012 (CVT.S.fmt): Don't use this instruction for paired-single format
1014 * sim-main.h (FP_formats): New value 'fmt_ps.'
1015 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1016 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1018 2002-06-12 Chris Demetriou <cgd@broadcom.com>
1020 * mips.igen: Fix formatting of function calls in
1023 2002-06-12 Chris Demetriou <cgd@broadcom.com>
1025 * mips.igen (MOVN, MOVZ): Trace result.
1026 (TNEI): Print "tnei" as the opcode name in traces.
1027 (CEIL.W): Add disassembly string for traces.
1028 (RSQRT.fmt): Make location of disassembly string consistent
1029 with other instructions.
1031 2002-06-12 Chris Demetriou <cgd@broadcom.com>
1033 * mips.igen (X): Delete unused function.
1035 2002-06-08 Andrew Cagney <cagney@redhat.com>
1037 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1039 2002-06-07 Chris Demetriou <cgd@broadcom.com>
1040 Ed Satterthwaite <ehs@broadcom.com>
1042 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1043 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1044 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1045 (fp_nmsub): New prototypes.
1046 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1047 (NegMultiplySub): New defines.
1048 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1049 (MADD.D, MADD.S): Replace with...
1050 (MADD.fmt): New instruction.
1051 (MSUB.D, MSUB.S): Replace with...
1052 (MSUB.fmt): New instruction.
1053 (NMADD.D, NMADD.S): Replace with...
1054 (NMADD.fmt): New instruction.
1055 (NMSUB.D, MSUB.S): Replace with...
1056 (NMSUB.fmt): New instruction.
1058 2002-06-07 Chris Demetriou <cgd@broadcom.com>
1059 Ed Satterthwaite <ehs@broadcom.com>
1061 * cp1.c: Fix more comment spelling and formatting.
1062 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1063 (denorm_mode): New function.
1064 (fpu_unary, fpu_binary): Round results after operation, collect
1065 status from rounding operations, and update the FCSR.
1066 (convert): Collect status from integer conversions and rounding
1067 operations, and update the FCSR. Adjust NaN values that result
1068 from conversions. Convert to use sim_io_eprintf rather than
1069 fprintf, and remove some debugging code.
1070 * cp1.h (fenr_FS): New define.
1072 2002-06-07 Chris Demetriou <cgd@broadcom.com>
1074 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1075 rounding mode to sim FP rounding mode flag conversion code into...
1076 (rounding_mode): New function.
1078 2002-06-07 Chris Demetriou <cgd@broadcom.com>
1080 * cp1.c: Clean up formatting of a few comments.
1081 (value_fpr): Reformat switch statement.
1083 2002-06-06 Chris Demetriou <cgd@broadcom.com>
1084 Ed Satterthwaite <ehs@broadcom.com>
1087 * sim-main.h: Include cp1.h.
1088 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1089 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1090 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1091 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1092 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1093 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1094 * cp1.c: Don't include sim-fpu.h; already included by
1095 sim-main.h. Clean up formatting of some comments.
1096 (NaN, Equal, Less): Remove.
1097 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1098 (fp_cmp): New functions.
1099 * mips.igen (do_c_cond_fmt): Remove.
1100 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1101 Compare. Add result tracing.
1102 (CxC1): Remove, replace with...
1103 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1104 (DMxC1): Remove, replace with...
1105 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
1106 (MxC1): Remove, replace with...
1107 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
1109 2002-06-04 Chris Demetriou <cgd@broadcom.com>
1111 * sim-main.h (FGRIDX): Remove, replace all uses with...
1112 (FGR_BASE): New macro.
1113 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1114 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1115 (NR_FGR, FGR): Likewise.
1116 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1117 * mips.igen: Likewise.
1119 2002-06-04 Chris Demetriou <cgd@broadcom.com>
1121 * cp1.c: Add an FSF Copyright notice to this file.
1123 2002-06-04 Chris Demetriou <cgd@broadcom.com>
1124 Ed Satterthwaite <ehs@broadcom.com>
1126 * cp1.c (Infinity): Remove.
1127 * sim-main.h (Infinity): Likewise.
1129 * cp1.c (fp_unary, fp_binary): New functions.
1130 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1131 (fp_sqrt): New functions, implemented in terms of the above.
1132 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1133 (Recip, SquareRoot): Remove (replaced by functions above).
1134 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1135 (fp_recip, fp_sqrt): New prototypes.
1136 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1137 (Recip, SquareRoot): Replace prototypes with #defines which
1138 invoke the functions above.
1140 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1142 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1143 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1144 file, remove PARAMS from prototypes.
1145 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1146 simulator state arguments.
1147 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1148 pass simulator state arguments.
1149 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1150 (store_fpr, convert): Remove 'sd' argument.
1151 (value_fpr): Likewise. Convert to use 'SD' instead.
1153 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1155 * cp1.c (Min, Max): Remove #if 0'd functions.
1156 * sim-main.h (Min, Max): Remove.
1158 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1160 * cp1.c: fix formatting of switch case and default labels.
1161 * interp.c: Likewise.
1162 * sim-main.c: Likewise.
1164 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1166 * cp1.c: Clean up comments which describe FP formats.
1167 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1169 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1170 Ed Satterthwaite <ehs@broadcom.com>
1172 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1173 Broadcom SiByte SB-1 processor configurations.
1174 * configure: Regenerate.
1175 * sb1.igen: New file.
1176 * mips.igen: Include sb1.igen.
1178 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1179 * mdmx.igen: Add "sb1" model to all appropriate functions and
1181 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1182 (ob_func, ob_acc): Reference the above.
1183 (qh_acc): Adjust to keep the same size as ob_acc.
1184 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1185 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1187 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1189 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1191 2002-06-02 Chris Demetriou <cgd@broadcom.com>
1192 Ed Satterthwaite <ehs@broadcom.com>
1194 * mips.igen (mdmx): New (pseudo-)model.
1195 * mdmx.c, mdmx.igen: New files.
1196 * Makefile.in (SIM_OBJS): Add mdmx.o.
1197 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1199 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1200 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1201 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1202 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1203 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1204 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1205 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1206 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1207 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1208 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1209 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1210 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1211 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1212 (qh_fmtsel): New macros.
1213 (_sim_cpu): New member "acc".
1214 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1215 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1217 2002-05-01 Chris Demetriou <cgd@broadcom.com>
1219 * interp.c: Use 'deprecated' rather than 'depreciated.'
1220 * sim-main.h: Likewise.
1222 2002-05-01 Chris Demetriou <cgd@broadcom.com>
1224 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1225 which wouldn't compile anyway.
1226 * sim-main.h (unpredictable_action): New function prototype.
1227 (Unpredictable): Define to call igen function unpredictable().
1228 (NotWordValue): New macro to call igen function not_word_value().
1229 (UndefinedResult): Remove.
1230 * interp.c (undefined_result): Remove.
1231 (unpredictable_action): New function.
1232 * mips.igen (not_word_value, unpredictable): New functions.
1233 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1234 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1235 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1236 NotWordValue() to check for unpredictable inputs, then
1237 Unpredictable() to handle them.
1239 2002-02-24 Chris Demetriou <cgd@broadcom.com>
1241 * mips.igen: Fix formatting of calls to Unpredictable().
1243 2002-04-20 Andrew Cagney <ac131313@redhat.com>
1245 * interp.c (sim_open): Revert previous change.
1247 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
1249 * interp.c (sim_open): Disable chunk of code that wrote code in
1250 vector table entries.
1252 2002-03-19 Chris Demetriou <cgd@broadcom.com>
1254 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1255 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1258 2002-03-19 Chris Demetriou <cgd@broadcom.com>
1260 * cp1.c: Fix many formatting issues.
1262 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1264 * cp1.c (fpu_format_name): New function to replace...
1265 (DOFMT): This. Delete, and update all callers.
1266 (fpu_rounding_mode_name): New function to replace...
1267 (RMMODE): This. Delete, and update all callers.
1269 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1271 * interp.c: Move FPU support routines from here to...
1272 * cp1.c: Here. New file.
1273 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1274 (cp1.o): New target.
1276 2002-03-12 Chris Demetriou <cgd@broadcom.com>
1278 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1279 * mips.igen (mips32, mips64): New models, add to all instructions
1280 and functions as appropriate.
1281 (loadstore_ea, check_u64): New variant for model mips64.
1282 (check_fmt_p): New variant for models mipsV and mips64, remove
1283 mipsV model marking fro other variant.
1286 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1287 for mips32 and mips64.
1288 (DCLO, DCLZ): New instructions for mips64.
1290 2002-03-07 Chris Demetriou <cgd@broadcom.com>
1292 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1293 immediate or code as a hex value with the "%#lx" format.
1294 (ANDI): Likewise, and fix printed instruction name.
1296 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1298 * sim-main.h (UndefinedResult, Unpredictable): New macros
1299 which currently do nothing.
1301 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1303 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1304 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1305 (status_CU3): New definitions.
1307 * sim-main.h (ExceptionCause): Add new values for MIPS32
1308 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1309 for DebugBreakPoint and NMIReset to note their status in
1311 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1312 (SignalExceptionCacheErr): New exception macros.
1314 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1316 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1317 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1319 (SignalExceptionCoProcessorUnusable): Take as argument the
1320 unusable coprocessor number.
1322 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1324 * mips.igen: Fix formatting of all SignalException calls.
1326 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1328 * sim-main.h (SIGNEXTEND): Remove.
1330 2002-03-04 Chris Demetriou <cgd@broadcom.com>
1332 * mips.igen: Remove gencode comment from top of file, fix
1333 spelling in another comment.
1335 2002-03-04 Chris Demetriou <cgd@broadcom.com>
1337 * mips.igen (check_fmt, check_fmt_p): New functions to check
1338 whether specific floating point formats are usable.
1339 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1340 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1341 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1342 Use the new functions.
1343 (do_c_cond_fmt): Remove format checks...
1344 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1346 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1348 * mips.igen: Fix formatting of check_fpu calls.
1350 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1352 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1354 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1356 * mips.igen: Remove whitespace at end of lines.
1358 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1360 * mips.igen (loadstore_ea): New function to do effective
1361 address calculations.
1362 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1363 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1364 CACHE): Use loadstore_ea to do effective address computations.
1366 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1368 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1369 * mips.igen (LL, CxC1, MxC1): Likewise.
1371 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1373 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1374 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1375 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1376 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1377 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1378 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1379 Don't split opcode fields by hand, use the opcode field values
1382 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1384 * mips.igen (do_divu): Fix spacing.
1386 * mips.igen (do_dsllv): Move to be right before DSLLV,
1387 to match the rest of the do_<shift> functions.
1389 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1391 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1392 DSRL32, do_dsrlv): Trace inputs and results.
1394 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1396 * mips.igen (CACHE): Provide instruction-printing string.
1398 * interp.c (signal_exception): Comment tokens after #endif.
1400 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1402 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1403 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1404 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1405 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1406 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1407 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1408 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1409 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1411 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1413 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1414 instruction-printing string.
1415 (LWU): Use '64' as the filter flag.
1417 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1419 * mips.igen (SDXC1): Fix instruction-printing string.
1421 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1423 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1424 filter flags "32,f".
1426 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1428 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1431 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1433 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1434 add a comma) so that it more closely match the MIPS ISA
1435 documentation opcode partitioning.
1436 (PREF): Put useful names on opcode fields, and include
1437 instruction-printing string.
1439 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1441 * mips.igen (check_u64): New function which in the future will
1442 check whether 64-bit instructions are usable and signal an
1443 exception if not. Currently a no-op.
1444 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1445 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1446 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1447 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1449 * mips.igen (check_fpu): New function which in the future will
1450 check whether FPU instructions are usable and signal an exception
1451 if not. Currently a no-op.
1452 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1453 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1454 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1455 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1456 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1457 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1458 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1459 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1461 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1463 * mips.igen (do_load_left, do_load_right): Move to be immediately
1465 (do_store_left, do_store_right): Move to be immediately following
1468 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1470 * mips.igen (mipsV): New model name. Also, add it to
1471 all instructions and functions where it is appropriate.
1473 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1475 * mips.igen: For all functions and instructions, list model
1476 names that support that instruction one per line.
1478 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1480 * mips.igen: Add some additional comments about supported
1481 models, and about which instructions go where.
1482 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1483 order as is used in the rest of the file.
1485 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1487 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1488 indicating that ALU32_END or ALU64_END are there to check
1490 (DADD): Likewise, but also remove previous comment about
1493 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1495 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1496 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1497 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1498 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1499 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1500 fields (i.e., add and move commas) so that they more closely
1501 match the MIPS ISA documentation opcode partitioning.
1503 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1505 * mips.igen (ADDI): Print immediate value.
1506 (BREAK): Print code.
1507 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1508 (SLL): Print "nop" specially, and don't run the code
1509 that does the shift for the "nop" case.
1511 2001-11-17 Fred Fish <fnf@redhat.com>
1513 * sim-main.h (float_operation): Move enum declaration outside
1514 of _sim_cpu struct declaration.
1516 2001-04-12 Jim Blandy <jimb@redhat.com>
1518 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1519 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1521 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1522 PENDING_FILL, and you can get the intended effect gracefully by
1523 calling PENDING_SCHED directly.
1525 2001-02-23 Ben Elliston <bje@redhat.com>
1527 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1528 already defined elsewhere.
1530 2001-02-19 Ben Elliston <bje@redhat.com>
1532 * sim-main.h (sim_monitor): Return an int.
1533 * interp.c (sim_monitor): Add return values.
1534 (signal_exception): Handle error conditions from sim_monitor.
1536 2001-02-08 Ben Elliston <bje@redhat.com>
1538 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1539 (store_memory): Likewise, pass cia to sim_core_write*.
1541 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1543 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1544 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1546 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1548 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1549 * Makefile.in: Don't delete *.igen when cleaning directory.
1551 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1553 * m16.igen (break): Call SignalException not sim_engine_halt.
1555 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1557 From Jason Eckhardt:
1558 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1560 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1562 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1564 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1566 * mips.igen (do_dmultx): Fix typo.
1568 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1570 * configure: Regenerated to track ../common/aclocal.m4 changes.
1572 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1574 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1576 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1578 * sim-main.h (GPR_CLEAR): Define macro.
1580 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1582 * interp.c (decode_coproc): Output long using %lx and not %s.
1584 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1586 * interp.c (sim_open): Sort & extend dummy memory regions for
1587 --board=jmr3904 for eCos.
1589 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1591 * configure: Regenerated.
1593 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1595 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1596 calls, conditional on the simulator being in verbose mode.
1598 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1600 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1601 cache don't get ReservedInstruction traps.
1603 1999-11-29 Mark Salter <msalter@cygnus.com>
1605 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1606 to clear status bits in sdisr register. This is how the hardware works.
1608 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1609 being used by cygmon.
1611 1999-11-11 Andrew Haley <aph@cygnus.com>
1613 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1616 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1618 * mips.igen (MULT): Correct previous mis-applied patch.
1620 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1622 * mips.igen (delayslot32): Handle sequence like
1623 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1624 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1625 (MULT): Actually pass the third register...
1627 1999-09-03 Mark Salter <msalter@cygnus.com>
1629 * interp.c (sim_open): Added more memory aliases for additional
1630 hardware being touched by cygmon on jmr3904 board.
1632 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1634 * configure: Regenerated to track ../common/aclocal.m4 changes.
1636 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1638 * interp.c (sim_store_register): Handle case where client - GDB -
1639 specifies that a 4 byte register is 8 bytes in size.
1640 (sim_fetch_register): Ditto.
1642 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1644 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1645 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1646 (idt_monitor_base): Base address for IDT monitor traps.
1647 (pmon_monitor_base): Ditto for PMON.
1648 (lsipmon_monitor_base): Ditto for LSI PMON.
1649 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1650 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1651 (sim_firmware_command): New function.
1652 (mips_option_handler): Call it for OPTION_FIRMWARE.
1653 (sim_open): Allocate memory for idt_monitor region. If "--board"
1654 option was given, add no monitor by default. Add BREAK hooks only if
1655 monitors are also there.
1657 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1659 * interp.c (sim_monitor): Flush output before reading input.
1661 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1663 * tconfig.in (SIM_HANDLES_LMA): Always define.
1665 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1667 From Mark Salter <msalter@cygnus.com>:
1668 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1669 (sim_open): Add setup for BSP board.
1671 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1673 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1674 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1675 them as unimplemented.
1677 1999-05-08 Felix Lee <flee@cygnus.com>
1679 * configure: Regenerated to track ../common/aclocal.m4 changes.
1681 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1683 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1685 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1687 * configure.in: Any mips64vr5*-*-* target should have
1688 -DTARGET_ENABLE_FR=1.
1689 (default_endian): Any mips64vr*el-*-* target should default to
1691 * configure: Re-generate.
1693 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1695 * mips.igen (ldl): Extend from _16_, not 32.
1697 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1699 * interp.c (sim_store_register): Force registers written to by GDB
1700 into an un-interpreted state.
1702 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1704 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1705 CPU, start periodic background I/O polls.
1706 (tx3904sio_poll): New function: periodic I/O poller.
1708 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1710 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1712 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1714 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1717 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1719 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1720 (load_word): Call SIM_CORE_SIGNAL hook on error.
1721 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1722 starting. For exception dispatching, pass PC instead of NULL_CIA.
1723 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1724 * sim-main.h (COP0_BADVADDR): Define.
1725 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1726 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1727 (_sim_cpu): Add exc_* fields to store register value snapshots.
1728 * mips.igen (*): Replace memory-related SignalException* calls
1729 with references to SIM_CORE_SIGNAL hook.
1731 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1733 * sim-main.c (*): Minor warning cleanups.
1735 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1737 * m16.igen (DADDIU5): Correct type-o.
1739 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1741 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1744 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1746 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1748 (interp.o): Add dependency on itable.h
1749 (oengine.c, gencode): Delete remaining references.
1750 (BUILT_SRC_FROM_GEN): Clean up.
1752 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1755 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1756 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1757 tmp-run-hack) : New.
1758 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1759 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1760 Drop the "64" qualifier to get the HACK generator working.
1761 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1762 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1763 qualifier to get the hack generator working.
1764 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1765 (DSLL): Use do_dsll.
1766 (DSLLV): Use do_dsllv.
1767 (DSRA): Use do_dsra.
1768 (DSRL): Use do_dsrl.
1769 (DSRLV): Use do_dsrlv.
1770 (BC1): Move *vr4100 to get the HACK generator working.
1771 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1772 get the HACK generator working.
1773 (MACC) Rename to get the HACK generator working.
1774 (DMACC,MACCS,DMACCS): Add the 64.
1776 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1778 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1779 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1781 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1783 * mips/interp.c (DEBUG): Cleanups.
1785 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1787 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1788 (tx3904sio_tickle): fflush after a stdout character output.
1790 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1792 * interp.c (sim_close): Uninstall modules.
1794 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1796 * sim-main.h, interp.c (sim_monitor): Change to global
1799 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1801 * configure.in (vr4100): Only include vr4100 instructions in
1803 * configure: Re-generate.
1804 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1806 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1808 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1809 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1812 * configure.in (sim_default_gen, sim_use_gen): Replace with
1814 (--enable-sim-igen): Delete config option. Always using IGEN.
1815 * configure: Re-generate.
1817 * Makefile.in (gencode): Kill, kill, kill.
1820 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1822 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1823 bit mips16 igen simulator.
1824 * configure: Re-generate.
1826 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1827 as part of vr4100 ISA.
1828 * vr.igen: Mark all instructions as 64 bit only.
1830 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1832 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1835 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1837 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1838 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1839 * configure: Re-generate.
1841 * m16.igen (BREAK): Define breakpoint instruction.
1842 (JALX32): Mark instruction as mips16 and not r3900.
1843 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1845 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1847 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1849 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1850 insn as a debug breakpoint.
1852 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1854 (PENDING_SCHED): Clean up trace statement.
1855 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1856 (PENDING_FILL): Delay write by only one cycle.
1857 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1859 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1861 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1863 (pending_tick): Move incrementing of index to FOR statement.
1864 (pending_tick): Only update PENDING_OUT after a write has occured.
1866 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1868 * configure: Re-generate.
1870 * interp.c (sim_engine_run OLD): Delete explicit call to
1871 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1873 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1875 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1876 interrupt level number to match changed SignalExceptionInterrupt
1879 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1881 * interp.c: #include "itable.h" if WITH_IGEN.
1882 (get_insn_name): New function.
1883 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1884 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1886 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1888 * configure: Rebuilt to inhale new common/aclocal.m4.
1890 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1892 * dv-tx3904sio.c: Include sim-assert.h.
1894 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1896 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1897 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1898 Reorganize target-specific sim-hardware checks.
1899 * configure: rebuilt.
1900 * interp.c (sim_open): For tx39 target boards, set
1901 OPERATING_ENVIRONMENT, add tx3904sio devices.
1902 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1903 ROM executables. Install dv-sockser into sim-modules list.
1905 * dv-tx3904irc.c: Compiler warning clean-up.
1906 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1907 frequent hw-trace messages.
1909 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1911 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1913 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1915 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1917 * vr.igen: New file.
1918 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1919 * mips.igen: Define vr4100 model. Include vr.igen.
1920 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1922 * mips.igen (check_mf_hilo): Correct check.
1924 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1926 * sim-main.h (interrupt_event): Add prototype.
1928 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1929 register_ptr, register_value.
1930 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1932 * sim-main.h (tracefh): Make extern.
1934 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1936 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1937 Reduce unnecessarily high timer event frequency.
1938 * dv-tx3904cpu.c: Ditto for interrupt event.
1940 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1942 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1944 (interrupt_event): Made non-static.
1946 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1947 interchange of configuration values for external vs. internal
1950 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1952 * mips.igen (BREAK): Moved code to here for
1953 simulator-reserved break instructions.
1954 * gencode.c (build_instruction): Ditto.
1955 * interp.c (signal_exception): Code moved from here. Non-
1956 reserved instructions now use exception vector, rather
1958 * sim-main.h: Moved magic constants to here.
1960 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1962 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1963 register upon non-zero interrupt event level, clear upon zero
1965 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1966 by passing zero event value.
1967 (*_io_{read,write}_buffer): Endianness fixes.
1968 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1969 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1971 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1972 serial I/O and timer module at base address 0xFFFF0000.
1974 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1976 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1979 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1981 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1983 * configure: Update.
1985 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1987 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1988 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1989 * configure.in: Include tx3904tmr in hw_device list.
1990 * configure: Rebuilt.
1991 * interp.c (sim_open): Instantiate three timer instances.
1992 Fix address typo of tx3904irc instance.
1994 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1996 * interp.c (signal_exception): SystemCall exception now uses
1997 the exception vector.
1999 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2001 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2004 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2006 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2008 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2010 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2012 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2013 sim-main.h. Declare a struct hw_descriptor instead of struct
2014 hw_device_descriptor.
2016 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2018 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2019 right bits and then re-align left hand bytes to correct byte
2020 lanes. Fix incorrect computation in do_store_left when loading
2021 bytes from second word.
2023 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2025 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2026 * interp.c (sim_open): Only create a device tree when HW is
2029 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2030 * interp.c (signal_exception): Ditto.
2032 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2034 * gencode.c: Mark BEGEZALL as LIKELY.
2036 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2038 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2039 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
2041 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2043 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2044 modules. Recognize TX39 target with "mips*tx39" pattern.
2045 * configure: Rebuilt.
2046 * sim-main.h (*): Added many macros defining bits in
2047 TX39 control registers.
2048 (SignalInterrupt): Send actual PC instead of NULL.
2049 (SignalNMIReset): New exception type.
2050 * interp.c (board): New variable for future use to identify
2051 a particular board being simulated.
2052 (mips_option_handler,mips_options): Added "--board" option.
2053 (interrupt_event): Send actual PC.
2054 (sim_open): Make memory layout conditional on board setting.
2055 (signal_exception): Initial implementation of hardware interrupt
2056 handling. Accept another break instruction variant for simulator
2058 (decode_coproc): Implement RFE instruction for TX39.
2059 (mips.igen): Decode RFE instruction as such.
2060 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2061 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2062 bbegin to implement memory map.
2063 * dv-tx3904cpu.c: New file.
2064 * dv-tx3904irc.c: New file.
2066 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2068 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2070 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2072 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2073 with calls to check_div_hilo.
2075 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2077 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2078 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
2079 Add special r3900 version of do_mult_hilo.
2080 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2081 with calls to check_mult_hilo.
2082 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2083 with calls to check_div_hilo.
2085 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2087 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2088 Document a replacement.
2090 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2092 * interp.c (sim_monitor): Make mon_printf work.
2094 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2096 * sim-main.h (INSN_NAME): New arg `cpu'.
2098 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2100 * configure: Regenerated to track ../common/aclocal.m4 changes.
2102 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2104 * configure: Regenerated to track ../common/aclocal.m4 changes.
2107 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2109 * acconfig.h: New file.
2110 * configure.in: Reverted change of Apr 24; use sinclude again.
2112 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2114 * configure: Regenerated to track ../common/aclocal.m4 changes.
2117 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2119 * configure.in: Don't call sinclude.
2121 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2123 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2125 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2127 * mips.igen (ERET): Implement.
2129 * interp.c (decode_coproc): Return sign-extended EPC.
2131 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2133 * interp.c (signal_exception): Do not ignore Trap.
2134 (signal_exception): On TRAP, restart at exception address.
2135 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2136 (signal_exception): Update.
2137 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2138 so that TRAP instructions are caught.
2140 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2142 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2143 contains HI/LO access history.
2144 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2145 (HIACCESS, LOACCESS): Delete, replace with
2146 (HIHISTORY, LOHISTORY): New macros.
2147 (CHECKHILO): Delete all, moved to mips.igen
2149 * gencode.c (build_instruction): Do not generate checks for
2150 correct HI/LO register usage.
2152 * interp.c (old_engine_run): Delete checks for correct HI/LO
2155 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2156 check_mf_cycles): New functions.
2157 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2158 do_divu, domultx, do_mult, do_multu): Use.
2160 * tx.igen ("madd", "maddu"): Use.
2162 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2164 * mips.igen (DSRAV): Use function do_dsrav.
2165 (SRAV): Use new function do_srav.
2167 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2168 (B): Sign extend 11 bit immediate.
2169 (EXT-B*): Shift 16 bit immediate left by 1.
2170 (ADDIU*): Don't sign extend immediate value.
2172 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2174 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2176 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2179 * mips.igen (delayslot32, nullify_next_insn): New functions.
2180 (m16.igen): Always include.
2181 (do_*): Add more tracing.
2183 * m16.igen (delayslot16): Add NIA argument, could be called by a
2184 32 bit MIPS16 instruction.
2186 * interp.c (ifetch16): Move function from here.
2187 * sim-main.c (ifetch16): To here.
2189 * sim-main.c (ifetch16, ifetch32): Update to match current
2190 implementations of LH, LW.
2191 (signal_exception): Don't print out incorrect hex value of illegal
2194 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2196 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2199 * m16.igen: Implement MIPS16 instructions.
2201 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2202 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2203 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2204 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2205 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2206 bodies of corresponding code from 32 bit insn to these. Also used
2207 by MIPS16 versions of functions.
2209 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2210 (IMEM16): Drop NR argument from macro.
2212 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2214 * Makefile.in (SIM_OBJS): Add sim-main.o.
2216 * sim-main.h (address_translation, load_memory, store_memory,
2217 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2219 (pr_addr, pr_uword64): Declare.
2220 (sim-main.c): Include when H_REVEALS_MODULE_P.
2222 * interp.c (address_translation, load_memory, store_memory,
2223 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2225 * sim-main.c: To here. Fix compilation problems.
2227 * configure.in: Enable inlining.
2228 * configure: Re-config.
2230 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2232 * configure: Regenerated to track ../common/aclocal.m4 changes.
2234 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2236 * mips.igen: Include tx.igen.
2237 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2238 * tx.igen: New file, contains MADD and MADDU.
2240 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2241 the hardwired constant `7'.
2242 (store_memory): Ditto.
2243 (LOADDRMASK): Move definition to sim-main.h.
2245 mips.igen (MTC0): Enable for r3900.
2248 mips.igen (do_load_byte): Delete.
2249 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2250 do_store_right): New functions.
2251 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2253 configure.in: Let the tx39 use igen again.
2256 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2258 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2259 not an address sized quantity. Return zero for cache sizes.
2261 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2263 * mips.igen (r3900): r3900 does not support 64 bit integer
2266 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2268 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2270 * configure : Rebuild.
2272 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2274 * configure: Regenerated to track ../common/aclocal.m4 changes.
2276 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2278 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2280 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2282 * configure: Regenerated to track ../common/aclocal.m4 changes.
2283 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2285 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2287 * configure: Regenerated to track ../common/aclocal.m4 changes.
2289 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2291 * interp.c (Max, Min): Comment out functions. Not yet used.
2293 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2295 * configure: Regenerated to track ../common/aclocal.m4 changes.
2297 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2299 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2300 configurable settings for stand-alone simulator.
2302 * configure.in: Added X11 search, just in case.
2304 * configure: Regenerated.
2306 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2308 * interp.c (sim_write, sim_read, load_memory, store_memory):
2309 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2311 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2313 * sim-main.h (GETFCC): Return an unsigned value.
2315 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2317 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2318 (DADD): Result destination is RD not RT.
2320 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2322 * sim-main.h (HIACCESS, LOACCESS): Always define.
2324 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2326 * interp.c (sim_info): Delete.
2328 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2330 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2331 (mips_option_handler): New argument `cpu'.
2332 (sim_open): Update call to sim_add_option_table.
2334 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2336 * mips.igen (CxC1): Add tracing.
2338 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2340 * sim-main.h (Max, Min): Declare.
2342 * interp.c (Max, Min): New functions.
2344 * mips.igen (BC1): Add tracing.
2346 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
2348 * interp.c Added memory map for stack in vr4100
2350 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2352 * interp.c (load_memory): Add missing "break"'s.
2354 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2356 * interp.c (sim_store_register, sim_fetch_register): Pass in
2357 length parameter. Return -1.
2359 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2361 * interp.c: Added hardware init hook, fixed warnings.
2363 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2365 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2367 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2369 * interp.c (ifetch16): New function.
2371 * sim-main.h (IMEM32): Rename IMEM.
2372 (IMEM16_IMMED): Define.
2374 (DELAY_SLOT): Update.
2376 * m16run.c (sim_engine_run): New file.
2378 * m16.igen: All instructions except LB.
2379 (LB): Call do_load_byte.
2380 * mips.igen (do_load_byte): New function.
2381 (LB): Call do_load_byte.
2383 * mips.igen: Move spec for insn bit size and high bit from here.
2384 * Makefile.in (tmp-igen, tmp-m16): To here.
2386 * m16.dc: New file, decode mips16 instructions.
2388 * Makefile.in (SIM_NO_ALL): Define.
2389 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2391 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2393 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2394 point unit to 32 bit registers.
2395 * configure: Re-generate.
2397 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2399 * configure.in (sim_use_gen): Make IGEN the default simulator
2400 generator for generic 32 and 64 bit mips targets.
2401 * configure: Re-generate.
2403 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2405 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2408 * interp.c (sim_fetch_register, sim_store_register): Read/write
2409 FGR from correct location.
2410 (sim_open): Set size of FGR's according to
2411 WITH_TARGET_FLOATING_POINT_BITSIZE.
2413 * sim-main.h (FGR): Store floating point registers in a separate
2416 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2418 * configure: Regenerated to track ../common/aclocal.m4 changes.
2420 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2422 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2424 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2426 * interp.c (pending_tick): New function. Deliver pending writes.
2428 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2429 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2430 it can handle mixed sized quantites and single bits.
2432 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2434 * interp.c (oengine.h): Do not include when building with IGEN.
2435 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2436 (sim_info): Ditto for PROCESSOR_64BIT.
2437 (sim_monitor): Replace ut_reg with unsigned_word.
2438 (*): Ditto for t_reg.
2439 (LOADDRMASK): Define.
2440 (sim_open): Remove defunct check that host FP is IEEE compliant,
2441 using software to emulate floating point.
2442 (value_fpr, ...): Always compile, was conditional on HASFPU.
2444 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2446 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2449 * interp.c (SD, CPU): Define.
2450 (mips_option_handler): Set flags in each CPU.
2451 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2452 (sim_close): Do not clear STATE, deleted anyway.
2453 (sim_write, sim_read): Assume CPU zero's vm should be used for
2455 (sim_create_inferior): Set the PC for all processors.
2456 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2458 (mips16_entry): Pass correct nr of args to store_word, load_word.
2459 (ColdReset): Cold reset all cpu's.
2460 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2461 (sim_monitor, load_memory, store_memory, signal_exception): Use
2462 `CPU' instead of STATE_CPU.
2465 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2468 * sim-main.h (signal_exception): Add sim_cpu arg.
2469 (SignalException*): Pass both SD and CPU to signal_exception.
2470 * interp.c (signal_exception): Update.
2472 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2474 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2475 address_translation): Ditto
2476 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2478 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2480 * configure: Regenerated to track ../common/aclocal.m4 changes.
2482 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2484 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2486 * mips.igen (model): Map processor names onto BFD name.
2488 * sim-main.h (CPU_CIA): Delete.
2489 (SET_CIA, GET_CIA): Define
2491 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2493 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2496 * configure.in (default_endian): Configure a big-endian simulator
2498 * configure: Re-generate.
2500 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2502 * configure: Regenerated to track ../common/aclocal.m4 changes.
2504 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2506 * interp.c (sim_monitor): Handle Densan monitor outbyte
2507 and inbyte functions.
2509 1997-12-29 Felix Lee <flee@cygnus.com>
2511 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2513 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2515 * Makefile.in (tmp-igen): Arrange for $zero to always be
2516 reset to zero after every instruction.
2518 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2520 * configure: Regenerated to track ../common/aclocal.m4 changes.
2523 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2525 * mips.igen (MSUB): Fix to work like MADD.
2526 * gencode.c (MSUB): Similarly.
2528 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2530 * configure: Regenerated to track ../common/aclocal.m4 changes.
2532 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2534 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2536 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2538 * sim-main.h (sim-fpu.h): Include.
2540 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2541 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2542 using host independant sim_fpu module.
2544 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2546 * interp.c (signal_exception): Report internal errors with SIGABRT
2549 * sim-main.h (C0_CONFIG): New register.
2550 (signal.h): No longer include.
2552 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2554 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2556 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2558 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2560 * mips.igen: Tag vr5000 instructions.
2561 (ANDI): Was missing mipsIV model, fix assembler syntax.
2562 (do_c_cond_fmt): New function.
2563 (C.cond.fmt): Handle mips I-III which do not support CC field
2565 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2566 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2568 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2569 vr5000 which saves LO in a GPR separatly.
2571 * configure.in (enable-sim-igen): For vr5000, select vr5000
2572 specific instructions.
2573 * configure: Re-generate.
2575 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2577 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2579 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2580 fmt_uninterpreted_64 bit cases to switch. Convert to
2583 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2585 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2586 as specified in IV3.2 spec.
2587 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2589 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2591 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2592 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2593 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2594 PENDING_FILL versions of instructions. Simplify.
2596 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2598 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2600 (MTHI, MFHI): Disable code checking HI-LO.
2602 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2604 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2606 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2608 * gencode.c (build_mips16_operands): Replace IPC with cia.
2610 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2611 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2613 (UndefinedResult): Replace function with macro/function
2615 (sim_engine_run): Don't save PC in IPC.
2617 * sim-main.h (IPC): Delete.
2620 * interp.c (signal_exception, store_word, load_word,
2621 address_translation, load_memory, store_memory, cache_op,
2622 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2623 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2624 current instruction address - cia - argument.
2625 (sim_read, sim_write): Call address_translation directly.
2626 (sim_engine_run): Rename variable vaddr to cia.
2627 (signal_exception): Pass cia to sim_monitor
2629 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2630 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2631 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2633 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2634 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2637 * interp.c (signal_exception): Pass restart address to
2640 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2641 idecode.o): Add dependency.
2643 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2645 (DELAY_SLOT): Update NIA not PC with branch address.
2646 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2648 * mips.igen: Use CIA not PC in branch calculations.
2649 (illegal): Call SignalException.
2650 (BEQ, ADDIU): Fix assembler.
2652 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2654 * m16.igen (JALX): Was missing.
2656 * configure.in (enable-sim-igen): New configuration option.
2657 * configure: Re-generate.
2659 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2661 * interp.c (load_memory, store_memory): Delete parameter RAW.
2662 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2663 bypassing {load,store}_memory.
2665 * sim-main.h (ByteSwapMem): Delete definition.
2667 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2669 * interp.c (sim_do_command, sim_commands): Delete mips specific
2670 commands. Handled by module sim-options.
2672 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2673 (WITH_MODULO_MEMORY): Define.
2675 * interp.c (sim_info): Delete code printing memory size.
2677 * interp.c (mips_size): Nee sim_size, delete function.
2679 (monitor, monitor_base, monitor_size): Delete global variables.
2680 (sim_open, sim_close): Delete code creating monitor and other
2681 memory regions. Use sim-memopts module, via sim_do_commandf, to
2682 manage memory regions.
2683 (load_memory, store_memory): Use sim-core for memory model.
2685 * interp.c (address_translation): Delete all memory map code
2686 except line forcing 32 bit addresses.
2688 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2690 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2693 * interp.c (logfh, logfile): Delete globals.
2694 (sim_open, sim_close): Delete code opening & closing log file.
2695 (mips_option_handler): Delete -l and -n options.
2696 (OPTION mips_options): Ditto.
2698 * interp.c (OPTION mips_options): Rename option trace to dinero.
2699 (mips_option_handler): Update.
2701 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2703 * interp.c (fetch_str): New function.
2704 (sim_monitor): Rewrite using sim_read & sim_write.
2705 (sim_open): Check magic number.
2706 (sim_open): Write monitor vectors into memory using sim_write.
2707 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2708 (sim_read, sim_write): Simplify - transfer data one byte at a
2710 (load_memory, store_memory): Clarify meaning of parameter RAW.
2712 * sim-main.h (isHOST): Defete definition.
2713 (isTARGET): Mark as depreciated.
2714 (address_translation): Delete parameter HOST.
2716 * interp.c (address_translation): Delete parameter HOST.
2718 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2722 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2723 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2725 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2727 * mips.igen: Add model filter field to records.
2729 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2731 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2733 interp.c (sim_engine_run): Do not compile function sim_engine_run
2734 when WITH_IGEN == 1.
2736 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2737 target architecture.
2739 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2740 igen. Replace with configuration variables sim_igen_flags /
2743 * m16.igen: New file. Copy mips16 insns here.
2744 * mips.igen: From here.
2746 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2748 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2750 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2752 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2754 * gencode.c (build_instruction): Follow sim_write's lead in using
2755 BigEndianMem instead of !ByteSwapMem.
2757 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2759 * configure.in (sim_gen): Dependent on target, select type of
2760 generator. Always select old style generator.
2762 configure: Re-generate.
2764 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2766 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2767 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2768 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2769 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2770 SIM_@sim_gen@_*, set by autoconf.
2772 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2774 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2776 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2777 CURRENT_FLOATING_POINT instead.
2779 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2780 (address_translation): Raise exception InstructionFetch when
2781 translation fails and isINSTRUCTION.
2783 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2784 sim_engine_run): Change type of of vaddr and paddr to
2786 (address_translation, prefetch, load_memory, store_memory,
2787 cache_op): Change type of vAddr and pAddr to address_word.
2789 * gencode.c (build_instruction): Change type of vaddr and paddr to
2792 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2794 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2795 macro to obtain result of ALU op.
2797 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2799 * interp.c (sim_info): Call profile_print.
2801 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2803 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2805 * sim-main.h (WITH_PROFILE): Do not define, defined in
2806 common/sim-config.h. Use sim-profile module.
2807 (simPROFILE): Delete defintion.
2809 * interp.c (PROFILE): Delete definition.
2810 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2811 (sim_close): Delete code writing profile histogram.
2812 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2814 (sim_engine_run): Delete code profiling the PC.
2816 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2818 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2820 * interp.c (sim_monitor): Make register pointers of type
2823 * sim-main.h: Make registers of type unsigned_word not
2826 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2828 * interp.c (sync_operation): Rename from SyncOperation, make
2829 global, add SD argument.
2830 (prefetch): Rename from Prefetch, make global, add SD argument.
2831 (decode_coproc): Make global.
2833 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2835 * gencode.c (build_instruction): Generate DecodeCoproc not
2836 decode_coproc calls.
2838 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2839 (SizeFGR): Move to sim-main.h
2840 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2841 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2842 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2844 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2845 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2846 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2847 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2848 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2849 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2851 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2853 (sim-alu.h): Include.
2854 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2855 (sim_cia): Typedef to instruction_address.
2857 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2859 * Makefile.in (interp.o): Rename generated file engine.c to
2864 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2866 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2868 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2870 * gencode.c (build_instruction): For "FPSQRT", output correct
2871 number of arguments to Recip.
2873 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2875 * Makefile.in (interp.o): Depends on sim-main.h
2877 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2879 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2880 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2881 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2882 STATE, DSSTATE): Define
2883 (GPR, FGRIDX, ..): Define.
2885 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2886 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2887 (GPR, FGRIDX, ...): Delete macros.
2889 * interp.c: Update names to match defines from sim-main.h
2891 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2893 * interp.c (sim_monitor): Add SD argument.
2894 (sim_warning): Delete. Replace calls with calls to
2896 (sim_error): Delete. Replace calls with sim_io_error.
2897 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2898 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2899 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2901 (mips_size): Rename from sim_size. Add SD argument.
2903 * interp.c (simulator): Delete global variable.
2904 (callback): Delete global variable.
2905 (mips_option_handler, sim_open, sim_write, sim_read,
2906 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2907 sim_size,sim_monitor): Use sim_io_* not callback->*.
2908 (sim_open): ZALLOC simulator struct.
2909 (PROFILE): Do not define.
2911 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2913 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2914 support.h with corresponding code.
2916 * sim-main.h (word64, uword64), support.h: Move definition to
2918 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2921 * Makefile.in: Update dependencies
2922 * interp.c: Do not include.
2924 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2926 * interp.c (address_translation, load_memory, store_memory,
2927 cache_op): Rename to from AddressTranslation et.al., make global,
2930 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2933 * interp.c (SignalException): Rename to signal_exception, make
2936 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2938 * sim-main.h (SignalException, SignalExceptionInterrupt,
2939 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2940 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2941 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2944 * interp.c, support.h: Use.
2946 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2948 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2949 to value_fpr / store_fpr. Add SD argument.
2950 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2951 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2953 * sim-main.h (ValueFPR, StoreFPR): Define.
2955 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2957 * interp.c (sim_engine_run): Check consistency between configure
2958 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2961 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2962 (mips_fpu): Configure WITH_FLOATING_POINT.
2963 (mips_endian): Configure WITH_TARGET_ENDIAN.
2964 * configure: Update.
2966 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2968 * configure: Regenerated to track ../common/aclocal.m4 changes.
2970 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2972 * configure: Regenerated.
2974 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2976 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2978 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2980 * gencode.c (print_igen_insn_models): Assume certain architectures
2981 include all mips* instructions.
2982 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2985 * Makefile.in (tmp.igen): Add target. Generate igen input from
2988 * gencode.c (FEATURE_IGEN): Define.
2989 (main): Add --igen option. Generate output in igen format.
2990 (process_instructions): Format output according to igen option.
2991 (print_igen_insn_format): New function.
2992 (print_igen_insn_models): New function.
2993 (process_instructions): Only issue warnings and ignore
2994 instructions when no FEATURE_IGEN.
2996 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2998 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3001 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3003 * configure: Regenerated to track ../common/aclocal.m4 changes.
3005 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3007 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3008 SIM_RESERVED_BITS): Delete, moved to common.
3009 (SIM_EXTRA_CFLAGS): Update.
3011 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3013 * configure.in: Configure non-strict memory alignment.
3014 * configure: Regenerated to track ../common/aclocal.m4 changes.
3016 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3018 * configure: Regenerated to track ../common/aclocal.m4 changes.
3020 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3022 * gencode.c (SDBBP,DERET): Added (3900) insns.
3023 (RFE): Turn on for 3900.
3024 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3025 (dsstate): Made global.
3026 (SUBTARGET_R3900): Added.
3027 (CANCELDELAYSLOT): New.
3028 (SignalException): Ignore SystemCall rather than ignore and
3029 terminate. Add DebugBreakPoint handling.
3030 (decode_coproc): New insns RFE, DERET; and new registers Debug
3031 and DEPC protected by SUBTARGET_R3900.
3032 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3034 * Makefile.in,configure.in: Add mips subtarget option.
3035 * configure: Update.
3037 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3039 * gencode.c: Add r3900 (tx39).
3042 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3044 * gencode.c (build_instruction): Don't need to subtract 4 for
3047 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3049 * interp.c: Correct some HASFPU problems.
3051 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3053 * configure: Regenerated to track ../common/aclocal.m4 changes.
3055 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3057 * interp.c (mips_options): Fix samples option short form, should
3060 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3062 * interp.c (sim_info): Enable info code. Was just returning.
3064 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3066 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3069 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3071 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3073 (build_instruction): Ditto for LL.
3075 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3077 * configure: Regenerated to track ../common/aclocal.m4 changes.
3079 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3081 * configure: Regenerated to track ../common/aclocal.m4 changes.
3084 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3086 * interp.c (sim_open): Add call to sim_analyze_program, update
3089 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3091 * interp.c (sim_kill): Delete.
3092 (sim_create_inferior): Add ABFD argument. Set PC from same.
3093 (sim_load): Move code initializing trap handlers from here.
3094 (sim_open): To here.
3095 (sim_load): Delete, use sim-hload.c.
3097 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3099 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3101 * configure: Regenerated to track ../common/aclocal.m4 changes.
3104 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3106 * interp.c (sim_open): Add ABFD argument.
3107 (sim_load): Move call to sim_config from here.
3108 (sim_open): To here. Check return status.
3110 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
3112 * gencode.c (build_instruction): Two arg MADD should
3113 not assign result to $0.
3115 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3117 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3118 * sim/mips/configure.in: Regenerate.
3120 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3122 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3123 signed8, unsigned8 et.al. types.
3125 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3126 hosts when selecting subreg.
3128 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3130 * interp.c (sim_engine_run): Reset the ZERO register to zero
3131 regardless of FEATURE_WARN_ZERO.
3132 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3134 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3136 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3137 (SignalException): For BreakPoints ignore any mode bits and just
3139 (SignalException): Always set the CAUSE register.
3141 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3143 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3144 exception has been taken.
3146 * interp.c: Implement the ERET and mt/f sr instructions.
3148 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3150 * interp.c (SignalException): Don't bother restarting an
3153 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3155 * interp.c (SignalException): Really take an interrupt.
3156 (interrupt_event): Only deliver interrupts when enabled.
3158 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3160 * interp.c (sim_info): Only print info when verbose.
3161 (sim_info) Use sim_io_printf for output.
3163 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3165 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3168 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3170 * interp.c (sim_do_command): Check for common commands if a
3171 simulator specific command fails.
3173 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3175 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3176 and simBE when DEBUG is defined.
3178 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3180 * interp.c (interrupt_event): New function. Pass exception event
3181 onto exception handler.
3183 * configure.in: Check for stdlib.h.
3184 * configure: Regenerate.
3186 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3187 variable declaration.
3188 (build_instruction): Initialize memval1.
3189 (build_instruction): Add UNUSED attribute to byte, bigend,
3191 (build_operands): Ditto.
3193 * interp.c: Fix GCC warnings.
3194 (sim_get_quit_code): Delete.
3196 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3197 * Makefile.in: Ditto.
3198 * configure: Re-generate.
3200 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3202 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3204 * interp.c (mips_option_handler): New function parse argumes using
3206 (myname): Replace with STATE_MY_NAME.
3207 (sim_open): Delete check for host endianness - performed by
3209 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3210 (sim_open): Move much of the initialization from here.
3211 (sim_load): To here. After the image has been loaded and
3213 (sim_open): Move ColdReset from here.
3214 (sim_create_inferior): To here.
3215 (sim_open): Make FP check less dependant on host endianness.
3217 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3219 * interp.c (sim_set_callbacks): Delete.
3221 * interp.c (membank, membank_base, membank_size): Replace with
3222 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3223 (sim_open): Remove call to callback->init. gdb/run do this.
3227 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3229 * interp.c (big_endian_p): Delete, replaced by
3230 current_target_byte_order.
3232 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3234 * interp.c (host_read_long, host_read_word, host_swap_word,
3235 host_swap_long): Delete. Using common sim-endian.
3236 (sim_fetch_register, sim_store_register): Use H2T.
3237 (pipeline_ticks): Delete. Handled by sim-events.
3239 (sim_engine_run): Update.
3241 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3243 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3245 (SignalException): To here. Signal using sim_engine_halt.
3246 (sim_stop_reason): Delete, moved to common.
3248 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3250 * interp.c (sim_open): Add callback argument.
3251 (sim_set_callbacks): Delete SIM_DESC argument.
3254 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3256 * Makefile.in (SIM_OBJS): Add common modules.
3258 * interp.c (sim_set_callbacks): Also set SD callback.
3259 (set_endianness, xfer_*, swap_*): Delete.
3260 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3261 Change to functions using sim-endian macros.
3262 (control_c, sim_stop): Delete, use common version.
3263 (simulate): Convert into.
3264 (sim_engine_run): This function.
3265 (sim_resume): Delete.
3267 * interp.c (simulation): New variable - the simulator object.
3268 (sim_kind): Delete global - merged into simulation.
3269 (sim_load): Cleanup. Move PC assignment from here.
3270 (sim_create_inferior): To here.
3272 * sim-main.h: New file.
3273 * interp.c (sim-main.h): Include.
3275 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3277 * configure: Regenerated to track ../common/aclocal.m4 changes.
3279 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3281 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3283 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3285 * gencode.c (build_instruction): DIV instructions: check
3286 for division by zero and integer overflow before using
3287 host's division operation.
3289 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3291 * Makefile.in (SIM_OBJS): Add sim-load.o.
3292 * interp.c: #include bfd.h.
3293 (target_byte_order): Delete.
3294 (sim_kind, myname, big_endian_p): New static locals.
3295 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3296 after argument parsing. Recognize -E arg, set endianness accordingly.
3297 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3298 load file into simulator. Set PC from bfd.
3299 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3300 (set_endianness): Use big_endian_p instead of target_byte_order.
3302 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3304 * interp.c (sim_size): Delete prototype - conflicts with
3305 definition in remote-sim.h. Correct definition.
3307 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3309 * configure: Regenerated to track ../common/aclocal.m4 changes.
3312 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3314 * interp.c (sim_open): New arg `kind'.
3316 * configure: Regenerated to track ../common/aclocal.m4 changes.
3318 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3320 * configure: Regenerated to track ../common/aclocal.m4 changes.
3322 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3324 * interp.c (sim_open): Set optind to 0 before calling getopt.
3326 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3328 * configure: Regenerated to track ../common/aclocal.m4 changes.
3330 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3332 * interp.c : Replace uses of pr_addr with pr_uword64
3333 where the bit length is always 64 independent of SIM_ADDR.
3334 (pr_uword64) : added.
3336 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3338 * configure: Re-generate.
3340 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3342 * configure: Regenerate to track ../common/aclocal.m4 changes.
3344 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3346 * interp.c (sim_open): New SIM_DESC result. Argument is now
3348 (other sim_*): New SIM_DESC argument.
3350 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3352 * interp.c: Fix printing of addresses for non-64-bit targets.
3353 (pr_addr): Add function to print address based on size.
3355 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3357 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3359 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3361 * gencode.c (build_mips16_operands): Correct computation of base
3362 address for extended PC relative instruction.
3364 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3366 * interp.c (mips16_entry): Add support for floating point cases.
3367 (SignalException): Pass floating point cases to mips16_entry.
3368 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3370 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3372 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3373 and then set the state to fmt_uninterpreted.
3374 (COP_SW): Temporarily set the state to fmt_word while calling
3377 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3379 * gencode.c (build_instruction): The high order may be set in the
3380 comparison flags at any ISA level, not just ISA 4.
3382 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3384 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3385 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3386 * configure.in: sinclude ../common/aclocal.m4.
3387 * configure: Regenerated.
3389 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3391 * configure: Rebuild after change to aclocal.m4.
3393 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3395 * configure configure.in Makefile.in: Update to new configure
3396 scheme which is more compatible with WinGDB builds.
3397 * configure.in: Improve comment on how to run autoconf.
3398 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3399 * Makefile.in: Use autoconf substitution to install common
3402 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3404 * gencode.c (build_instruction): Use BigEndianCPU instead of
3407 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3409 * interp.c (sim_monitor): Make output to stdout visible in
3410 wingdb's I/O log window.
3412 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3414 * support.h: Undo previous change to SIGTRAP
3417 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3419 * interp.c (store_word, load_word): New static functions.
3420 (mips16_entry): New static function.
3421 (SignalException): Look for mips16 entry and exit instructions.
3422 (simulate): Use the correct index when setting fpr_state after
3423 doing a pending move.
3425 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3427 * interp.c: Fix byte-swapping code throughout to work on
3428 both little- and big-endian hosts.
3430 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3432 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3433 with gdb/config/i386/xm-windows.h.
3435 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3437 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3438 that messes up arithmetic shifts.
3440 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3442 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3443 SIGTRAP and SIGQUIT for _WIN32.
3445 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3447 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3448 force a 64 bit multiplication.
3449 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3450 destination register is 0, since that is the default mips16 nop
3453 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3455 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3456 (build_endian_shift): Don't check proc64.
3457 (build_instruction): Always set memval to uword64. Cast op2 to
3458 uword64 when shifting it left in memory instructions. Always use
3459 the same code for stores--don't special case proc64.
3461 * gencode.c (build_mips16_operands): Fix base PC value for PC
3463 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3465 * interp.c (simJALDELAYSLOT): Define.
3466 (JALDELAYSLOT): Define.
3467 (INDELAYSLOT, INJALDELAYSLOT): Define.
3468 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3470 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3472 * interp.c (sim_open): add flush_cache as a PMON routine
3473 (sim_monitor): handle flush_cache by ignoring it
3475 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3477 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3479 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3480 (BigEndianMem): Rename to ByteSwapMem and change sense.
3481 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3482 BigEndianMem references to !ByteSwapMem.
3483 (set_endianness): New function, with prototype.
3484 (sim_open): Call set_endianness.
3485 (sim_info): Use simBE instead of BigEndianMem.
3486 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3487 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3488 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3489 ifdefs, keeping the prototype declaration.
3490 (swap_word): Rewrite correctly.
3491 (ColdReset): Delete references to CONFIG. Delete endianness related
3492 code; moved to set_endianness.
3494 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3496 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3497 * interp.c (CHECKHILO): Define away.
3498 (simSIGINT): New macro.
3499 (membank_size): Increase from 1MB to 2MB.
3500 (control_c): New function.
3501 (sim_resume): Rename parameter signal to signal_number. Add local
3502 variable prev. Call signal before and after simulate.
3503 (sim_stop_reason): Add simSIGINT support.
3504 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3506 (sim_warning): Delete call to SignalException. Do call printf_filtered
3508 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3509 a call to sim_warning.
3511 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3513 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3514 16 bit instructions.
3516 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3518 Add support for mips16 (16 bit MIPS implementation):
3519 * gencode.c (inst_type): Add mips16 instruction encoding types.
3520 (GETDATASIZEINSN): Define.
3521 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3522 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3524 (MIPS16_DECODE): New table, for mips16 instructions.
3525 (bitmap_val): New static function.
3526 (struct mips16_op): Define.
3527 (mips16_op_table): New table, for mips16 operands.
3528 (build_mips16_operands): New static function.
3529 (process_instructions): If PC is odd, decode a mips16
3530 instruction. Break out instruction handling into new
3531 build_instruction function.
3532 (build_instruction): New static function, broken out of
3533 process_instructions. Check modifiers rather than flags for SHIFT
3534 bit count and m[ft]{hi,lo} direction.
3535 (usage): Pass program name to fprintf.
3536 (main): Remove unused variable this_option_optind. Change
3537 ``*loptarg++'' to ``loptarg++''.
3538 (my_strtoul): Parenthesize && within ||.
3539 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3540 (simulate): If PC is odd, fetch a 16 bit instruction, and
3541 increment PC by 2 rather than 4.
3542 * configure.in: Add case for mips16*-*-*.
3543 * configure: Rebuild.
3545 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3547 * interp.c: Allow -t to enable tracing in standalone simulator.
3548 Fix garbage output in trace file and error messages.
3550 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3552 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3553 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3554 * configure.in: Simplify using macros in ../common/aclocal.m4.
3555 * configure: Regenerated.
3556 * tconfig.in: New file.
3558 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3560 * interp.c: Fix bugs in 64-bit port.
3561 Use ansi function declarations for msvc compiler.
3562 Initialize and test file pointer in trace code.
3563 Prevent duplicate definition of LAST_EMED_REGNUM.
3565 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3567 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3569 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3571 * interp.c (SignalException): Check for explicit terminating
3573 * gencode.c: Pass instruction value through SignalException()
3574 calls for Trap, Breakpoint and Syscall.
3576 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3578 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3579 only used on those hosts that provide it.
3580 * configure.in: Add sqrt() to list of functions to be checked for.
3581 * config.in: Re-generated.
3582 * configure: Re-generated.
3584 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3586 * gencode.c (process_instructions): Call build_endian_shift when
3587 expanding STORE RIGHT, to fix swr.
3588 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3589 clear the high bits.
3590 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3591 Fix float to int conversions to produce signed values.
3593 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3595 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3596 (process_instructions): Correct handling of nor instruction.
3597 Correct shift count for 32 bit shift instructions. Correct sign
3598 extension for arithmetic shifts to not shift the number of bits in
3599 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3600 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3602 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3603 It's OK to have a mult follow a mult. What's not OK is to have a
3604 mult follow an mfhi.
3605 (Convert): Comment out incorrect rounding code.
3607 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3609 * interp.c (sim_monitor): Improved monitor printf
3610 simulation. Tidied up simulator warnings, and added "--log" option
3611 for directing warning message output.
3612 * gencode.c: Use sim_warning() rather than WARNING macro.
3614 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3616 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3617 getopt1.o, rather than on gencode.c. Link objects together.
3618 Don't link against -liberty.
3619 (gencode.o, getopt.o, getopt1.o): New targets.
3620 * gencode.c: Include <ctype.h> and "ansidecl.h".
3621 (AND): Undefine after including "ansidecl.h".
3622 (ULONG_MAX): Define if not defined.
3623 (OP_*): Don't define macros; now defined in opcode/mips.h.
3624 (main): Call my_strtoul rather than strtoul.
3625 (my_strtoul): New static function.
3627 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3629 * gencode.c (process_instructions): Generate word64 and uword64
3630 instead of `long long' and `unsigned long long' data types.
3631 * interp.c: #include sysdep.h to get signals, and define default
3633 * (Convert): Work around for Visual-C++ compiler bug with type
3635 * support.h: Make things compile under Visual-C++ by using
3636 __int64 instead of `long long'. Change many refs to long long
3637 into word64/uword64 typedefs.
3639 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3641 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3642 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3644 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3645 (AC_PROG_INSTALL): Added.
3646 (AC_PROG_CC): Moved to before configure.host call.
3647 * configure: Rebuilt.
3649 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3651 * configure.in: Define @SIMCONF@ depending on mips target.
3652 * configure: Rebuild.
3653 * Makefile.in (run): Add @SIMCONF@ to control simulator
3655 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3656 * interp.c: Remove some debugging, provide more detailed error
3657 messages, update memory accesses to use LOADDRMASK.
3659 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3661 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3662 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3664 * configure: Rebuild.
3665 * config.in: New file, generated by autoheader.
3666 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3667 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3668 HAVE_ANINT and HAVE_AINT, as appropriate.
3669 * Makefile.in (run): Use @LIBS@ rather than -lm.
3670 (interp.o): Depend upon config.h.
3671 (Makefile): Just rebuild Makefile.
3672 (clean): Remove stamp-h.
3673 (mostlyclean): Make the same as clean, not as distclean.
3674 (config.h, stamp-h): New targets.
3676 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3678 * interp.c (ColdReset): Fix boolean test. Make all simulator
3681 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3683 * interp.c (xfer_direct_word, xfer_direct_long,
3684 swap_direct_word, swap_direct_long, xfer_big_word,
3685 xfer_big_long, xfer_little_word, xfer_little_long,
3686 swap_word,swap_long): Added.
3687 * interp.c (ColdReset): Provide function indirection to
3688 host<->simulated_target transfer routines.
3689 * interp.c (sim_store_register, sim_fetch_register): Updated to
3690 make use of indirected transfer routines.
3692 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3694 * gencode.c (process_instructions): Ensure FP ABS instruction
3696 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3697 system call support.
3699 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3701 * interp.c (sim_do_command): Complain if callback structure not
3704 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3706 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3707 support for Sun hosts.
3708 * Makefile.in (gencode): Ensure the host compiler and libraries
3709 used for cross-hosted build.
3711 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3713 * interp.c, gencode.c: Some more (TODO) tidying.
3715 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3717 * gencode.c, interp.c: Replaced explicit long long references with
3718 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3719 * support.h (SET64LO, SET64HI): Macros added.
3721 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3723 * configure: Regenerate with autoconf 2.7.
3725 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3727 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3728 * support.h: Remove superfluous "1" from #if.
3729 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3731 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3733 * interp.c (StoreFPR): Control UndefinedResult() call on
3734 WARN_RESULT manifest.
3736 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3738 * gencode.c: Tidied instruction decoding, and added FP instruction
3741 * interp.c: Added dineroIII, and BSD profiling support. Also
3742 run-time FP handling.
3744 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3746 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3747 gencode.c, interp.c, support.h: created.