1 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
3 * interp.c (sim_store_register): Handle case where client - GDB -
4 specifies that a 4 byte register is 8 bytes in size.
5 (sim_fetch_register): Ditto.
7 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
9 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
10 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
11 (idt_monitor_base): Base address for IDT monitor traps.
12 (pmon_monitor_base): Ditto for PMON.
13 (lsipmon_monitor_base): Ditto for LSI PMON.
14 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
15 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
16 (sim_firmware_command): New function.
17 (mips_option_handler): Call it for OPTION_FIRMWARE.
18 (sim_open): Allocate memory for idt_monitor region. If "--board"
19 option was given, add no monitor by default. Add BREAK hooks only if
20 monitors are also there.
22 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
24 * interp.c (sim_monitor): Flush output before reading input.
26 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
28 * tconfig.in (SIM_HANDLES_LMA): Always define.
30 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
32 From Mark Salter <msalter@cygnus.com>:
33 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
34 (sim_open): Add setup for BSP board.
36 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
38 * mips.igen (MULT, MULTU): Add syntax for two operand version.
39 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
40 them as unimplemented.
42 1999-05-08 Felix Lee <flee@cygnus.com>
44 * configure: Regenerated to track ../common/aclocal.m4 changes.
46 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
48 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
50 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
52 * configure.in: Any mips64vr5*-*-* target should have
54 (default_endian): Any mips64vr*el-*-* target should default to
56 * configure: Re-generate.
58 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
60 * mips.igen (ldl): Extend from _16_, not 32.
62 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
64 * interp.c (sim_store_register): Force registers written to by GDB
65 into an un-interpreted state.
67 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
69 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
70 CPU, start periodic background I/O polls.
71 (tx3904sio_poll): New function: periodic I/O poller.
73 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
75 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
77 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
79 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
82 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
84 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
85 (load_word): Call SIM_CORE_SIGNAL hook on error.
86 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
87 starting. For exception dispatching, pass PC instead of NULL_CIA.
88 (decode_coproc): Use COP0_BADVADDR to store faulting address.
89 * sim-main.h (COP0_BADVADDR): Define.
90 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
91 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
92 (_sim_cpu): Add exc_* fields to store register value snapshots.
93 * mips.igen (*): Replace memory-related SignalException* calls
94 with references to SIM_CORE_SIGNAL hook.
96 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
98 * sim-main.c (*): Minor warning cleanups.
100 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
102 * m16.igen (DADDIU5): Correct type-o.
104 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
106 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
109 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
111 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
113 (interp.o): Add dependency on itable.h
114 (oengine.c, gencode): Delete remaining references.
115 (BUILT_SRC_FROM_GEN): Clean up.
117 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
120 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
121 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
123 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
124 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
125 Drop the "64" qualifier to get the HACK generator working.
126 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
127 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
128 qualifier to get the hack generator working.
129 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
131 (DSLLV): Use do_dsllv.
134 (DSRLV): Use do_dsrlv.
135 (BC1): Move *vr4100 to get the HACK generator working.
136 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
137 get the HACK generator working.
138 (MACC) Rename to get the HACK generator working.
139 (DMACC,MACCS,DMACCS): Add the 64.
141 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
143 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
144 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
146 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
148 * mips/interp.c (DEBUG): Cleanups.
150 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
152 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
153 (tx3904sio_tickle): fflush after a stdout character output.
155 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
157 * interp.c (sim_close): Uninstall modules.
159 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
161 * sim-main.h, interp.c (sim_monitor): Change to global
164 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
166 * configure.in (vr4100): Only include vr4100 instructions in
168 * configure: Re-generate.
169 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
171 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
173 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
174 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
177 * configure.in (sim_default_gen, sim_use_gen): Replace with
179 (--enable-sim-igen): Delete config option. Always using IGEN.
180 * configure: Re-generate.
182 * Makefile.in (gencode): Kill, kill, kill.
185 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
187 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
188 bit mips16 igen simulator.
189 * configure: Re-generate.
191 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
192 as part of vr4100 ISA.
193 * vr.igen: Mark all instructions as 64 bit only.
195 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
197 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
200 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
202 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
203 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
204 * configure: Re-generate.
206 * m16.igen (BREAK): Define breakpoint instruction.
207 (JALX32): Mark instruction as mips16 and not r3900.
208 * mips.igen (C.cond.fmt): Fix typo in instruction format.
210 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
212 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
214 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
215 insn as a debug breakpoint.
217 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
219 (PENDING_SCHED): Clean up trace statement.
220 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
221 (PENDING_FILL): Delay write by only one cycle.
222 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
224 * sim-main.c (pending_tick): Clean up trace statements. Add trace
226 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
228 (pending_tick): Move incrementing of index to FOR statement.
229 (pending_tick): Only update PENDING_OUT after a write has occured.
231 * configure.in: Add explicit mips-lsi-* target. Use gencode to
233 * configure: Re-generate.
235 * interp.c (sim_engine_run OLD): Delete explicit call to
236 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
238 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
240 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
241 interrupt level number to match changed SignalExceptionInterrupt
244 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
246 * interp.c: #include "itable.h" if WITH_IGEN.
247 (get_insn_name): New function.
248 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
249 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
251 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
253 * configure: Rebuilt to inhale new common/aclocal.m4.
255 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
257 * dv-tx3904sio.c: Include sim-assert.h.
259 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
261 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
262 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
263 Reorganize target-specific sim-hardware checks.
264 * configure: rebuilt.
265 * interp.c (sim_open): For tx39 target boards, set
266 OPERATING_ENVIRONMENT, add tx3904sio devices.
267 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
268 ROM executables. Install dv-sockser into sim-modules list.
270 * dv-tx3904irc.c: Compiler warning clean-up.
271 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
272 frequent hw-trace messages.
274 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
276 * vr.igen (MulAcc): Identify as a vr4100 specific function.
278 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
280 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
283 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
284 * mips.igen: Define vr4100 model. Include vr.igen.
285 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
287 * mips.igen (check_mf_hilo): Correct check.
289 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
291 * sim-main.h (interrupt_event): Add prototype.
293 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
294 register_ptr, register_value.
295 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
297 * sim-main.h (tracefh): Make extern.
299 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
301 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
302 Reduce unnecessarily high timer event frequency.
303 * dv-tx3904cpu.c: Ditto for interrupt event.
305 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
307 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
309 (interrupt_event): Made non-static.
311 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
312 interchange of configuration values for external vs. internal
315 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
317 * mips.igen (BREAK): Moved code to here for
318 simulator-reserved break instructions.
319 * gencode.c (build_instruction): Ditto.
320 * interp.c (signal_exception): Code moved from here. Non-
321 reserved instructions now use exception vector, rather
323 * sim-main.h: Moved magic constants to here.
325 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
327 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
328 register upon non-zero interrupt event level, clear upon zero
330 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
331 by passing zero event value.
332 (*_io_{read,write}_buffer): Endianness fixes.
333 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
334 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
336 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
337 serial I/O and timer module at base address 0xFFFF0000.
339 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
341 * mips.igen (SWC1) : Correct the handling of ReverseEndian
344 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
346 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
350 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
352 * dv-tx3904tmr.c: New file - implements tx3904 timer.
353 * dv-tx3904{irc,cpu}.c: Mild reformatting.
354 * configure.in: Include tx3904tmr in hw_device list.
355 * configure: Rebuilt.
356 * interp.c (sim_open): Instantiate three timer instances.
357 Fix address typo of tx3904irc instance.
359 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
361 * interp.c (signal_exception): SystemCall exception now uses
362 the exception vector.
364 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
366 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
369 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
371 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
373 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
375 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
377 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
378 sim-main.h. Declare a struct hw_descriptor instead of struct
379 hw_device_descriptor.
381 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
383 * mips.igen (do_store_left, do_load_left): Compute nr of left and
384 right bits and then re-align left hand bytes to correct byte
385 lanes. Fix incorrect computation in do_store_left when loading
386 bytes from second word.
388 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
390 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
391 * interp.c (sim_open): Only create a device tree when HW is
394 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
395 * interp.c (signal_exception): Ditto.
397 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
399 * gencode.c: Mark BEGEZALL as LIKELY.
401 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
403 * sim-main.h (ALU32_END): Sign extend 32 bit results.
404 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
406 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
408 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
409 modules. Recognize TX39 target with "mips*tx39" pattern.
410 * configure: Rebuilt.
411 * sim-main.h (*): Added many macros defining bits in
412 TX39 control registers.
413 (SignalInterrupt): Send actual PC instead of NULL.
414 (SignalNMIReset): New exception type.
415 * interp.c (board): New variable for future use to identify
416 a particular board being simulated.
417 (mips_option_handler,mips_options): Added "--board" option.
418 (interrupt_event): Send actual PC.
419 (sim_open): Make memory layout conditional on board setting.
420 (signal_exception): Initial implementation of hardware interrupt
421 handling. Accept another break instruction variant for simulator
423 (decode_coproc): Implement RFE instruction for TX39.
424 (mips.igen): Decode RFE instruction as such.
425 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
426 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
427 bbegin to implement memory map.
428 * dv-tx3904cpu.c: New file.
429 * dv-tx3904irc.c: New file.
431 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
433 * mips.igen (check_mt_hilo): Create a separate r3900 version.
435 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
437 * tx.igen (madd,maddu): Replace calls to check_op_hilo
438 with calls to check_div_hilo.
440 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
442 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
443 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
444 Add special r3900 version of do_mult_hilo.
445 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
446 with calls to check_mult_hilo.
447 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
448 with calls to check_div_hilo.
450 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
452 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
453 Document a replacement.
455 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
457 * interp.c (sim_monitor): Make mon_printf work.
459 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
461 * sim-main.h (INSN_NAME): New arg `cpu'.
463 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
465 * configure: Regenerated to track ../common/aclocal.m4 changes.
467 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
469 * configure: Regenerated to track ../common/aclocal.m4 changes.
472 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
474 * acconfig.h: New file.
475 * configure.in: Reverted change of Apr 24; use sinclude again.
477 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
479 * configure: Regenerated to track ../common/aclocal.m4 changes.
482 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
484 * configure.in: Don't call sinclude.
486 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
488 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
490 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
492 * mips.igen (ERET): Implement.
494 * interp.c (decode_coproc): Return sign-extended EPC.
496 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
498 * interp.c (signal_exception): Do not ignore Trap.
499 (signal_exception): On TRAP, restart at exception address.
500 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
501 (signal_exception): Update.
502 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
503 so that TRAP instructions are caught.
505 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
507 * sim-main.h (struct hilo_access, struct hilo_history): Define,
508 contains HI/LO access history.
509 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
510 (HIACCESS, LOACCESS): Delete, replace with
511 (HIHISTORY, LOHISTORY): New macros.
512 (CHECKHILO): Delete all, moved to mips.igen
514 * gencode.c (build_instruction): Do not generate checks for
515 correct HI/LO register usage.
517 * interp.c (old_engine_run): Delete checks for correct HI/LO
520 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
521 check_mf_cycles): New functions.
522 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
523 do_divu, domultx, do_mult, do_multu): Use.
525 * tx.igen ("madd", "maddu"): Use.
527 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
529 * mips.igen (DSRAV): Use function do_dsrav.
530 (SRAV): Use new function do_srav.
532 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
533 (B): Sign extend 11 bit immediate.
534 (EXT-B*): Shift 16 bit immediate left by 1.
535 (ADDIU*): Don't sign extend immediate value.
537 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
539 * m16run.c (sim_engine_run): Restore CIA after handling an event.
541 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
544 * mips.igen (delayslot32, nullify_next_insn): New functions.
545 (m16.igen): Always include.
546 (do_*): Add more tracing.
548 * m16.igen (delayslot16): Add NIA argument, could be called by a
549 32 bit MIPS16 instruction.
551 * interp.c (ifetch16): Move function from here.
552 * sim-main.c (ifetch16): To here.
554 * sim-main.c (ifetch16, ifetch32): Update to match current
555 implementations of LH, LW.
556 (signal_exception): Don't print out incorrect hex value of illegal
559 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
561 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
564 * m16.igen: Implement MIPS16 instructions.
566 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
567 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
568 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
569 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
570 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
571 bodies of corresponding code from 32 bit insn to these. Also used
572 by MIPS16 versions of functions.
574 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
575 (IMEM16): Drop NR argument from macro.
577 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
579 * Makefile.in (SIM_OBJS): Add sim-main.o.
581 * sim-main.h (address_translation, load_memory, store_memory,
582 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
584 (pr_addr, pr_uword64): Declare.
585 (sim-main.c): Include when H_REVEALS_MODULE_P.
587 * interp.c (address_translation, load_memory, store_memory,
588 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
590 * sim-main.c: To here. Fix compilation problems.
592 * configure.in: Enable inlining.
593 * configure: Re-config.
595 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
597 * configure: Regenerated to track ../common/aclocal.m4 changes.
599 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
601 * mips.igen: Include tx.igen.
602 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
603 * tx.igen: New file, contains MADD and MADDU.
605 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
606 the hardwired constant `7'.
607 (store_memory): Ditto.
608 (LOADDRMASK): Move definition to sim-main.h.
610 mips.igen (MTC0): Enable for r3900.
613 mips.igen (do_load_byte): Delete.
614 (do_load, do_store, do_load_left, do_load_write, do_store_left,
615 do_store_right): New functions.
616 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
618 configure.in: Let the tx39 use igen again.
621 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
623 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
624 not an address sized quantity. Return zero for cache sizes.
626 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
628 * mips.igen (r3900): r3900 does not support 64 bit integer
631 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
633 * configure.in (mipstx39*-*-*): Use gencode simulator rather
635 * configure : Rebuild.
637 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
639 * configure: Regenerated to track ../common/aclocal.m4 changes.
641 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
643 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
645 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
647 * configure: Regenerated to track ../common/aclocal.m4 changes.
648 * config.in: Regenerated to track ../common/aclocal.m4 changes.
650 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
652 * configure: Regenerated to track ../common/aclocal.m4 changes.
654 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
656 * interp.c (Max, Min): Comment out functions. Not yet used.
658 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
660 * configure: Regenerated to track ../common/aclocal.m4 changes.
662 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
664 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
665 configurable settings for stand-alone simulator.
667 * configure.in: Added X11 search, just in case.
669 * configure: Regenerated.
671 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
673 * interp.c (sim_write, sim_read, load_memory, store_memory):
674 Replace sim_core_*_map with read_map, write_map, exec_map resp.
676 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
678 * sim-main.h (GETFCC): Return an unsigned value.
680 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
682 * mips.igen (DIV): Fix check for -1 / MIN_INT.
683 (DADD): Result destination is RD not RT.
685 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
687 * sim-main.h (HIACCESS, LOACCESS): Always define.
689 * mdmx.igen (Maxi, Mini): Rename Max, Min.
691 * interp.c (sim_info): Delete.
693 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
695 * interp.c (DECLARE_OPTION_HANDLER): Use it.
696 (mips_option_handler): New argument `cpu'.
697 (sim_open): Update call to sim_add_option_table.
699 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
701 * mips.igen (CxC1): Add tracing.
703 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
705 * sim-main.h (Max, Min): Declare.
707 * interp.c (Max, Min): New functions.
709 * mips.igen (BC1): Add tracing.
711 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
713 * interp.c Added memory map for stack in vr4100
715 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
717 * interp.c (load_memory): Add missing "break"'s.
719 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
721 * interp.c (sim_store_register, sim_fetch_register): Pass in
722 length parameter. Return -1.
724 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
726 * interp.c: Added hardware init hook, fixed warnings.
728 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
730 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
732 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
734 * interp.c (ifetch16): New function.
736 * sim-main.h (IMEM32): Rename IMEM.
737 (IMEM16_IMMED): Define.
739 (DELAY_SLOT): Update.
741 * m16run.c (sim_engine_run): New file.
743 * m16.igen: All instructions except LB.
744 (LB): Call do_load_byte.
745 * mips.igen (do_load_byte): New function.
746 (LB): Call do_load_byte.
748 * mips.igen: Move spec for insn bit size and high bit from here.
749 * Makefile.in (tmp-igen, tmp-m16): To here.
751 * m16.dc: New file, decode mips16 instructions.
753 * Makefile.in (SIM_NO_ALL): Define.
754 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
756 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
758 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
759 point unit to 32 bit registers.
760 * configure: Re-generate.
762 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
764 * configure.in (sim_use_gen): Make IGEN the default simulator
765 generator for generic 32 and 64 bit mips targets.
766 * configure: Re-generate.
768 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
770 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
773 * interp.c (sim_fetch_register, sim_store_register): Read/write
774 FGR from correct location.
775 (sim_open): Set size of FGR's according to
776 WITH_TARGET_FLOATING_POINT_BITSIZE.
778 * sim-main.h (FGR): Store floating point registers in a separate
781 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
783 * configure: Regenerated to track ../common/aclocal.m4 changes.
785 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
787 * interp.c (ColdReset): Call PENDING_INVALIDATE.
789 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
791 * interp.c (pending_tick): New function. Deliver pending writes.
793 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
794 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
795 it can handle mixed sized quantites and single bits.
797 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
799 * interp.c (oengine.h): Do not include when building with IGEN.
800 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
801 (sim_info): Ditto for PROCESSOR_64BIT.
802 (sim_monitor): Replace ut_reg with unsigned_word.
803 (*): Ditto for t_reg.
804 (LOADDRMASK): Define.
805 (sim_open): Remove defunct check that host FP is IEEE compliant,
806 using software to emulate floating point.
807 (value_fpr, ...): Always compile, was conditional on HASFPU.
809 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
811 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
814 * interp.c (SD, CPU): Define.
815 (mips_option_handler): Set flags in each CPU.
816 (interrupt_event): Assume CPU 0 is the one being iterrupted.
817 (sim_close): Do not clear STATE, deleted anyway.
818 (sim_write, sim_read): Assume CPU zero's vm should be used for
820 (sim_create_inferior): Set the PC for all processors.
821 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
823 (mips16_entry): Pass correct nr of args to store_word, load_word.
824 (ColdReset): Cold reset all cpu's.
825 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
826 (sim_monitor, load_memory, store_memory, signal_exception): Use
827 `CPU' instead of STATE_CPU.
830 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
833 * sim-main.h (signal_exception): Add sim_cpu arg.
834 (SignalException*): Pass both SD and CPU to signal_exception.
835 * interp.c (signal_exception): Update.
837 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
839 (sync_operation, prefetch, cache_op, store_memory, load_memory,
840 address_translation): Ditto
841 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
843 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
845 * configure: Regenerated to track ../common/aclocal.m4 changes.
847 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
849 * interp.c (sim_engine_run): Add `nr_cpus' argument.
851 * mips.igen (model): Map processor names onto BFD name.
853 * sim-main.h (CPU_CIA): Delete.
854 (SET_CIA, GET_CIA): Define
856 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
858 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
861 * configure.in (default_endian): Configure a big-endian simulator
863 * configure: Re-generate.
865 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
867 * configure: Regenerated to track ../common/aclocal.m4 changes.
869 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
871 * interp.c (sim_monitor): Handle Densan monitor outbyte
872 and inbyte functions.
874 1997-12-29 Felix Lee <flee@cygnus.com>
876 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
878 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
880 * Makefile.in (tmp-igen): Arrange for $zero to always be
881 reset to zero after every instruction.
883 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
885 * configure: Regenerated to track ../common/aclocal.m4 changes.
888 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
890 * mips.igen (MSUB): Fix to work like MADD.
891 * gencode.c (MSUB): Similarly.
893 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
895 * configure: Regenerated to track ../common/aclocal.m4 changes.
897 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
899 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
901 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
903 * sim-main.h (sim-fpu.h): Include.
905 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
906 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
907 using host independant sim_fpu module.
909 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
911 * interp.c (signal_exception): Report internal errors with SIGABRT
914 * sim-main.h (C0_CONFIG): New register.
915 (signal.h): No longer include.
917 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
919 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
921 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
923 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
925 * mips.igen: Tag vr5000 instructions.
926 (ANDI): Was missing mipsIV model, fix assembler syntax.
927 (do_c_cond_fmt): New function.
928 (C.cond.fmt): Handle mips I-III which do not support CC field
930 (bc1): Handle mips IV which do not have a delaed FCC separatly.
931 (SDR): Mask paddr when BigEndianMem, not the converse as specified
933 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
934 vr5000 which saves LO in a GPR separatly.
936 * configure.in (enable-sim-igen): For vr5000, select vr5000
937 specific instructions.
938 * configure: Re-generate.
940 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
942 * Makefile.in (SIM_OBJS): Add sim-fpu module.
944 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
945 fmt_uninterpreted_64 bit cases to switch. Convert to
948 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
950 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
951 as specified in IV3.2 spec.
952 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
954 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
956 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
957 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
958 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
959 PENDING_FILL versions of instructions. Simplify.
961 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
963 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
965 (MTHI, MFHI): Disable code checking HI-LO.
967 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
969 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
971 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
973 * gencode.c (build_mips16_operands): Replace IPC with cia.
975 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
976 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
978 (UndefinedResult): Replace function with macro/function
980 (sim_engine_run): Don't save PC in IPC.
982 * sim-main.h (IPC): Delete.
985 * interp.c (signal_exception, store_word, load_word,
986 address_translation, load_memory, store_memory, cache_op,
987 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
988 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
989 current instruction address - cia - argument.
990 (sim_read, sim_write): Call address_translation directly.
991 (sim_engine_run): Rename variable vaddr to cia.
992 (signal_exception): Pass cia to sim_monitor
994 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
995 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
996 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
998 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
999 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1002 * interp.c (signal_exception): Pass restart address to
1005 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1006 idecode.o): Add dependency.
1008 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1010 (DELAY_SLOT): Update NIA not PC with branch address.
1011 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1013 * mips.igen: Use CIA not PC in branch calculations.
1014 (illegal): Call SignalException.
1015 (BEQ, ADDIU): Fix assembler.
1017 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1019 * m16.igen (JALX): Was missing.
1021 * configure.in (enable-sim-igen): New configuration option.
1022 * configure: Re-generate.
1024 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1026 * interp.c (load_memory, store_memory): Delete parameter RAW.
1027 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1028 bypassing {load,store}_memory.
1030 * sim-main.h (ByteSwapMem): Delete definition.
1032 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1034 * interp.c (sim_do_command, sim_commands): Delete mips specific
1035 commands. Handled by module sim-options.
1037 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1038 (WITH_MODULO_MEMORY): Define.
1040 * interp.c (sim_info): Delete code printing memory size.
1042 * interp.c (mips_size): Nee sim_size, delete function.
1044 (monitor, monitor_base, monitor_size): Delete global variables.
1045 (sim_open, sim_close): Delete code creating monitor and other
1046 memory regions. Use sim-memopts module, via sim_do_commandf, to
1047 manage memory regions.
1048 (load_memory, store_memory): Use sim-core for memory model.
1050 * interp.c (address_translation): Delete all memory map code
1051 except line forcing 32 bit addresses.
1053 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1055 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1058 * interp.c (logfh, logfile): Delete globals.
1059 (sim_open, sim_close): Delete code opening & closing log file.
1060 (mips_option_handler): Delete -l and -n options.
1061 (OPTION mips_options): Ditto.
1063 * interp.c (OPTION mips_options): Rename option trace to dinero.
1064 (mips_option_handler): Update.
1066 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1068 * interp.c (fetch_str): New function.
1069 (sim_monitor): Rewrite using sim_read & sim_write.
1070 (sim_open): Check magic number.
1071 (sim_open): Write monitor vectors into memory using sim_write.
1072 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1073 (sim_read, sim_write): Simplify - transfer data one byte at a
1075 (load_memory, store_memory): Clarify meaning of parameter RAW.
1077 * sim-main.h (isHOST): Defete definition.
1078 (isTARGET): Mark as depreciated.
1079 (address_translation): Delete parameter HOST.
1081 * interp.c (address_translation): Delete parameter HOST.
1083 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1087 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1088 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1090 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1092 * mips.igen: Add model filter field to records.
1094 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1096 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1098 interp.c (sim_engine_run): Do not compile function sim_engine_run
1099 when WITH_IGEN == 1.
1101 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1102 target architecture.
1104 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1105 igen. Replace with configuration variables sim_igen_flags /
1108 * m16.igen: New file. Copy mips16 insns here.
1109 * mips.igen: From here.
1111 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1113 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1115 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1117 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1119 * gencode.c (build_instruction): Follow sim_write's lead in using
1120 BigEndianMem instead of !ByteSwapMem.
1122 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1124 * configure.in (sim_gen): Dependent on target, select type of
1125 generator. Always select old style generator.
1127 configure: Re-generate.
1129 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1131 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1132 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1133 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1134 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1135 SIM_@sim_gen@_*, set by autoconf.
1137 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1139 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1141 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1142 CURRENT_FLOATING_POINT instead.
1144 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1145 (address_translation): Raise exception InstructionFetch when
1146 translation fails and isINSTRUCTION.
1148 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1149 sim_engine_run): Change type of of vaddr and paddr to
1151 (address_translation, prefetch, load_memory, store_memory,
1152 cache_op): Change type of vAddr and pAddr to address_word.
1154 * gencode.c (build_instruction): Change type of vaddr and paddr to
1157 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1159 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1160 macro to obtain result of ALU op.
1162 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1164 * interp.c (sim_info): Call profile_print.
1166 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1168 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1170 * sim-main.h (WITH_PROFILE): Do not define, defined in
1171 common/sim-config.h. Use sim-profile module.
1172 (simPROFILE): Delete defintion.
1174 * interp.c (PROFILE): Delete definition.
1175 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1176 (sim_close): Delete code writing profile histogram.
1177 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1179 (sim_engine_run): Delete code profiling the PC.
1181 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1183 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1185 * interp.c (sim_monitor): Make register pointers of type
1188 * sim-main.h: Make registers of type unsigned_word not
1191 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1193 * interp.c (sync_operation): Rename from SyncOperation, make
1194 global, add SD argument.
1195 (prefetch): Rename from Prefetch, make global, add SD argument.
1196 (decode_coproc): Make global.
1198 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1200 * gencode.c (build_instruction): Generate DecodeCoproc not
1201 decode_coproc calls.
1203 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1204 (SizeFGR): Move to sim-main.h
1205 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1206 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1207 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1209 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1210 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1211 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1212 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1213 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1214 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1216 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1218 (sim-alu.h): Include.
1219 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1220 (sim_cia): Typedef to instruction_address.
1222 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1224 * Makefile.in (interp.o): Rename generated file engine.c to
1229 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1231 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1233 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1235 * gencode.c (build_instruction): For "FPSQRT", output correct
1236 number of arguments to Recip.
1238 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1240 * Makefile.in (interp.o): Depends on sim-main.h
1242 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1244 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1245 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1246 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1247 STATE, DSSTATE): Define
1248 (GPR, FGRIDX, ..): Define.
1250 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1251 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1252 (GPR, FGRIDX, ...): Delete macros.
1254 * interp.c: Update names to match defines from sim-main.h
1256 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1258 * interp.c (sim_monitor): Add SD argument.
1259 (sim_warning): Delete. Replace calls with calls to
1261 (sim_error): Delete. Replace calls with sim_io_error.
1262 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1263 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1264 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1266 (mips_size): Rename from sim_size. Add SD argument.
1268 * interp.c (simulator): Delete global variable.
1269 (callback): Delete global variable.
1270 (mips_option_handler, sim_open, sim_write, sim_read,
1271 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1272 sim_size,sim_monitor): Use sim_io_* not callback->*.
1273 (sim_open): ZALLOC simulator struct.
1274 (PROFILE): Do not define.
1276 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1278 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1279 support.h with corresponding code.
1281 * sim-main.h (word64, uword64), support.h: Move definition to
1283 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1286 * Makefile.in: Update dependencies
1287 * interp.c: Do not include.
1289 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1291 * interp.c (address_translation, load_memory, store_memory,
1292 cache_op): Rename to from AddressTranslation et.al., make global,
1295 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1298 * interp.c (SignalException): Rename to signal_exception, make
1301 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1303 * sim-main.h (SignalException, SignalExceptionInterrupt,
1304 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1305 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1306 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1309 * interp.c, support.h: Use.
1311 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1313 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1314 to value_fpr / store_fpr. Add SD argument.
1315 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1316 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1318 * sim-main.h (ValueFPR, StoreFPR): Define.
1320 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1322 * interp.c (sim_engine_run): Check consistency between configure
1323 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1326 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1327 (mips_fpu): Configure WITH_FLOATING_POINT.
1328 (mips_endian): Configure WITH_TARGET_ENDIAN.
1329 * configure: Update.
1331 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1333 * configure: Regenerated to track ../common/aclocal.m4 changes.
1335 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1337 * configure: Regenerated.
1339 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1341 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1343 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1345 * gencode.c (print_igen_insn_models): Assume certain architectures
1346 include all mips* instructions.
1347 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1350 * Makefile.in (tmp.igen): Add target. Generate igen input from
1353 * gencode.c (FEATURE_IGEN): Define.
1354 (main): Add --igen option. Generate output in igen format.
1355 (process_instructions): Format output according to igen option.
1356 (print_igen_insn_format): New function.
1357 (print_igen_insn_models): New function.
1358 (process_instructions): Only issue warnings and ignore
1359 instructions when no FEATURE_IGEN.
1361 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1363 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1366 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1368 * configure: Regenerated to track ../common/aclocal.m4 changes.
1370 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1372 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1373 SIM_RESERVED_BITS): Delete, moved to common.
1374 (SIM_EXTRA_CFLAGS): Update.
1376 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1378 * configure.in: Configure non-strict memory alignment.
1379 * configure: Regenerated to track ../common/aclocal.m4 changes.
1381 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1383 * configure: Regenerated to track ../common/aclocal.m4 changes.
1385 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1387 * gencode.c (SDBBP,DERET): Added (3900) insns.
1388 (RFE): Turn on for 3900.
1389 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1390 (dsstate): Made global.
1391 (SUBTARGET_R3900): Added.
1392 (CANCELDELAYSLOT): New.
1393 (SignalException): Ignore SystemCall rather than ignore and
1394 terminate. Add DebugBreakPoint handling.
1395 (decode_coproc): New insns RFE, DERET; and new registers Debug
1396 and DEPC protected by SUBTARGET_R3900.
1397 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1399 * Makefile.in,configure.in: Add mips subtarget option.
1400 * configure: Update.
1402 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1404 * gencode.c: Add r3900 (tx39).
1407 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1409 * gencode.c (build_instruction): Don't need to subtract 4 for
1412 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1414 * interp.c: Correct some HASFPU problems.
1416 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1418 * configure: Regenerated to track ../common/aclocal.m4 changes.
1420 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1422 * interp.c (mips_options): Fix samples option short form, should
1425 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1427 * interp.c (sim_info): Enable info code. Was just returning.
1429 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1431 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1434 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1436 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1438 (build_instruction): Ditto for LL.
1440 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1442 * configure: Regenerated to track ../common/aclocal.m4 changes.
1444 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1446 * configure: Regenerated to track ../common/aclocal.m4 changes.
1449 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1451 * interp.c (sim_open): Add call to sim_analyze_program, update
1454 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1456 * interp.c (sim_kill): Delete.
1457 (sim_create_inferior): Add ABFD argument. Set PC from same.
1458 (sim_load): Move code initializing trap handlers from here.
1459 (sim_open): To here.
1460 (sim_load): Delete, use sim-hload.c.
1462 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1464 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1466 * configure: Regenerated to track ../common/aclocal.m4 changes.
1469 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1471 * interp.c (sim_open): Add ABFD argument.
1472 (sim_load): Move call to sim_config from here.
1473 (sim_open): To here. Check return status.
1475 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1477 * gencode.c (build_instruction): Two arg MADD should
1478 not assign result to $0.
1480 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1482 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1483 * sim/mips/configure.in: Regenerate.
1485 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1487 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1488 signed8, unsigned8 et.al. types.
1490 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1491 hosts when selecting subreg.
1493 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1495 * interp.c (sim_engine_run): Reset the ZERO register to zero
1496 regardless of FEATURE_WARN_ZERO.
1497 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1499 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1501 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1502 (SignalException): For BreakPoints ignore any mode bits and just
1504 (SignalException): Always set the CAUSE register.
1506 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1508 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1509 exception has been taken.
1511 * interp.c: Implement the ERET and mt/f sr instructions.
1513 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1515 * interp.c (SignalException): Don't bother restarting an
1518 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1520 * interp.c (SignalException): Really take an interrupt.
1521 (interrupt_event): Only deliver interrupts when enabled.
1523 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1525 * interp.c (sim_info): Only print info when verbose.
1526 (sim_info) Use sim_io_printf for output.
1528 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1530 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1533 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1535 * interp.c (sim_do_command): Check for common commands if a
1536 simulator specific command fails.
1538 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1540 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1541 and simBE when DEBUG is defined.
1543 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1545 * interp.c (interrupt_event): New function. Pass exception event
1546 onto exception handler.
1548 * configure.in: Check for stdlib.h.
1549 * configure: Regenerate.
1551 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1552 variable declaration.
1553 (build_instruction): Initialize memval1.
1554 (build_instruction): Add UNUSED attribute to byte, bigend,
1556 (build_operands): Ditto.
1558 * interp.c: Fix GCC warnings.
1559 (sim_get_quit_code): Delete.
1561 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1562 * Makefile.in: Ditto.
1563 * configure: Re-generate.
1565 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1567 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1569 * interp.c (mips_option_handler): New function parse argumes using
1571 (myname): Replace with STATE_MY_NAME.
1572 (sim_open): Delete check for host endianness - performed by
1574 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1575 (sim_open): Move much of the initialization from here.
1576 (sim_load): To here. After the image has been loaded and
1578 (sim_open): Move ColdReset from here.
1579 (sim_create_inferior): To here.
1580 (sim_open): Make FP check less dependant on host endianness.
1582 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1584 * interp.c (sim_set_callbacks): Delete.
1586 * interp.c (membank, membank_base, membank_size): Replace with
1587 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1588 (sim_open): Remove call to callback->init. gdb/run do this.
1592 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1594 * interp.c (big_endian_p): Delete, replaced by
1595 current_target_byte_order.
1597 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1599 * interp.c (host_read_long, host_read_word, host_swap_word,
1600 host_swap_long): Delete. Using common sim-endian.
1601 (sim_fetch_register, sim_store_register): Use H2T.
1602 (pipeline_ticks): Delete. Handled by sim-events.
1604 (sim_engine_run): Update.
1606 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1608 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1610 (SignalException): To here. Signal using sim_engine_halt.
1611 (sim_stop_reason): Delete, moved to common.
1613 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1615 * interp.c (sim_open): Add callback argument.
1616 (sim_set_callbacks): Delete SIM_DESC argument.
1619 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1621 * Makefile.in (SIM_OBJS): Add common modules.
1623 * interp.c (sim_set_callbacks): Also set SD callback.
1624 (set_endianness, xfer_*, swap_*): Delete.
1625 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1626 Change to functions using sim-endian macros.
1627 (control_c, sim_stop): Delete, use common version.
1628 (simulate): Convert into.
1629 (sim_engine_run): This function.
1630 (sim_resume): Delete.
1632 * interp.c (simulation): New variable - the simulator object.
1633 (sim_kind): Delete global - merged into simulation.
1634 (sim_load): Cleanup. Move PC assignment from here.
1635 (sim_create_inferior): To here.
1637 * sim-main.h: New file.
1638 * interp.c (sim-main.h): Include.
1640 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1642 * configure: Regenerated to track ../common/aclocal.m4 changes.
1644 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1646 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1648 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1650 * gencode.c (build_instruction): DIV instructions: check
1651 for division by zero and integer overflow before using
1652 host's division operation.
1654 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1656 * Makefile.in (SIM_OBJS): Add sim-load.o.
1657 * interp.c: #include bfd.h.
1658 (target_byte_order): Delete.
1659 (sim_kind, myname, big_endian_p): New static locals.
1660 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1661 after argument parsing. Recognize -E arg, set endianness accordingly.
1662 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1663 load file into simulator. Set PC from bfd.
1664 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1665 (set_endianness): Use big_endian_p instead of target_byte_order.
1667 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1669 * interp.c (sim_size): Delete prototype - conflicts with
1670 definition in remote-sim.h. Correct definition.
1672 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1674 * configure: Regenerated to track ../common/aclocal.m4 changes.
1677 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1679 * interp.c (sim_open): New arg `kind'.
1681 * configure: Regenerated to track ../common/aclocal.m4 changes.
1683 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1685 * configure: Regenerated to track ../common/aclocal.m4 changes.
1687 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1689 * interp.c (sim_open): Set optind to 0 before calling getopt.
1691 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1693 * configure: Regenerated to track ../common/aclocal.m4 changes.
1695 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1697 * interp.c : Replace uses of pr_addr with pr_uword64
1698 where the bit length is always 64 independent of SIM_ADDR.
1699 (pr_uword64) : added.
1701 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1703 * configure: Re-generate.
1705 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1707 * configure: Regenerate to track ../common/aclocal.m4 changes.
1709 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1711 * interp.c (sim_open): New SIM_DESC result. Argument is now
1713 (other sim_*): New SIM_DESC argument.
1715 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1717 * interp.c: Fix printing of addresses for non-64-bit targets.
1718 (pr_addr): Add function to print address based on size.
1720 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1722 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1724 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1726 * gencode.c (build_mips16_operands): Correct computation of base
1727 address for extended PC relative instruction.
1729 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1731 * interp.c (mips16_entry): Add support for floating point cases.
1732 (SignalException): Pass floating point cases to mips16_entry.
1733 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1735 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1737 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1738 and then set the state to fmt_uninterpreted.
1739 (COP_SW): Temporarily set the state to fmt_word while calling
1742 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1744 * gencode.c (build_instruction): The high order may be set in the
1745 comparison flags at any ISA level, not just ISA 4.
1747 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1749 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1750 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1751 * configure.in: sinclude ../common/aclocal.m4.
1752 * configure: Regenerated.
1754 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1756 * configure: Rebuild after change to aclocal.m4.
1758 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1760 * configure configure.in Makefile.in: Update to new configure
1761 scheme which is more compatible with WinGDB builds.
1762 * configure.in: Improve comment on how to run autoconf.
1763 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1764 * Makefile.in: Use autoconf substitution to install common
1767 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1769 * gencode.c (build_instruction): Use BigEndianCPU instead of
1772 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1774 * interp.c (sim_monitor): Make output to stdout visible in
1775 wingdb's I/O log window.
1777 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1779 * support.h: Undo previous change to SIGTRAP
1782 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1784 * interp.c (store_word, load_word): New static functions.
1785 (mips16_entry): New static function.
1786 (SignalException): Look for mips16 entry and exit instructions.
1787 (simulate): Use the correct index when setting fpr_state after
1788 doing a pending move.
1790 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1792 * interp.c: Fix byte-swapping code throughout to work on
1793 both little- and big-endian hosts.
1795 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1797 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1798 with gdb/config/i386/xm-windows.h.
1800 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1802 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1803 that messes up arithmetic shifts.
1805 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1807 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1808 SIGTRAP and SIGQUIT for _WIN32.
1810 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1812 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1813 force a 64 bit multiplication.
1814 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1815 destination register is 0, since that is the default mips16 nop
1818 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1820 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1821 (build_endian_shift): Don't check proc64.
1822 (build_instruction): Always set memval to uword64. Cast op2 to
1823 uword64 when shifting it left in memory instructions. Always use
1824 the same code for stores--don't special case proc64.
1826 * gencode.c (build_mips16_operands): Fix base PC value for PC
1828 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1830 * interp.c (simJALDELAYSLOT): Define.
1831 (JALDELAYSLOT): Define.
1832 (INDELAYSLOT, INJALDELAYSLOT): Define.
1833 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1835 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1837 * interp.c (sim_open): add flush_cache as a PMON routine
1838 (sim_monitor): handle flush_cache by ignoring it
1840 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1842 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1844 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1845 (BigEndianMem): Rename to ByteSwapMem and change sense.
1846 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1847 BigEndianMem references to !ByteSwapMem.
1848 (set_endianness): New function, with prototype.
1849 (sim_open): Call set_endianness.
1850 (sim_info): Use simBE instead of BigEndianMem.
1851 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1852 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1853 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1854 ifdefs, keeping the prototype declaration.
1855 (swap_word): Rewrite correctly.
1856 (ColdReset): Delete references to CONFIG. Delete endianness related
1857 code; moved to set_endianness.
1859 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1861 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1862 * interp.c (CHECKHILO): Define away.
1863 (simSIGINT): New macro.
1864 (membank_size): Increase from 1MB to 2MB.
1865 (control_c): New function.
1866 (sim_resume): Rename parameter signal to signal_number. Add local
1867 variable prev. Call signal before and after simulate.
1868 (sim_stop_reason): Add simSIGINT support.
1869 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1871 (sim_warning): Delete call to SignalException. Do call printf_filtered
1873 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1874 a call to sim_warning.
1876 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1878 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1879 16 bit instructions.
1881 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1883 Add support for mips16 (16 bit MIPS implementation):
1884 * gencode.c (inst_type): Add mips16 instruction encoding types.
1885 (GETDATASIZEINSN): Define.
1886 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1887 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1889 (MIPS16_DECODE): New table, for mips16 instructions.
1890 (bitmap_val): New static function.
1891 (struct mips16_op): Define.
1892 (mips16_op_table): New table, for mips16 operands.
1893 (build_mips16_operands): New static function.
1894 (process_instructions): If PC is odd, decode a mips16
1895 instruction. Break out instruction handling into new
1896 build_instruction function.
1897 (build_instruction): New static function, broken out of
1898 process_instructions. Check modifiers rather than flags for SHIFT
1899 bit count and m[ft]{hi,lo} direction.
1900 (usage): Pass program name to fprintf.
1901 (main): Remove unused variable this_option_optind. Change
1902 ``*loptarg++'' to ``loptarg++''.
1903 (my_strtoul): Parenthesize && within ||.
1904 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1905 (simulate): If PC is odd, fetch a 16 bit instruction, and
1906 increment PC by 2 rather than 4.
1907 * configure.in: Add case for mips16*-*-*.
1908 * configure: Rebuild.
1910 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1912 * interp.c: Allow -t to enable tracing in standalone simulator.
1913 Fix garbage output in trace file and error messages.
1915 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1917 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1918 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1919 * configure.in: Simplify using macros in ../common/aclocal.m4.
1920 * configure: Regenerated.
1921 * tconfig.in: New file.
1923 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1925 * interp.c: Fix bugs in 64-bit port.
1926 Use ansi function declarations for msvc compiler.
1927 Initialize and test file pointer in trace code.
1928 Prevent duplicate definition of LAST_EMED_REGNUM.
1930 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1932 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1934 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1936 * interp.c (SignalException): Check for explicit terminating
1938 * gencode.c: Pass instruction value through SignalException()
1939 calls for Trap, Breakpoint and Syscall.
1941 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1943 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1944 only used on those hosts that provide it.
1945 * configure.in: Add sqrt() to list of functions to be checked for.
1946 * config.in: Re-generated.
1947 * configure: Re-generated.
1949 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1951 * gencode.c (process_instructions): Call build_endian_shift when
1952 expanding STORE RIGHT, to fix swr.
1953 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1954 clear the high bits.
1955 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1956 Fix float to int conversions to produce signed values.
1958 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
1960 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1961 (process_instructions): Correct handling of nor instruction.
1962 Correct shift count for 32 bit shift instructions. Correct sign
1963 extension for arithmetic shifts to not shift the number of bits in
1964 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
1965 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
1967 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
1968 It's OK to have a mult follow a mult. What's not OK is to have a
1969 mult follow an mfhi.
1970 (Convert): Comment out incorrect rounding code.
1972 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
1974 * interp.c (sim_monitor): Improved monitor printf
1975 simulation. Tidied up simulator warnings, and added "--log" option
1976 for directing warning message output.
1977 * gencode.c: Use sim_warning() rather than WARNING macro.
1979 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
1981 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
1982 getopt1.o, rather than on gencode.c. Link objects together.
1983 Don't link against -liberty.
1984 (gencode.o, getopt.o, getopt1.o): New targets.
1985 * gencode.c: Include <ctype.h> and "ansidecl.h".
1986 (AND): Undefine after including "ansidecl.h".
1987 (ULONG_MAX): Define if not defined.
1988 (OP_*): Don't define macros; now defined in opcode/mips.h.
1989 (main): Call my_strtoul rather than strtoul.
1990 (my_strtoul): New static function.
1992 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
1994 * gencode.c (process_instructions): Generate word64 and uword64
1995 instead of `long long' and `unsigned long long' data types.
1996 * interp.c: #include sysdep.h to get signals, and define default
1998 * (Convert): Work around for Visual-C++ compiler bug with type
2000 * support.h: Make things compile under Visual-C++ by using
2001 __int64 instead of `long long'. Change many refs to long long
2002 into word64/uword64 typedefs.
2004 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2006 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2007 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2009 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2010 (AC_PROG_INSTALL): Added.
2011 (AC_PROG_CC): Moved to before configure.host call.
2012 * configure: Rebuilt.
2014 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2016 * configure.in: Define @SIMCONF@ depending on mips target.
2017 * configure: Rebuild.
2018 * Makefile.in (run): Add @SIMCONF@ to control simulator
2020 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2021 * interp.c: Remove some debugging, provide more detailed error
2022 messages, update memory accesses to use LOADDRMASK.
2024 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2026 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2027 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2029 * configure: Rebuild.
2030 * config.in: New file, generated by autoheader.
2031 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2032 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2033 HAVE_ANINT and HAVE_AINT, as appropriate.
2034 * Makefile.in (run): Use @LIBS@ rather than -lm.
2035 (interp.o): Depend upon config.h.
2036 (Makefile): Just rebuild Makefile.
2037 (clean): Remove stamp-h.
2038 (mostlyclean): Make the same as clean, not as distclean.
2039 (config.h, stamp-h): New targets.
2041 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2043 * interp.c (ColdReset): Fix boolean test. Make all simulator
2046 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2048 * interp.c (xfer_direct_word, xfer_direct_long,
2049 swap_direct_word, swap_direct_long, xfer_big_word,
2050 xfer_big_long, xfer_little_word, xfer_little_long,
2051 swap_word,swap_long): Added.
2052 * interp.c (ColdReset): Provide function indirection to
2053 host<->simulated_target transfer routines.
2054 * interp.c (sim_store_register, sim_fetch_register): Updated to
2055 make use of indirected transfer routines.
2057 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2059 * gencode.c (process_instructions): Ensure FP ABS instruction
2061 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2062 system call support.
2064 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2066 * interp.c (sim_do_command): Complain if callback structure not
2069 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2071 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2072 support for Sun hosts.
2073 * Makefile.in (gencode): Ensure the host compiler and libraries
2074 used for cross-hosted build.
2076 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2078 * interp.c, gencode.c: Some more (TODO) tidying.
2080 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2082 * gencode.c, interp.c: Replaced explicit long long references with
2083 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2084 * support.h (SET64LO, SET64HI): Macros added.
2086 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2088 * configure: Regenerate with autoconf 2.7.
2090 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2092 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2093 * support.h: Remove superfluous "1" from #if.
2094 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2096 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2098 * interp.c (StoreFPR): Control UndefinedResult() call on
2099 WARN_RESULT manifest.
2101 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2103 * gencode.c: Tidied instruction decoding, and added FP instruction
2106 * interp.c: Added dineroIII, and BSD profiling support. Also
2107 run-time FP handling.
2109 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2111 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2112 gencode.c, interp.c, support.h: created.
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