1 2004-04-29 Chris Demetriou <cgd@broadcom.com>
2 Richard Sandiford <rsandifo@redhat.com>
4 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
5 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
6 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
7 separate implementations for mipsIV and mipsV. Use new macros to
8 determine whether the restrictions apply.
10 2004-01-19 Chris Demetriou <cgd@broadcom.com>
12 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
13 (check_mult_hilo): Improve comments.
14 (check_div_hilo): Likewise. Also, fork off a new version
15 to handle mips32/mips64 (since there are no hazards to check
18 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
20 * mips.igen (do_dmultx): Fix check for negative operands.
22 2003-05-16 Ian Lance Taylor <ian@airs.com>
24 * Makefile.in (SHELL): Make sure this is defined.
25 (various): Use $(SHELL) whenever we invoke move-if-change.
27 2003-05-03 Chris Demetriou <cgd@broadcom.com>
29 * cp1.c: Tweak attribution slightly.
32 * mdmx.igen: Likewise.
33 * mips3d.igen: Likewise.
36 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
38 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
41 2003-02-27 Andrew Cagney <cagney@redhat.com>
43 * interp.c (sim_open): Rename _bfd to bfd.
44 (sim_create_inferior): Ditto.
46 2003-01-14 Chris Demetriou <cgd@broadcom.com>
48 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
50 2003-01-14 Chris Demetriou <cgd@broadcom.com>
52 * mips.igen (EI, DI): Remove.
54 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
56 * Makefile.in (tmp-run-multi): Fix mips16 filter.
58 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
59 Andrew Cagney <ac131313@redhat.com>
60 Gavin Romig-Koch <gavin@redhat.com>
61 Graydon Hoare <graydon@redhat.com>
62 Aldy Hernandez <aldyh@redhat.com>
63 Dave Brolley <brolley@redhat.com>
64 Chris Demetriou <cgd@broadcom.com>
66 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
67 (sim_mach_default): New variable.
68 (mips64vr-*-*, mips64vrel-*-*): New configurations.
69 Add a new simulator generator, MULTI.
70 * configure: Regenerate.
71 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
72 (multi-run.o): New dependency.
73 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
74 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
75 (tmp-multi): Combine them.
76 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
77 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
78 (distclean-extra): New rule.
79 * sim-main.h: Include bfd.h.
80 (MIPS_MACH): New macro.
81 * mips.igen (vr4120, vr5400, vr5500): New models.
82 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
83 * vr.igen: Replace with new version.
85 2003-01-04 Chris Demetriou <cgd@broadcom.com>
87 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
88 * configure: Regenerate.
90 2002-12-31 Chris Demetriou <cgd@broadcom.com>
92 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
93 * mips.igen: Remove all invocations of check_branch_bug and
96 2002-12-16 Chris Demetriou <cgd@broadcom.com>
98 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
100 2002-07-30 Chris Demetriou <cgd@broadcom.com>
102 * mips.igen (do_load_double, do_store_double): New functions.
103 (LDC1, SDC1): Rename to...
104 (LDC1b, SDC1b): respectively.
105 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
107 2002-07-29 Michael Snyder <msnyder@redhat.com>
109 * cp1.c (fp_recip2): Modify initialization expression so that
110 GCC will recognize it as constant.
112 2002-06-18 Chris Demetriou <cgd@broadcom.com>
114 * mdmx.c (SD_): Delete.
115 (Unpredictable): Re-define, for now, to directly invoke
116 unpredictable_action().
117 (mdmx_acc_op): Fix error in .ob immediate handling.
119 2002-06-18 Andrew Cagney <cagney@redhat.com>
121 * interp.c (sim_firmware_command): Initialize `address'.
123 2002-06-16 Andrew Cagney <ac131313@redhat.com>
125 * configure: Regenerated to track ../common/aclocal.m4 changes.
127 2002-06-14 Chris Demetriou <cgd@broadcom.com>
128 Ed Satterthwaite <ehs@broadcom.com>
130 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
131 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
132 * mips.igen: Include mips3d.igen.
133 (mips3d): New model name for MIPS-3D ASE instructions.
134 (CVT.W.fmt): Don't use this instruction for word (source) format
136 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
137 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
138 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
139 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
140 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
141 (RSquareRoot1, RSquareRoot2): New macros.
142 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
143 (fp_rsqrt2): New functions.
144 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
145 * configure: Regenerate.
147 2002-06-13 Chris Demetriou <cgd@broadcom.com>
148 Ed Satterthwaite <ehs@broadcom.com>
150 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
151 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
152 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
153 (convert): Note that this function is not used for paired-single
155 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
156 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
157 (check_fmt_p): Enable paired-single support.
158 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
159 (PUU.PS): New instructions.
160 (CVT.S.fmt): Don't use this instruction for paired-single format
162 * sim-main.h (FP_formats): New value 'fmt_ps.'
163 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
164 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
166 2002-06-12 Chris Demetriou <cgd@broadcom.com>
168 * mips.igen: Fix formatting of function calls in
171 2002-06-12 Chris Demetriou <cgd@broadcom.com>
173 * mips.igen (MOVN, MOVZ): Trace result.
174 (TNEI): Print "tnei" as the opcode name in traces.
175 (CEIL.W): Add disassembly string for traces.
176 (RSQRT.fmt): Make location of disassembly string consistent
177 with other instructions.
179 2002-06-12 Chris Demetriou <cgd@broadcom.com>
181 * mips.igen (X): Delete unused function.
183 2002-06-08 Andrew Cagney <cagney@redhat.com>
185 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
187 2002-06-07 Chris Demetriou <cgd@broadcom.com>
188 Ed Satterthwaite <ehs@broadcom.com>
190 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
191 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
192 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
193 (fp_nmsub): New prototypes.
194 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
195 (NegMultiplySub): New defines.
196 * mips.igen (RSQRT.fmt): Use RSquareRoot().
197 (MADD.D, MADD.S): Replace with...
198 (MADD.fmt): New instruction.
199 (MSUB.D, MSUB.S): Replace with...
200 (MSUB.fmt): New instruction.
201 (NMADD.D, NMADD.S): Replace with...
202 (NMADD.fmt): New instruction.
203 (NMSUB.D, MSUB.S): Replace with...
204 (NMSUB.fmt): New instruction.
206 2002-06-07 Chris Demetriou <cgd@broadcom.com>
207 Ed Satterthwaite <ehs@broadcom.com>
209 * cp1.c: Fix more comment spelling and formatting.
210 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
211 (denorm_mode): New function.
212 (fpu_unary, fpu_binary): Round results after operation, collect
213 status from rounding operations, and update the FCSR.
214 (convert): Collect status from integer conversions and rounding
215 operations, and update the FCSR. Adjust NaN values that result
216 from conversions. Convert to use sim_io_eprintf rather than
217 fprintf, and remove some debugging code.
218 * cp1.h (fenr_FS): New define.
220 2002-06-07 Chris Demetriou <cgd@broadcom.com>
222 * cp1.c (convert): Remove unusable debugging code, and move MIPS
223 rounding mode to sim FP rounding mode flag conversion code into...
224 (rounding_mode): New function.
226 2002-06-07 Chris Demetriou <cgd@broadcom.com>
228 * cp1.c: Clean up formatting of a few comments.
229 (value_fpr): Reformat switch statement.
231 2002-06-06 Chris Demetriou <cgd@broadcom.com>
232 Ed Satterthwaite <ehs@broadcom.com>
235 * sim-main.h: Include cp1.h.
236 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
237 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
238 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
239 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
240 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
241 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
242 * cp1.c: Don't include sim-fpu.h; already included by
243 sim-main.h. Clean up formatting of some comments.
244 (NaN, Equal, Less): Remove.
245 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
246 (fp_cmp): New functions.
247 * mips.igen (do_c_cond_fmt): Remove.
248 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
249 Compare. Add result tracing.
250 (CxC1): Remove, replace with...
251 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
252 (DMxC1): Remove, replace with...
253 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
254 (MxC1): Remove, replace with...
255 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
257 2002-06-04 Chris Demetriou <cgd@broadcom.com>
259 * sim-main.h (FGRIDX): Remove, replace all uses with...
260 (FGR_BASE): New macro.
261 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
262 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
263 (NR_FGR, FGR): Likewise.
264 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
265 * mips.igen: Likewise.
267 2002-06-04 Chris Demetriou <cgd@broadcom.com>
269 * cp1.c: Add an FSF Copyright notice to this file.
271 2002-06-04 Chris Demetriou <cgd@broadcom.com>
272 Ed Satterthwaite <ehs@broadcom.com>
274 * cp1.c (Infinity): Remove.
275 * sim-main.h (Infinity): Likewise.
277 * cp1.c (fp_unary, fp_binary): New functions.
278 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
279 (fp_sqrt): New functions, implemented in terms of the above.
280 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
281 (Recip, SquareRoot): Remove (replaced by functions above).
282 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
283 (fp_recip, fp_sqrt): New prototypes.
284 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
285 (Recip, SquareRoot): Replace prototypes with #defines which
286 invoke the functions above.
288 2002-06-03 Chris Demetriou <cgd@broadcom.com>
290 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
291 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
292 file, remove PARAMS from prototypes.
293 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
294 simulator state arguments.
295 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
296 pass simulator state arguments.
297 * cp1.c (SD): Redefine as CPU_STATE(cpu).
298 (store_fpr, convert): Remove 'sd' argument.
299 (value_fpr): Likewise. Convert to use 'SD' instead.
301 2002-06-03 Chris Demetriou <cgd@broadcom.com>
303 * cp1.c (Min, Max): Remove #if 0'd functions.
304 * sim-main.h (Min, Max): Remove.
306 2002-06-03 Chris Demetriou <cgd@broadcom.com>
308 * cp1.c: fix formatting of switch case and default labels.
309 * interp.c: Likewise.
310 * sim-main.c: Likewise.
312 2002-06-03 Chris Demetriou <cgd@broadcom.com>
314 * cp1.c: Clean up comments which describe FP formats.
315 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
317 2002-06-03 Chris Demetriou <cgd@broadcom.com>
318 Ed Satterthwaite <ehs@broadcom.com>
320 * configure.in (mipsisa64sb1*-*-*): New target for supporting
321 Broadcom SiByte SB-1 processor configurations.
322 * configure: Regenerate.
323 * sb1.igen: New file.
324 * mips.igen: Include sb1.igen.
326 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
327 * mdmx.igen: Add "sb1" model to all appropriate functions and
329 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
330 (ob_func, ob_acc): Reference the above.
331 (qh_acc): Adjust to keep the same size as ob_acc.
332 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
333 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
335 2002-06-03 Chris Demetriou <cgd@broadcom.com>
337 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
339 2002-06-02 Chris Demetriou <cgd@broadcom.com>
340 Ed Satterthwaite <ehs@broadcom.com>
342 * mips.igen (mdmx): New (pseudo-)model.
343 * mdmx.c, mdmx.igen: New files.
344 * Makefile.in (SIM_OBJS): Add mdmx.o.
345 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
347 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
348 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
349 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
350 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
351 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
352 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
353 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
354 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
355 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
356 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
357 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
358 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
359 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
360 (qh_fmtsel): New macros.
361 (_sim_cpu): New member "acc".
362 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
363 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
365 2002-05-01 Chris Demetriou <cgd@broadcom.com>
367 * interp.c: Use 'deprecated' rather than 'depreciated.'
368 * sim-main.h: Likewise.
370 2002-05-01 Chris Demetriou <cgd@broadcom.com>
372 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
373 which wouldn't compile anyway.
374 * sim-main.h (unpredictable_action): New function prototype.
375 (Unpredictable): Define to call igen function unpredictable().
376 (NotWordValue): New macro to call igen function not_word_value().
377 (UndefinedResult): Remove.
378 * interp.c (undefined_result): Remove.
379 (unpredictable_action): New function.
380 * mips.igen (not_word_value, unpredictable): New functions.
381 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
382 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
383 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
384 NotWordValue() to check for unpredictable inputs, then
385 Unpredictable() to handle them.
387 2002-02-24 Chris Demetriou <cgd@broadcom.com>
389 * mips.igen: Fix formatting of calls to Unpredictable().
391 2002-04-20 Andrew Cagney <ac131313@redhat.com>
393 * interp.c (sim_open): Revert previous change.
395 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
397 * interp.c (sim_open): Disable chunk of code that wrote code in
398 vector table entries.
400 2002-03-19 Chris Demetriou <cgd@broadcom.com>
402 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
403 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
406 2002-03-19 Chris Demetriou <cgd@broadcom.com>
408 * cp1.c: Fix many formatting issues.
410 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
412 * cp1.c (fpu_format_name): New function to replace...
413 (DOFMT): This. Delete, and update all callers.
414 (fpu_rounding_mode_name): New function to replace...
415 (RMMODE): This. Delete, and update all callers.
417 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
419 * interp.c: Move FPU support routines from here to...
420 * cp1.c: Here. New file.
421 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
424 2002-03-12 Chris Demetriou <cgd@broadcom.com>
426 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
427 * mips.igen (mips32, mips64): New models, add to all instructions
428 and functions as appropriate.
429 (loadstore_ea, check_u64): New variant for model mips64.
430 (check_fmt_p): New variant for models mipsV and mips64, remove
431 mipsV model marking fro other variant.
434 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
435 for mips32 and mips64.
436 (DCLO, DCLZ): New instructions for mips64.
438 2002-03-07 Chris Demetriou <cgd@broadcom.com>
440 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
441 immediate or code as a hex value with the "%#lx" format.
442 (ANDI): Likewise, and fix printed instruction name.
444 2002-03-05 Chris Demetriou <cgd@broadcom.com>
446 * sim-main.h (UndefinedResult, Unpredictable): New macros
447 which currently do nothing.
449 2002-03-05 Chris Demetriou <cgd@broadcom.com>
451 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
452 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
453 (status_CU3): New definitions.
455 * sim-main.h (ExceptionCause): Add new values for MIPS32
456 and MIPS64: MDMX, MCheck, CacheErr. Update comments
457 for DebugBreakPoint and NMIReset to note their status in
459 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
460 (SignalExceptionCacheErr): New exception macros.
462 2002-03-05 Chris Demetriou <cgd@broadcom.com>
464 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
465 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
467 (SignalExceptionCoProcessorUnusable): Take as argument the
468 unusable coprocessor number.
470 2002-03-05 Chris Demetriou <cgd@broadcom.com>
472 * mips.igen: Fix formatting of all SignalException calls.
474 2002-03-05 Chris Demetriou <cgd@broadcom.com>
476 * sim-main.h (SIGNEXTEND): Remove.
478 2002-03-04 Chris Demetriou <cgd@broadcom.com>
480 * mips.igen: Remove gencode comment from top of file, fix
481 spelling in another comment.
483 2002-03-04 Chris Demetriou <cgd@broadcom.com>
485 * mips.igen (check_fmt, check_fmt_p): New functions to check
486 whether specific floating point formats are usable.
487 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
488 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
489 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
490 Use the new functions.
491 (do_c_cond_fmt): Remove format checks...
492 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
494 2002-03-03 Chris Demetriou <cgd@broadcom.com>
496 * mips.igen: Fix formatting of check_fpu calls.
498 2002-03-03 Chris Demetriou <cgd@broadcom.com>
500 * mips.igen (FLOOR.L.fmt): Store correct destination register.
502 2002-03-03 Chris Demetriou <cgd@broadcom.com>
504 * mips.igen: Remove whitespace at end of lines.
506 2002-03-02 Chris Demetriou <cgd@broadcom.com>
508 * mips.igen (loadstore_ea): New function to do effective
509 address calculations.
510 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
511 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
512 CACHE): Use loadstore_ea to do effective address computations.
514 2002-03-02 Chris Demetriou <cgd@broadcom.com>
516 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
517 * mips.igen (LL, CxC1, MxC1): Likewise.
519 2002-03-02 Chris Demetriou <cgd@broadcom.com>
521 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
522 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
523 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
524 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
525 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
526 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
527 Don't split opcode fields by hand, use the opcode field values
530 2002-03-01 Chris Demetriou <cgd@broadcom.com>
532 * mips.igen (do_divu): Fix spacing.
534 * mips.igen (do_dsllv): Move to be right before DSLLV,
535 to match the rest of the do_<shift> functions.
537 2002-03-01 Chris Demetriou <cgd@broadcom.com>
539 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
540 DSRL32, do_dsrlv): Trace inputs and results.
542 2002-03-01 Chris Demetriou <cgd@broadcom.com>
544 * mips.igen (CACHE): Provide instruction-printing string.
546 * interp.c (signal_exception): Comment tokens after #endif.
548 2002-02-28 Chris Demetriou <cgd@broadcom.com>
550 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
551 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
552 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
553 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
554 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
555 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
556 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
557 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
559 2002-02-28 Chris Demetriou <cgd@broadcom.com>
561 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
562 instruction-printing string.
563 (LWU): Use '64' as the filter flag.
565 2002-02-28 Chris Demetriou <cgd@broadcom.com>
567 * mips.igen (SDXC1): Fix instruction-printing string.
569 2002-02-28 Chris Demetriou <cgd@broadcom.com>
571 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
574 2002-02-27 Chris Demetriou <cgd@broadcom.com>
576 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
579 2002-02-27 Chris Demetriou <cgd@broadcom.com>
581 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
582 add a comma) so that it more closely match the MIPS ISA
583 documentation opcode partitioning.
584 (PREF): Put useful names on opcode fields, and include
585 instruction-printing string.
587 2002-02-27 Chris Demetriou <cgd@broadcom.com>
589 * mips.igen (check_u64): New function which in the future will
590 check whether 64-bit instructions are usable and signal an
591 exception if not. Currently a no-op.
592 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
593 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
594 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
595 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
597 * mips.igen (check_fpu): New function which in the future will
598 check whether FPU instructions are usable and signal an exception
599 if not. Currently a no-op.
600 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
601 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
602 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
603 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
604 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
605 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
606 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
607 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
609 2002-02-27 Chris Demetriou <cgd@broadcom.com>
611 * mips.igen (do_load_left, do_load_right): Move to be immediately
613 (do_store_left, do_store_right): Move to be immediately following
616 2002-02-27 Chris Demetriou <cgd@broadcom.com>
618 * mips.igen (mipsV): New model name. Also, add it to
619 all instructions and functions where it is appropriate.
621 2002-02-18 Chris Demetriou <cgd@broadcom.com>
623 * mips.igen: For all functions and instructions, list model
624 names that support that instruction one per line.
626 2002-02-11 Chris Demetriou <cgd@broadcom.com>
628 * mips.igen: Add some additional comments about supported
629 models, and about which instructions go where.
630 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
631 order as is used in the rest of the file.
633 2002-02-11 Chris Demetriou <cgd@broadcom.com>
635 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
636 indicating that ALU32_END or ALU64_END are there to check
638 (DADD): Likewise, but also remove previous comment about
641 2002-02-10 Chris Demetriou <cgd@broadcom.com>
643 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
644 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
645 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
646 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
647 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
648 fields (i.e., add and move commas) so that they more closely
649 match the MIPS ISA documentation opcode partitioning.
651 2002-02-10 Chris Demetriou <cgd@broadcom.com>
653 * mips.igen (ADDI): Print immediate value.
655 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
656 (SLL): Print "nop" specially, and don't run the code
657 that does the shift for the "nop" case.
659 2001-11-17 Fred Fish <fnf@redhat.com>
661 * sim-main.h (float_operation): Move enum declaration outside
662 of _sim_cpu struct declaration.
664 2001-04-12 Jim Blandy <jimb@redhat.com>
666 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
667 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
669 * sim-main.h (COCIDX): Remove definition; this isn't supported by
670 PENDING_FILL, and you can get the intended effect gracefully by
671 calling PENDING_SCHED directly.
673 2001-02-23 Ben Elliston <bje@redhat.com>
675 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
676 already defined elsewhere.
678 2001-02-19 Ben Elliston <bje@redhat.com>
680 * sim-main.h (sim_monitor): Return an int.
681 * interp.c (sim_monitor): Add return values.
682 (signal_exception): Handle error conditions from sim_monitor.
684 2001-02-08 Ben Elliston <bje@redhat.com>
686 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
687 (store_memory): Likewise, pass cia to sim_core_write*.
689 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
691 On advice from Chris G. Demetriou <cgd@sibyte.com>:
692 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
694 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
696 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
697 * Makefile.in: Don't delete *.igen when cleaning directory.
699 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
701 * m16.igen (break): Call SignalException not sim_engine_halt.
703 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
706 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
708 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
710 * mips.igen (MxC1, DMxC1): Fix printf formatting.
712 2000-05-24 Michael Hayes <mhayes@cygnus.com>
714 * mips.igen (do_dmultx): Fix typo.
716 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
718 * configure: Regenerated to track ../common/aclocal.m4 changes.
720 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
722 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
724 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
726 * sim-main.h (GPR_CLEAR): Define macro.
728 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
730 * interp.c (decode_coproc): Output long using %lx and not %s.
732 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
734 * interp.c (sim_open): Sort & extend dummy memory regions for
735 --board=jmr3904 for eCos.
737 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
739 * configure: Regenerated.
741 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
743 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
744 calls, conditional on the simulator being in verbose mode.
746 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
748 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
749 cache don't get ReservedInstruction traps.
751 1999-11-29 Mark Salter <msalter@cygnus.com>
753 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
754 to clear status bits in sdisr register. This is how the hardware works.
756 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
757 being used by cygmon.
759 1999-11-11 Andrew Haley <aph@cygnus.com>
761 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
764 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
766 * mips.igen (MULT): Correct previous mis-applied patch.
768 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
770 * mips.igen (delayslot32): Handle sequence like
771 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
772 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
773 (MULT): Actually pass the third register...
775 1999-09-03 Mark Salter <msalter@cygnus.com>
777 * interp.c (sim_open): Added more memory aliases for additional
778 hardware being touched by cygmon on jmr3904 board.
780 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
782 * configure: Regenerated to track ../common/aclocal.m4 changes.
784 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
786 * interp.c (sim_store_register): Handle case where client - GDB -
787 specifies that a 4 byte register is 8 bytes in size.
788 (sim_fetch_register): Ditto.
790 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
792 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
793 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
794 (idt_monitor_base): Base address for IDT monitor traps.
795 (pmon_monitor_base): Ditto for PMON.
796 (lsipmon_monitor_base): Ditto for LSI PMON.
797 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
798 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
799 (sim_firmware_command): New function.
800 (mips_option_handler): Call it for OPTION_FIRMWARE.
801 (sim_open): Allocate memory for idt_monitor region. If "--board"
802 option was given, add no monitor by default. Add BREAK hooks only if
803 monitors are also there.
805 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
807 * interp.c (sim_monitor): Flush output before reading input.
809 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
811 * tconfig.in (SIM_HANDLES_LMA): Always define.
813 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
815 From Mark Salter <msalter@cygnus.com>:
816 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
817 (sim_open): Add setup for BSP board.
819 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
821 * mips.igen (MULT, MULTU): Add syntax for two operand version.
822 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
823 them as unimplemented.
825 1999-05-08 Felix Lee <flee@cygnus.com>
827 * configure: Regenerated to track ../common/aclocal.m4 changes.
829 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
831 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
833 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
835 * configure.in: Any mips64vr5*-*-* target should have
836 -DTARGET_ENABLE_FR=1.
837 (default_endian): Any mips64vr*el-*-* target should default to
839 * configure: Re-generate.
841 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
843 * mips.igen (ldl): Extend from _16_, not 32.
845 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
847 * interp.c (sim_store_register): Force registers written to by GDB
848 into an un-interpreted state.
850 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
852 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
853 CPU, start periodic background I/O polls.
854 (tx3904sio_poll): New function: periodic I/O poller.
856 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
858 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
860 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
862 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
865 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
867 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
868 (load_word): Call SIM_CORE_SIGNAL hook on error.
869 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
870 starting. For exception dispatching, pass PC instead of NULL_CIA.
871 (decode_coproc): Use COP0_BADVADDR to store faulting address.
872 * sim-main.h (COP0_BADVADDR): Define.
873 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
874 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
875 (_sim_cpu): Add exc_* fields to store register value snapshots.
876 * mips.igen (*): Replace memory-related SignalException* calls
877 with references to SIM_CORE_SIGNAL hook.
879 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
881 * sim-main.c (*): Minor warning cleanups.
883 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
885 * m16.igen (DADDIU5): Correct type-o.
887 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
889 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
892 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
894 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
896 (interp.o): Add dependency on itable.h
897 (oengine.c, gencode): Delete remaining references.
898 (BUILT_SRC_FROM_GEN): Clean up.
900 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
903 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
904 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
906 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
907 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
908 Drop the "64" qualifier to get the HACK generator working.
909 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
910 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
911 qualifier to get the hack generator working.
912 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
914 (DSLLV): Use do_dsllv.
917 (DSRLV): Use do_dsrlv.
918 (BC1): Move *vr4100 to get the HACK generator working.
919 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
920 get the HACK generator working.
921 (MACC) Rename to get the HACK generator working.
922 (DMACC,MACCS,DMACCS): Add the 64.
924 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
926 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
927 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
929 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
931 * mips/interp.c (DEBUG): Cleanups.
933 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
935 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
936 (tx3904sio_tickle): fflush after a stdout character output.
938 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
940 * interp.c (sim_close): Uninstall modules.
942 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
944 * sim-main.h, interp.c (sim_monitor): Change to global
947 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
949 * configure.in (vr4100): Only include vr4100 instructions in
951 * configure: Re-generate.
952 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
954 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
956 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
957 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
960 * configure.in (sim_default_gen, sim_use_gen): Replace with
962 (--enable-sim-igen): Delete config option. Always using IGEN.
963 * configure: Re-generate.
965 * Makefile.in (gencode): Kill, kill, kill.
968 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
970 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
971 bit mips16 igen simulator.
972 * configure: Re-generate.
974 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
975 as part of vr4100 ISA.
976 * vr.igen: Mark all instructions as 64 bit only.
978 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
980 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
983 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
985 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
986 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
987 * configure: Re-generate.
989 * m16.igen (BREAK): Define breakpoint instruction.
990 (JALX32): Mark instruction as mips16 and not r3900.
991 * mips.igen (C.cond.fmt): Fix typo in instruction format.
993 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
995 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
997 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
998 insn as a debug breakpoint.
1000 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1002 (PENDING_SCHED): Clean up trace statement.
1003 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1004 (PENDING_FILL): Delay write by only one cycle.
1005 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1007 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1009 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1011 (pending_tick): Move incrementing of index to FOR statement.
1012 (pending_tick): Only update PENDING_OUT after a write has occured.
1014 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1016 * configure: Re-generate.
1018 * interp.c (sim_engine_run OLD): Delete explicit call to
1019 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1021 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1023 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1024 interrupt level number to match changed SignalExceptionInterrupt
1027 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1029 * interp.c: #include "itable.h" if WITH_IGEN.
1030 (get_insn_name): New function.
1031 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1032 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1034 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1036 * configure: Rebuilt to inhale new common/aclocal.m4.
1038 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1040 * dv-tx3904sio.c: Include sim-assert.h.
1042 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1044 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1045 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1046 Reorganize target-specific sim-hardware checks.
1047 * configure: rebuilt.
1048 * interp.c (sim_open): For tx39 target boards, set
1049 OPERATING_ENVIRONMENT, add tx3904sio devices.
1050 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1051 ROM executables. Install dv-sockser into sim-modules list.
1053 * dv-tx3904irc.c: Compiler warning clean-up.
1054 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1055 frequent hw-trace messages.
1057 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1059 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1061 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1063 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1065 * vr.igen: New file.
1066 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1067 * mips.igen: Define vr4100 model. Include vr.igen.
1068 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1070 * mips.igen (check_mf_hilo): Correct check.
1072 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1074 * sim-main.h (interrupt_event): Add prototype.
1076 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1077 register_ptr, register_value.
1078 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1080 * sim-main.h (tracefh): Make extern.
1082 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1084 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1085 Reduce unnecessarily high timer event frequency.
1086 * dv-tx3904cpu.c: Ditto for interrupt event.
1088 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1090 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1092 (interrupt_event): Made non-static.
1094 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1095 interchange of configuration values for external vs. internal
1098 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1100 * mips.igen (BREAK): Moved code to here for
1101 simulator-reserved break instructions.
1102 * gencode.c (build_instruction): Ditto.
1103 * interp.c (signal_exception): Code moved from here. Non-
1104 reserved instructions now use exception vector, rather
1106 * sim-main.h: Moved magic constants to here.
1108 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1110 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1111 register upon non-zero interrupt event level, clear upon zero
1113 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1114 by passing zero event value.
1115 (*_io_{read,write}_buffer): Endianness fixes.
1116 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1117 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1119 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1120 serial I/O and timer module at base address 0xFFFF0000.
1122 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1124 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1127 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1129 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1131 * configure: Update.
1133 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1135 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1136 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1137 * configure.in: Include tx3904tmr in hw_device list.
1138 * configure: Rebuilt.
1139 * interp.c (sim_open): Instantiate three timer instances.
1140 Fix address typo of tx3904irc instance.
1142 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1144 * interp.c (signal_exception): SystemCall exception now uses
1145 the exception vector.
1147 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1149 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1152 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1154 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1156 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1158 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1160 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1161 sim-main.h. Declare a struct hw_descriptor instead of struct
1162 hw_device_descriptor.
1164 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1166 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1167 right bits and then re-align left hand bytes to correct byte
1168 lanes. Fix incorrect computation in do_store_left when loading
1169 bytes from second word.
1171 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1173 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1174 * interp.c (sim_open): Only create a device tree when HW is
1177 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1178 * interp.c (signal_exception): Ditto.
1180 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1182 * gencode.c: Mark BEGEZALL as LIKELY.
1184 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1186 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1187 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1189 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1191 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1192 modules. Recognize TX39 target with "mips*tx39" pattern.
1193 * configure: Rebuilt.
1194 * sim-main.h (*): Added many macros defining bits in
1195 TX39 control registers.
1196 (SignalInterrupt): Send actual PC instead of NULL.
1197 (SignalNMIReset): New exception type.
1198 * interp.c (board): New variable for future use to identify
1199 a particular board being simulated.
1200 (mips_option_handler,mips_options): Added "--board" option.
1201 (interrupt_event): Send actual PC.
1202 (sim_open): Make memory layout conditional on board setting.
1203 (signal_exception): Initial implementation of hardware interrupt
1204 handling. Accept another break instruction variant for simulator
1206 (decode_coproc): Implement RFE instruction for TX39.
1207 (mips.igen): Decode RFE instruction as such.
1208 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1209 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1210 bbegin to implement memory map.
1211 * dv-tx3904cpu.c: New file.
1212 * dv-tx3904irc.c: New file.
1214 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1216 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1218 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1220 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1221 with calls to check_div_hilo.
1223 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1225 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1226 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1227 Add special r3900 version of do_mult_hilo.
1228 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1229 with calls to check_mult_hilo.
1230 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1231 with calls to check_div_hilo.
1233 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1235 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1236 Document a replacement.
1238 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1240 * interp.c (sim_monitor): Make mon_printf work.
1242 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1244 * sim-main.h (INSN_NAME): New arg `cpu'.
1246 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1248 * configure: Regenerated to track ../common/aclocal.m4 changes.
1250 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1252 * configure: Regenerated to track ../common/aclocal.m4 changes.
1255 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1257 * acconfig.h: New file.
1258 * configure.in: Reverted change of Apr 24; use sinclude again.
1260 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1262 * configure: Regenerated to track ../common/aclocal.m4 changes.
1265 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1267 * configure.in: Don't call sinclude.
1269 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1271 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1273 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1275 * mips.igen (ERET): Implement.
1277 * interp.c (decode_coproc): Return sign-extended EPC.
1279 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1281 * interp.c (signal_exception): Do not ignore Trap.
1282 (signal_exception): On TRAP, restart at exception address.
1283 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1284 (signal_exception): Update.
1285 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1286 so that TRAP instructions are caught.
1288 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1290 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1291 contains HI/LO access history.
1292 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1293 (HIACCESS, LOACCESS): Delete, replace with
1294 (HIHISTORY, LOHISTORY): New macros.
1295 (CHECKHILO): Delete all, moved to mips.igen
1297 * gencode.c (build_instruction): Do not generate checks for
1298 correct HI/LO register usage.
1300 * interp.c (old_engine_run): Delete checks for correct HI/LO
1303 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1304 check_mf_cycles): New functions.
1305 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1306 do_divu, domultx, do_mult, do_multu): Use.
1308 * tx.igen ("madd", "maddu"): Use.
1310 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1312 * mips.igen (DSRAV): Use function do_dsrav.
1313 (SRAV): Use new function do_srav.
1315 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1316 (B): Sign extend 11 bit immediate.
1317 (EXT-B*): Shift 16 bit immediate left by 1.
1318 (ADDIU*): Don't sign extend immediate value.
1320 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1322 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1324 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1327 * mips.igen (delayslot32, nullify_next_insn): New functions.
1328 (m16.igen): Always include.
1329 (do_*): Add more tracing.
1331 * m16.igen (delayslot16): Add NIA argument, could be called by a
1332 32 bit MIPS16 instruction.
1334 * interp.c (ifetch16): Move function from here.
1335 * sim-main.c (ifetch16): To here.
1337 * sim-main.c (ifetch16, ifetch32): Update to match current
1338 implementations of LH, LW.
1339 (signal_exception): Don't print out incorrect hex value of illegal
1342 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1344 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1347 * m16.igen: Implement MIPS16 instructions.
1349 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1350 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1351 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1352 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1353 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1354 bodies of corresponding code from 32 bit insn to these. Also used
1355 by MIPS16 versions of functions.
1357 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1358 (IMEM16): Drop NR argument from macro.
1360 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1362 * Makefile.in (SIM_OBJS): Add sim-main.o.
1364 * sim-main.h (address_translation, load_memory, store_memory,
1365 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1367 (pr_addr, pr_uword64): Declare.
1368 (sim-main.c): Include when H_REVEALS_MODULE_P.
1370 * interp.c (address_translation, load_memory, store_memory,
1371 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1373 * sim-main.c: To here. Fix compilation problems.
1375 * configure.in: Enable inlining.
1376 * configure: Re-config.
1378 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1380 * configure: Regenerated to track ../common/aclocal.m4 changes.
1382 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1384 * mips.igen: Include tx.igen.
1385 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1386 * tx.igen: New file, contains MADD and MADDU.
1388 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1389 the hardwired constant `7'.
1390 (store_memory): Ditto.
1391 (LOADDRMASK): Move definition to sim-main.h.
1393 mips.igen (MTC0): Enable for r3900.
1396 mips.igen (do_load_byte): Delete.
1397 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1398 do_store_right): New functions.
1399 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1401 configure.in: Let the tx39 use igen again.
1404 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1406 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1407 not an address sized quantity. Return zero for cache sizes.
1409 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1411 * mips.igen (r3900): r3900 does not support 64 bit integer
1414 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1416 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1418 * configure : Rebuild.
1420 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1422 * configure: Regenerated to track ../common/aclocal.m4 changes.
1424 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1426 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1428 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1430 * configure: Regenerated to track ../common/aclocal.m4 changes.
1431 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1433 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1435 * configure: Regenerated to track ../common/aclocal.m4 changes.
1437 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1439 * interp.c (Max, Min): Comment out functions. Not yet used.
1441 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1443 * configure: Regenerated to track ../common/aclocal.m4 changes.
1445 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1447 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1448 configurable settings for stand-alone simulator.
1450 * configure.in: Added X11 search, just in case.
1452 * configure: Regenerated.
1454 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1456 * interp.c (sim_write, sim_read, load_memory, store_memory):
1457 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1459 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1461 * sim-main.h (GETFCC): Return an unsigned value.
1463 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1465 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1466 (DADD): Result destination is RD not RT.
1468 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1470 * sim-main.h (HIACCESS, LOACCESS): Always define.
1472 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1474 * interp.c (sim_info): Delete.
1476 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1478 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1479 (mips_option_handler): New argument `cpu'.
1480 (sim_open): Update call to sim_add_option_table.
1482 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1484 * mips.igen (CxC1): Add tracing.
1486 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1488 * sim-main.h (Max, Min): Declare.
1490 * interp.c (Max, Min): New functions.
1492 * mips.igen (BC1): Add tracing.
1494 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1496 * interp.c Added memory map for stack in vr4100
1498 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1500 * interp.c (load_memory): Add missing "break"'s.
1502 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1504 * interp.c (sim_store_register, sim_fetch_register): Pass in
1505 length parameter. Return -1.
1507 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1509 * interp.c: Added hardware init hook, fixed warnings.
1511 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1513 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1515 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1517 * interp.c (ifetch16): New function.
1519 * sim-main.h (IMEM32): Rename IMEM.
1520 (IMEM16_IMMED): Define.
1522 (DELAY_SLOT): Update.
1524 * m16run.c (sim_engine_run): New file.
1526 * m16.igen: All instructions except LB.
1527 (LB): Call do_load_byte.
1528 * mips.igen (do_load_byte): New function.
1529 (LB): Call do_load_byte.
1531 * mips.igen: Move spec for insn bit size and high bit from here.
1532 * Makefile.in (tmp-igen, tmp-m16): To here.
1534 * m16.dc: New file, decode mips16 instructions.
1536 * Makefile.in (SIM_NO_ALL): Define.
1537 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1539 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1541 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1542 point unit to 32 bit registers.
1543 * configure: Re-generate.
1545 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1547 * configure.in (sim_use_gen): Make IGEN the default simulator
1548 generator for generic 32 and 64 bit mips targets.
1549 * configure: Re-generate.
1551 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1553 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1556 * interp.c (sim_fetch_register, sim_store_register): Read/write
1557 FGR from correct location.
1558 (sim_open): Set size of FGR's according to
1559 WITH_TARGET_FLOATING_POINT_BITSIZE.
1561 * sim-main.h (FGR): Store floating point registers in a separate
1564 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1566 * configure: Regenerated to track ../common/aclocal.m4 changes.
1568 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1570 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1572 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1574 * interp.c (pending_tick): New function. Deliver pending writes.
1576 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1577 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1578 it can handle mixed sized quantites and single bits.
1580 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1582 * interp.c (oengine.h): Do not include when building with IGEN.
1583 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1584 (sim_info): Ditto for PROCESSOR_64BIT.
1585 (sim_monitor): Replace ut_reg with unsigned_word.
1586 (*): Ditto for t_reg.
1587 (LOADDRMASK): Define.
1588 (sim_open): Remove defunct check that host FP is IEEE compliant,
1589 using software to emulate floating point.
1590 (value_fpr, ...): Always compile, was conditional on HASFPU.
1592 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1594 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1597 * interp.c (SD, CPU): Define.
1598 (mips_option_handler): Set flags in each CPU.
1599 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1600 (sim_close): Do not clear STATE, deleted anyway.
1601 (sim_write, sim_read): Assume CPU zero's vm should be used for
1603 (sim_create_inferior): Set the PC for all processors.
1604 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1606 (mips16_entry): Pass correct nr of args to store_word, load_word.
1607 (ColdReset): Cold reset all cpu's.
1608 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1609 (sim_monitor, load_memory, store_memory, signal_exception): Use
1610 `CPU' instead of STATE_CPU.
1613 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1616 * sim-main.h (signal_exception): Add sim_cpu arg.
1617 (SignalException*): Pass both SD and CPU to signal_exception.
1618 * interp.c (signal_exception): Update.
1620 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1622 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1623 address_translation): Ditto
1624 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1626 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1628 * configure: Regenerated to track ../common/aclocal.m4 changes.
1630 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1632 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1634 * mips.igen (model): Map processor names onto BFD name.
1636 * sim-main.h (CPU_CIA): Delete.
1637 (SET_CIA, GET_CIA): Define
1639 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1641 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1644 * configure.in (default_endian): Configure a big-endian simulator
1646 * configure: Re-generate.
1648 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1650 * configure: Regenerated to track ../common/aclocal.m4 changes.
1652 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1654 * interp.c (sim_monitor): Handle Densan monitor outbyte
1655 and inbyte functions.
1657 1997-12-29 Felix Lee <flee@cygnus.com>
1659 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1661 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1663 * Makefile.in (tmp-igen): Arrange for $zero to always be
1664 reset to zero after every instruction.
1666 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1668 * configure: Regenerated to track ../common/aclocal.m4 changes.
1671 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1673 * mips.igen (MSUB): Fix to work like MADD.
1674 * gencode.c (MSUB): Similarly.
1676 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1678 * configure: Regenerated to track ../common/aclocal.m4 changes.
1680 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1682 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1684 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1686 * sim-main.h (sim-fpu.h): Include.
1688 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1689 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1690 using host independant sim_fpu module.
1692 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1694 * interp.c (signal_exception): Report internal errors with SIGABRT
1697 * sim-main.h (C0_CONFIG): New register.
1698 (signal.h): No longer include.
1700 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1702 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1704 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1706 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1708 * mips.igen: Tag vr5000 instructions.
1709 (ANDI): Was missing mipsIV model, fix assembler syntax.
1710 (do_c_cond_fmt): New function.
1711 (C.cond.fmt): Handle mips I-III which do not support CC field
1713 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1714 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1716 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1717 vr5000 which saves LO in a GPR separatly.
1719 * configure.in (enable-sim-igen): For vr5000, select vr5000
1720 specific instructions.
1721 * configure: Re-generate.
1723 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1725 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1727 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1728 fmt_uninterpreted_64 bit cases to switch. Convert to
1731 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1733 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1734 as specified in IV3.2 spec.
1735 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1737 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1739 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1740 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1741 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1742 PENDING_FILL versions of instructions. Simplify.
1744 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1746 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1748 (MTHI, MFHI): Disable code checking HI-LO.
1750 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1752 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1754 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1756 * gencode.c (build_mips16_operands): Replace IPC with cia.
1758 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1759 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1761 (UndefinedResult): Replace function with macro/function
1763 (sim_engine_run): Don't save PC in IPC.
1765 * sim-main.h (IPC): Delete.
1768 * interp.c (signal_exception, store_word, load_word,
1769 address_translation, load_memory, store_memory, cache_op,
1770 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1771 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1772 current instruction address - cia - argument.
1773 (sim_read, sim_write): Call address_translation directly.
1774 (sim_engine_run): Rename variable vaddr to cia.
1775 (signal_exception): Pass cia to sim_monitor
1777 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1778 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1779 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1781 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1782 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1785 * interp.c (signal_exception): Pass restart address to
1788 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1789 idecode.o): Add dependency.
1791 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1793 (DELAY_SLOT): Update NIA not PC with branch address.
1794 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1796 * mips.igen: Use CIA not PC in branch calculations.
1797 (illegal): Call SignalException.
1798 (BEQ, ADDIU): Fix assembler.
1800 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1802 * m16.igen (JALX): Was missing.
1804 * configure.in (enable-sim-igen): New configuration option.
1805 * configure: Re-generate.
1807 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1809 * interp.c (load_memory, store_memory): Delete parameter RAW.
1810 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1811 bypassing {load,store}_memory.
1813 * sim-main.h (ByteSwapMem): Delete definition.
1815 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1817 * interp.c (sim_do_command, sim_commands): Delete mips specific
1818 commands. Handled by module sim-options.
1820 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1821 (WITH_MODULO_MEMORY): Define.
1823 * interp.c (sim_info): Delete code printing memory size.
1825 * interp.c (mips_size): Nee sim_size, delete function.
1827 (monitor, monitor_base, monitor_size): Delete global variables.
1828 (sim_open, sim_close): Delete code creating monitor and other
1829 memory regions. Use sim-memopts module, via sim_do_commandf, to
1830 manage memory regions.
1831 (load_memory, store_memory): Use sim-core for memory model.
1833 * interp.c (address_translation): Delete all memory map code
1834 except line forcing 32 bit addresses.
1836 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1838 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1841 * interp.c (logfh, logfile): Delete globals.
1842 (sim_open, sim_close): Delete code opening & closing log file.
1843 (mips_option_handler): Delete -l and -n options.
1844 (OPTION mips_options): Ditto.
1846 * interp.c (OPTION mips_options): Rename option trace to dinero.
1847 (mips_option_handler): Update.
1849 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1851 * interp.c (fetch_str): New function.
1852 (sim_monitor): Rewrite using sim_read & sim_write.
1853 (sim_open): Check magic number.
1854 (sim_open): Write monitor vectors into memory using sim_write.
1855 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1856 (sim_read, sim_write): Simplify - transfer data one byte at a
1858 (load_memory, store_memory): Clarify meaning of parameter RAW.
1860 * sim-main.h (isHOST): Defete definition.
1861 (isTARGET): Mark as depreciated.
1862 (address_translation): Delete parameter HOST.
1864 * interp.c (address_translation): Delete parameter HOST.
1866 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1870 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1871 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1873 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1875 * mips.igen: Add model filter field to records.
1877 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1879 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1881 interp.c (sim_engine_run): Do not compile function sim_engine_run
1882 when WITH_IGEN == 1.
1884 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1885 target architecture.
1887 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1888 igen. Replace with configuration variables sim_igen_flags /
1891 * m16.igen: New file. Copy mips16 insns here.
1892 * mips.igen: From here.
1894 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1896 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1898 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1900 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1902 * gencode.c (build_instruction): Follow sim_write's lead in using
1903 BigEndianMem instead of !ByteSwapMem.
1905 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1907 * configure.in (sim_gen): Dependent on target, select type of
1908 generator. Always select old style generator.
1910 configure: Re-generate.
1912 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1914 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1915 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1916 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1917 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1918 SIM_@sim_gen@_*, set by autoconf.
1920 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1922 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1924 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1925 CURRENT_FLOATING_POINT instead.
1927 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1928 (address_translation): Raise exception InstructionFetch when
1929 translation fails and isINSTRUCTION.
1931 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1932 sim_engine_run): Change type of of vaddr and paddr to
1934 (address_translation, prefetch, load_memory, store_memory,
1935 cache_op): Change type of vAddr and pAddr to address_word.
1937 * gencode.c (build_instruction): Change type of vaddr and paddr to
1940 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1942 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1943 macro to obtain result of ALU op.
1945 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1947 * interp.c (sim_info): Call profile_print.
1949 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1951 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1953 * sim-main.h (WITH_PROFILE): Do not define, defined in
1954 common/sim-config.h. Use sim-profile module.
1955 (simPROFILE): Delete defintion.
1957 * interp.c (PROFILE): Delete definition.
1958 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1959 (sim_close): Delete code writing profile histogram.
1960 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1962 (sim_engine_run): Delete code profiling the PC.
1964 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1966 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1968 * interp.c (sim_monitor): Make register pointers of type
1971 * sim-main.h: Make registers of type unsigned_word not
1974 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1976 * interp.c (sync_operation): Rename from SyncOperation, make
1977 global, add SD argument.
1978 (prefetch): Rename from Prefetch, make global, add SD argument.
1979 (decode_coproc): Make global.
1981 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1983 * gencode.c (build_instruction): Generate DecodeCoproc not
1984 decode_coproc calls.
1986 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1987 (SizeFGR): Move to sim-main.h
1988 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1989 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1990 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1992 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1993 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1994 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1995 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1996 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1997 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1999 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2001 (sim-alu.h): Include.
2002 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2003 (sim_cia): Typedef to instruction_address.
2005 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2007 * Makefile.in (interp.o): Rename generated file engine.c to
2012 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2014 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2016 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2018 * gencode.c (build_instruction): For "FPSQRT", output correct
2019 number of arguments to Recip.
2021 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2023 * Makefile.in (interp.o): Depends on sim-main.h
2025 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2027 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2028 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2029 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2030 STATE, DSSTATE): Define
2031 (GPR, FGRIDX, ..): Define.
2033 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2034 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2035 (GPR, FGRIDX, ...): Delete macros.
2037 * interp.c: Update names to match defines from sim-main.h
2039 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2041 * interp.c (sim_monitor): Add SD argument.
2042 (sim_warning): Delete. Replace calls with calls to
2044 (sim_error): Delete. Replace calls with sim_io_error.
2045 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2046 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2047 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2049 (mips_size): Rename from sim_size. Add SD argument.
2051 * interp.c (simulator): Delete global variable.
2052 (callback): Delete global variable.
2053 (mips_option_handler, sim_open, sim_write, sim_read,
2054 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2055 sim_size,sim_monitor): Use sim_io_* not callback->*.
2056 (sim_open): ZALLOC simulator struct.
2057 (PROFILE): Do not define.
2059 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2061 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2062 support.h with corresponding code.
2064 * sim-main.h (word64, uword64), support.h: Move definition to
2066 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2069 * Makefile.in: Update dependencies
2070 * interp.c: Do not include.
2072 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2074 * interp.c (address_translation, load_memory, store_memory,
2075 cache_op): Rename to from AddressTranslation et.al., make global,
2078 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2081 * interp.c (SignalException): Rename to signal_exception, make
2084 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2086 * sim-main.h (SignalException, SignalExceptionInterrupt,
2087 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2088 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2089 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2092 * interp.c, support.h: Use.
2094 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2096 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2097 to value_fpr / store_fpr. Add SD argument.
2098 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2099 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2101 * sim-main.h (ValueFPR, StoreFPR): Define.
2103 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2105 * interp.c (sim_engine_run): Check consistency between configure
2106 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2109 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2110 (mips_fpu): Configure WITH_FLOATING_POINT.
2111 (mips_endian): Configure WITH_TARGET_ENDIAN.
2112 * configure: Update.
2114 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2116 * configure: Regenerated to track ../common/aclocal.m4 changes.
2118 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2120 * configure: Regenerated.
2122 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2124 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2126 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2128 * gencode.c (print_igen_insn_models): Assume certain architectures
2129 include all mips* instructions.
2130 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2133 * Makefile.in (tmp.igen): Add target. Generate igen input from
2136 * gencode.c (FEATURE_IGEN): Define.
2137 (main): Add --igen option. Generate output in igen format.
2138 (process_instructions): Format output according to igen option.
2139 (print_igen_insn_format): New function.
2140 (print_igen_insn_models): New function.
2141 (process_instructions): Only issue warnings and ignore
2142 instructions when no FEATURE_IGEN.
2144 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2146 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2149 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2151 * configure: Regenerated to track ../common/aclocal.m4 changes.
2153 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2155 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2156 SIM_RESERVED_BITS): Delete, moved to common.
2157 (SIM_EXTRA_CFLAGS): Update.
2159 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2161 * configure.in: Configure non-strict memory alignment.
2162 * configure: Regenerated to track ../common/aclocal.m4 changes.
2164 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2166 * configure: Regenerated to track ../common/aclocal.m4 changes.
2168 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2170 * gencode.c (SDBBP,DERET): Added (3900) insns.
2171 (RFE): Turn on for 3900.
2172 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2173 (dsstate): Made global.
2174 (SUBTARGET_R3900): Added.
2175 (CANCELDELAYSLOT): New.
2176 (SignalException): Ignore SystemCall rather than ignore and
2177 terminate. Add DebugBreakPoint handling.
2178 (decode_coproc): New insns RFE, DERET; and new registers Debug
2179 and DEPC protected by SUBTARGET_R3900.
2180 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2182 * Makefile.in,configure.in: Add mips subtarget option.
2183 * configure: Update.
2185 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2187 * gencode.c: Add r3900 (tx39).
2190 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2192 * gencode.c (build_instruction): Don't need to subtract 4 for
2195 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2197 * interp.c: Correct some HASFPU problems.
2199 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2201 * configure: Regenerated to track ../common/aclocal.m4 changes.
2203 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2205 * interp.c (mips_options): Fix samples option short form, should
2208 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2210 * interp.c (sim_info): Enable info code. Was just returning.
2212 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2214 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2217 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2219 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2221 (build_instruction): Ditto for LL.
2223 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2225 * configure: Regenerated to track ../common/aclocal.m4 changes.
2227 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2229 * configure: Regenerated to track ../common/aclocal.m4 changes.
2232 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2234 * interp.c (sim_open): Add call to sim_analyze_program, update
2237 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2239 * interp.c (sim_kill): Delete.
2240 (sim_create_inferior): Add ABFD argument. Set PC from same.
2241 (sim_load): Move code initializing trap handlers from here.
2242 (sim_open): To here.
2243 (sim_load): Delete, use sim-hload.c.
2245 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2247 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2249 * configure: Regenerated to track ../common/aclocal.m4 changes.
2252 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2254 * interp.c (sim_open): Add ABFD argument.
2255 (sim_load): Move call to sim_config from here.
2256 (sim_open): To here. Check return status.
2258 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2260 * gencode.c (build_instruction): Two arg MADD should
2261 not assign result to $0.
2263 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2265 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2266 * sim/mips/configure.in: Regenerate.
2268 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2270 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2271 signed8, unsigned8 et.al. types.
2273 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2274 hosts when selecting subreg.
2276 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2278 * interp.c (sim_engine_run): Reset the ZERO register to zero
2279 regardless of FEATURE_WARN_ZERO.
2280 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2282 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2284 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2285 (SignalException): For BreakPoints ignore any mode bits and just
2287 (SignalException): Always set the CAUSE register.
2289 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2291 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2292 exception has been taken.
2294 * interp.c: Implement the ERET and mt/f sr instructions.
2296 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2298 * interp.c (SignalException): Don't bother restarting an
2301 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2303 * interp.c (SignalException): Really take an interrupt.
2304 (interrupt_event): Only deliver interrupts when enabled.
2306 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2308 * interp.c (sim_info): Only print info when verbose.
2309 (sim_info) Use sim_io_printf for output.
2311 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2313 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2316 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2318 * interp.c (sim_do_command): Check for common commands if a
2319 simulator specific command fails.
2321 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2323 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2324 and simBE when DEBUG is defined.
2326 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2328 * interp.c (interrupt_event): New function. Pass exception event
2329 onto exception handler.
2331 * configure.in: Check for stdlib.h.
2332 * configure: Regenerate.
2334 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2335 variable declaration.
2336 (build_instruction): Initialize memval1.
2337 (build_instruction): Add UNUSED attribute to byte, bigend,
2339 (build_operands): Ditto.
2341 * interp.c: Fix GCC warnings.
2342 (sim_get_quit_code): Delete.
2344 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2345 * Makefile.in: Ditto.
2346 * configure: Re-generate.
2348 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2350 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2352 * interp.c (mips_option_handler): New function parse argumes using
2354 (myname): Replace with STATE_MY_NAME.
2355 (sim_open): Delete check for host endianness - performed by
2357 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2358 (sim_open): Move much of the initialization from here.
2359 (sim_load): To here. After the image has been loaded and
2361 (sim_open): Move ColdReset from here.
2362 (sim_create_inferior): To here.
2363 (sim_open): Make FP check less dependant on host endianness.
2365 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2367 * interp.c (sim_set_callbacks): Delete.
2369 * interp.c (membank, membank_base, membank_size): Replace with
2370 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2371 (sim_open): Remove call to callback->init. gdb/run do this.
2375 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2377 * interp.c (big_endian_p): Delete, replaced by
2378 current_target_byte_order.
2380 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2382 * interp.c (host_read_long, host_read_word, host_swap_word,
2383 host_swap_long): Delete. Using common sim-endian.
2384 (sim_fetch_register, sim_store_register): Use H2T.
2385 (pipeline_ticks): Delete. Handled by sim-events.
2387 (sim_engine_run): Update.
2389 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2391 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2393 (SignalException): To here. Signal using sim_engine_halt.
2394 (sim_stop_reason): Delete, moved to common.
2396 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2398 * interp.c (sim_open): Add callback argument.
2399 (sim_set_callbacks): Delete SIM_DESC argument.
2402 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2404 * Makefile.in (SIM_OBJS): Add common modules.
2406 * interp.c (sim_set_callbacks): Also set SD callback.
2407 (set_endianness, xfer_*, swap_*): Delete.
2408 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2409 Change to functions using sim-endian macros.
2410 (control_c, sim_stop): Delete, use common version.
2411 (simulate): Convert into.
2412 (sim_engine_run): This function.
2413 (sim_resume): Delete.
2415 * interp.c (simulation): New variable - the simulator object.
2416 (sim_kind): Delete global - merged into simulation.
2417 (sim_load): Cleanup. Move PC assignment from here.
2418 (sim_create_inferior): To here.
2420 * sim-main.h: New file.
2421 * interp.c (sim-main.h): Include.
2423 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2425 * configure: Regenerated to track ../common/aclocal.m4 changes.
2427 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2429 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2431 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2433 * gencode.c (build_instruction): DIV instructions: check
2434 for division by zero and integer overflow before using
2435 host's division operation.
2437 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2439 * Makefile.in (SIM_OBJS): Add sim-load.o.
2440 * interp.c: #include bfd.h.
2441 (target_byte_order): Delete.
2442 (sim_kind, myname, big_endian_p): New static locals.
2443 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2444 after argument parsing. Recognize -E arg, set endianness accordingly.
2445 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2446 load file into simulator. Set PC from bfd.
2447 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2448 (set_endianness): Use big_endian_p instead of target_byte_order.
2450 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2452 * interp.c (sim_size): Delete prototype - conflicts with
2453 definition in remote-sim.h. Correct definition.
2455 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2457 * configure: Regenerated to track ../common/aclocal.m4 changes.
2460 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2462 * interp.c (sim_open): New arg `kind'.
2464 * configure: Regenerated to track ../common/aclocal.m4 changes.
2466 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2468 * configure: Regenerated to track ../common/aclocal.m4 changes.
2470 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2472 * interp.c (sim_open): Set optind to 0 before calling getopt.
2474 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2476 * configure: Regenerated to track ../common/aclocal.m4 changes.
2478 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2480 * interp.c : Replace uses of pr_addr with pr_uword64
2481 where the bit length is always 64 independent of SIM_ADDR.
2482 (pr_uword64) : added.
2484 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2486 * configure: Re-generate.
2488 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2490 * configure: Regenerate to track ../common/aclocal.m4 changes.
2492 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2494 * interp.c (sim_open): New SIM_DESC result. Argument is now
2496 (other sim_*): New SIM_DESC argument.
2498 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2500 * interp.c: Fix printing of addresses for non-64-bit targets.
2501 (pr_addr): Add function to print address based on size.
2503 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2505 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2507 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2509 * gencode.c (build_mips16_operands): Correct computation of base
2510 address for extended PC relative instruction.
2512 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2514 * interp.c (mips16_entry): Add support for floating point cases.
2515 (SignalException): Pass floating point cases to mips16_entry.
2516 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2518 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2520 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2521 and then set the state to fmt_uninterpreted.
2522 (COP_SW): Temporarily set the state to fmt_word while calling
2525 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2527 * gencode.c (build_instruction): The high order may be set in the
2528 comparison flags at any ISA level, not just ISA 4.
2530 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2532 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2533 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2534 * configure.in: sinclude ../common/aclocal.m4.
2535 * configure: Regenerated.
2537 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2539 * configure: Rebuild after change to aclocal.m4.
2541 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2543 * configure configure.in Makefile.in: Update to new configure
2544 scheme which is more compatible with WinGDB builds.
2545 * configure.in: Improve comment on how to run autoconf.
2546 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2547 * Makefile.in: Use autoconf substitution to install common
2550 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2552 * gencode.c (build_instruction): Use BigEndianCPU instead of
2555 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2557 * interp.c (sim_monitor): Make output to stdout visible in
2558 wingdb's I/O log window.
2560 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2562 * support.h: Undo previous change to SIGTRAP
2565 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2567 * interp.c (store_word, load_word): New static functions.
2568 (mips16_entry): New static function.
2569 (SignalException): Look for mips16 entry and exit instructions.
2570 (simulate): Use the correct index when setting fpr_state after
2571 doing a pending move.
2573 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2575 * interp.c: Fix byte-swapping code throughout to work on
2576 both little- and big-endian hosts.
2578 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2580 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2581 with gdb/config/i386/xm-windows.h.
2583 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2585 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2586 that messes up arithmetic shifts.
2588 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2590 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2591 SIGTRAP and SIGQUIT for _WIN32.
2593 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2595 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2596 force a 64 bit multiplication.
2597 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2598 destination register is 0, since that is the default mips16 nop
2601 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2603 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2604 (build_endian_shift): Don't check proc64.
2605 (build_instruction): Always set memval to uword64. Cast op2 to
2606 uword64 when shifting it left in memory instructions. Always use
2607 the same code for stores--don't special case proc64.
2609 * gencode.c (build_mips16_operands): Fix base PC value for PC
2611 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2613 * interp.c (simJALDELAYSLOT): Define.
2614 (JALDELAYSLOT): Define.
2615 (INDELAYSLOT, INJALDELAYSLOT): Define.
2616 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2618 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2620 * interp.c (sim_open): add flush_cache as a PMON routine
2621 (sim_monitor): handle flush_cache by ignoring it
2623 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2625 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2627 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2628 (BigEndianMem): Rename to ByteSwapMem and change sense.
2629 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2630 BigEndianMem references to !ByteSwapMem.
2631 (set_endianness): New function, with prototype.
2632 (sim_open): Call set_endianness.
2633 (sim_info): Use simBE instead of BigEndianMem.
2634 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2635 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2636 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2637 ifdefs, keeping the prototype declaration.
2638 (swap_word): Rewrite correctly.
2639 (ColdReset): Delete references to CONFIG. Delete endianness related
2640 code; moved to set_endianness.
2642 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2644 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2645 * interp.c (CHECKHILO): Define away.
2646 (simSIGINT): New macro.
2647 (membank_size): Increase from 1MB to 2MB.
2648 (control_c): New function.
2649 (sim_resume): Rename parameter signal to signal_number. Add local
2650 variable prev. Call signal before and after simulate.
2651 (sim_stop_reason): Add simSIGINT support.
2652 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2654 (sim_warning): Delete call to SignalException. Do call printf_filtered
2656 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2657 a call to sim_warning.
2659 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2661 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2662 16 bit instructions.
2664 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2666 Add support for mips16 (16 bit MIPS implementation):
2667 * gencode.c (inst_type): Add mips16 instruction encoding types.
2668 (GETDATASIZEINSN): Define.
2669 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2670 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2672 (MIPS16_DECODE): New table, for mips16 instructions.
2673 (bitmap_val): New static function.
2674 (struct mips16_op): Define.
2675 (mips16_op_table): New table, for mips16 operands.
2676 (build_mips16_operands): New static function.
2677 (process_instructions): If PC is odd, decode a mips16
2678 instruction. Break out instruction handling into new
2679 build_instruction function.
2680 (build_instruction): New static function, broken out of
2681 process_instructions. Check modifiers rather than flags for SHIFT
2682 bit count and m[ft]{hi,lo} direction.
2683 (usage): Pass program name to fprintf.
2684 (main): Remove unused variable this_option_optind. Change
2685 ``*loptarg++'' to ``loptarg++''.
2686 (my_strtoul): Parenthesize && within ||.
2687 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2688 (simulate): If PC is odd, fetch a 16 bit instruction, and
2689 increment PC by 2 rather than 4.
2690 * configure.in: Add case for mips16*-*-*.
2691 * configure: Rebuild.
2693 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2695 * interp.c: Allow -t to enable tracing in standalone simulator.
2696 Fix garbage output in trace file and error messages.
2698 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2700 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2701 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2702 * configure.in: Simplify using macros in ../common/aclocal.m4.
2703 * configure: Regenerated.
2704 * tconfig.in: New file.
2706 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2708 * interp.c: Fix bugs in 64-bit port.
2709 Use ansi function declarations for msvc compiler.
2710 Initialize and test file pointer in trace code.
2711 Prevent duplicate definition of LAST_EMED_REGNUM.
2713 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2715 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2717 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2719 * interp.c (SignalException): Check for explicit terminating
2721 * gencode.c: Pass instruction value through SignalException()
2722 calls for Trap, Breakpoint and Syscall.
2724 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2726 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2727 only used on those hosts that provide it.
2728 * configure.in: Add sqrt() to list of functions to be checked for.
2729 * config.in: Re-generated.
2730 * configure: Re-generated.
2732 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2734 * gencode.c (process_instructions): Call build_endian_shift when
2735 expanding STORE RIGHT, to fix swr.
2736 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2737 clear the high bits.
2738 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2739 Fix float to int conversions to produce signed values.
2741 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2743 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2744 (process_instructions): Correct handling of nor instruction.
2745 Correct shift count for 32 bit shift instructions. Correct sign
2746 extension for arithmetic shifts to not shift the number of bits in
2747 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2748 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2750 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2751 It's OK to have a mult follow a mult. What's not OK is to have a
2752 mult follow an mfhi.
2753 (Convert): Comment out incorrect rounding code.
2755 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2757 * interp.c (sim_monitor): Improved monitor printf
2758 simulation. Tidied up simulator warnings, and added "--log" option
2759 for directing warning message output.
2760 * gencode.c: Use sim_warning() rather than WARNING macro.
2762 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2764 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2765 getopt1.o, rather than on gencode.c. Link objects together.
2766 Don't link against -liberty.
2767 (gencode.o, getopt.o, getopt1.o): New targets.
2768 * gencode.c: Include <ctype.h> and "ansidecl.h".
2769 (AND): Undefine after including "ansidecl.h".
2770 (ULONG_MAX): Define if not defined.
2771 (OP_*): Don't define macros; now defined in opcode/mips.h.
2772 (main): Call my_strtoul rather than strtoul.
2773 (my_strtoul): New static function.
2775 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2777 * gencode.c (process_instructions): Generate word64 and uword64
2778 instead of `long long' and `unsigned long long' data types.
2779 * interp.c: #include sysdep.h to get signals, and define default
2781 * (Convert): Work around for Visual-C++ compiler bug with type
2783 * support.h: Make things compile under Visual-C++ by using
2784 __int64 instead of `long long'. Change many refs to long long
2785 into word64/uword64 typedefs.
2787 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2789 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2790 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2792 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2793 (AC_PROG_INSTALL): Added.
2794 (AC_PROG_CC): Moved to before configure.host call.
2795 * configure: Rebuilt.
2797 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2799 * configure.in: Define @SIMCONF@ depending on mips target.
2800 * configure: Rebuild.
2801 * Makefile.in (run): Add @SIMCONF@ to control simulator
2803 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2804 * interp.c: Remove some debugging, provide more detailed error
2805 messages, update memory accesses to use LOADDRMASK.
2807 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2809 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2810 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2812 * configure: Rebuild.
2813 * config.in: New file, generated by autoheader.
2814 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2815 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2816 HAVE_ANINT and HAVE_AINT, as appropriate.
2817 * Makefile.in (run): Use @LIBS@ rather than -lm.
2818 (interp.o): Depend upon config.h.
2819 (Makefile): Just rebuild Makefile.
2820 (clean): Remove stamp-h.
2821 (mostlyclean): Make the same as clean, not as distclean.
2822 (config.h, stamp-h): New targets.
2824 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2826 * interp.c (ColdReset): Fix boolean test. Make all simulator
2829 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2831 * interp.c (xfer_direct_word, xfer_direct_long,
2832 swap_direct_word, swap_direct_long, xfer_big_word,
2833 xfer_big_long, xfer_little_word, xfer_little_long,
2834 swap_word,swap_long): Added.
2835 * interp.c (ColdReset): Provide function indirection to
2836 host<->simulated_target transfer routines.
2837 * interp.c (sim_store_register, sim_fetch_register): Updated to
2838 make use of indirected transfer routines.
2840 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2842 * gencode.c (process_instructions): Ensure FP ABS instruction
2844 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2845 system call support.
2847 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2849 * interp.c (sim_do_command): Complain if callback structure not
2852 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2854 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2855 support for Sun hosts.
2856 * Makefile.in (gencode): Ensure the host compiler and libraries
2857 used for cross-hosted build.
2859 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2861 * interp.c, gencode.c: Some more (TODO) tidying.
2863 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2865 * gencode.c, interp.c: Replaced explicit long long references with
2866 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2867 * support.h (SET64LO, SET64HI): Macros added.
2869 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2871 * configure: Regenerate with autoconf 2.7.
2873 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2875 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2876 * support.h: Remove superfluous "1" from #if.
2877 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2879 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2881 * interp.c (StoreFPR): Control UndefinedResult() call on
2882 WARN_RESULT manifest.
2884 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2886 * gencode.c: Tidied instruction decoding, and added FP instruction
2889 * interp.c: Added dineroIII, and BSD profiling support. Also
2890 run-time FP handling.
2892 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2894 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2895 gencode.c, interp.c, support.h: created.