1 2012-03-24 Mike Frysinger <vapier@gentoo.org>
3 * aclocal.m4, config.in, configure: Regenerate.
5 2011-12-03 Mike Frysinger <vapier@gentoo.org>
7 * aclocal.m4: New file.
8 * configure: Regenerate.
10 2011-10-19 Mike Frysinger <vapier@gentoo.org>
12 * configure: Regenerate after common/acinclude.m4 update.
14 2011-10-17 Mike Frysinger <vapier@gentoo.org>
16 * configure.ac: Change include to common/acinclude.m4.
18 2011-10-17 Mike Frysinger <vapier@gentoo.org>
20 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
21 call. Replace common.m4 include with SIM_AC_COMMON.
22 * configure: Regenerate.
24 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
26 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
28 (tmp-mach-multi): Exit early when igen fails.
30 2011-07-05 Mike Frysinger <vapier@gentoo.org>
32 * interp.c (sim_do_command): Delete.
34 2011-02-14 Mike Frysinger <vapier@gentoo.org>
36 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
37 (tx3904sio_fifo_reset): Likewise.
38 * interp.c (sim_monitor): Likewise.
40 2010-04-14 Mike Frysinger <vapier@gentoo.org>
42 * interp.c (sim_write): Add const to buffer arg.
44 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
46 * interp.c: Don't include sysdep.h
48 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
50 * configure: Regenerate.
52 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
54 * config.in: Regenerate.
55 * configure: Likewise.
57 * configure: Regenerate.
59 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
61 * configure: Regenerate to track ../common/common.m4 changes.
64 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
65 Daniel Jacobowitz <dan@codesourcery.com>
66 Joseph Myers <joseph@codesourcery.com>
68 * configure: Regenerate.
70 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
72 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
73 that unconditionally allows fmt_ps.
74 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
75 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
76 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
77 filter from 64,f to 32,f.
78 (PREFX): Change filter from 64 to 32.
79 (LDXC1, LUXC1): Provide separate mips32r2 implementations
80 that use do_load_double instead of do_load. Make both LUXC1
81 versions unpredictable if SizeFGR () != 64.
82 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
83 instead of do_store. Remove unused variable. Make both SUXC1
84 versions unpredictable if SizeFGR () != 64.
86 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
88 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
89 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
92 2007-09-04 Nick Clifton <nickc@redhat.com>
94 * interp.c (options enum): Add OPTION_INFO_MEMORY.
95 (display_mem_info): New static variable.
96 (mips_option_handler): Handle OPTION_INFO_MEMORY.
97 (mips_options): Add info-memory and memory-info.
98 (sim_open): After processing the command line and board
99 specification, check display_mem_info. If it is set then
100 call the real handler for the --memory-info command line
103 2007-08-24 Joel Brobecker <brobecker@adacore.com>
105 * configure.ac: Change license of multi-run.c to GPL version 3.
106 * configure: Regenerate.
108 2007-06-28 Richard Sandiford <richard@codesourcery.com>
110 * configure.ac, configure: Revert last patch.
112 2007-06-26 Richard Sandiford <richard@codesourcery.com>
114 * configure.ac (sim_mipsisa3264_configs): New variable.
115 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
116 every configuration support all four targets, using the triplet to
117 determine the default.
118 * configure: Regenerate.
120 2007-06-25 Richard Sandiford <richard@codesourcery.com>
122 * Makefile.in (m16run.o): New rule.
124 2007-05-15 Thiemo Seufer <ths@mips.com>
126 * mips3264r2.igen (DSHD): Fix compile warning.
128 2007-05-14 Thiemo Seufer <ths@mips.com>
130 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
131 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
132 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
133 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
136 2007-03-01 Thiemo Seufer <ths@mips.com>
138 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
141 2007-02-20 Thiemo Seufer <ths@mips.com>
143 * dsp.igen: Update copyright notice.
144 * dsp2.igen: Fix copyright notice.
146 2007-02-20 Thiemo Seufer <ths@mips.com>
147 Chao-Ying Fu <fu@mips.com>
149 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
150 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
151 Add dsp2 to sim_igen_machine.
152 * configure: Regenerate.
153 * dsp.igen (do_ph_op): Add MUL support when op = 2.
154 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
155 (mulq_rs.ph): Use do_ph_mulq.
156 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
157 * mips.igen: Add dsp2 model and include dsp2.igen.
158 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
159 for *mips32r2, *mips64r2, *dsp.
160 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
161 for *mips32r2, *mips64r2, *dsp2.
162 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
164 2007-02-19 Thiemo Seufer <ths@mips.com>
165 Nigel Stephens <nigel@mips.com>
167 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
168 jumps with hazard barrier.
170 2007-02-19 Thiemo Seufer <ths@mips.com>
171 Nigel Stephens <nigel@mips.com>
173 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
174 after each call to sim_io_write.
176 2007-02-19 Thiemo Seufer <ths@mips.com>
177 Nigel Stephens <nigel@mips.com>
179 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
180 supported by this simulator.
181 (decode_coproc): Recognise additional CP0 Config registers
184 2007-02-19 Thiemo Seufer <ths@mips.com>
185 Nigel Stephens <nigel@mips.com>
186 David Ung <davidu@mips.com>
188 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
189 uninterpreted formats. If fmt is one of the uninterpreted types
190 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
191 fmt_word, and fmt_uninterpreted_64 like fmt_long.
192 (store_fpr): When writing an invalid odd register, set the
193 matching even register to fmt_unknown, not the following register.
194 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
195 the the memory window at offset 0 set by --memory-size command
197 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
199 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
201 (sim_monitor): When returning the memory size to the MIPS
202 application, use the value in STATE_MEM_SIZE, not an arbitrary
204 (cop_lw): Don' mess around with FPR_STATE, just pass
205 fmt_uninterpreted_32 to StoreFPR.
207 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
209 * mips.igen (not_word_value): Single version for mips32, mips64
212 2007-02-19 Thiemo Seufer <ths@mips.com>
213 Nigel Stephens <nigel@mips.com>
215 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
218 2007-02-17 Thiemo Seufer <ths@mips.com>
220 * configure.ac (mips*-sde-elf*): Move in front of generic machine
222 * configure: Regenerate.
224 2007-02-17 Thiemo Seufer <ths@mips.com>
226 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
227 Add mdmx to sim_igen_machine.
228 (mipsisa64*-*-*): Likewise. Remove dsp.
229 (mipsisa32*-*-*): Remove dsp.
230 * configure: Regenerate.
232 2007-02-13 Thiemo Seufer <ths@mips.com>
234 * configure.ac: Add mips*-sde-elf* target.
235 * configure: Regenerate.
237 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
239 * acconfig.h: Remove.
240 * config.in, configure: Regenerate.
242 2006-11-07 Thiemo Seufer <ths@mips.com>
244 * dsp.igen (do_w_op): Fix compiler warning.
246 2006-08-29 Thiemo Seufer <ths@mips.com>
247 David Ung <davidu@mips.com>
249 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
251 * configure: Regenerate.
252 * mips.igen (model): Add smartmips.
253 (MADDU): Increment ACX if carry.
254 (do_mult): Clear ACX.
255 (ROR,RORV): Add smartmips.
256 (include): Include smartmips.igen.
257 * sim-main.h (ACX): Set to REGISTERS[89].
258 * smartmips.igen: New file.
260 2006-08-29 Thiemo Seufer <ths@mips.com>
261 David Ung <davidu@mips.com>
263 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
264 mips3264r2.igen. Add missing dependency rules.
265 * m16e.igen: Support for mips16e save/restore instructions.
267 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
269 * configure: Regenerated.
271 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
273 * configure: Regenerated.
275 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
277 * configure: Regenerated.
279 2006-05-15 Chao-ying Fu <fu@mips.com>
281 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
283 2006-04-18 Nick Clifton <nickc@redhat.com>
285 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
288 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
290 * configure: Regenerate.
292 2005-12-14 Chao-ying Fu <fu@mips.com>
294 * Makefile.in (SIM_OBJS): Add dsp.o.
295 (dsp.o): New dependency.
296 (IGEN_INCLUDE): Add dsp.igen.
297 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
298 mipsisa64*-*-*): Add dsp to sim_igen_machine.
299 * configure: Regenerate.
300 * mips.igen: Add dsp model and include dsp.igen.
301 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
302 because these instructions are extended in DSP ASE.
303 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
304 adding 6 DSP accumulator registers and 1 DSP control register.
305 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
306 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
307 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
308 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
309 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
310 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
311 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
312 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
313 DSPCR_CCOND_SMASK): New define.
314 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
315 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
317 2005-07-08 Ian Lance Taylor <ian@airs.com>
319 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
321 2005-06-16 David Ung <davidu@mips.com>
322 Nigel Stephens <nigel@mips.com>
324 * mips.igen: New mips16e model and include m16e.igen.
325 (check_u64): Add mips16e tag.
326 * m16e.igen: New file for MIPS16e instructions.
327 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
328 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
330 * configure: Regenerate.
332 2005-05-26 David Ung <davidu@mips.com>
334 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
335 tags to all instructions which are applicable to the new ISAs.
336 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
338 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
340 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
342 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
343 * configure: Regenerate.
345 2005-03-23 Mark Kettenis <kettenis@gnu.org>
347 * configure: Regenerate.
349 2005-01-14 Andrew Cagney <cagney@gnu.org>
351 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
352 explicit call to AC_CONFIG_HEADER.
353 * configure: Regenerate.
355 2005-01-12 Andrew Cagney <cagney@gnu.org>
357 * configure.ac: Update to use ../common/common.m4.
358 * configure: Re-generate.
360 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
362 * configure: Regenerated to track ../common/aclocal.m4 changes.
364 2005-01-07 Andrew Cagney <cagney@gnu.org>
366 * configure.ac: Rename configure.in, require autoconf 2.59.
367 * configure: Re-generate.
369 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
371 * configure: Regenerate for ../common/aclocal.m4 update.
373 2004-09-24 Monika Chaddha <monika@acmet.com>
375 Committed by Andrew Cagney.
376 * m16.igen (CMP, CMPI): Fix assembler.
378 2004-08-18 Chris Demetriou <cgd@broadcom.com>
380 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
381 * configure: Regenerate.
383 2004-06-25 Chris Demetriou <cgd@broadcom.com>
385 * configure.in (sim_m16_machine): Include mipsIII.
386 * configure: Regenerate.
388 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
390 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
392 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
394 2004-04-10 Chris Demetriou <cgd@broadcom.com>
396 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
398 2004-04-09 Chris Demetriou <cgd@broadcom.com>
400 * mips.igen (check_fmt): Remove.
401 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
402 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
403 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
404 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
405 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
406 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
407 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
408 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
409 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
410 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
412 2004-04-09 Chris Demetriou <cgd@broadcom.com>
414 * sb1.igen (check_sbx): New function.
415 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
417 2004-03-29 Chris Demetriou <cgd@broadcom.com>
418 Richard Sandiford <rsandifo@redhat.com>
420 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
421 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
422 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
423 separate implementations for mipsIV and mipsV. Use new macros to
424 determine whether the restrictions apply.
426 2004-01-19 Chris Demetriou <cgd@broadcom.com>
428 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
429 (check_mult_hilo): Improve comments.
430 (check_div_hilo): Likewise. Also, fork off a new version
431 to handle mips32/mips64 (since there are no hazards to check
434 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
436 * mips.igen (do_dmultx): Fix check for negative operands.
438 2003-05-16 Ian Lance Taylor <ian@airs.com>
440 * Makefile.in (SHELL): Make sure this is defined.
441 (various): Use $(SHELL) whenever we invoke move-if-change.
443 2003-05-03 Chris Demetriou <cgd@broadcom.com>
445 * cp1.c: Tweak attribution slightly.
448 * mdmx.igen: Likewise.
449 * mips3d.igen: Likewise.
450 * sb1.igen: Likewise.
452 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
454 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
457 2003-02-27 Andrew Cagney <cagney@redhat.com>
459 * interp.c (sim_open): Rename _bfd to bfd.
460 (sim_create_inferior): Ditto.
462 2003-01-14 Chris Demetriou <cgd@broadcom.com>
464 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
466 2003-01-14 Chris Demetriou <cgd@broadcom.com>
468 * mips.igen (EI, DI): Remove.
470 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
472 * Makefile.in (tmp-run-multi): Fix mips16 filter.
474 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
475 Andrew Cagney <ac131313@redhat.com>
476 Gavin Romig-Koch <gavin@redhat.com>
477 Graydon Hoare <graydon@redhat.com>
478 Aldy Hernandez <aldyh@redhat.com>
479 Dave Brolley <brolley@redhat.com>
480 Chris Demetriou <cgd@broadcom.com>
482 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
483 (sim_mach_default): New variable.
484 (mips64vr-*-*, mips64vrel-*-*): New configurations.
485 Add a new simulator generator, MULTI.
486 * configure: Regenerate.
487 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
488 (multi-run.o): New dependency.
489 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
490 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
491 (tmp-multi): Combine them.
492 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
493 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
494 (distclean-extra): New rule.
495 * sim-main.h: Include bfd.h.
496 (MIPS_MACH): New macro.
497 * mips.igen (vr4120, vr5400, vr5500): New models.
498 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
499 * vr.igen: Replace with new version.
501 2003-01-04 Chris Demetriou <cgd@broadcom.com>
503 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
504 * configure: Regenerate.
506 2002-12-31 Chris Demetriou <cgd@broadcom.com>
508 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
509 * mips.igen: Remove all invocations of check_branch_bug and
512 2002-12-16 Chris Demetriou <cgd@broadcom.com>
514 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
516 2002-07-30 Chris Demetriou <cgd@broadcom.com>
518 * mips.igen (do_load_double, do_store_double): New functions.
519 (LDC1, SDC1): Rename to...
520 (LDC1b, SDC1b): respectively.
521 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
523 2002-07-29 Michael Snyder <msnyder@redhat.com>
525 * cp1.c (fp_recip2): Modify initialization expression so that
526 GCC will recognize it as constant.
528 2002-06-18 Chris Demetriou <cgd@broadcom.com>
530 * mdmx.c (SD_): Delete.
531 (Unpredictable): Re-define, for now, to directly invoke
532 unpredictable_action().
533 (mdmx_acc_op): Fix error in .ob immediate handling.
535 2002-06-18 Andrew Cagney <cagney@redhat.com>
537 * interp.c (sim_firmware_command): Initialize `address'.
539 2002-06-16 Andrew Cagney <ac131313@redhat.com>
541 * configure: Regenerated to track ../common/aclocal.m4 changes.
543 2002-06-14 Chris Demetriou <cgd@broadcom.com>
544 Ed Satterthwaite <ehs@broadcom.com>
546 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
547 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
548 * mips.igen: Include mips3d.igen.
549 (mips3d): New model name for MIPS-3D ASE instructions.
550 (CVT.W.fmt): Don't use this instruction for word (source) format
552 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
553 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
554 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
555 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
556 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
557 (RSquareRoot1, RSquareRoot2): New macros.
558 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
559 (fp_rsqrt2): New functions.
560 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
561 * configure: Regenerate.
563 2002-06-13 Chris Demetriou <cgd@broadcom.com>
564 Ed Satterthwaite <ehs@broadcom.com>
566 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
567 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
568 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
569 (convert): Note that this function is not used for paired-single
571 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
572 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
573 (check_fmt_p): Enable paired-single support.
574 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
575 (PUU.PS): New instructions.
576 (CVT.S.fmt): Don't use this instruction for paired-single format
578 * sim-main.h (FP_formats): New value 'fmt_ps.'
579 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
580 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
582 2002-06-12 Chris Demetriou <cgd@broadcom.com>
584 * mips.igen: Fix formatting of function calls in
587 2002-06-12 Chris Demetriou <cgd@broadcom.com>
589 * mips.igen (MOVN, MOVZ): Trace result.
590 (TNEI): Print "tnei" as the opcode name in traces.
591 (CEIL.W): Add disassembly string for traces.
592 (RSQRT.fmt): Make location of disassembly string consistent
593 with other instructions.
595 2002-06-12 Chris Demetriou <cgd@broadcom.com>
597 * mips.igen (X): Delete unused function.
599 2002-06-08 Andrew Cagney <cagney@redhat.com>
601 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
603 2002-06-07 Chris Demetriou <cgd@broadcom.com>
604 Ed Satterthwaite <ehs@broadcom.com>
606 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
607 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
608 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
609 (fp_nmsub): New prototypes.
610 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
611 (NegMultiplySub): New defines.
612 * mips.igen (RSQRT.fmt): Use RSquareRoot().
613 (MADD.D, MADD.S): Replace with...
614 (MADD.fmt): New instruction.
615 (MSUB.D, MSUB.S): Replace with...
616 (MSUB.fmt): New instruction.
617 (NMADD.D, NMADD.S): Replace with...
618 (NMADD.fmt): New instruction.
619 (NMSUB.D, MSUB.S): Replace with...
620 (NMSUB.fmt): New instruction.
622 2002-06-07 Chris Demetriou <cgd@broadcom.com>
623 Ed Satterthwaite <ehs@broadcom.com>
625 * cp1.c: Fix more comment spelling and formatting.
626 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
627 (denorm_mode): New function.
628 (fpu_unary, fpu_binary): Round results after operation, collect
629 status from rounding operations, and update the FCSR.
630 (convert): Collect status from integer conversions and rounding
631 operations, and update the FCSR. Adjust NaN values that result
632 from conversions. Convert to use sim_io_eprintf rather than
633 fprintf, and remove some debugging code.
634 * cp1.h (fenr_FS): New define.
636 2002-06-07 Chris Demetriou <cgd@broadcom.com>
638 * cp1.c (convert): Remove unusable debugging code, and move MIPS
639 rounding mode to sim FP rounding mode flag conversion code into...
640 (rounding_mode): New function.
642 2002-06-07 Chris Demetriou <cgd@broadcom.com>
644 * cp1.c: Clean up formatting of a few comments.
645 (value_fpr): Reformat switch statement.
647 2002-06-06 Chris Demetriou <cgd@broadcom.com>
648 Ed Satterthwaite <ehs@broadcom.com>
651 * sim-main.h: Include cp1.h.
652 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
653 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
654 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
655 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
656 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
657 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
658 * cp1.c: Don't include sim-fpu.h; already included by
659 sim-main.h. Clean up formatting of some comments.
660 (NaN, Equal, Less): Remove.
661 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
662 (fp_cmp): New functions.
663 * mips.igen (do_c_cond_fmt): Remove.
664 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
665 Compare. Add result tracing.
666 (CxC1): Remove, replace with...
667 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
668 (DMxC1): Remove, replace with...
669 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
670 (MxC1): Remove, replace with...
671 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
673 2002-06-04 Chris Demetriou <cgd@broadcom.com>
675 * sim-main.h (FGRIDX): Remove, replace all uses with...
676 (FGR_BASE): New macro.
677 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
678 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
679 (NR_FGR, FGR): Likewise.
680 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
681 * mips.igen: Likewise.
683 2002-06-04 Chris Demetriou <cgd@broadcom.com>
685 * cp1.c: Add an FSF Copyright notice to this file.
687 2002-06-04 Chris Demetriou <cgd@broadcom.com>
688 Ed Satterthwaite <ehs@broadcom.com>
690 * cp1.c (Infinity): Remove.
691 * sim-main.h (Infinity): Likewise.
693 * cp1.c (fp_unary, fp_binary): New functions.
694 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
695 (fp_sqrt): New functions, implemented in terms of the above.
696 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
697 (Recip, SquareRoot): Remove (replaced by functions above).
698 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
699 (fp_recip, fp_sqrt): New prototypes.
700 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
701 (Recip, SquareRoot): Replace prototypes with #defines which
702 invoke the functions above.
704 2002-06-03 Chris Demetriou <cgd@broadcom.com>
706 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
707 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
708 file, remove PARAMS from prototypes.
709 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
710 simulator state arguments.
711 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
712 pass simulator state arguments.
713 * cp1.c (SD): Redefine as CPU_STATE(cpu).
714 (store_fpr, convert): Remove 'sd' argument.
715 (value_fpr): Likewise. Convert to use 'SD' instead.
717 2002-06-03 Chris Demetriou <cgd@broadcom.com>
719 * cp1.c (Min, Max): Remove #if 0'd functions.
720 * sim-main.h (Min, Max): Remove.
722 2002-06-03 Chris Demetriou <cgd@broadcom.com>
724 * cp1.c: fix formatting of switch case and default labels.
725 * interp.c: Likewise.
726 * sim-main.c: Likewise.
728 2002-06-03 Chris Demetriou <cgd@broadcom.com>
730 * cp1.c: Clean up comments which describe FP formats.
731 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
733 2002-06-03 Chris Demetriou <cgd@broadcom.com>
734 Ed Satterthwaite <ehs@broadcom.com>
736 * configure.in (mipsisa64sb1*-*-*): New target for supporting
737 Broadcom SiByte SB-1 processor configurations.
738 * configure: Regenerate.
739 * sb1.igen: New file.
740 * mips.igen: Include sb1.igen.
742 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
743 * mdmx.igen: Add "sb1" model to all appropriate functions and
745 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
746 (ob_func, ob_acc): Reference the above.
747 (qh_acc): Adjust to keep the same size as ob_acc.
748 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
749 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
751 2002-06-03 Chris Demetriou <cgd@broadcom.com>
753 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
755 2002-06-02 Chris Demetriou <cgd@broadcom.com>
756 Ed Satterthwaite <ehs@broadcom.com>
758 * mips.igen (mdmx): New (pseudo-)model.
759 * mdmx.c, mdmx.igen: New files.
760 * Makefile.in (SIM_OBJS): Add mdmx.o.
761 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
763 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
764 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
765 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
766 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
767 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
768 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
769 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
770 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
771 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
772 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
773 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
774 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
775 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
776 (qh_fmtsel): New macros.
777 (_sim_cpu): New member "acc".
778 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
779 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
781 2002-05-01 Chris Demetriou <cgd@broadcom.com>
783 * interp.c: Use 'deprecated' rather than 'depreciated.'
784 * sim-main.h: Likewise.
786 2002-05-01 Chris Demetriou <cgd@broadcom.com>
788 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
789 which wouldn't compile anyway.
790 * sim-main.h (unpredictable_action): New function prototype.
791 (Unpredictable): Define to call igen function unpredictable().
792 (NotWordValue): New macro to call igen function not_word_value().
793 (UndefinedResult): Remove.
794 * interp.c (undefined_result): Remove.
795 (unpredictable_action): New function.
796 * mips.igen (not_word_value, unpredictable): New functions.
797 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
798 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
799 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
800 NotWordValue() to check for unpredictable inputs, then
801 Unpredictable() to handle them.
803 2002-02-24 Chris Demetriou <cgd@broadcom.com>
805 * mips.igen: Fix formatting of calls to Unpredictable().
807 2002-04-20 Andrew Cagney <ac131313@redhat.com>
809 * interp.c (sim_open): Revert previous change.
811 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
813 * interp.c (sim_open): Disable chunk of code that wrote code in
814 vector table entries.
816 2002-03-19 Chris Demetriou <cgd@broadcom.com>
818 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
819 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
822 2002-03-19 Chris Demetriou <cgd@broadcom.com>
824 * cp1.c: Fix many formatting issues.
826 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
828 * cp1.c (fpu_format_name): New function to replace...
829 (DOFMT): This. Delete, and update all callers.
830 (fpu_rounding_mode_name): New function to replace...
831 (RMMODE): This. Delete, and update all callers.
833 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
835 * interp.c: Move FPU support routines from here to...
836 * cp1.c: Here. New file.
837 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
840 2002-03-12 Chris Demetriou <cgd@broadcom.com>
842 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
843 * mips.igen (mips32, mips64): New models, add to all instructions
844 and functions as appropriate.
845 (loadstore_ea, check_u64): New variant for model mips64.
846 (check_fmt_p): New variant for models mipsV and mips64, remove
847 mipsV model marking fro other variant.
850 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
851 for mips32 and mips64.
852 (DCLO, DCLZ): New instructions for mips64.
854 2002-03-07 Chris Demetriou <cgd@broadcom.com>
856 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
857 immediate or code as a hex value with the "%#lx" format.
858 (ANDI): Likewise, and fix printed instruction name.
860 2002-03-05 Chris Demetriou <cgd@broadcom.com>
862 * sim-main.h (UndefinedResult, Unpredictable): New macros
863 which currently do nothing.
865 2002-03-05 Chris Demetriou <cgd@broadcom.com>
867 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
868 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
869 (status_CU3): New definitions.
871 * sim-main.h (ExceptionCause): Add new values for MIPS32
872 and MIPS64: MDMX, MCheck, CacheErr. Update comments
873 for DebugBreakPoint and NMIReset to note their status in
875 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
876 (SignalExceptionCacheErr): New exception macros.
878 2002-03-05 Chris Demetriou <cgd@broadcom.com>
880 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
881 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
883 (SignalExceptionCoProcessorUnusable): Take as argument the
884 unusable coprocessor number.
886 2002-03-05 Chris Demetriou <cgd@broadcom.com>
888 * mips.igen: Fix formatting of all SignalException calls.
890 2002-03-05 Chris Demetriou <cgd@broadcom.com>
892 * sim-main.h (SIGNEXTEND): Remove.
894 2002-03-04 Chris Demetriou <cgd@broadcom.com>
896 * mips.igen: Remove gencode comment from top of file, fix
897 spelling in another comment.
899 2002-03-04 Chris Demetriou <cgd@broadcom.com>
901 * mips.igen (check_fmt, check_fmt_p): New functions to check
902 whether specific floating point formats are usable.
903 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
904 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
905 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
906 Use the new functions.
907 (do_c_cond_fmt): Remove format checks...
908 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
910 2002-03-03 Chris Demetriou <cgd@broadcom.com>
912 * mips.igen: Fix formatting of check_fpu calls.
914 2002-03-03 Chris Demetriou <cgd@broadcom.com>
916 * mips.igen (FLOOR.L.fmt): Store correct destination register.
918 2002-03-03 Chris Demetriou <cgd@broadcom.com>
920 * mips.igen: Remove whitespace at end of lines.
922 2002-03-02 Chris Demetriou <cgd@broadcom.com>
924 * mips.igen (loadstore_ea): New function to do effective
925 address calculations.
926 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
927 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
928 CACHE): Use loadstore_ea to do effective address computations.
930 2002-03-02 Chris Demetriou <cgd@broadcom.com>
932 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
933 * mips.igen (LL, CxC1, MxC1): Likewise.
935 2002-03-02 Chris Demetriou <cgd@broadcom.com>
937 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
938 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
939 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
940 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
941 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
942 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
943 Don't split opcode fields by hand, use the opcode field values
946 2002-03-01 Chris Demetriou <cgd@broadcom.com>
948 * mips.igen (do_divu): Fix spacing.
950 * mips.igen (do_dsllv): Move to be right before DSLLV,
951 to match the rest of the do_<shift> functions.
953 2002-03-01 Chris Demetriou <cgd@broadcom.com>
955 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
956 DSRL32, do_dsrlv): Trace inputs and results.
958 2002-03-01 Chris Demetriou <cgd@broadcom.com>
960 * mips.igen (CACHE): Provide instruction-printing string.
962 * interp.c (signal_exception): Comment tokens after #endif.
964 2002-02-28 Chris Demetriou <cgd@broadcom.com>
966 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
967 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
968 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
969 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
970 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
971 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
972 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
973 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
975 2002-02-28 Chris Demetriou <cgd@broadcom.com>
977 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
978 instruction-printing string.
979 (LWU): Use '64' as the filter flag.
981 2002-02-28 Chris Demetriou <cgd@broadcom.com>
983 * mips.igen (SDXC1): Fix instruction-printing string.
985 2002-02-28 Chris Demetriou <cgd@broadcom.com>
987 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
990 2002-02-27 Chris Demetriou <cgd@broadcom.com>
992 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
995 2002-02-27 Chris Demetriou <cgd@broadcom.com>
997 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
998 add a comma) so that it more closely match the MIPS ISA
999 documentation opcode partitioning.
1000 (PREF): Put useful names on opcode fields, and include
1001 instruction-printing string.
1003 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1005 * mips.igen (check_u64): New function which in the future will
1006 check whether 64-bit instructions are usable and signal an
1007 exception if not. Currently a no-op.
1008 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1009 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1010 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1011 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1013 * mips.igen (check_fpu): New function which in the future will
1014 check whether FPU instructions are usable and signal an exception
1015 if not. Currently a no-op.
1016 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1017 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1018 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1019 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1020 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1021 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1022 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1023 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1025 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1027 * mips.igen (do_load_left, do_load_right): Move to be immediately
1029 (do_store_left, do_store_right): Move to be immediately following
1032 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1034 * mips.igen (mipsV): New model name. Also, add it to
1035 all instructions and functions where it is appropriate.
1037 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1039 * mips.igen: For all functions and instructions, list model
1040 names that support that instruction one per line.
1042 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1044 * mips.igen: Add some additional comments about supported
1045 models, and about which instructions go where.
1046 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1047 order as is used in the rest of the file.
1049 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1051 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1052 indicating that ALU32_END or ALU64_END are there to check
1054 (DADD): Likewise, but also remove previous comment about
1057 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1059 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1060 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1061 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1062 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1063 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1064 fields (i.e., add and move commas) so that they more closely
1065 match the MIPS ISA documentation opcode partitioning.
1067 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1069 * mips.igen (ADDI): Print immediate value.
1070 (BREAK): Print code.
1071 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1072 (SLL): Print "nop" specially, and don't run the code
1073 that does the shift for the "nop" case.
1075 2001-11-17 Fred Fish <fnf@redhat.com>
1077 * sim-main.h (float_operation): Move enum declaration outside
1078 of _sim_cpu struct declaration.
1080 2001-04-12 Jim Blandy <jimb@redhat.com>
1082 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1083 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1085 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1086 PENDING_FILL, and you can get the intended effect gracefully by
1087 calling PENDING_SCHED directly.
1089 2001-02-23 Ben Elliston <bje@redhat.com>
1091 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1092 already defined elsewhere.
1094 2001-02-19 Ben Elliston <bje@redhat.com>
1096 * sim-main.h (sim_monitor): Return an int.
1097 * interp.c (sim_monitor): Add return values.
1098 (signal_exception): Handle error conditions from sim_monitor.
1100 2001-02-08 Ben Elliston <bje@redhat.com>
1102 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1103 (store_memory): Likewise, pass cia to sim_core_write*.
1105 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1107 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1108 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1110 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1112 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1113 * Makefile.in: Don't delete *.igen when cleaning directory.
1115 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1117 * m16.igen (break): Call SignalException not sim_engine_halt.
1119 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1121 From Jason Eckhardt:
1122 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1124 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1126 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1128 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1130 * mips.igen (do_dmultx): Fix typo.
1132 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1134 * configure: Regenerated to track ../common/aclocal.m4 changes.
1136 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1138 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1140 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1142 * sim-main.h (GPR_CLEAR): Define macro.
1144 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1146 * interp.c (decode_coproc): Output long using %lx and not %s.
1148 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1150 * interp.c (sim_open): Sort & extend dummy memory regions for
1151 --board=jmr3904 for eCos.
1153 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1155 * configure: Regenerated.
1157 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1159 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1160 calls, conditional on the simulator being in verbose mode.
1162 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1164 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1165 cache don't get ReservedInstruction traps.
1167 1999-11-29 Mark Salter <msalter@cygnus.com>
1169 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1170 to clear status bits in sdisr register. This is how the hardware works.
1172 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1173 being used by cygmon.
1175 1999-11-11 Andrew Haley <aph@cygnus.com>
1177 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1180 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1182 * mips.igen (MULT): Correct previous mis-applied patch.
1184 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1186 * mips.igen (delayslot32): Handle sequence like
1187 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1188 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1189 (MULT): Actually pass the third register...
1191 1999-09-03 Mark Salter <msalter@cygnus.com>
1193 * interp.c (sim_open): Added more memory aliases for additional
1194 hardware being touched by cygmon on jmr3904 board.
1196 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1198 * configure: Regenerated to track ../common/aclocal.m4 changes.
1200 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1202 * interp.c (sim_store_register): Handle case where client - GDB -
1203 specifies that a 4 byte register is 8 bytes in size.
1204 (sim_fetch_register): Ditto.
1206 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1208 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1209 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1210 (idt_monitor_base): Base address for IDT monitor traps.
1211 (pmon_monitor_base): Ditto for PMON.
1212 (lsipmon_monitor_base): Ditto for LSI PMON.
1213 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1214 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1215 (sim_firmware_command): New function.
1216 (mips_option_handler): Call it for OPTION_FIRMWARE.
1217 (sim_open): Allocate memory for idt_monitor region. If "--board"
1218 option was given, add no monitor by default. Add BREAK hooks only if
1219 monitors are also there.
1221 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1223 * interp.c (sim_monitor): Flush output before reading input.
1225 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1227 * tconfig.in (SIM_HANDLES_LMA): Always define.
1229 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1231 From Mark Salter <msalter@cygnus.com>:
1232 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1233 (sim_open): Add setup for BSP board.
1235 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1237 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1238 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1239 them as unimplemented.
1241 1999-05-08 Felix Lee <flee@cygnus.com>
1243 * configure: Regenerated to track ../common/aclocal.m4 changes.
1245 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1247 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1249 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1251 * configure.in: Any mips64vr5*-*-* target should have
1252 -DTARGET_ENABLE_FR=1.
1253 (default_endian): Any mips64vr*el-*-* target should default to
1255 * configure: Re-generate.
1257 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1259 * mips.igen (ldl): Extend from _16_, not 32.
1261 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1263 * interp.c (sim_store_register): Force registers written to by GDB
1264 into an un-interpreted state.
1266 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1268 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1269 CPU, start periodic background I/O polls.
1270 (tx3904sio_poll): New function: periodic I/O poller.
1272 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1274 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1276 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1278 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1281 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1283 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1284 (load_word): Call SIM_CORE_SIGNAL hook on error.
1285 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1286 starting. For exception dispatching, pass PC instead of NULL_CIA.
1287 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1288 * sim-main.h (COP0_BADVADDR): Define.
1289 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1290 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1291 (_sim_cpu): Add exc_* fields to store register value snapshots.
1292 * mips.igen (*): Replace memory-related SignalException* calls
1293 with references to SIM_CORE_SIGNAL hook.
1295 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1297 * sim-main.c (*): Minor warning cleanups.
1299 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1301 * m16.igen (DADDIU5): Correct type-o.
1303 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1305 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1308 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1310 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1312 (interp.o): Add dependency on itable.h
1313 (oengine.c, gencode): Delete remaining references.
1314 (BUILT_SRC_FROM_GEN): Clean up.
1316 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1319 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1320 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1321 tmp-run-hack) : New.
1322 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1323 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1324 Drop the "64" qualifier to get the HACK generator working.
1325 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1326 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1327 qualifier to get the hack generator working.
1328 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1329 (DSLL): Use do_dsll.
1330 (DSLLV): Use do_dsllv.
1331 (DSRA): Use do_dsra.
1332 (DSRL): Use do_dsrl.
1333 (DSRLV): Use do_dsrlv.
1334 (BC1): Move *vr4100 to get the HACK generator working.
1335 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1336 get the HACK generator working.
1337 (MACC) Rename to get the HACK generator working.
1338 (DMACC,MACCS,DMACCS): Add the 64.
1340 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1342 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1343 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1345 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1347 * mips/interp.c (DEBUG): Cleanups.
1349 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1351 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1352 (tx3904sio_tickle): fflush after a stdout character output.
1354 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1356 * interp.c (sim_close): Uninstall modules.
1358 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1360 * sim-main.h, interp.c (sim_monitor): Change to global
1363 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1365 * configure.in (vr4100): Only include vr4100 instructions in
1367 * configure: Re-generate.
1368 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1370 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1372 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1373 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1376 * configure.in (sim_default_gen, sim_use_gen): Replace with
1378 (--enable-sim-igen): Delete config option. Always using IGEN.
1379 * configure: Re-generate.
1381 * Makefile.in (gencode): Kill, kill, kill.
1384 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1386 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1387 bit mips16 igen simulator.
1388 * configure: Re-generate.
1390 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1391 as part of vr4100 ISA.
1392 * vr.igen: Mark all instructions as 64 bit only.
1394 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1396 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1399 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1401 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1402 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1403 * configure: Re-generate.
1405 * m16.igen (BREAK): Define breakpoint instruction.
1406 (JALX32): Mark instruction as mips16 and not r3900.
1407 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1409 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1411 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1413 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1414 insn as a debug breakpoint.
1416 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1418 (PENDING_SCHED): Clean up trace statement.
1419 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1420 (PENDING_FILL): Delay write by only one cycle.
1421 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1423 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1425 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1427 (pending_tick): Move incrementing of index to FOR statement.
1428 (pending_tick): Only update PENDING_OUT after a write has occured.
1430 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1432 * configure: Re-generate.
1434 * interp.c (sim_engine_run OLD): Delete explicit call to
1435 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1437 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1439 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1440 interrupt level number to match changed SignalExceptionInterrupt
1443 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1445 * interp.c: #include "itable.h" if WITH_IGEN.
1446 (get_insn_name): New function.
1447 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1448 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1450 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1452 * configure: Rebuilt to inhale new common/aclocal.m4.
1454 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1456 * dv-tx3904sio.c: Include sim-assert.h.
1458 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1460 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1461 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1462 Reorganize target-specific sim-hardware checks.
1463 * configure: rebuilt.
1464 * interp.c (sim_open): For tx39 target boards, set
1465 OPERATING_ENVIRONMENT, add tx3904sio devices.
1466 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1467 ROM executables. Install dv-sockser into sim-modules list.
1469 * dv-tx3904irc.c: Compiler warning clean-up.
1470 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1471 frequent hw-trace messages.
1473 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1475 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1477 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1479 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1481 * vr.igen: New file.
1482 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1483 * mips.igen: Define vr4100 model. Include vr.igen.
1484 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1486 * mips.igen (check_mf_hilo): Correct check.
1488 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1490 * sim-main.h (interrupt_event): Add prototype.
1492 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1493 register_ptr, register_value.
1494 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1496 * sim-main.h (tracefh): Make extern.
1498 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1500 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1501 Reduce unnecessarily high timer event frequency.
1502 * dv-tx3904cpu.c: Ditto for interrupt event.
1504 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1506 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1508 (interrupt_event): Made non-static.
1510 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1511 interchange of configuration values for external vs. internal
1514 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1516 * mips.igen (BREAK): Moved code to here for
1517 simulator-reserved break instructions.
1518 * gencode.c (build_instruction): Ditto.
1519 * interp.c (signal_exception): Code moved from here. Non-
1520 reserved instructions now use exception vector, rather
1522 * sim-main.h: Moved magic constants to here.
1524 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1526 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1527 register upon non-zero interrupt event level, clear upon zero
1529 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1530 by passing zero event value.
1531 (*_io_{read,write}_buffer): Endianness fixes.
1532 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1533 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1535 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1536 serial I/O and timer module at base address 0xFFFF0000.
1538 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1540 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1543 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1545 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1547 * configure: Update.
1549 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1551 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1552 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1553 * configure.in: Include tx3904tmr in hw_device list.
1554 * configure: Rebuilt.
1555 * interp.c (sim_open): Instantiate three timer instances.
1556 Fix address typo of tx3904irc instance.
1558 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1560 * interp.c (signal_exception): SystemCall exception now uses
1561 the exception vector.
1563 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1565 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1568 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1570 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1572 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1574 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1576 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1577 sim-main.h. Declare a struct hw_descriptor instead of struct
1578 hw_device_descriptor.
1580 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1582 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1583 right bits and then re-align left hand bytes to correct byte
1584 lanes. Fix incorrect computation in do_store_left when loading
1585 bytes from second word.
1587 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1589 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1590 * interp.c (sim_open): Only create a device tree when HW is
1593 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1594 * interp.c (signal_exception): Ditto.
1596 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1598 * gencode.c: Mark BEGEZALL as LIKELY.
1600 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1602 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1603 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1605 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1607 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1608 modules. Recognize TX39 target with "mips*tx39" pattern.
1609 * configure: Rebuilt.
1610 * sim-main.h (*): Added many macros defining bits in
1611 TX39 control registers.
1612 (SignalInterrupt): Send actual PC instead of NULL.
1613 (SignalNMIReset): New exception type.
1614 * interp.c (board): New variable for future use to identify
1615 a particular board being simulated.
1616 (mips_option_handler,mips_options): Added "--board" option.
1617 (interrupt_event): Send actual PC.
1618 (sim_open): Make memory layout conditional on board setting.
1619 (signal_exception): Initial implementation of hardware interrupt
1620 handling. Accept another break instruction variant for simulator
1622 (decode_coproc): Implement RFE instruction for TX39.
1623 (mips.igen): Decode RFE instruction as such.
1624 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1625 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1626 bbegin to implement memory map.
1627 * dv-tx3904cpu.c: New file.
1628 * dv-tx3904irc.c: New file.
1630 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1632 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1634 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1636 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1637 with calls to check_div_hilo.
1639 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1641 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1642 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1643 Add special r3900 version of do_mult_hilo.
1644 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1645 with calls to check_mult_hilo.
1646 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1647 with calls to check_div_hilo.
1649 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1651 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1652 Document a replacement.
1654 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1656 * interp.c (sim_monitor): Make mon_printf work.
1658 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1660 * sim-main.h (INSN_NAME): New arg `cpu'.
1662 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1664 * configure: Regenerated to track ../common/aclocal.m4 changes.
1666 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1668 * configure: Regenerated to track ../common/aclocal.m4 changes.
1671 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1673 * acconfig.h: New file.
1674 * configure.in: Reverted change of Apr 24; use sinclude again.
1676 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1678 * configure: Regenerated to track ../common/aclocal.m4 changes.
1681 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1683 * configure.in: Don't call sinclude.
1685 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1687 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1689 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1691 * mips.igen (ERET): Implement.
1693 * interp.c (decode_coproc): Return sign-extended EPC.
1695 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1697 * interp.c (signal_exception): Do not ignore Trap.
1698 (signal_exception): On TRAP, restart at exception address.
1699 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1700 (signal_exception): Update.
1701 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1702 so that TRAP instructions are caught.
1704 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1706 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1707 contains HI/LO access history.
1708 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1709 (HIACCESS, LOACCESS): Delete, replace with
1710 (HIHISTORY, LOHISTORY): New macros.
1711 (CHECKHILO): Delete all, moved to mips.igen
1713 * gencode.c (build_instruction): Do not generate checks for
1714 correct HI/LO register usage.
1716 * interp.c (old_engine_run): Delete checks for correct HI/LO
1719 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1720 check_mf_cycles): New functions.
1721 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1722 do_divu, domultx, do_mult, do_multu): Use.
1724 * tx.igen ("madd", "maddu"): Use.
1726 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1728 * mips.igen (DSRAV): Use function do_dsrav.
1729 (SRAV): Use new function do_srav.
1731 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1732 (B): Sign extend 11 bit immediate.
1733 (EXT-B*): Shift 16 bit immediate left by 1.
1734 (ADDIU*): Don't sign extend immediate value.
1736 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1738 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1740 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1743 * mips.igen (delayslot32, nullify_next_insn): New functions.
1744 (m16.igen): Always include.
1745 (do_*): Add more tracing.
1747 * m16.igen (delayslot16): Add NIA argument, could be called by a
1748 32 bit MIPS16 instruction.
1750 * interp.c (ifetch16): Move function from here.
1751 * sim-main.c (ifetch16): To here.
1753 * sim-main.c (ifetch16, ifetch32): Update to match current
1754 implementations of LH, LW.
1755 (signal_exception): Don't print out incorrect hex value of illegal
1758 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1760 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1763 * m16.igen: Implement MIPS16 instructions.
1765 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1766 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1767 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1768 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1769 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1770 bodies of corresponding code from 32 bit insn to these. Also used
1771 by MIPS16 versions of functions.
1773 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1774 (IMEM16): Drop NR argument from macro.
1776 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1778 * Makefile.in (SIM_OBJS): Add sim-main.o.
1780 * sim-main.h (address_translation, load_memory, store_memory,
1781 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1783 (pr_addr, pr_uword64): Declare.
1784 (sim-main.c): Include when H_REVEALS_MODULE_P.
1786 * interp.c (address_translation, load_memory, store_memory,
1787 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1789 * sim-main.c: To here. Fix compilation problems.
1791 * configure.in: Enable inlining.
1792 * configure: Re-config.
1794 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1796 * configure: Regenerated to track ../common/aclocal.m4 changes.
1798 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1800 * mips.igen: Include tx.igen.
1801 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1802 * tx.igen: New file, contains MADD and MADDU.
1804 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1805 the hardwired constant `7'.
1806 (store_memory): Ditto.
1807 (LOADDRMASK): Move definition to sim-main.h.
1809 mips.igen (MTC0): Enable for r3900.
1812 mips.igen (do_load_byte): Delete.
1813 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1814 do_store_right): New functions.
1815 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1817 configure.in: Let the tx39 use igen again.
1820 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1822 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1823 not an address sized quantity. Return zero for cache sizes.
1825 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1827 * mips.igen (r3900): r3900 does not support 64 bit integer
1830 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1832 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1834 * configure : Rebuild.
1836 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1838 * configure: Regenerated to track ../common/aclocal.m4 changes.
1840 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1842 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1844 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1846 * configure: Regenerated to track ../common/aclocal.m4 changes.
1847 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1849 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1851 * configure: Regenerated to track ../common/aclocal.m4 changes.
1853 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1855 * interp.c (Max, Min): Comment out functions. Not yet used.
1857 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1859 * configure: Regenerated to track ../common/aclocal.m4 changes.
1861 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1863 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1864 configurable settings for stand-alone simulator.
1866 * configure.in: Added X11 search, just in case.
1868 * configure: Regenerated.
1870 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1872 * interp.c (sim_write, sim_read, load_memory, store_memory):
1873 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1875 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1877 * sim-main.h (GETFCC): Return an unsigned value.
1879 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1881 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1882 (DADD): Result destination is RD not RT.
1884 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1886 * sim-main.h (HIACCESS, LOACCESS): Always define.
1888 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1890 * interp.c (sim_info): Delete.
1892 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1894 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1895 (mips_option_handler): New argument `cpu'.
1896 (sim_open): Update call to sim_add_option_table.
1898 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1900 * mips.igen (CxC1): Add tracing.
1902 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1904 * sim-main.h (Max, Min): Declare.
1906 * interp.c (Max, Min): New functions.
1908 * mips.igen (BC1): Add tracing.
1910 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1912 * interp.c Added memory map for stack in vr4100
1914 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1916 * interp.c (load_memory): Add missing "break"'s.
1918 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1920 * interp.c (sim_store_register, sim_fetch_register): Pass in
1921 length parameter. Return -1.
1923 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1925 * interp.c: Added hardware init hook, fixed warnings.
1927 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1929 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1931 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1933 * interp.c (ifetch16): New function.
1935 * sim-main.h (IMEM32): Rename IMEM.
1936 (IMEM16_IMMED): Define.
1938 (DELAY_SLOT): Update.
1940 * m16run.c (sim_engine_run): New file.
1942 * m16.igen: All instructions except LB.
1943 (LB): Call do_load_byte.
1944 * mips.igen (do_load_byte): New function.
1945 (LB): Call do_load_byte.
1947 * mips.igen: Move spec for insn bit size and high bit from here.
1948 * Makefile.in (tmp-igen, tmp-m16): To here.
1950 * m16.dc: New file, decode mips16 instructions.
1952 * Makefile.in (SIM_NO_ALL): Define.
1953 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1955 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1957 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1958 point unit to 32 bit registers.
1959 * configure: Re-generate.
1961 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1963 * configure.in (sim_use_gen): Make IGEN the default simulator
1964 generator for generic 32 and 64 bit mips targets.
1965 * configure: Re-generate.
1967 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1969 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1972 * interp.c (sim_fetch_register, sim_store_register): Read/write
1973 FGR from correct location.
1974 (sim_open): Set size of FGR's according to
1975 WITH_TARGET_FLOATING_POINT_BITSIZE.
1977 * sim-main.h (FGR): Store floating point registers in a separate
1980 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1982 * configure: Regenerated to track ../common/aclocal.m4 changes.
1984 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1986 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1988 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1990 * interp.c (pending_tick): New function. Deliver pending writes.
1992 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1993 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1994 it can handle mixed sized quantites and single bits.
1996 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1998 * interp.c (oengine.h): Do not include when building with IGEN.
1999 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2000 (sim_info): Ditto for PROCESSOR_64BIT.
2001 (sim_monitor): Replace ut_reg with unsigned_word.
2002 (*): Ditto for t_reg.
2003 (LOADDRMASK): Define.
2004 (sim_open): Remove defunct check that host FP is IEEE compliant,
2005 using software to emulate floating point.
2006 (value_fpr, ...): Always compile, was conditional on HASFPU.
2008 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2010 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2013 * interp.c (SD, CPU): Define.
2014 (mips_option_handler): Set flags in each CPU.
2015 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2016 (sim_close): Do not clear STATE, deleted anyway.
2017 (sim_write, sim_read): Assume CPU zero's vm should be used for
2019 (sim_create_inferior): Set the PC for all processors.
2020 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2022 (mips16_entry): Pass correct nr of args to store_word, load_word.
2023 (ColdReset): Cold reset all cpu's.
2024 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2025 (sim_monitor, load_memory, store_memory, signal_exception): Use
2026 `CPU' instead of STATE_CPU.
2029 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2032 * sim-main.h (signal_exception): Add sim_cpu arg.
2033 (SignalException*): Pass both SD and CPU to signal_exception.
2034 * interp.c (signal_exception): Update.
2036 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2038 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2039 address_translation): Ditto
2040 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2042 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2044 * configure: Regenerated to track ../common/aclocal.m4 changes.
2046 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2048 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2050 * mips.igen (model): Map processor names onto BFD name.
2052 * sim-main.h (CPU_CIA): Delete.
2053 (SET_CIA, GET_CIA): Define
2055 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2057 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2060 * configure.in (default_endian): Configure a big-endian simulator
2062 * configure: Re-generate.
2064 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2066 * configure: Regenerated to track ../common/aclocal.m4 changes.
2068 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2070 * interp.c (sim_monitor): Handle Densan monitor outbyte
2071 and inbyte functions.
2073 1997-12-29 Felix Lee <flee@cygnus.com>
2075 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2077 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2079 * Makefile.in (tmp-igen): Arrange for $zero to always be
2080 reset to zero after every instruction.
2082 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2084 * configure: Regenerated to track ../common/aclocal.m4 changes.
2087 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2089 * mips.igen (MSUB): Fix to work like MADD.
2090 * gencode.c (MSUB): Similarly.
2092 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2094 * configure: Regenerated to track ../common/aclocal.m4 changes.
2096 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2098 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2100 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2102 * sim-main.h (sim-fpu.h): Include.
2104 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2105 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2106 using host independant sim_fpu module.
2108 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2110 * interp.c (signal_exception): Report internal errors with SIGABRT
2113 * sim-main.h (C0_CONFIG): New register.
2114 (signal.h): No longer include.
2116 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2118 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2120 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2122 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2124 * mips.igen: Tag vr5000 instructions.
2125 (ANDI): Was missing mipsIV model, fix assembler syntax.
2126 (do_c_cond_fmt): New function.
2127 (C.cond.fmt): Handle mips I-III which do not support CC field
2129 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2130 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2132 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2133 vr5000 which saves LO in a GPR separatly.
2135 * configure.in (enable-sim-igen): For vr5000, select vr5000
2136 specific instructions.
2137 * configure: Re-generate.
2139 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2141 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2143 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2144 fmt_uninterpreted_64 bit cases to switch. Convert to
2147 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2149 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2150 as specified in IV3.2 spec.
2151 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2153 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2155 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2156 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2157 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2158 PENDING_FILL versions of instructions. Simplify.
2160 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2162 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2164 (MTHI, MFHI): Disable code checking HI-LO.
2166 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2168 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2170 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2172 * gencode.c (build_mips16_operands): Replace IPC with cia.
2174 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2175 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2177 (UndefinedResult): Replace function with macro/function
2179 (sim_engine_run): Don't save PC in IPC.
2181 * sim-main.h (IPC): Delete.
2184 * interp.c (signal_exception, store_word, load_word,
2185 address_translation, load_memory, store_memory, cache_op,
2186 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2187 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2188 current instruction address - cia - argument.
2189 (sim_read, sim_write): Call address_translation directly.
2190 (sim_engine_run): Rename variable vaddr to cia.
2191 (signal_exception): Pass cia to sim_monitor
2193 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2194 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2195 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2197 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2198 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2201 * interp.c (signal_exception): Pass restart address to
2204 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2205 idecode.o): Add dependency.
2207 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2209 (DELAY_SLOT): Update NIA not PC with branch address.
2210 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2212 * mips.igen: Use CIA not PC in branch calculations.
2213 (illegal): Call SignalException.
2214 (BEQ, ADDIU): Fix assembler.
2216 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2218 * m16.igen (JALX): Was missing.
2220 * configure.in (enable-sim-igen): New configuration option.
2221 * configure: Re-generate.
2223 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2225 * interp.c (load_memory, store_memory): Delete parameter RAW.
2226 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2227 bypassing {load,store}_memory.
2229 * sim-main.h (ByteSwapMem): Delete definition.
2231 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2233 * interp.c (sim_do_command, sim_commands): Delete mips specific
2234 commands. Handled by module sim-options.
2236 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2237 (WITH_MODULO_MEMORY): Define.
2239 * interp.c (sim_info): Delete code printing memory size.
2241 * interp.c (mips_size): Nee sim_size, delete function.
2243 (monitor, monitor_base, monitor_size): Delete global variables.
2244 (sim_open, sim_close): Delete code creating monitor and other
2245 memory regions. Use sim-memopts module, via sim_do_commandf, to
2246 manage memory regions.
2247 (load_memory, store_memory): Use sim-core for memory model.
2249 * interp.c (address_translation): Delete all memory map code
2250 except line forcing 32 bit addresses.
2252 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2254 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2257 * interp.c (logfh, logfile): Delete globals.
2258 (sim_open, sim_close): Delete code opening & closing log file.
2259 (mips_option_handler): Delete -l and -n options.
2260 (OPTION mips_options): Ditto.
2262 * interp.c (OPTION mips_options): Rename option trace to dinero.
2263 (mips_option_handler): Update.
2265 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2267 * interp.c (fetch_str): New function.
2268 (sim_monitor): Rewrite using sim_read & sim_write.
2269 (sim_open): Check magic number.
2270 (sim_open): Write monitor vectors into memory using sim_write.
2271 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2272 (sim_read, sim_write): Simplify - transfer data one byte at a
2274 (load_memory, store_memory): Clarify meaning of parameter RAW.
2276 * sim-main.h (isHOST): Defete definition.
2277 (isTARGET): Mark as depreciated.
2278 (address_translation): Delete parameter HOST.
2280 * interp.c (address_translation): Delete parameter HOST.
2282 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2286 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2287 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2289 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2291 * mips.igen: Add model filter field to records.
2293 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2295 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2297 interp.c (sim_engine_run): Do not compile function sim_engine_run
2298 when WITH_IGEN == 1.
2300 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2301 target architecture.
2303 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2304 igen. Replace with configuration variables sim_igen_flags /
2307 * m16.igen: New file. Copy mips16 insns here.
2308 * mips.igen: From here.
2310 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2312 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2314 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2316 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2318 * gencode.c (build_instruction): Follow sim_write's lead in using
2319 BigEndianMem instead of !ByteSwapMem.
2321 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2323 * configure.in (sim_gen): Dependent on target, select type of
2324 generator. Always select old style generator.
2326 configure: Re-generate.
2328 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2330 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2331 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2332 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2333 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2334 SIM_@sim_gen@_*, set by autoconf.
2336 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2338 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2340 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2341 CURRENT_FLOATING_POINT instead.
2343 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2344 (address_translation): Raise exception InstructionFetch when
2345 translation fails and isINSTRUCTION.
2347 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2348 sim_engine_run): Change type of of vaddr and paddr to
2350 (address_translation, prefetch, load_memory, store_memory,
2351 cache_op): Change type of vAddr and pAddr to address_word.
2353 * gencode.c (build_instruction): Change type of vaddr and paddr to
2356 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2358 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2359 macro to obtain result of ALU op.
2361 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2363 * interp.c (sim_info): Call profile_print.
2365 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2367 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2369 * sim-main.h (WITH_PROFILE): Do not define, defined in
2370 common/sim-config.h. Use sim-profile module.
2371 (simPROFILE): Delete defintion.
2373 * interp.c (PROFILE): Delete definition.
2374 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2375 (sim_close): Delete code writing profile histogram.
2376 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2378 (sim_engine_run): Delete code profiling the PC.
2380 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2382 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2384 * interp.c (sim_monitor): Make register pointers of type
2387 * sim-main.h: Make registers of type unsigned_word not
2390 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2392 * interp.c (sync_operation): Rename from SyncOperation, make
2393 global, add SD argument.
2394 (prefetch): Rename from Prefetch, make global, add SD argument.
2395 (decode_coproc): Make global.
2397 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2399 * gencode.c (build_instruction): Generate DecodeCoproc not
2400 decode_coproc calls.
2402 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2403 (SizeFGR): Move to sim-main.h
2404 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2405 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2406 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2408 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2409 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2410 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2411 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2412 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2413 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2415 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2417 (sim-alu.h): Include.
2418 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2419 (sim_cia): Typedef to instruction_address.
2421 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2423 * Makefile.in (interp.o): Rename generated file engine.c to
2428 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2430 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2432 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2434 * gencode.c (build_instruction): For "FPSQRT", output correct
2435 number of arguments to Recip.
2437 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2439 * Makefile.in (interp.o): Depends on sim-main.h
2441 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2443 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2444 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2445 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2446 STATE, DSSTATE): Define
2447 (GPR, FGRIDX, ..): Define.
2449 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2450 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2451 (GPR, FGRIDX, ...): Delete macros.
2453 * interp.c: Update names to match defines from sim-main.h
2455 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2457 * interp.c (sim_monitor): Add SD argument.
2458 (sim_warning): Delete. Replace calls with calls to
2460 (sim_error): Delete. Replace calls with sim_io_error.
2461 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2462 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2463 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2465 (mips_size): Rename from sim_size. Add SD argument.
2467 * interp.c (simulator): Delete global variable.
2468 (callback): Delete global variable.
2469 (mips_option_handler, sim_open, sim_write, sim_read,
2470 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2471 sim_size,sim_monitor): Use sim_io_* not callback->*.
2472 (sim_open): ZALLOC simulator struct.
2473 (PROFILE): Do not define.
2475 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2477 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2478 support.h with corresponding code.
2480 * sim-main.h (word64, uword64), support.h: Move definition to
2482 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2485 * Makefile.in: Update dependencies
2486 * interp.c: Do not include.
2488 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2490 * interp.c (address_translation, load_memory, store_memory,
2491 cache_op): Rename to from AddressTranslation et.al., make global,
2494 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2497 * interp.c (SignalException): Rename to signal_exception, make
2500 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2502 * sim-main.h (SignalException, SignalExceptionInterrupt,
2503 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2504 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2505 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2508 * interp.c, support.h: Use.
2510 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2512 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2513 to value_fpr / store_fpr. Add SD argument.
2514 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2515 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2517 * sim-main.h (ValueFPR, StoreFPR): Define.
2519 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2521 * interp.c (sim_engine_run): Check consistency between configure
2522 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2525 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2526 (mips_fpu): Configure WITH_FLOATING_POINT.
2527 (mips_endian): Configure WITH_TARGET_ENDIAN.
2528 * configure: Update.
2530 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2532 * configure: Regenerated to track ../common/aclocal.m4 changes.
2534 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2536 * configure: Regenerated.
2538 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2540 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2542 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2544 * gencode.c (print_igen_insn_models): Assume certain architectures
2545 include all mips* instructions.
2546 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2549 * Makefile.in (tmp.igen): Add target. Generate igen input from
2552 * gencode.c (FEATURE_IGEN): Define.
2553 (main): Add --igen option. Generate output in igen format.
2554 (process_instructions): Format output according to igen option.
2555 (print_igen_insn_format): New function.
2556 (print_igen_insn_models): New function.
2557 (process_instructions): Only issue warnings and ignore
2558 instructions when no FEATURE_IGEN.
2560 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2562 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2565 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2567 * configure: Regenerated to track ../common/aclocal.m4 changes.
2569 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2571 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2572 SIM_RESERVED_BITS): Delete, moved to common.
2573 (SIM_EXTRA_CFLAGS): Update.
2575 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2577 * configure.in: Configure non-strict memory alignment.
2578 * configure: Regenerated to track ../common/aclocal.m4 changes.
2580 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2582 * configure: Regenerated to track ../common/aclocal.m4 changes.
2584 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2586 * gencode.c (SDBBP,DERET): Added (3900) insns.
2587 (RFE): Turn on for 3900.
2588 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2589 (dsstate): Made global.
2590 (SUBTARGET_R3900): Added.
2591 (CANCELDELAYSLOT): New.
2592 (SignalException): Ignore SystemCall rather than ignore and
2593 terminate. Add DebugBreakPoint handling.
2594 (decode_coproc): New insns RFE, DERET; and new registers Debug
2595 and DEPC protected by SUBTARGET_R3900.
2596 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2598 * Makefile.in,configure.in: Add mips subtarget option.
2599 * configure: Update.
2601 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2603 * gencode.c: Add r3900 (tx39).
2606 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2608 * gencode.c (build_instruction): Don't need to subtract 4 for
2611 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2613 * interp.c: Correct some HASFPU problems.
2615 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2617 * configure: Regenerated to track ../common/aclocal.m4 changes.
2619 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2621 * interp.c (mips_options): Fix samples option short form, should
2624 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2626 * interp.c (sim_info): Enable info code. Was just returning.
2628 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2630 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2633 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2635 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2637 (build_instruction): Ditto for LL.
2639 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2641 * configure: Regenerated to track ../common/aclocal.m4 changes.
2643 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2645 * configure: Regenerated to track ../common/aclocal.m4 changes.
2648 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2650 * interp.c (sim_open): Add call to sim_analyze_program, update
2653 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2655 * interp.c (sim_kill): Delete.
2656 (sim_create_inferior): Add ABFD argument. Set PC from same.
2657 (sim_load): Move code initializing trap handlers from here.
2658 (sim_open): To here.
2659 (sim_load): Delete, use sim-hload.c.
2661 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2663 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2665 * configure: Regenerated to track ../common/aclocal.m4 changes.
2668 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2670 * interp.c (sim_open): Add ABFD argument.
2671 (sim_load): Move call to sim_config from here.
2672 (sim_open): To here. Check return status.
2674 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2676 * gencode.c (build_instruction): Two arg MADD should
2677 not assign result to $0.
2679 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2681 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2682 * sim/mips/configure.in: Regenerate.
2684 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2686 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2687 signed8, unsigned8 et.al. types.
2689 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2690 hosts when selecting subreg.
2692 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2694 * interp.c (sim_engine_run): Reset the ZERO register to zero
2695 regardless of FEATURE_WARN_ZERO.
2696 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2698 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2700 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2701 (SignalException): For BreakPoints ignore any mode bits and just
2703 (SignalException): Always set the CAUSE register.
2705 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2707 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2708 exception has been taken.
2710 * interp.c: Implement the ERET and mt/f sr instructions.
2712 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2714 * interp.c (SignalException): Don't bother restarting an
2717 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2719 * interp.c (SignalException): Really take an interrupt.
2720 (interrupt_event): Only deliver interrupts when enabled.
2722 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2724 * interp.c (sim_info): Only print info when verbose.
2725 (sim_info) Use sim_io_printf for output.
2727 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2729 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2732 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2734 * interp.c (sim_do_command): Check for common commands if a
2735 simulator specific command fails.
2737 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2739 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2740 and simBE when DEBUG is defined.
2742 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2744 * interp.c (interrupt_event): New function. Pass exception event
2745 onto exception handler.
2747 * configure.in: Check for stdlib.h.
2748 * configure: Regenerate.
2750 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2751 variable declaration.
2752 (build_instruction): Initialize memval1.
2753 (build_instruction): Add UNUSED attribute to byte, bigend,
2755 (build_operands): Ditto.
2757 * interp.c: Fix GCC warnings.
2758 (sim_get_quit_code): Delete.
2760 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2761 * Makefile.in: Ditto.
2762 * configure: Re-generate.
2764 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2766 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2768 * interp.c (mips_option_handler): New function parse argumes using
2770 (myname): Replace with STATE_MY_NAME.
2771 (sim_open): Delete check for host endianness - performed by
2773 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2774 (sim_open): Move much of the initialization from here.
2775 (sim_load): To here. After the image has been loaded and
2777 (sim_open): Move ColdReset from here.
2778 (sim_create_inferior): To here.
2779 (sim_open): Make FP check less dependant on host endianness.
2781 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2783 * interp.c (sim_set_callbacks): Delete.
2785 * interp.c (membank, membank_base, membank_size): Replace with
2786 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2787 (sim_open): Remove call to callback->init. gdb/run do this.
2791 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2793 * interp.c (big_endian_p): Delete, replaced by
2794 current_target_byte_order.
2796 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2798 * interp.c (host_read_long, host_read_word, host_swap_word,
2799 host_swap_long): Delete. Using common sim-endian.
2800 (sim_fetch_register, sim_store_register): Use H2T.
2801 (pipeline_ticks): Delete. Handled by sim-events.
2803 (sim_engine_run): Update.
2805 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2807 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2809 (SignalException): To here. Signal using sim_engine_halt.
2810 (sim_stop_reason): Delete, moved to common.
2812 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2814 * interp.c (sim_open): Add callback argument.
2815 (sim_set_callbacks): Delete SIM_DESC argument.
2818 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2820 * Makefile.in (SIM_OBJS): Add common modules.
2822 * interp.c (sim_set_callbacks): Also set SD callback.
2823 (set_endianness, xfer_*, swap_*): Delete.
2824 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2825 Change to functions using sim-endian macros.
2826 (control_c, sim_stop): Delete, use common version.
2827 (simulate): Convert into.
2828 (sim_engine_run): This function.
2829 (sim_resume): Delete.
2831 * interp.c (simulation): New variable - the simulator object.
2832 (sim_kind): Delete global - merged into simulation.
2833 (sim_load): Cleanup. Move PC assignment from here.
2834 (sim_create_inferior): To here.
2836 * sim-main.h: New file.
2837 * interp.c (sim-main.h): Include.
2839 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2841 * configure: Regenerated to track ../common/aclocal.m4 changes.
2843 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2845 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2847 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2849 * gencode.c (build_instruction): DIV instructions: check
2850 for division by zero and integer overflow before using
2851 host's division operation.
2853 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2855 * Makefile.in (SIM_OBJS): Add sim-load.o.
2856 * interp.c: #include bfd.h.
2857 (target_byte_order): Delete.
2858 (sim_kind, myname, big_endian_p): New static locals.
2859 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2860 after argument parsing. Recognize -E arg, set endianness accordingly.
2861 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2862 load file into simulator. Set PC from bfd.
2863 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2864 (set_endianness): Use big_endian_p instead of target_byte_order.
2866 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2868 * interp.c (sim_size): Delete prototype - conflicts with
2869 definition in remote-sim.h. Correct definition.
2871 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2873 * configure: Regenerated to track ../common/aclocal.m4 changes.
2876 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2878 * interp.c (sim_open): New arg `kind'.
2880 * configure: Regenerated to track ../common/aclocal.m4 changes.
2882 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2884 * configure: Regenerated to track ../common/aclocal.m4 changes.
2886 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2888 * interp.c (sim_open): Set optind to 0 before calling getopt.
2890 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2892 * configure: Regenerated to track ../common/aclocal.m4 changes.
2894 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2896 * interp.c : Replace uses of pr_addr with pr_uword64
2897 where the bit length is always 64 independent of SIM_ADDR.
2898 (pr_uword64) : added.
2900 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2902 * configure: Re-generate.
2904 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2906 * configure: Regenerate to track ../common/aclocal.m4 changes.
2908 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2910 * interp.c (sim_open): New SIM_DESC result. Argument is now
2912 (other sim_*): New SIM_DESC argument.
2914 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2916 * interp.c: Fix printing of addresses for non-64-bit targets.
2917 (pr_addr): Add function to print address based on size.
2919 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2921 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2923 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2925 * gencode.c (build_mips16_operands): Correct computation of base
2926 address for extended PC relative instruction.
2928 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2930 * interp.c (mips16_entry): Add support for floating point cases.
2931 (SignalException): Pass floating point cases to mips16_entry.
2932 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2934 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2936 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2937 and then set the state to fmt_uninterpreted.
2938 (COP_SW): Temporarily set the state to fmt_word while calling
2941 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2943 * gencode.c (build_instruction): The high order may be set in the
2944 comparison flags at any ISA level, not just ISA 4.
2946 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2948 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2949 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2950 * configure.in: sinclude ../common/aclocal.m4.
2951 * configure: Regenerated.
2953 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2955 * configure: Rebuild after change to aclocal.m4.
2957 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2959 * configure configure.in Makefile.in: Update to new configure
2960 scheme which is more compatible with WinGDB builds.
2961 * configure.in: Improve comment on how to run autoconf.
2962 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2963 * Makefile.in: Use autoconf substitution to install common
2966 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2968 * gencode.c (build_instruction): Use BigEndianCPU instead of
2971 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2973 * interp.c (sim_monitor): Make output to stdout visible in
2974 wingdb's I/O log window.
2976 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2978 * support.h: Undo previous change to SIGTRAP
2981 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2983 * interp.c (store_word, load_word): New static functions.
2984 (mips16_entry): New static function.
2985 (SignalException): Look for mips16 entry and exit instructions.
2986 (simulate): Use the correct index when setting fpr_state after
2987 doing a pending move.
2989 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2991 * interp.c: Fix byte-swapping code throughout to work on
2992 both little- and big-endian hosts.
2994 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2996 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2997 with gdb/config/i386/xm-windows.h.
2999 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3001 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3002 that messes up arithmetic shifts.
3004 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3006 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3007 SIGTRAP and SIGQUIT for _WIN32.
3009 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3011 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3012 force a 64 bit multiplication.
3013 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3014 destination register is 0, since that is the default mips16 nop
3017 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3019 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3020 (build_endian_shift): Don't check proc64.
3021 (build_instruction): Always set memval to uword64. Cast op2 to
3022 uword64 when shifting it left in memory instructions. Always use
3023 the same code for stores--don't special case proc64.
3025 * gencode.c (build_mips16_operands): Fix base PC value for PC
3027 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3029 * interp.c (simJALDELAYSLOT): Define.
3030 (JALDELAYSLOT): Define.
3031 (INDELAYSLOT, INJALDELAYSLOT): Define.
3032 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3034 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3036 * interp.c (sim_open): add flush_cache as a PMON routine
3037 (sim_monitor): handle flush_cache by ignoring it
3039 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3041 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3043 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3044 (BigEndianMem): Rename to ByteSwapMem and change sense.
3045 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3046 BigEndianMem references to !ByteSwapMem.
3047 (set_endianness): New function, with prototype.
3048 (sim_open): Call set_endianness.
3049 (sim_info): Use simBE instead of BigEndianMem.
3050 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3051 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3052 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3053 ifdefs, keeping the prototype declaration.
3054 (swap_word): Rewrite correctly.
3055 (ColdReset): Delete references to CONFIG. Delete endianness related
3056 code; moved to set_endianness.
3058 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3060 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3061 * interp.c (CHECKHILO): Define away.
3062 (simSIGINT): New macro.
3063 (membank_size): Increase from 1MB to 2MB.
3064 (control_c): New function.
3065 (sim_resume): Rename parameter signal to signal_number. Add local
3066 variable prev. Call signal before and after simulate.
3067 (sim_stop_reason): Add simSIGINT support.
3068 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3070 (sim_warning): Delete call to SignalException. Do call printf_filtered
3072 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3073 a call to sim_warning.
3075 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3077 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3078 16 bit instructions.
3080 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3082 Add support for mips16 (16 bit MIPS implementation):
3083 * gencode.c (inst_type): Add mips16 instruction encoding types.
3084 (GETDATASIZEINSN): Define.
3085 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3086 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3088 (MIPS16_DECODE): New table, for mips16 instructions.
3089 (bitmap_val): New static function.
3090 (struct mips16_op): Define.
3091 (mips16_op_table): New table, for mips16 operands.
3092 (build_mips16_operands): New static function.
3093 (process_instructions): If PC is odd, decode a mips16
3094 instruction. Break out instruction handling into new
3095 build_instruction function.
3096 (build_instruction): New static function, broken out of
3097 process_instructions. Check modifiers rather than flags for SHIFT
3098 bit count and m[ft]{hi,lo} direction.
3099 (usage): Pass program name to fprintf.
3100 (main): Remove unused variable this_option_optind. Change
3101 ``*loptarg++'' to ``loptarg++''.
3102 (my_strtoul): Parenthesize && within ||.
3103 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3104 (simulate): If PC is odd, fetch a 16 bit instruction, and
3105 increment PC by 2 rather than 4.
3106 * configure.in: Add case for mips16*-*-*.
3107 * configure: Rebuild.
3109 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3111 * interp.c: Allow -t to enable tracing in standalone simulator.
3112 Fix garbage output in trace file and error messages.
3114 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3116 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3117 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3118 * configure.in: Simplify using macros in ../common/aclocal.m4.
3119 * configure: Regenerated.
3120 * tconfig.in: New file.
3122 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3124 * interp.c: Fix bugs in 64-bit port.
3125 Use ansi function declarations for msvc compiler.
3126 Initialize and test file pointer in trace code.
3127 Prevent duplicate definition of LAST_EMED_REGNUM.
3129 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3131 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3133 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3135 * interp.c (SignalException): Check for explicit terminating
3137 * gencode.c: Pass instruction value through SignalException()
3138 calls for Trap, Breakpoint and Syscall.
3140 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3142 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3143 only used on those hosts that provide it.
3144 * configure.in: Add sqrt() to list of functions to be checked for.
3145 * config.in: Re-generated.
3146 * configure: Re-generated.
3148 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3150 * gencode.c (process_instructions): Call build_endian_shift when
3151 expanding STORE RIGHT, to fix swr.
3152 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3153 clear the high bits.
3154 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3155 Fix float to int conversions to produce signed values.
3157 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3159 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3160 (process_instructions): Correct handling of nor instruction.
3161 Correct shift count for 32 bit shift instructions. Correct sign
3162 extension for arithmetic shifts to not shift the number of bits in
3163 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3164 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3166 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3167 It's OK to have a mult follow a mult. What's not OK is to have a
3168 mult follow an mfhi.
3169 (Convert): Comment out incorrect rounding code.
3171 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3173 * interp.c (sim_monitor): Improved monitor printf
3174 simulation. Tidied up simulator warnings, and added "--log" option
3175 for directing warning message output.
3176 * gencode.c: Use sim_warning() rather than WARNING macro.
3178 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3180 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3181 getopt1.o, rather than on gencode.c. Link objects together.
3182 Don't link against -liberty.
3183 (gencode.o, getopt.o, getopt1.o): New targets.
3184 * gencode.c: Include <ctype.h> and "ansidecl.h".
3185 (AND): Undefine after including "ansidecl.h".
3186 (ULONG_MAX): Define if not defined.
3187 (OP_*): Don't define macros; now defined in opcode/mips.h.
3188 (main): Call my_strtoul rather than strtoul.
3189 (my_strtoul): New static function.
3191 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3193 * gencode.c (process_instructions): Generate word64 and uword64
3194 instead of `long long' and `unsigned long long' data types.
3195 * interp.c: #include sysdep.h to get signals, and define default
3197 * (Convert): Work around for Visual-C++ compiler bug with type
3199 * support.h: Make things compile under Visual-C++ by using
3200 __int64 instead of `long long'. Change many refs to long long
3201 into word64/uword64 typedefs.
3203 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3205 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3206 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3208 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3209 (AC_PROG_INSTALL): Added.
3210 (AC_PROG_CC): Moved to before configure.host call.
3211 * configure: Rebuilt.
3213 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3215 * configure.in: Define @SIMCONF@ depending on mips target.
3216 * configure: Rebuild.
3217 * Makefile.in (run): Add @SIMCONF@ to control simulator
3219 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3220 * interp.c: Remove some debugging, provide more detailed error
3221 messages, update memory accesses to use LOADDRMASK.
3223 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3225 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3226 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3228 * configure: Rebuild.
3229 * config.in: New file, generated by autoheader.
3230 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3231 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3232 HAVE_ANINT and HAVE_AINT, as appropriate.
3233 * Makefile.in (run): Use @LIBS@ rather than -lm.
3234 (interp.o): Depend upon config.h.
3235 (Makefile): Just rebuild Makefile.
3236 (clean): Remove stamp-h.
3237 (mostlyclean): Make the same as clean, not as distclean.
3238 (config.h, stamp-h): New targets.
3240 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3242 * interp.c (ColdReset): Fix boolean test. Make all simulator
3245 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3247 * interp.c (xfer_direct_word, xfer_direct_long,
3248 swap_direct_word, swap_direct_long, xfer_big_word,
3249 xfer_big_long, xfer_little_word, xfer_little_long,
3250 swap_word,swap_long): Added.
3251 * interp.c (ColdReset): Provide function indirection to
3252 host<->simulated_target transfer routines.
3253 * interp.c (sim_store_register, sim_fetch_register): Updated to
3254 make use of indirected transfer routines.
3256 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3258 * gencode.c (process_instructions): Ensure FP ABS instruction
3260 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3261 system call support.
3263 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3265 * interp.c (sim_do_command): Complain if callback structure not
3268 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3270 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3271 support for Sun hosts.
3272 * Makefile.in (gencode): Ensure the host compiler and libraries
3273 used for cross-hosted build.
3275 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3277 * interp.c, gencode.c: Some more (TODO) tidying.
3279 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3281 * gencode.c, interp.c: Replaced explicit long long references with
3282 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3283 * support.h (SET64LO, SET64HI): Macros added.
3285 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3287 * configure: Regenerate with autoconf 2.7.
3289 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3291 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3292 * support.h: Remove superfluous "1" from #if.
3293 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3295 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3297 * interp.c (StoreFPR): Control UndefinedResult() call on
3298 WARN_RESULT manifest.
3300 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3302 * gencode.c: Tidied instruction decoding, and added FP instruction
3305 * interp.c: Added dineroIII, and BSD profiling support. Also
3306 run-time FP handling.
3308 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3310 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3311 gencode.c, interp.c, support.h: created.