sim/mips/ChangeLog

   1 2007-02-17  Thiemo Seufer  <ths@mips.com>
   2
   3         * configure.ac (mips*-sde-elf*): Move in front of generic machine
   4         configuration.
   5         * configure: Regenerate.
   6
   7 2007-02-17  Thiemo Seufer  <ths@mips.com>
   8
   9         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
  10         Add mdmx to sim_igen_machine.
  11         (mipsisa64*-*-*): Likewise. Remove dsp.
  12         (mipsisa32*-*-*): Remove dsp.
  13         * configure: Regenerate.
  14
  15 2007-02-13  Thiemo Seufer  <ths@mips.com>
  16
  17         * configure.ac: Add mips*-sde-elf* target.
  18         * configure: Regenerate.
  19
  20 2006-12-21  Hans-Peter Nilsson  <hp@axis.com>
  21
  22         * acconfig.h: Remove.
  23         * config.in, configure: Regenerate.
  24
  25 2006-11-07  Thiemo Seufer  <ths@mips.com>
  26
  27         * dsp.igen (do_w_op): Fix compiler warning.
  28
  29 2006-08-29  Thiemo Seufer  <ths@mips.com>
  30             David Ung  <davidu@mips.com>
  31
  32         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
  33         sim_igen_machine.
  34         * configure: Regenerate.
  35         * mips.igen (model): Add smartmips.
  36         (MADDU): Increment ACX if carry.
  37         (do_mult): Clear ACX.
  38         (ROR,RORV): Add smartmips.
  39         (include): Include smartmips.igen.
  40         * sim-main.h (ACX): Set to REGISTERS[89].
  41         * smartmips.igen: New file.
  42
  43 2006-08-29  Thiemo Seufer  <ths@mips.com>
  44             David Ung  <davidu@mips.com>
  45
  46         * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
  47         mips3264r2.igen. Add missing dependency rules.
  48         * m16e.igen: Support for mips16e save/restore instructions.
  49
  50 2006-06-13  Richard Earnshaw  <rearnsha@arm.com>
  51
  52         * configure: Regenerated.
  53
  54 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
  55
  56         * configure: Regenerated.
  57
  58 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
  59
  60         * configure: Regenerated.
  61
  62 2006-05-15 Chao-ying Fu  <fu@mips.com>
  63
  64         * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
  65
  66 2006-04-18  Nick Clifton  <nickc@redhat.com>
  67
  68         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
  69         statement.
  70
  71 2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
  72
  73         * configure: Regenerate.
  74
  75 2005-12-14  Chao-ying Fu  <fu@mips.com>
  76
  77         * Makefile.in (SIM_OBJS): Add dsp.o.
  78         (dsp.o): New dependency.
  79         (IGEN_INCLUDE): Add dsp.igen.
  80         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
  81         mipsisa64*-*-*): Add dsp to sim_igen_machine.
  82         * configure: Regenerate.
  83         * mips.igen: Add dsp model and include dsp.igen.
  84         (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
  85         because these instructions are extended in DSP ASE.
  86         * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
  87         adding 6 DSP accumulator registers and 1 DSP control register.
  88         (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
  89         AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
  90         DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
  91         DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
  92         DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
  93         DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
  94         DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
  95         DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
  96         DSPCR_CCOND_SMASK): New define.
  97         (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
  98         * dsp.c, dsp.igen: New files for MIPS DSP ASE.
  99
 100 2005-07-08  Ian Lance Taylor  <ian@airs.com>
 101
 102         * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
 103
 104 2005-06-16  David Ung  <davidu@mips.com>
 105             Nigel Stephens  <nigel@mips.com>
 106
 107         * mips.igen: New mips16e model and include m16e.igen.
 108         (check_u64): Add mips16e tag.
 109         * m16e.igen: New file for MIPS16e instructions.
 110         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
 111         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
 112         models.
 113         * configure: Regenerate.
 114
 115 2005-05-26  David Ung  <davidu@mips.com>
 116
 117         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
 118         tags to all instructions which are applicable to the new ISAs.
 119         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
 120         vr.igen.
 121         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
 122         instructions.
 123         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
 124         to mips.igen.
 125         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
 126         * configure: Regenerate.
 127
 128 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
 129
 130         * configure: Regenerate.
 131
 132 2005-01-14  Andrew Cagney  <cagney@gnu.org>
 133
 134         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
 135         explicit call to AC_CONFIG_HEADER.
 136         * configure: Regenerate.
 137
 138 2005-01-12  Andrew Cagney  <cagney@gnu.org>
 139
 140         * configure.ac: Update to use ../common/common.m4.
 141         * configure: Re-generate.
 142
 143 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
 144
 145         * configure: Regenerated to track ../common/aclocal.m4 changes.
 146
 147 2005-01-07  Andrew Cagney  <cagney@gnu.org>
 148
 149         * configure.ac: Rename configure.in, require autoconf 2.59.
 150         * configure: Re-generate.
 151
 152 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
 153
 154         * configure: Regenerate for ../common/aclocal.m4 update.
 155
 156 2004-09-24  Monika Chaddha  <monika@acmet.com>
 157
 158         Committed by Andrew Cagney.
 159         * m16.igen (CMP, CMPI): Fix assembler.
 160
 161 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
 162
 163         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
 164         * configure: Regenerate.
 165
 166 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
 167
 168         * configure.in (sim_m16_machine): Include mipsIII.
 169         * configure: Regenerate.
 170
 171 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 172
 173         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
 174         from COP0_BADVADDR.
 175         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
 176
 177 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 178
 179         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
 180
 181 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 182
 183         * mips.igen (check_fmt): Remove.
 184         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
 185         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
 186         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
 187         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
 188         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
 189         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
 190         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 191         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
 192         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
 193         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
 194
 195 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 196
 197         * sb1.igen (check_sbx): New function.
 198         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
 199
 200 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
 201             Richard Sandiford  <rsandifo@redhat.com>
 202
 203         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 204         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 205         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 206         separate implementations for mipsIV and mipsV.  Use new macros to
 207         determine whether the restrictions apply.
 208
 209 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 210
 211         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 212         (check_mult_hilo): Improve comments.
 213         (check_div_hilo): Likewise.  Also, fork off a new version
 214         to handle mips32/mips64 (since there are no hazards to check
 215         in MIPS32/MIPS64).
 216
 217 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 218
 219         * mips.igen (do_dmultx): Fix check for negative operands.
 220
 221 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 222
 223         * Makefile.in (SHELL): Make sure this is defined.
 224         (various): Use $(SHELL) whenever we invoke move-if-change.
 225
 226 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 227
 228         * cp1.c: Tweak attribution slightly.
 229         * cp1.h: Likewise.
 230         * mdmx.c: Likewise.
 231         * mdmx.igen: Likewise.
 232         * mips3d.igen: Likewise.
 233         * sb1.igen: Likewise.
 234
 235 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 236
 237         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 238         unsigned operands.
 239
 240 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 241
 242         * interp.c (sim_open): Rename _bfd to bfd.
 243         (sim_create_inferior): Ditto.
 244
 245 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 246
 247         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 248
 249 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 250
 251         * mips.igen (EI, DI): Remove.
 252
 253 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 254
 255         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 256
 257 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 258             Andrew Cagney  <ac131313@redhat.com>
 259             Gavin Romig-Koch  <gavin@redhat.com>
 260             Graydon Hoare  <graydon@redhat.com>
 261             Aldy Hernandez  <aldyh@redhat.com>
 262             Dave Brolley  <brolley@redhat.com>
 263             Chris Demetriou  <cgd@broadcom.com>
 264
 265         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 266         (sim_mach_default): New variable.
 267         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 268         Add a new simulator generator, MULTI.
 269         * configure: Regenerate.
 270         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 271         (multi-run.o): New dependency.
 272         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 273         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 274         (tmp-multi): Combine them.
 275         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 276         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 277         (distclean-extra): New rule.
 278         * sim-main.h: Include bfd.h.
 279         (MIPS_MACH): New macro.
 280         * mips.igen (vr4120, vr5400, vr5500): New models.
 281         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 282         * vr.igen: Replace with new version.
 283
 284 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 285
 286         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 287         * configure: Regenerate.
 288
 289 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 290
 291         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 292         * mips.igen: Remove all invocations of check_branch_bug and
 293         mark_branch_bug.
 294
 295 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 296
 297         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 298
 299 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 300
 301         * mips.igen (do_load_double, do_store_double): New functions.
 302         (LDC1, SDC1): Rename to...
 303         (LDC1b, SDC1b): respectively.
 304         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 305
 306 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 307
 308         * cp1.c (fp_recip2): Modify initialization expression so that
 309         GCC will recognize it as constant.
 310
 311 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 312
 313         * mdmx.c (SD_): Delete.
 314         (Unpredictable): Re-define, for now, to directly invoke
 315         unpredictable_action().
 316         (mdmx_acc_op): Fix error in .ob immediate handling.
 317
 318 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 319
 320         * interp.c (sim_firmware_command): Initialize `address'.
 321
 322 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 323
 324         * configure: Regenerated to track ../common/aclocal.m4 changes.
 325
 326 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 327             Ed Satterthwaite  <ehs@broadcom.com>
 328
 329         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 330         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 331         * mips.igen: Include mips3d.igen.
 332         (mips3d): New model name for MIPS-3D ASE instructions.
 333         (CVT.W.fmt): Don't use this instruction for word (source) format
 334         instructions.
 335         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 336         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 337         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 338         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 339         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 340         (RSquareRoot1, RSquareRoot2): New macros.
 341         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 342         (fp_rsqrt2): New functions.
 343         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 344         * configure: Regenerate.
 345
 346 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 347             Ed Satterthwaite  <ehs@broadcom.com>
 348
 349         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 350         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 351         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 352         (convert): Note that this function is not used for paired-single
 353         format conversions.
 354         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 355         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 356         (check_fmt_p): Enable paired-single support.
 357         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 358         (PUU.PS): New instructions.
 359         (CVT.S.fmt): Don't use this instruction for paired-single format
 360         destinations.
 361         * sim-main.h (FP_formats): New value 'fmt_ps.'
 362         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 363         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 364
 365 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 366
 367         * mips.igen: Fix formatting of function calls in
 368         many FP operations.
 369
 370 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 371
 372         * mips.igen (MOVN, MOVZ): Trace result.
 373         (TNEI): Print "tnei" as the opcode name in traces.
 374         (CEIL.W): Add disassembly string for traces.
 375         (RSQRT.fmt): Make location of disassembly string consistent
 376         with other instructions.
 377
 378 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 379
 380         * mips.igen (X): Delete unused function.
 381
 382 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 383
 384         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 385
 386 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 387             Ed Satterthwaite  <ehs@broadcom.com>
 388
 389         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 390         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 391         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 392         (fp_nmsub): New prototypes.
 393         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 394         (NegMultiplySub): New defines.
 395         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 396         (MADD.D, MADD.S): Replace with...
 397         (MADD.fmt): New instruction.
 398         (MSUB.D, MSUB.S): Replace with...
 399         (MSUB.fmt): New instruction.
 400         (NMADD.D, NMADD.S): Replace with...
 401         (NMADD.fmt): New instruction.
 402         (NMSUB.D, MSUB.S): Replace with...
 403         (NMSUB.fmt): New instruction.
 404
 405 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 406             Ed Satterthwaite  <ehs@broadcom.com>
 407
 408         * cp1.c: Fix more comment spelling and formatting.
 409         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 410         (denorm_mode): New function.
 411         (fpu_unary, fpu_binary): Round results after operation, collect
 412         status from rounding operations, and update the FCSR.
 413         (convert): Collect status from integer conversions and rounding
 414         operations, and update the FCSR.  Adjust NaN values that result
 415         from conversions.  Convert to use sim_io_eprintf rather than
 416         fprintf, and remove some debugging code.
 417         * cp1.h (fenr_FS): New define.
 418
 419 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 420
 421         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 422         rounding mode to sim FP rounding mode flag conversion code into...
 423         (rounding_mode): New function.
 424
 425 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 426
 427         * cp1.c: Clean up formatting of a few comments.
 428         (value_fpr): Reformat switch statement.
 429
 430 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 431             Ed Satterthwaite  <ehs@broadcom.com>
 432
 433         * cp1.h: New file.
 434         * sim-main.h: Include cp1.h.
 435         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 436         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 437         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 438         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 439         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 440         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 441         * cp1.c: Don't include sim-fpu.h; already included by
 442         sim-main.h.  Clean up formatting of some comments.
 443         (NaN, Equal, Less): Remove.
 444         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 445         (fp_cmp): New functions.
 446         * mips.igen (do_c_cond_fmt): Remove.
 447         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 448         Compare.  Add result tracing.
 449         (CxC1): Remove, replace with...
 450         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 451         (DMxC1): Remove, replace with...
 452         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 453         (MxC1): Remove, replace with...
 454         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 455
 456 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 457
 458         * sim-main.h (FGRIDX): Remove, replace all uses with...
 459         (FGR_BASE): New macro.
 460         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 461         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 462         (NR_FGR, FGR): Likewise.
 463         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 464         * mips.igen: Likewise.
 465
 466 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 467
 468         * cp1.c: Add an FSF Copyright notice to this file.
 469
 470 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 471             Ed Satterthwaite  <ehs@broadcom.com>
 472
 473         * cp1.c (Infinity): Remove.
 474         * sim-main.h (Infinity): Likewise.
 475
 476         * cp1.c (fp_unary, fp_binary): New functions.
 477         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 478         (fp_sqrt): New functions, implemented in terms of the above.
 479         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 480         (Recip, SquareRoot): Remove (replaced by functions above).
 481         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 482         (fp_recip, fp_sqrt): New prototypes.
 483         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 484         (Recip, SquareRoot): Replace prototypes with #defines which
 485         invoke the functions above.
 486
 487 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 488
 489         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 490         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 491         file, remove PARAMS from prototypes.
 492         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 493         simulator state arguments.
 494         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 495         pass simulator state arguments.
 496         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 497         (store_fpr, convert): Remove 'sd' argument.
 498         (value_fpr): Likewise.  Convert to use 'SD' instead.
 499
 500 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 501
 502         * cp1.c (Min, Max): Remove #if 0'd functions.
 503         * sim-main.h (Min, Max): Remove.
 504
 505 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 506
 507         * cp1.c: fix formatting of switch case and default labels.
 508         * interp.c: Likewise.
 509         * sim-main.c: Likewise.
 510
 511 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 512
 513         * cp1.c: Clean up comments which describe FP formats.
 514          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 515
 516 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 517             Ed Satterthwaite  <ehs@broadcom.com>
 518
 519         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 520         Broadcom SiByte SB-1 processor configurations.
 521         * configure: Regenerate.
 522         * sb1.igen: New file.
 523         * mips.igen: Include sb1.igen.
 524         (sb1): New model.
 525         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 526         * mdmx.igen: Add "sb1" model to all appropriate functions and
 527         instructions.
 528         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 529         (ob_func, ob_acc): Reference the above.
 530         (qh_acc): Adjust to keep the same size as ob_acc.
 531         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 532         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 533
 534 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 535
 536         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 537
 538 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 539             Ed Satterthwaite  <ehs@broadcom.com>
 540
 541         * mips.igen (mdmx): New (pseudo-)model.
 542         * mdmx.c, mdmx.igen: New files.
 543         * Makefile.in (SIM_OBJS): Add mdmx.o.
 544         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 545         New typedefs.
 546         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 547         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 548         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 549         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 550         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 551         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 552         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 553         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 554         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 555         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 556         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 557         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 558         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 559         (qh_fmtsel): New macros.
 560         (_sim_cpu): New member "acc".
 561         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 562         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 563
 564 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 565
 566         * interp.c: Use 'deprecated' rather than 'depreciated.'
 567         * sim-main.h: Likewise.
 568
 569 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 570
 571         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 572         which wouldn't compile anyway.
 573         * sim-main.h (unpredictable_action): New function prototype.
 574         (Unpredictable): Define to call igen function unpredictable().
 575         (NotWordValue): New macro to call igen function not_word_value().
 576         (UndefinedResult): Remove.
 577         * interp.c (undefined_result): Remove.
 578         (unpredictable_action): New function.
 579         * mips.igen (not_word_value, unpredictable): New functions.
 580         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 581         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 582         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 583         NotWordValue() to check for unpredictable inputs, then
 584         Unpredictable() to handle them.
 585
 586 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 587
 588         * mips.igen: Fix formatting of calls to Unpredictable().
 589
 590 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 591
 592         * interp.c (sim_open): Revert previous change.
 593
 594 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 595
 596         * interp.c (sim_open): Disable chunk of code that wrote code in
 597         vector table entries.
 598
 599 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 600
 601         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 602         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 603         unused definitions.
 604
 605 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 606
 607         * cp1.c: Fix many formatting issues.
 608
 609 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 610
 611         * cp1.c (fpu_format_name): New function to replace...
 612         (DOFMT): This.  Delete, and update all callers.
 613         (fpu_rounding_mode_name): New function to replace...
 614         (RMMODE): This.  Delete, and update all callers.
 615
 616 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 617
 618         * interp.c: Move FPU support routines from here to...
 619         * cp1.c: Here.  New file.
 620         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 621         (cp1.o): New target.
 622
 623 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 624
 625         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 626         * mips.igen (mips32, mips64): New models, add to all instructions
 627         and functions as appropriate.
 628         (loadstore_ea, check_u64): New variant for model mips64.
 629         (check_fmt_p): New variant for models mipsV and mips64, remove
 630         mipsV model marking fro other variant.
 631         (SLL) Rename to...
 632         (SLLa) this.
 633         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 634         for mips32 and mips64.
 635         (DCLO, DCLZ): New instructions for mips64.
 636
 637 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 638
 639         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 640         immediate or code as a hex value with the "%#lx" format.
 641         (ANDI): Likewise, and fix printed instruction name.
 642
 643 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 644
 645         * sim-main.h (UndefinedResult, Unpredictable): New macros
 646         which currently do nothing.
 647
 648 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 649
 650         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 651         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 652         (status_CU3): New definitions.
 653
 654         * sim-main.h (ExceptionCause): Add new values for MIPS32
 655         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 656         for DebugBreakPoint and NMIReset to note their status in
 657         MIPS32 and MIPS64.
 658         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 659         (SignalExceptionCacheErr): New exception macros.
 660
 661 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 662
 663         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 664         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 665         is always enabled.
 666         (SignalExceptionCoProcessorUnusable): Take as argument the
 667         unusable coprocessor number.
 668
 669 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 670
 671         * mips.igen: Fix formatting of all SignalException calls.
 672
 673 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 674
 675         * sim-main.h (SIGNEXTEND): Remove.
 676
 677 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 678
 679         * mips.igen: Remove gencode comment from top of file, fix
 680         spelling in another comment.
 681
 682 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 683
 684         * mips.igen (check_fmt, check_fmt_p): New functions to check
 685         whether specific floating point formats are usable.
 686         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 687         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 688         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 689         Use the new functions.
 690         (do_c_cond_fmt): Remove format checks...
 691         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 692
 693 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 694
 695         * mips.igen: Fix formatting of check_fpu calls.
 696
 697 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 698
 699         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 700
 701 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 702
 703         * mips.igen: Remove whitespace at end of lines.
 704
 705 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 706
 707         * mips.igen (loadstore_ea): New function to do effective
 708         address calculations.
 709         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 710         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 711         CACHE): Use loadstore_ea to do effective address computations.
 712
 713 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 714
 715         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 716         * mips.igen (LL, CxC1, MxC1): Likewise.
 717
 718 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 719
 720         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 721         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 722         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 723         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 724         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 725         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 726         Don't split opcode fields by hand, use the opcode field values
 727         provided by igen.
 728
 729 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 730
 731         * mips.igen (do_divu): Fix spacing.
 732
 733         * mips.igen (do_dsllv): Move to be right before DSLLV,
 734         to match the rest of the do_<shift> functions.
 735
 736 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 737
 738         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 739         DSRL32, do_dsrlv): Trace inputs and results.
 740
 741 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 742
 743         * mips.igen (CACHE): Provide instruction-printing string.
 744
 745         * interp.c (signal_exception): Comment tokens after #endif.
 746
 747 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 748
 749         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 750         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 751         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 752         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 753         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 754         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 755         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 756         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 757
 758 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 759
 760         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 761         instruction-printing string.
 762         (LWU): Use '64' as the filter flag.
 763
 764 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 765
 766         * mips.igen (SDXC1): Fix instruction-printing string.
 767
 768 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 769
 770         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 771         filter flags "32,f".
 772
 773 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 774
 775         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 776         as the filter flag.
 777
 778 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 779
 780         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 781         add a comma) so that it more closely match the MIPS ISA
 782         documentation opcode partitioning.
 783         (PREF): Put useful names on opcode fields, and include
 784         instruction-printing string.
 785
 786 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 787
 788         * mips.igen (check_u64): New function which in the future will
 789         check whether 64-bit instructions are usable and signal an
 790         exception if not.  Currently a no-op.
 791         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 792         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 793         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 794         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 795
 796         * mips.igen (check_fpu): New function which in the future will
 797         check whether FPU instructions are usable and signal an exception
 798         if not.  Currently a no-op.
 799         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 800         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 801         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 802         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 803         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 804         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 805         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 806         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 807
 808 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 809
 810         * mips.igen (do_load_left, do_load_right): Move to be immediately
 811         following do_load.
 812         (do_store_left, do_store_right): Move to be immediately following
 813         do_store.
 814
 815 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 816
 817         * mips.igen (mipsV): New model name.  Also, add it to
 818         all instructions and functions where it is appropriate.
 819
 820 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 821
 822         * mips.igen: For all functions and instructions, list model
 823         names that support that instruction one per line.
 824
 825 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 826
 827         * mips.igen: Add some additional comments about supported
 828         models, and about which instructions go where.
 829         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 830         order as is used in the rest of the file.
 831
 832 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 833
 834         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 835         indicating that ALU32_END or ALU64_END are there to check
 836         for overflow.
 837         (DADD): Likewise, but also remove previous comment about
 838         overflow checking.
 839
 840 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 841
 842         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 843         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 844         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 845         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 846         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 847         fields (i.e., add and move commas) so that they more closely
 848         match the MIPS ISA documentation opcode partitioning.
 849
 850 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 851
 852         * mips.igen (ADDI): Print immediate value.
 853         (BREAK): Print code.
 854         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 855         (SLL): Print "nop" specially, and don't run the code
 856         that does the shift for the "nop" case.
 857
 858 2001-11-17  Fred Fish  <fnf@redhat.com>
 859
 860         * sim-main.h (float_operation): Move enum declaration outside
 861         of _sim_cpu struct declaration.
 862
 863 2001-04-12  Jim Blandy  <jimb@redhat.com>
 864
 865         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 866         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 867         set of the FCSR.
 868         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 869         PENDING_FILL, and you can get the intended effect gracefully by
 870         calling PENDING_SCHED directly.
 871
 872 2001-02-23  Ben Elliston  <bje@redhat.com>
 873
 874         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 875         already defined elsewhere.
 876
 877 2001-02-19  Ben Elliston  <bje@redhat.com>
 878
 879         * sim-main.h (sim_monitor): Return an int.
 880         * interp.c (sim_monitor): Add return values.
 881         (signal_exception): Handle error conditions from sim_monitor.
 882
 883 2001-02-08  Ben Elliston  <bje@redhat.com>
 884
 885         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 886         (store_memory): Likewise, pass cia to sim_core_write*.
 887
 888 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 889
 890         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 891         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 892
 893 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 894
 895         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 896         * Makefile.in: Don't delete *.igen when cleaning directory.
 897
 898 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 899
 900         * m16.igen (break): Call SignalException not sim_engine_halt.
 901
 902 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 903
 904         From Jason Eckhardt:
 905         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 906
 907 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 908
 909         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 910
 911 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 912
 913         * mips.igen (do_dmultx): Fix typo.
 914
 915 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 916
 917         * configure: Regenerated to track ../common/aclocal.m4 changes.
 918
 919 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 920
 921         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 922
 923 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 924
 925         * sim-main.h (GPR_CLEAR): Define macro.
 926
 927 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 928
 929         * interp.c (decode_coproc): Output long using %lx and not %s.
 930
 931 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 932
 933         * interp.c (sim_open): Sort & extend dummy memory regions for
 934         --board=jmr3904 for eCos.
 935
 936 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 937
 938         * configure: Regenerated.
 939
 940 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 941
 942         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 943         calls, conditional on the simulator being in verbose mode.
 944
 945 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 946
 947         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 948         cache don't get ReservedInstruction traps.
 949
 950 1999-11-29  Mark Salter  <msalter@cygnus.com>
 951
 952         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 953         to clear status bits in sdisr register. This is how the hardware works.
 954
 955         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 956         being used by cygmon.
 957
 958 1999-11-11  Andrew Haley  <aph@cygnus.com>
 959
 960         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 961         instructions.
 962
 963 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 964
 965         * mips.igen (MULT): Correct previous mis-applied patch.
 966
 967 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 968
 969         * mips.igen (delayslot32): Handle sequence like
 970         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 971         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 972         (MULT): Actually pass the third register...
 973
 974 1999-09-03  Mark Salter  <msalter@cygnus.com>
 975
 976         * interp.c (sim_open): Added more memory aliases for additional
 977         hardware being touched by cygmon on jmr3904 board.
 978
 979 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 980
 981         * configure: Regenerated to track ../common/aclocal.m4 changes.
 982
 983 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 984
 985         * interp.c (sim_store_register): Handle case where client - GDB -
 986         specifies that a 4 byte register is 8 bytes in size.
 987         (sim_fetch_register): Ditto.
 988
 989 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 990
 991         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 992         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 993         (idt_monitor_base): Base address for IDT monitor traps.
 994         (pmon_monitor_base): Ditto for PMON.
 995         (lsipmon_monitor_base): Ditto for LSI PMON.
 996         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 997         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 998         (sim_firmware_command): New function.
 999         (mips_option_handler): Call it for OPTION_FIRMWARE.
1000         (sim_open): Allocate memory for idt_monitor region.  If "--board"
1001         option was given, add no monitor by default.  Add BREAK hooks only if
1002         monitors are also there.
1003
1004 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1005
1006         * interp.c (sim_monitor): Flush output before reading input.
1007
1008 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1009
1010         * tconfig.in (SIM_HANDLES_LMA): Always define.
1011
1012 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1013
1014         From Mark Salter <msalter@cygnus.com>:
1015         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
1016         (sim_open): Add setup for BSP board.
1017
1018 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1019
1020         * mips.igen (MULT, MULTU): Add syntax for two operand version.
1021         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
1022         them as unimplemented.
1023
1024 1999-05-08  Felix Lee  <flee@cygnus.com>
1025
1026         * configure: Regenerated to track ../common/aclocal.m4 changes.
1027
1028 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
1029
1030         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1031
1032 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1033
1034         * configure.in: Any mips64vr5*-*-* target should have
1035         -DTARGET_ENABLE_FR=1.
1036         (default_endian): Any mips64vr*el-*-* target should default to
1037         LITTLE_ENDIAN.
1038         * configure: Re-generate.
1039
1040 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
1041
1042         * mips.igen (ldl): Extend from _16_, not 32.
1043
1044 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
1045
1046         * interp.c (sim_store_register): Force registers written to by GDB
1047         into an un-interpreted state.
1048
1049 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
1050
1051         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1052         CPU, start periodic background I/O polls.
1053         (tx3904sio_poll): New function: periodic I/O poller.
1054
1055 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
1056
1057         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1058
1059 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
1060
1061         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1062         case statement.
1063
1064 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
1065
1066         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1067         (load_word): Call SIM_CORE_SIGNAL hook on error.
1068         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1069         starting.  For exception dispatching, pass PC instead of NULL_CIA.
1070         (decode_coproc): Use COP0_BADVADDR to store faulting address.
1071         * sim-main.h (COP0_BADVADDR): Define.
1072         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1073         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1074         (_sim_cpu): Add exc_* fields to store register value snapshots.
1075         * mips.igen (*): Replace memory-related SignalException* calls
1076         with references to SIM_CORE_SIGNAL hook.
1077
1078         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1079         fix.
1080         * sim-main.c (*): Minor warning cleanups.
1081
1082 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
1083
1084         * m16.igen (DADDIU5): Correct type-o.
1085
1086 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
1087
1088         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1089         variables.
1090
1091 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
1092
1093         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1094         to include path.
1095         (interp.o): Add dependency on itable.h
1096         (oengine.c, gencode): Delete remaining references.
1097         (BUILT_SRC_FROM_GEN): Clean up.
1098
1099 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
1100
1101         * vr4run.c: New.
1102         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1103         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1104         tmp-run-hack) : New.
1105         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1106         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1107         Drop the "64" qualifier to get the HACK generator working.
1108         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1109         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1110         qualifier to get the hack generator working.
1111         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1112         (DSLL): Use do_dsll.
1113         (DSLLV): Use do_dsllv.
1114         (DSRA): Use do_dsra.
1115         (DSRL): Use do_dsrl.
1116         (DSRLV): Use do_dsrlv.
1117         (BC1): Move *vr4100 to get the HACK generator working.
1118         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1119         get the HACK generator working.
1120         (MACC) Rename to get the HACK generator working.
1121         (DMACC,MACCS,DMACCS): Add the 64.
1122
1123 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1124
1125         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1126         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1127
1128 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1129
1130     * mips/interp.c (DEBUG): Cleanups.
1131
1132 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1133
1134         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1135         (tx3904sio_tickle): fflush after a stdout character output.
1136
1137 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1138
1139         * interp.c (sim_close): Uninstall modules.
1140
1141 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1142
1143         * sim-main.h, interp.c (sim_monitor): Change to global
1144         function.
1145
1146 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1147
1148         * configure.in (vr4100): Only include vr4100 instructions in
1149         simulator.
1150         * configure: Re-generate.
1151         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1152
1153 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1154
1155         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1156         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1157         true alternative.
1158
1159         * configure.in (sim_default_gen, sim_use_gen): Replace with
1160         sim_gen.
1161         (--enable-sim-igen): Delete config option. Always using IGEN.
1162         * configure: Re-generate.
1163
1164         * Makefile.in (gencode): Kill, kill, kill.
1165         * gencode.c: Ditto.
1166
1167 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1168
1169         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1170         bit mips16 igen simulator.
1171         * configure: Re-generate.
1172
1173         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1174         as part of vr4100 ISA.
1175         * vr.igen: Mark all instructions as 64 bit only.
1176
1177 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1178
1179         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1180         Pacify GCC.
1181
1182 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1183
1184         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1185         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1186         * configure: Re-generate.
1187
1188         * m16.igen (BREAK): Define breakpoint instruction.
1189         (JALX32): Mark instruction as mips16 and not r3900.
1190         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1191
1192         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1193
1194 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1195
1196         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1197         insn as a debug breakpoint.
1198
1199         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1200         pending.slot_size.
1201         (PENDING_SCHED): Clean up trace statement.
1202         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1203         (PENDING_FILL): Delay write by only one cycle.
1204         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1205
1206         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1207         of pending writes.
1208         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1209         32 & 64.
1210         (pending_tick): Move incrementing of index to FOR statement.
1211         (pending_tick): Only update PENDING_OUT after a write has occured.
1212
1213         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1214         build simulator.
1215         * configure: Re-generate.
1216
1217         * interp.c (sim_engine_run OLD): Delete explicit call to
1218         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1219
1220 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1221
1222         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1223         interrupt level number to match changed SignalExceptionInterrupt
1224         macro.
1225
1226 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1227
1228         * interp.c: #include "itable.h" if WITH_IGEN.
1229         (get_insn_name): New function.
1230         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1231         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1232
1233 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1234
1235         * configure: Rebuilt to inhale new common/aclocal.m4.
1236
1237 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1238
1239         * dv-tx3904sio.c: Include sim-assert.h.
1240
1241 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1242
1243         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1244         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1245         Reorganize target-specific sim-hardware checks.
1246         * configure: rebuilt.
1247         * interp.c (sim_open): For tx39 target boards, set
1248         OPERATING_ENVIRONMENT, add tx3904sio devices.
1249         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1250         ROM executables.  Install dv-sockser into sim-modules list.
1251
1252         * dv-tx3904irc.c: Compiler warning clean-up.
1253         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1254         frequent hw-trace messages.
1255
1256 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1257
1258         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1259
1260 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1261
1262         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1263
1264         * vr.igen: New file.
1265         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1266         * mips.igen: Define vr4100 model. Include vr.igen.
1267 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1268
1269         * mips.igen (check_mf_hilo): Correct check.
1270
1271 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1272
1273         * sim-main.h (interrupt_event): Add prototype.
1274
1275         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1276         register_ptr, register_value.
1277         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1278
1279         * sim-main.h (tracefh): Make extern.
1280
1281 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1282
1283         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1284         Reduce unnecessarily high timer event frequency.
1285         * dv-tx3904cpu.c: Ditto for interrupt event.
1286
1287 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1288
1289         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1290         to allay warnings.
1291         (interrupt_event): Made non-static.
1292
1293         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1294         interchange of configuration values for external vs. internal
1295         clock dividers.
1296
1297 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1298
1299         * mips.igen (BREAK): Moved code to here for
1300         simulator-reserved break instructions.
1301         * gencode.c (build_instruction): Ditto.
1302         * interp.c (signal_exception): Code moved from here.  Non-
1303         reserved instructions now use exception vector, rather
1304         than halting sim.
1305         * sim-main.h: Moved magic constants to here.
1306
1307 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1308
1309         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1310         register upon non-zero interrupt event level, clear upon zero
1311         event value.
1312         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1313         by passing zero event value.
1314         (*_io_{read,write}_buffer): Endianness fixes.
1315         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1316         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1317
1318         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1319         serial I/O and timer module at base address 0xFFFF0000.
1320
1321 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1322
1323         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1324         and BigEndianCPU.
1325
1326 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1327
1328         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1329         parts.
1330         * configure: Update.
1331
1332 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1333
1334         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1335         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1336         * configure.in: Include tx3904tmr in hw_device list.
1337         * configure: Rebuilt.
1338         * interp.c (sim_open): Instantiate three timer instances.
1339         Fix address typo of tx3904irc instance.
1340
1341 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1342
1343         * interp.c (signal_exception): SystemCall exception now uses
1344         the exception vector.
1345
1346 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1347
1348         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1349         to allay warnings.
1350
1351 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1352
1353         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1354
1355 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1356
1357         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1358
1359         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1360         sim-main.h. Declare a struct hw_descriptor instead of struct
1361         hw_device_descriptor.
1362
1363 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1364
1365         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1366         right bits and then re-align left hand bytes to correct byte
1367         lanes.  Fix incorrect computation in do_store_left when loading
1368         bytes from second word.
1369
1370 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1371
1372         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1373         * interp.c (sim_open): Only create a device tree when HW is
1374         enabled.
1375
1376         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1377         * interp.c (signal_exception): Ditto.
1378
1379 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1380
1381         * gencode.c: Mark BEGEZALL as LIKELY.
1382
1383 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1384
1385         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1386         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1387
1388 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1389
1390         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1391         modules.  Recognize TX39 target with "mips*tx39" pattern.
1392         * configure: Rebuilt.
1393         * sim-main.h (*): Added many macros defining bits in
1394         TX39 control registers.
1395         (SignalInterrupt): Send actual PC instead of NULL.
1396         (SignalNMIReset): New exception type.
1397         * interp.c (board): New variable for future use to identify
1398         a particular board being simulated.
1399         (mips_option_handler,mips_options): Added "--board" option.
1400         (interrupt_event): Send actual PC.
1401         (sim_open): Make memory layout conditional on board setting.
1402         (signal_exception): Initial implementation of hardware interrupt
1403         handling.  Accept another break instruction variant for simulator
1404         exit.
1405         (decode_coproc): Implement RFE instruction for TX39.
1406         (mips.igen): Decode RFE instruction as such.
1407         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1408         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1409         bbegin to implement memory map.
1410         * dv-tx3904cpu.c: New file.
1411         * dv-tx3904irc.c: New file.
1412
1413 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1414
1415         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1416
1417 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1418
1419         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1420         with calls to check_div_hilo.
1421
1422 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1423
1424         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1425         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1426         Add special r3900 version of do_mult_hilo.
1427         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1428         with calls to check_mult_hilo.
1429         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1430         with calls to check_div_hilo.
1431
1432 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1433
1434         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1435         Document a replacement.
1436
1437 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1438
1439         * interp.c (sim_monitor): Make mon_printf work.
1440
1441 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1442
1443         * sim-main.h (INSN_NAME): New arg `cpu'.
1444
1445 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1446
1447         * configure: Regenerated to track ../common/aclocal.m4 changes.
1448
1449 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1450
1451         * configure: Regenerated to track ../common/aclocal.m4 changes.
1452         * config.in: Ditto.
1453
1454 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1455
1456         * acconfig.h: New file.
1457         * configure.in: Reverted change of Apr 24; use sinclude again.
1458
1459 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1460
1461         * configure: Regenerated to track ../common/aclocal.m4 changes.
1462         * config.in: Ditto.
1463
1464 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1465
1466         * configure.in: Don't call sinclude.
1467
1468 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1469
1470         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1471
1472 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1473
1474         * mips.igen (ERET): Implement.
1475
1476         * interp.c (decode_coproc): Return sign-extended EPC.
1477
1478         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1479
1480         * interp.c (signal_exception): Do not ignore Trap.
1481         (signal_exception): On TRAP, restart at exception address.
1482         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1483         (signal_exception): Update.
1484         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1485         so that TRAP instructions are caught.
1486
1487 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1488
1489         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1490         contains HI/LO access history.
1491         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1492         (HIACCESS, LOACCESS): Delete, replace with
1493         (HIHISTORY, LOHISTORY): New macros.
1494         (CHECKHILO): Delete all, moved to mips.igen
1495
1496         * gencode.c (build_instruction): Do not generate checks for
1497         correct HI/LO register usage.
1498
1499         * interp.c (old_engine_run): Delete checks for correct HI/LO
1500         register usage.
1501
1502         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1503         check_mf_cycles): New functions.
1504         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1505         do_divu, domultx, do_mult, do_multu): Use.
1506
1507         * tx.igen ("madd", "maddu"): Use.
1508
1509 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1510
1511         * mips.igen (DSRAV): Use function do_dsrav.
1512         (SRAV): Use new function do_srav.
1513
1514         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1515         (B): Sign extend 11 bit immediate.
1516         (EXT-B*): Shift 16 bit immediate left by 1.
1517         (ADDIU*): Don't sign extend immediate value.
1518
1519 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1520
1521         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1522
1523         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1524         functions.
1525
1526         * mips.igen (delayslot32, nullify_next_insn): New functions.
1527         (m16.igen): Always include.
1528         (do_*): Add more tracing.
1529
1530         * m16.igen (delayslot16): Add NIA argument, could be called by a
1531         32 bit MIPS16 instruction.
1532
1533         * interp.c (ifetch16): Move function from here.
1534         * sim-main.c (ifetch16): To here.
1535
1536         * sim-main.c (ifetch16, ifetch32): Update to match current
1537         implementations of LH, LW.
1538         (signal_exception): Don't print out incorrect hex value of illegal
1539         instruction.
1540
1541 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1542
1543         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1544         instruction.
1545
1546         * m16.igen: Implement MIPS16 instructions.
1547
1548         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1549         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1550         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1551         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1552         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1553         bodies of corresponding code from 32 bit insn to these.  Also used
1554         by MIPS16 versions of functions.
1555
1556         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1557         (IMEM16): Drop NR argument from macro.
1558
1559 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1560
1561         * Makefile.in (SIM_OBJS): Add sim-main.o.
1562
1563         * sim-main.h (address_translation, load_memory, store_memory,
1564         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1565         as INLINE_SIM_MAIN.
1566         (pr_addr, pr_uword64): Declare.
1567         (sim-main.c): Include when H_REVEALS_MODULE_P.
1568
1569         * interp.c (address_translation, load_memory, store_memory,
1570         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1571         from here.
1572         * sim-main.c: To here. Fix compilation problems.
1573
1574         * configure.in: Enable inlining.
1575         * configure: Re-config.
1576
1577 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1578
1579         * configure: Regenerated to track ../common/aclocal.m4 changes.
1580
1581 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1582
1583         * mips.igen: Include tx.igen.
1584         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1585         * tx.igen: New file, contains MADD and MADDU.
1586
1587         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1588         the hardwired constant `7'.
1589         (store_memory): Ditto.
1590         (LOADDRMASK): Move definition to sim-main.h.
1591
1592         mips.igen (MTC0): Enable for r3900.
1593         (ADDU): Add trace.
1594
1595         mips.igen (do_load_byte): Delete.
1596         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1597         do_store_right): New functions.
1598         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1599
1600         configure.in: Let the tx39 use igen again.
1601         configure: Update.
1602
1603 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1604
1605         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1606         not an address sized quantity.  Return zero for cache sizes.
1607
1608 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1609
1610         * mips.igen (r3900): r3900 does not support 64 bit integer
1611         operations.
1612
1613 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1614
1615         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1616         than igen one.
1617         * configure : Rebuild.
1618
1619 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1620
1621         * configure: Regenerated to track ../common/aclocal.m4 changes.
1622
1623 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1624
1625         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1626
1627 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1628
1629         * configure: Regenerated to track ../common/aclocal.m4 changes.
1630         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1631
1632 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1633
1634         * configure: Regenerated to track ../common/aclocal.m4 changes.
1635
1636 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1637
1638         * interp.c (Max, Min): Comment out functions. Not yet used.
1639
1640 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1641
1642         * configure: Regenerated to track ../common/aclocal.m4 changes.
1643
1644 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1645
1646         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1647         configurable settings for stand-alone simulator.
1648
1649         * configure.in: Added X11 search, just in case.
1650
1651         * configure: Regenerated.
1652
1653 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1654
1655         * interp.c (sim_write, sim_read, load_memory, store_memory):
1656         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1657
1658 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1659
1660         * sim-main.h (GETFCC): Return an unsigned value.
1661
1662 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1663
1664         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1665         (DADD): Result destination is RD not RT.
1666
1667 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1668
1669         * sim-main.h (HIACCESS, LOACCESS): Always define.
1670
1671         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1672
1673         * interp.c (sim_info): Delete.
1674
1675 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1676
1677         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1678         (mips_option_handler): New argument `cpu'.
1679         (sim_open): Update call to sim_add_option_table.
1680
1681 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1682
1683         * mips.igen (CxC1): Add tracing.
1684
1685 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1686
1687         * sim-main.h (Max, Min): Declare.
1688
1689         * interp.c (Max, Min): New functions.
1690
1691         * mips.igen (BC1): Add tracing.
1692
1693 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1694
1695         * interp.c Added memory map for stack in vr4100
1696
1697 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1698
1699         * interp.c (load_memory): Add missing "break"'s.
1700
1701 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1702
1703         * interp.c (sim_store_register, sim_fetch_register): Pass in
1704         length parameter.  Return -1.
1705
1706 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1707
1708         * interp.c: Added hardware init hook, fixed warnings.
1709
1710 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1711
1712         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1713
1714 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1715
1716         * interp.c (ifetch16): New function.
1717
1718         * sim-main.h (IMEM32): Rename IMEM.
1719         (IMEM16_IMMED): Define.
1720         (IMEM16): Define.
1721         (DELAY_SLOT): Update.
1722
1723         * m16run.c (sim_engine_run): New file.
1724
1725         * m16.igen: All instructions except LB.
1726         (LB): Call do_load_byte.
1727         * mips.igen (do_load_byte): New function.
1728         (LB): Call do_load_byte.
1729
1730         * mips.igen: Move spec for insn bit size and high bit from here.
1731         * Makefile.in (tmp-igen, tmp-m16): To here.
1732
1733         * m16.dc: New file, decode mips16 instructions.
1734
1735         * Makefile.in (SIM_NO_ALL): Define.
1736         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1737
1738 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1739
1740         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1741         point unit to 32 bit registers.
1742         * configure: Re-generate.
1743
1744 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1745
1746         * configure.in (sim_use_gen): Make IGEN the default simulator
1747         generator for generic 32 and 64 bit mips targets.
1748         * configure: Re-generate.
1749
1750 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1751
1752         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1753         bitsize.
1754
1755         * interp.c (sim_fetch_register, sim_store_register): Read/write
1756         FGR from correct location.
1757         (sim_open): Set size of FGR's according to
1758         WITH_TARGET_FLOATING_POINT_BITSIZE.
1759
1760         * sim-main.h (FGR): Store floating point registers in a separate
1761         array.
1762
1763 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1764
1765         * configure: Regenerated to track ../common/aclocal.m4 changes.
1766
1767 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1768
1769         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1770
1771         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1772
1773         * interp.c (pending_tick): New function.  Deliver pending writes.
1774
1775         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1776         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1777         it can handle mixed sized quantites and single bits.
1778
1779 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1780
1781         * interp.c (oengine.h): Do not include when building with IGEN.
1782         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1783         (sim_info): Ditto for PROCESSOR_64BIT.
1784         (sim_monitor): Replace ut_reg with unsigned_word.
1785         (*): Ditto for t_reg.
1786         (LOADDRMASK): Define.
1787         (sim_open): Remove defunct check that host FP is IEEE compliant,
1788         using software to emulate floating point.
1789         (value_fpr, ...): Always compile, was conditional on HASFPU.
1790
1791 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1792
1793         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1794         size.
1795
1796         * interp.c (SD, CPU): Define.
1797         (mips_option_handler): Set flags in each CPU.
1798         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1799         (sim_close): Do not clear STATE, deleted anyway.
1800         (sim_write, sim_read): Assume CPU zero's vm should be used for
1801         data transfers.
1802         (sim_create_inferior): Set the PC for all processors.
1803         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1804         argument.
1805         (mips16_entry): Pass correct nr of args to store_word, load_word.
1806         (ColdReset): Cold reset all cpu's.
1807         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1808         (sim_monitor, load_memory, store_memory, signal_exception): Use
1809         `CPU' instead of STATE_CPU.
1810
1811
1812         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1813         SD or CPU_.
1814
1815         * sim-main.h (signal_exception): Add sim_cpu arg.
1816         (SignalException*): Pass both SD and CPU to signal_exception.
1817         * interp.c (signal_exception): Update.
1818
1819         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1820         Ditto
1821         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1822         address_translation): Ditto
1823         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1824
1825 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1826
1827         * configure: Regenerated to track ../common/aclocal.m4 changes.
1828
1829 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1830
1831         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1832
1833         * mips.igen (model): Map processor names onto BFD name.
1834
1835         * sim-main.h (CPU_CIA): Delete.
1836         (SET_CIA, GET_CIA): Define
1837
1838 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1839
1840         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1841         regiser.
1842
1843         * configure.in (default_endian): Configure a big-endian simulator
1844         by default.
1845         * configure: Re-generate.
1846
1847 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1848
1849         * configure: Regenerated to track ../common/aclocal.m4 changes.
1850
1851 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1852
1853         * interp.c (sim_monitor): Handle Densan monitor outbyte
1854         and inbyte functions.
1855
1856 1997-12-29  Felix Lee  <flee@cygnus.com>
1857
1858         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1859
1860 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1861
1862         * Makefile.in (tmp-igen): Arrange for $zero to always be
1863         reset to zero after every instruction.
1864
1865 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1866
1867         * configure: Regenerated to track ../common/aclocal.m4 changes.
1868         * config.in: Ditto.
1869
1870 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1871
1872         * mips.igen (MSUB): Fix to work like MADD.
1873         * gencode.c (MSUB): Similarly.
1874
1875 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1876
1877         * configure: Regenerated to track ../common/aclocal.m4 changes.
1878
1879 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1880
1881         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1882
1883 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1884
1885         * sim-main.h (sim-fpu.h): Include.
1886
1887         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1888         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1889         using host independant sim_fpu module.
1890
1891 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1892
1893         * interp.c (signal_exception): Report internal errors with SIGABRT
1894         not SIGQUIT.
1895
1896         * sim-main.h (C0_CONFIG): New register.
1897         (signal.h): No longer include.
1898
1899         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1900
1901 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1902
1903         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1904
1905 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1906
1907         * mips.igen: Tag vr5000 instructions.
1908         (ANDI): Was missing mipsIV model, fix assembler syntax.
1909         (do_c_cond_fmt): New function.
1910         (C.cond.fmt): Handle mips I-III which do not support CC field
1911         separatly.
1912         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1913         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1914         in IV3.2 spec.
1915         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1916         vr5000 which saves LO in a GPR separatly.
1917
1918         * configure.in (enable-sim-igen): For vr5000, select vr5000
1919         specific instructions.
1920         * configure: Re-generate.
1921
1922 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1923
1924         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1925
1926         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1927         fmt_uninterpreted_64 bit cases to switch.  Convert to
1928         fmt_formatted,
1929
1930         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1931
1932         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1933         as specified in IV3.2 spec.
1934         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1935
1936 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1937
1938         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1939         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1940         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1941         PENDING_FILL versions of instructions.  Simplify.
1942         (X): New function.
1943         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1944         instructions.
1945         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1946         a signed value.
1947         (MTHI, MFHI): Disable code checking HI-LO.
1948
1949         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1950         global.
1951         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1952
1953 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1954
1955         * gencode.c (build_mips16_operands): Replace IPC with cia.
1956
1957         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1958         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1959         IPC to `cia'.
1960         (UndefinedResult): Replace function with macro/function
1961         combination.
1962         (sim_engine_run): Don't save PC in IPC.
1963
1964         * sim-main.h (IPC): Delete.
1965
1966
1967         * interp.c (signal_exception, store_word, load_word,
1968         address_translation, load_memory, store_memory, cache_op,
1969         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1970         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1971         current instruction address - cia - argument.
1972         (sim_read, sim_write): Call address_translation directly.
1973         (sim_engine_run): Rename variable vaddr to cia.
1974         (signal_exception): Pass cia to sim_monitor
1975
1976         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1977         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1978         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1979
1980         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1981         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1982         SIM_ASSERT.
1983
1984         * interp.c (signal_exception): Pass restart address to
1985         sim_engine_restart.
1986
1987         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1988         idecode.o): Add dependency.
1989
1990         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1991         Delete definitions
1992         (DELAY_SLOT): Update NIA not PC with branch address.
1993         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1994
1995         * mips.igen: Use CIA not PC in branch calculations.
1996         (illegal): Call SignalException.
1997         (BEQ, ADDIU): Fix assembler.
1998
1999 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2000
2001         * m16.igen (JALX): Was missing.
2002
2003         * configure.in (enable-sim-igen): New configuration option.
2004         * configure: Re-generate.
2005
2006         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2007
2008         * interp.c (load_memory, store_memory): Delete parameter RAW.
2009         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2010         bypassing {load,store}_memory.
2011
2012         * sim-main.h (ByteSwapMem): Delete definition.
2013
2014         * Makefile.in (SIM_OBJS): Add sim-memopt module.
2015
2016         * interp.c (sim_do_command, sim_commands): Delete mips specific
2017         commands.  Handled by module sim-options.
2018
2019         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2020         (WITH_MODULO_MEMORY): Define.
2021
2022         * interp.c (sim_info): Delete code printing memory size.
2023
2024         * interp.c (mips_size): Nee sim_size, delete function.
2025         (power2): Delete.
2026         (monitor, monitor_base, monitor_size): Delete global variables.
2027         (sim_open, sim_close): Delete code creating monitor and other
2028         memory regions.  Use sim-memopts module, via sim_do_commandf, to
2029         manage memory regions.
2030         (load_memory, store_memory): Use sim-core for memory model.
2031
2032         * interp.c (address_translation): Delete all memory map code
2033         except line forcing 32 bit addresses.
2034
2035 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2036
2037         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
2038         trace options.
2039
2040         * interp.c (logfh, logfile): Delete globals.
2041         (sim_open, sim_close): Delete code opening & closing log file.
2042         (mips_option_handler): Delete -l and -n options.
2043         (OPTION mips_options): Ditto.
2044
2045         * interp.c (OPTION mips_options): Rename option trace to dinero.
2046         (mips_option_handler): Update.
2047
2048 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2049
2050         * interp.c (fetch_str): New function.
2051         (sim_monitor): Rewrite using sim_read & sim_write.
2052         (sim_open): Check magic number.
2053         (sim_open): Write monitor vectors into memory using sim_write.
2054         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2055         (sim_read, sim_write): Simplify - transfer data one byte at a
2056         time.
2057         (load_memory, store_memory): Clarify meaning of parameter RAW.
2058
2059         * sim-main.h (isHOST): Defete definition.
2060         (isTARGET): Mark as depreciated.
2061         (address_translation): Delete parameter HOST.
2062
2063         * interp.c (address_translation): Delete parameter HOST.
2064
2065 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2066
2067         * mips.igen:
2068
2069         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2070         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2071
2072 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2073
2074         * mips.igen: Add model filter field to records.
2075
2076 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2077
2078         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
2079
2080         interp.c (sim_engine_run): Do not compile function sim_engine_run
2081         when WITH_IGEN == 1.
2082
2083         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2084         target architecture.
2085
2086         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2087         igen. Replace with configuration variables sim_igen_flags /
2088         sim_m16_flags.
2089
2090         * m16.igen: New file.  Copy mips16 insns here.
2091         * mips.igen: From here.
2092
2093 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2094
2095         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2096         to top.
2097         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2098
2099 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
2100
2101         * gencode.c (build_instruction): Follow sim_write's lead in using
2102         BigEndianMem instead of !ByteSwapMem.
2103
2104 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2105
2106         * configure.in (sim_gen): Dependent on target, select type of
2107         generator.  Always select old style generator.
2108
2109         configure: Re-generate.
2110
2111         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2112         targets.
2113         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2114         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2115         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2116         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2117         SIM_@sim_gen@_*, set by autoconf.
2118
2119 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2120
2121         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2122
2123         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2124         CURRENT_FLOATING_POINT instead.
2125
2126         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2127         (address_translation): Raise exception InstructionFetch when
2128         translation fails and isINSTRUCTION.
2129
2130         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2131         sim_engine_run): Change type of of vaddr and paddr to
2132         address_word.
2133         (address_translation, prefetch, load_memory, store_memory,
2134         cache_op): Change type of vAddr and pAddr to address_word.
2135
2136         * gencode.c (build_instruction): Change type of vaddr and paddr to
2137         address_word.
2138
2139 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2140
2141         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2142         macro to obtain result of ALU op.
2143
2144 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2145
2146         * interp.c (sim_info): Call profile_print.
2147
2148 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2149
2150         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2151
2152         * sim-main.h (WITH_PROFILE): Do not define, defined in
2153         common/sim-config.h.  Use sim-profile module.
2154         (simPROFILE): Delete defintion.
2155
2156         * interp.c (PROFILE): Delete definition.
2157         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2158         (sim_close): Delete code writing profile histogram.
2159         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2160         Delete.
2161         (sim_engine_run): Delete code profiling the PC.
2162
2163 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2164
2165         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2166
2167         * interp.c (sim_monitor): Make register pointers of type
2168         unsigned_word*.
2169
2170         * sim-main.h: Make registers of type unsigned_word not
2171         signed_word.
2172
2173 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2174
2175         * interp.c (sync_operation): Rename from SyncOperation, make
2176         global, add SD argument.
2177         (prefetch): Rename from Prefetch, make global, add SD argument.
2178         (decode_coproc): Make global.
2179
2180         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2181
2182         * gencode.c (build_instruction): Generate DecodeCoproc not
2183         decode_coproc calls.
2184
2185         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2186         (SizeFGR): Move to sim-main.h
2187         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2188         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2189         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2190         sim-main.h.
2191         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2192         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2193         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2194         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2195         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2196         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2197
2198         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2199         exception.
2200         (sim-alu.h): Include.
2201         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2202         (sim_cia): Typedef to instruction_address.
2203
2204 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2205
2206         * Makefile.in (interp.o): Rename generated file engine.c to
2207         oengine.c.
2208
2209         * interp.c: Update.
2210
2211 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2212
2213         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2214
2215 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2216
2217         * gencode.c (build_instruction): For "FPSQRT", output correct
2218         number of arguments to Recip.
2219
2220 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2221
2222         * Makefile.in (interp.o): Depends on sim-main.h
2223
2224         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2225
2226         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2227         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2228         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2229         STATE, DSSTATE): Define
2230         (GPR, FGRIDX, ..): Define.
2231
2232         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2233         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2234         (GPR, FGRIDX, ...): Delete macros.
2235
2236         * interp.c: Update names to match defines from sim-main.h
2237
2238 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2239
2240         * interp.c (sim_monitor): Add SD argument.
2241         (sim_warning): Delete.  Replace calls with calls to
2242         sim_io_eprintf.
2243         (sim_error): Delete. Replace calls with sim_io_error.
2244         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2245         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2246         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2247         argument.
2248         (mips_size): Rename from sim_size. Add SD argument.
2249
2250         * interp.c (simulator): Delete global variable.
2251         (callback): Delete global variable.
2252         (mips_option_handler, sim_open, sim_write, sim_read,
2253         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2254         sim_size,sim_monitor): Use sim_io_* not callback->*.
2255         (sim_open): ZALLOC simulator struct.
2256         (PROFILE): Do not define.
2257
2258 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2259
2260         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2261         support.h with corresponding code.
2262
2263         * sim-main.h (word64, uword64), support.h: Move definition to
2264         sim-main.h.
2265         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2266
2267         * support.h: Delete
2268         * Makefile.in: Update dependencies
2269         * interp.c: Do not include.
2270
2271 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2272
2273         * interp.c (address_translation, load_memory, store_memory,
2274         cache_op): Rename to from AddressTranslation et.al., make global,
2275         add SD argument
2276
2277         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2278         CacheOp): Define.
2279
2280         * interp.c (SignalException): Rename to signal_exception, make
2281         global.
2282
2283         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2284
2285         * sim-main.h (SignalException, SignalExceptionInterrupt,
2286         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2287         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2288         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2289         Define.
2290
2291         * interp.c, support.h: Use.
2292
2293 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2294
2295         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2296         to value_fpr / store_fpr. Add SD argument.
2297         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2298         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2299
2300         * sim-main.h (ValueFPR, StoreFPR): Define.
2301
2302 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2303
2304         * interp.c (sim_engine_run): Check consistency between configure
2305         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2306         and HASFPU.
2307
2308         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2309         (mips_fpu): Configure WITH_FLOATING_POINT.
2310         (mips_endian): Configure WITH_TARGET_ENDIAN.
2311         * configure: Update.
2312
2313 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2314
2315         * configure: Regenerated to track ../common/aclocal.m4 changes.
2316
2317 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2318
2319         * configure: Regenerated.
2320
2321 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2322
2323         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2324
2325 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2326
2327         * gencode.c (print_igen_insn_models): Assume certain architectures
2328         include all mips* instructions.
2329         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2330         instruction.
2331
2332         * Makefile.in (tmp.igen): Add target. Generate igen input from
2333         gencode file.
2334
2335         * gencode.c (FEATURE_IGEN): Define.
2336         (main): Add --igen option.  Generate output in igen format.
2337         (process_instructions): Format output according to igen option.
2338         (print_igen_insn_format): New function.
2339         (print_igen_insn_models): New function.
2340         (process_instructions): Only issue warnings and ignore
2341         instructions when no FEATURE_IGEN.
2342
2343 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2344
2345         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2346         MIPS targets.
2347
2348 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2349
2350         * configure: Regenerated to track ../common/aclocal.m4 changes.
2351
2352 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2353
2354         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2355         SIM_RESERVED_BITS): Delete, moved to common.
2356         (SIM_EXTRA_CFLAGS): Update.
2357
2358 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2359
2360         * configure.in: Configure non-strict memory alignment.
2361         * configure: Regenerated to track ../common/aclocal.m4 changes.
2362
2363 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2364
2365         * configure: Regenerated to track ../common/aclocal.m4 changes.
2366
2367 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2368
2369         * gencode.c (SDBBP,DERET): Added (3900) insns.
2370         (RFE): Turn on for 3900.
2371         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2372         (dsstate): Made global.
2373         (SUBTARGET_R3900): Added.
2374         (CANCELDELAYSLOT): New.
2375         (SignalException): Ignore SystemCall rather than ignore and
2376         terminate.  Add DebugBreakPoint handling.
2377         (decode_coproc): New insns RFE, DERET; and new registers Debug
2378         and DEPC protected by SUBTARGET_R3900.
2379         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2380         bits explicitly.
2381         * Makefile.in,configure.in: Add mips subtarget option.
2382         * configure: Update.
2383
2384 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2385
2386         * gencode.c: Add r3900 (tx39).
2387
2388
2389 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2390
2391         * gencode.c (build_instruction): Don't need to subtract 4 for
2392         JALR, just 2.
2393
2394 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2395
2396         * interp.c: Correct some HASFPU problems.
2397
2398 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2399
2400         * configure: Regenerated to track ../common/aclocal.m4 changes.
2401
2402 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2403
2404         * interp.c (mips_options): Fix samples option short form, should
2405         be `x'.
2406
2407 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2408
2409         * interp.c (sim_info): Enable info code.  Was just returning.
2410
2411 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2412
2413         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2414         MFC0.
2415
2416 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2417
2418         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2419         constants.
2420         (build_instruction): Ditto for LL.
2421
2422 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2423
2424         * configure: Regenerated to track ../common/aclocal.m4 changes.
2425
2426 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2427
2428         * configure: Regenerated to track ../common/aclocal.m4 changes.
2429         * config.in: Ditto.
2430
2431 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2432
2433         * interp.c (sim_open): Add call to sim_analyze_program, update
2434         call to sim_config.
2435
2436 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2437
2438         * interp.c (sim_kill): Delete.
2439         (sim_create_inferior): Add ABFD argument. Set PC from same.
2440         (sim_load): Move code initializing trap handlers from here.
2441         (sim_open): To here.
2442         (sim_load): Delete, use sim-hload.c.
2443
2444         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2445
2446 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2447
2448         * configure: Regenerated to track ../common/aclocal.m4 changes.
2449         * config.in: Ditto.
2450
2451 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2452
2453         * interp.c (sim_open): Add ABFD argument.
2454         (sim_load): Move call to sim_config from here.
2455         (sim_open): To here.  Check return status.
2456
2457 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2458
2459         * gencode.c (build_instruction): Two arg MADD should
2460         not assign result to $0.
2461
2462 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2463
2464         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2465         * sim/mips/configure.in: Regenerate.
2466
2467 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2468
2469         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2470         signed8, unsigned8 et.al. types.
2471
2472         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2473         hosts when selecting subreg.
2474
2475 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2476
2477         * interp.c (sim_engine_run): Reset the ZERO register to zero
2478         regardless of FEATURE_WARN_ZERO.
2479         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2480
2481 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2482
2483         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2484         (SignalException): For BreakPoints ignore any mode bits and just
2485         save the PC.
2486         (SignalException): Always set the CAUSE register.
2487
2488 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2489
2490         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2491         exception has been taken.
2492
2493         * interp.c: Implement the ERET and mt/f sr instructions.
2494
2495 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2496
2497         * interp.c (SignalException): Don't bother restarting an
2498         interrupt.
2499
2500 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2501
2502         * interp.c (SignalException): Really take an interrupt.
2503         (interrupt_event): Only deliver interrupts when enabled.
2504
2505 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2506
2507         * interp.c (sim_info): Only print info when verbose.
2508         (sim_info) Use sim_io_printf for output.
2509
2510 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2511
2512         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2513         mips architectures.
2514
2515 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2516
2517         * interp.c (sim_do_command): Check for common commands if a
2518         simulator specific command fails.
2519
2520 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2521
2522         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2523         and simBE when DEBUG is defined.
2524
2525 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2526
2527         * interp.c (interrupt_event): New function.  Pass exception event
2528         onto exception handler.
2529
2530         * configure.in: Check for stdlib.h.
2531         * configure: Regenerate.
2532
2533         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2534         variable declaration.
2535         (build_instruction): Initialize memval1.
2536         (build_instruction): Add UNUSED attribute to byte, bigend,
2537         reverse.
2538         (build_operands): Ditto.
2539
2540         * interp.c: Fix GCC warnings.
2541         (sim_get_quit_code): Delete.
2542
2543         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2544         * Makefile.in: Ditto.
2545         * configure: Re-generate.
2546
2547         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2548
2549 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2550
2551         * interp.c (mips_option_handler): New function parse argumes using
2552         sim-options.
2553         (myname): Replace with STATE_MY_NAME.
2554         (sim_open): Delete check for host endianness - performed by
2555         sim_config.
2556         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2557         (sim_open): Move much of the initialization from here.
2558         (sim_load): To here.  After the image has been loaded and
2559         endianness set.
2560         (sim_open): Move ColdReset from here.
2561         (sim_create_inferior): To here.
2562         (sim_open): Make FP check less dependant on host endianness.
2563
2564         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2565         run.
2566         * interp.c (sim_set_callbacks): Delete.
2567
2568         * interp.c (membank, membank_base, membank_size): Replace with
2569         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2570         (sim_open): Remove call to callback->init. gdb/run do this.
2571
2572         * interp.c: Update
2573
2574         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2575
2576         * interp.c (big_endian_p): Delete, replaced by
2577         current_target_byte_order.
2578
2579 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2580
2581         * interp.c (host_read_long, host_read_word, host_swap_word,
2582         host_swap_long): Delete. Using common sim-endian.
2583         (sim_fetch_register, sim_store_register): Use H2T.
2584         (pipeline_ticks): Delete.  Handled by sim-events.
2585         (sim_info): Update.
2586         (sim_engine_run): Update.
2587
2588 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2589
2590         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2591         reason from here.
2592         (SignalException): To here. Signal using sim_engine_halt.
2593         (sim_stop_reason): Delete, moved to common.
2594
2595 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2596
2597         * interp.c (sim_open): Add callback argument.
2598         (sim_set_callbacks): Delete SIM_DESC argument.
2599         (sim_size): Ditto.
2600
2601 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2602
2603         * Makefile.in (SIM_OBJS): Add common modules.
2604
2605         * interp.c (sim_set_callbacks): Also set SD callback.
2606         (set_endianness, xfer_*, swap_*): Delete.
2607         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2608         Change to functions using sim-endian macros.
2609         (control_c, sim_stop): Delete, use common version.
2610         (simulate): Convert into.
2611         (sim_engine_run): This function.
2612         (sim_resume): Delete.
2613
2614         * interp.c (simulation): New variable - the simulator object.
2615         (sim_kind): Delete global - merged into simulation.
2616         (sim_load): Cleanup.  Move PC assignment from here.
2617         (sim_create_inferior): To here.
2618
2619         * sim-main.h: New file.
2620         * interp.c (sim-main.h): Include.
2621
2622 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2623
2624         * configure: Regenerated to track ../common/aclocal.m4 changes.
2625
2626 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2627
2628         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2629
2630 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2631
2632         * gencode.c (build_instruction): DIV instructions: check
2633         for division by zero and integer overflow before using
2634         host's division operation.
2635
2636 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2637
2638         * Makefile.in (SIM_OBJS): Add sim-load.o.
2639         * interp.c: #include bfd.h.
2640         (target_byte_order): Delete.
2641         (sim_kind, myname, big_endian_p): New static locals.
2642         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2643         after argument parsing.  Recognize -E arg, set endianness accordingly.
2644         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2645         load file into simulator.  Set PC from bfd.
2646         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2647         (set_endianness): Use big_endian_p instead of target_byte_order.
2648
2649 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2650
2651         * interp.c (sim_size): Delete prototype - conflicts with
2652         definition in remote-sim.h.  Correct definition.
2653
2654 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2655
2656         * configure: Regenerated to track ../common/aclocal.m4 changes.
2657         * config.in: Ditto.
2658
2659 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2660
2661         * interp.c (sim_open): New arg `kind'.
2662
2663         * configure: Regenerated to track ../common/aclocal.m4 changes.
2664
2665 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2666
2667         * configure: Regenerated to track ../common/aclocal.m4 changes.
2668
2669 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2670
2671         * interp.c (sim_open): Set optind to 0 before calling getopt.
2672
2673 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2674
2675         * configure: Regenerated to track ../common/aclocal.m4 changes.
2676
2677 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2678
2679         * interp.c : Replace uses of pr_addr with pr_uword64
2680         where the bit length is always 64 independent of SIM_ADDR.
2681         (pr_uword64) : added.
2682
2683 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2684
2685         * configure: Re-generate.
2686
2687 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2688
2689         * configure: Regenerate to track ../common/aclocal.m4 changes.
2690
2691 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2692
2693         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2694         in argv form.
2695         (other sim_*): New SIM_DESC argument.
2696
2697 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2698
2699         * interp.c: Fix printing of addresses for non-64-bit targets.
2700         (pr_addr): Add function to print address based on size.
2701
2702 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2703
2704         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2705
2706 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2707
2708         * gencode.c (build_mips16_operands): Correct computation of base
2709         address for extended PC relative instruction.
2710
2711 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2712
2713         * interp.c (mips16_entry): Add support for floating point cases.
2714         (SignalException): Pass floating point cases to mips16_entry.
2715         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2716         registers.
2717         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2718         or fmt_word.
2719         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2720         and then set the state to fmt_uninterpreted.
2721         (COP_SW): Temporarily set the state to fmt_word while calling
2722         ValueFPR.
2723
2724 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2725
2726         * gencode.c (build_instruction): The high order may be set in the
2727         comparison flags at any ISA level, not just ISA 4.
2728
2729 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2730
2731         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2732         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2733         * configure.in: sinclude ../common/aclocal.m4.
2734         * configure: Regenerated.
2735
2736 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2737
2738         * configure: Rebuild after change to aclocal.m4.
2739
2740 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2741
2742         * configure configure.in Makefile.in:  Update to new configure
2743         scheme which is more compatible with WinGDB builds.
2744         * configure.in:  Improve comment on how to run autoconf.
2745         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2746         * Makefile.in:  Use autoconf substitution to install common
2747         makefile fragment.
2748
2749 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2750
2751         * gencode.c (build_instruction): Use BigEndianCPU instead of
2752         ByteSwapMem.
2753
2754 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2755
2756         * interp.c (sim_monitor): Make output to stdout visible in
2757         wingdb's I/O log window.
2758
2759 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2760
2761         * support.h: Undo previous change to SIGTRAP
2762         and SIGQUIT values.
2763
2764 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2765
2766         * interp.c (store_word, load_word): New static functions.
2767         (mips16_entry): New static function.
2768         (SignalException): Look for mips16 entry and exit instructions.
2769         (simulate): Use the correct index when setting fpr_state after
2770         doing a pending move.
2771
2772 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2773
2774         * interp.c: Fix byte-swapping code throughout to work on
2775         both little- and big-endian hosts.
2776
2777 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2778
2779         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2780         with gdb/config/i386/xm-windows.h.
2781
2782 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2783
2784         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2785         that messes up arithmetic shifts.
2786
2787 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2788
2789         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2790         SIGTRAP and SIGQUIT for _WIN32.
2791
2792 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2793
2794         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2795         force a 64 bit multiplication.
2796         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2797         destination register is 0, since that is the default mips16 nop
2798         instruction.
2799
2800 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2801
2802         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2803         (build_endian_shift): Don't check proc64.
2804         (build_instruction): Always set memval to uword64.  Cast op2 to
2805         uword64 when shifting it left in memory instructions.  Always use
2806         the same code for stores--don't special case proc64.
2807
2808         * gencode.c (build_mips16_operands): Fix base PC value for PC
2809         relative operands.
2810         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2811         jal instruction.
2812         * interp.c (simJALDELAYSLOT): Define.
2813         (JALDELAYSLOT): Define.
2814         (INDELAYSLOT, INJALDELAYSLOT): Define.
2815         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2816
2817 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2818
2819         * interp.c (sim_open): add flush_cache as a PMON routine
2820         (sim_monitor): handle flush_cache by ignoring it
2821
2822 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2823
2824         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2825         BigEndianMem.
2826         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2827         (BigEndianMem): Rename to ByteSwapMem and change sense.
2828         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2829         BigEndianMem references to !ByteSwapMem.
2830         (set_endianness): New function, with prototype.
2831         (sim_open): Call set_endianness.
2832         (sim_info): Use simBE instead of BigEndianMem.
2833         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2834         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2835         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2836         ifdefs, keeping the prototype declaration.
2837         (swap_word): Rewrite correctly.
2838         (ColdReset): Delete references to CONFIG.  Delete endianness related
2839         code; moved to set_endianness.
2840
2841 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2842
2843         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2844         * interp.c (CHECKHILO): Define away.
2845         (simSIGINT): New macro.
2846         (membank_size): Increase from 1MB to 2MB.
2847         (control_c): New function.
2848         (sim_resume): Rename parameter signal to signal_number.  Add local
2849         variable prev.  Call signal before and after simulate.
2850         (sim_stop_reason): Add simSIGINT support.
2851         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2852         functions always.
2853         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2854         if logfh is NULL.
2855         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2856         a call to sim_warning.
2857
2858 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2859
2860         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2861         16 bit instructions.
2862
2863 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2864
2865         Add support for mips16 (16 bit MIPS implementation):
2866         * gencode.c (inst_type): Add mips16 instruction encoding types.
2867         (GETDATASIZEINSN): Define.
2868         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2869         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2870         mtlo.
2871         (MIPS16_DECODE): New table, for mips16 instructions.
2872         (bitmap_val): New static function.
2873         (struct mips16_op): Define.
2874         (mips16_op_table): New table, for mips16 operands.
2875         (build_mips16_operands): New static function.
2876         (process_instructions): If PC is odd, decode a mips16
2877         instruction.  Break out instruction handling into new
2878         build_instruction function.
2879         (build_instruction): New static function, broken out of
2880         process_instructions.  Check modifiers rather than flags for SHIFT
2881         bit count and m[ft]{hi,lo} direction.
2882         (usage): Pass program name to fprintf.
2883         (main): Remove unused variable this_option_optind.  Change
2884         ``*loptarg++'' to ``loptarg++''.
2885         (my_strtoul): Parenthesize && within ||.
2886         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2887         (simulate): If PC is odd, fetch a 16 bit instruction, and
2888         increment PC by 2 rather than 4.
2889         * configure.in: Add case for mips16*-*-*.
2890         * configure: Rebuild.
2891
2892 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2893
2894         * interp.c: Allow -t to enable tracing in standalone simulator.
2895         Fix garbage output in trace file and error messages.
2896
2897 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2898
2899         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2900         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2901         * configure.in: Simplify using macros in ../common/aclocal.m4.
2902         * configure: Regenerated.
2903         * tconfig.in: New file.
2904
2905 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2906
2907         * interp.c: Fix bugs in 64-bit port.
2908         Use ansi function declarations for msvc compiler.
2909         Initialize and test file pointer in trace code.
2910         Prevent duplicate definition of LAST_EMED_REGNUM.
2911
2912 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2913
2914         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2915
2916 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2917
2918         * interp.c (SignalException): Check for explicit terminating
2919         breakpoint value.
2920         * gencode.c: Pass instruction value through SignalException()
2921         calls for Trap, Breakpoint and Syscall.
2922
2923 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2924
2925         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2926         only used on those hosts that provide it.
2927         * configure.in: Add sqrt() to list of functions to be checked for.
2928         * config.in: Re-generated.
2929         * configure: Re-generated.
2930
2931 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2932
2933         * gencode.c (process_instructions): Call build_endian_shift when
2934         expanding STORE RIGHT, to fix swr.
2935         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2936         clear the high bits.
2937         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2938         Fix float to int conversions to produce signed values.
2939
2940 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2941
2942         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2943         (process_instructions): Correct handling of nor instruction.
2944         Correct shift count for 32 bit shift instructions. Correct sign
2945         extension for arithmetic shifts to not shift the number of bits in
2946         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2947         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2948         Fix madd.
2949         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2950         It's OK to have a mult follow a mult.  What's not OK is to have a
2951         mult follow an mfhi.
2952         (Convert): Comment out incorrect rounding code.
2953
2954 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2955
2956         * interp.c (sim_monitor): Improved monitor printf
2957         simulation. Tidied up simulator warnings, and added "--log" option
2958         for directing warning message output.
2959         * gencode.c: Use sim_warning() rather than WARNING macro.
2960
2961 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2962
2963         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2964         getopt1.o, rather than on gencode.c.  Link objects together.
2965         Don't link against -liberty.
2966         (gencode.o, getopt.o, getopt1.o): New targets.
2967         * gencode.c: Include <ctype.h> and "ansidecl.h".
2968         (AND): Undefine after including "ansidecl.h".
2969         (ULONG_MAX): Define if not defined.
2970         (OP_*): Don't define macros; now defined in opcode/mips.h.
2971         (main): Call my_strtoul rather than strtoul.
2972         (my_strtoul): New static function.
2973
2974 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2975
2976         * gencode.c (process_instructions):  Generate word64 and uword64
2977         instead of `long long' and `unsigned long long' data types.
2978         * interp.c:  #include sysdep.h to get signals, and define default
2979         for SIGBUS.
2980         * (Convert):  Work around for Visual-C++ compiler bug with type
2981         conversion.
2982         * support.h:  Make things compile under Visual-C++ by using
2983         __int64 instead of `long long'.  Change many refs to long long
2984         into word64/uword64 typedefs.
2985
2986 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2987
2988         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2989         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2990         (docdir): Removed.
2991         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2992         (AC_PROG_INSTALL): Added.
2993         (AC_PROG_CC): Moved to before configure.host call.
2994         * configure: Rebuilt.
2995
2996 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2997
2998         * configure.in: Define @SIMCONF@ depending on mips target.
2999         * configure: Rebuild.
3000         * Makefile.in (run): Add @SIMCONF@ to control simulator
3001         construction.
3002         * gencode.c: Change LOADDRMASK to 64bit memory model only.
3003         * interp.c: Remove some debugging, provide more detailed error
3004         messages, update memory accesses to use LOADDRMASK.
3005
3006 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
3007
3008         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3009         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
3010         stamp-h.
3011         * configure: Rebuild.
3012         * config.in: New file, generated by autoheader.
3013         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
3014         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
3015         HAVE_ANINT and HAVE_AINT, as appropriate.
3016         * Makefile.in (run): Use @LIBS@ rather than -lm.
3017         (interp.o): Depend upon config.h.
3018         (Makefile): Just rebuild Makefile.
3019         (clean): Remove stamp-h.
3020         (mostlyclean): Make the same as clean, not as distclean.
3021         (config.h, stamp-h): New targets.
3022
3023 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3024
3025         * interp.c (ColdReset): Fix boolean test. Make all simulator
3026         globals static.
3027
3028 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
3029
3030         * interp.c (xfer_direct_word, xfer_direct_long,
3031         swap_direct_word, swap_direct_long, xfer_big_word,
3032         xfer_big_long, xfer_little_word, xfer_little_long,
3033         swap_word,swap_long): Added.
3034         * interp.c (ColdReset): Provide function indirection to
3035         host<->simulated_target transfer routines.
3036         * interp.c (sim_store_register, sim_fetch_register): Updated to
3037         make use of indirected transfer routines.
3038
3039 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
3040
3041         * gencode.c (process_instructions): Ensure FP ABS instruction
3042         recognised.
3043         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3044         system call support.
3045
3046 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
3047
3048         * interp.c (sim_do_command): Complain if callback structure not
3049         initialised.
3050
3051 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
3052
3053         * interp.c (Convert): Provide round-to-nearest and round-to-zero
3054         support for Sun hosts.
3055         * Makefile.in (gencode): Ensure the host compiler and libraries
3056         used for cross-hosted build.
3057
3058 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
3059
3060         * interp.c, gencode.c: Some more (TODO) tidying.
3061
3062 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
3063
3064         * gencode.c, interp.c: Replaced explicit long long references with
3065         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3066         * support.h (SET64LO, SET64HI): Macros added.
3067
3068 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
3069
3070         * configure: Regenerate with autoconf 2.7.
3071
3072 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
3073
3074         * interp.c (LoadMemory): Enclose text following #endif in /* */.
3075         * support.h: Remove superfluous "1" from #if.
3076         * support.h (CHECKSIM): Remove stray 'a' at end of line.
3077
3078 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
3079
3080         * interp.c (StoreFPR): Control UndefinedResult() call on
3081         WARN_RESULT manifest.
3082
3083 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
3084
3085         * gencode.c: Tidied instruction decoding, and added FP instruction
3086         support.
3087
3088         * interp.c: Added dineroIII, and BSD profiling support. Also
3089         run-time FP handling.
3090
3091 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
3092
3093         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3094         gencode.c, interp.c, support.h: created.