sim/mips/ChangeLog

   1 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
   2
   3         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
   4
   5 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
   6
   7         * mips.igen (do_load_double, do_store_double): New functions.
   8         (LDC1, SDC1): Rename to...
   9         (LDC1b, SDC1b): respectively.
  10         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
  11
  12 2002-07-29  Michael Snyder  <msnyder@redhat.com>
  13
  14         * cp1.c (fp_recip2): Modify initialization expression so that
  15         GCC will recognize it as constant.
  16
  17 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
  18
  19         * mdmx.c (SD_): Delete.
  20         (Unpredictable): Re-define, for now, to directly invoke
  21         unpredictable_action().
  22         (mdmx_acc_op): Fix error in .ob immediate handling.
  23
  24 2002-06-18  Andrew Cagney  <cagney@redhat.com>
  25
  26         * interp.c (sim_firmware_command): Initialize `address'.
  27
  28 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
  29
  30         * configure: Regenerated to track ../common/aclocal.m4 changes.
  31
  32 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
  33             Ed Satterthwaite  <ehs@broadcom.com>
  34
  35         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
  36         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
  37         * mips.igen: Include mips3d.igen.
  38         (mips3d): New model name for MIPS-3D ASE instructions.
  39         (CVT.W.fmt): Don't use this instruction for word (source) format
  40         instructions.
  41         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
  42         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
  43         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
  44         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
  45         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
  46         (RSquareRoot1, RSquareRoot2): New macros.
  47         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
  48         (fp_rsqrt2): New functions.
  49         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
  50         * configure: Regenerate.
  51
  52 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
  53             Ed Satterthwaite  <ehs@broadcom.com>
  54
  55         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
  56         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
  57         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
  58         (convert): Note that this function is not used for paired-single
  59         format conversions.
  60         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
  61         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
  62         (check_fmt_p): Enable paired-single support.
  63         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
  64         (PUU.PS): New instructions.
  65         (CVT.S.fmt): Don't use this instruction for paired-single format
  66         destinations.
  67         * sim-main.h (FP_formats): New value 'fmt_ps.'
  68         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
  69         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
  70
  71 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
  72
  73         * mips.igen: Fix formatting of function calls in
  74         many FP operations.
  75
  76 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
  77
  78         * mips.igen (MOVN, MOVZ): Trace result.
  79         (TNEI): Print "tnei" as the opcode name in traces.
  80         (CEIL.W): Add disassembly string for traces.
  81         (RSQRT.fmt): Make location of disassembly string consistent
  82         with other instructions.
  83
  84 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
  85
  86         * mips.igen (X): Delete unused function.
  87
  88 2002-06-08  Andrew Cagney  <cagney@redhat.com>
  89
  90         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
  91
  92 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  93             Ed Satterthwaite  <ehs@broadcom.com>
  94
  95         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
  96         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
  97         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
  98         (fp_nmsub): New prototypes.
  99         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 100         (NegMultiplySub): New defines.
 101         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 102         (MADD.D, MADD.S): Replace with...
 103         (MADD.fmt): New instruction.
 104         (MSUB.D, MSUB.S): Replace with...
 105         (MSUB.fmt): New instruction.
 106         (NMADD.D, NMADD.S): Replace with...
 107         (NMADD.fmt): New instruction.
 108         (NMSUB.D, MSUB.S): Replace with...
 109         (NMSUB.fmt): New instruction.
 110
 111 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 112             Ed Satterthwaite  <ehs@broadcom.com>
 113
 114         * cp1.c: Fix more comment spelling and formatting.
 115         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 116         (denorm_mode): New function.
 117         (fpu_unary, fpu_binary): Round results after operation, collect
 118         status from rounding operations, and update the FCSR.
 119         (convert): Collect status from integer conversions and rounding
 120         operations, and update the FCSR.  Adjust NaN values that result
 121         from conversions.  Convert to use sim_io_eprintf rather than
 122         fprintf, and remove some debugging code.
 123         * cp1.h (fenr_FS): New define.
 124
 125 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 126
 127         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 128         rounding mode to sim FP rounding mode flag conversion code into...
 129         (rounding_mode): New function.
 130
 131 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 132
 133         * cp1.c: Clean up formatting of a few comments.
 134         (value_fpr): Reformat switch statement.
 135
 136 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 137             Ed Satterthwaite  <ehs@broadcom.com>
 138
 139         * cp1.h: New file.
 140         * sim-main.h: Include cp1.h.
 141         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 142         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 143         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 144         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 145         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 146         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 147         * cp1.c: Don't include sim-fpu.h; already included by
 148         sim-main.h.  Clean up formatting of some comments.
 149         (NaN, Equal, Less): Remove.
 150         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 151         (fp_cmp): New functions.
 152         * mips.igen (do_c_cond_fmt): Remove.
 153         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 154         Compare.  Add result tracing.
 155         (CxC1): Remove, replace with...
 156         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 157         (DMxC1): Remove, replace with...
 158         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 159         (MxC1): Remove, replace with...
 160         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 161
 162 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 163
 164         * sim-main.h (FGRIDX): Remove, replace all uses with...
 165         (FGR_BASE): New macro.
 166         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 167         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 168         (NR_FGR, FGR): Likewise.
 169         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 170         * mips.igen: Likewise.
 171
 172 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 173
 174         * cp1.c: Add an FSF Copyright notice to this file.
 175
 176 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 177             Ed Satterthwaite  <ehs@broadcom.com>
 178
 179         * cp1.c (Infinity): Remove.
 180         * sim-main.h (Infinity): Likewise.
 181
 182         * cp1.c (fp_unary, fp_binary): New functions.
 183         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 184         (fp_sqrt): New functions, implemented in terms of the above.
 185         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 186         (Recip, SquareRoot): Remove (replaced by functions above).
 187         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 188         (fp_recip, fp_sqrt): New prototypes.
 189         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 190         (Recip, SquareRoot): Replace prototypes with #defines which
 191         invoke the functions above.
 192
 193 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 194
 195         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 196         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 197         file, remove PARAMS from prototypes.
 198         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 199         simulator state arguments.
 200         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 201         pass simulator state arguments.
 202         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 203         (store_fpr, convert): Remove 'sd' argument.
 204         (value_fpr): Likewise.  Convert to use 'SD' instead.
 205
 206 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 207
 208         * cp1.c (Min, Max): Remove #if 0'd functions.
 209         * sim-main.h (Min, Max): Remove.
 210
 211 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 212
 213         * cp1.c: fix formatting of switch case and default labels.
 214         * interp.c: Likewise.
 215         * sim-main.c: Likewise.
 216
 217 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 218
 219         * cp1.c: Clean up comments which describe FP formats.
 220          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 221
 222 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 223             Ed Satterthwaite  <ehs@broadcom.com>
 224
 225         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 226         Broadcom SiByte SB-1 processor configurations.
 227         * configure: Regenerate.
 228         * sb1.igen: New file.
 229         * mips.igen: Include sb1.igen.
 230         (sb1): New model.
 231         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 232         * mdmx.igen: Add "sb1" model to all appropriate functions and
 233         instructions.
 234         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 235         (ob_func, ob_acc): Reference the above.
 236         (qh_acc): Adjust to keep the same size as ob_acc.
 237         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 238         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 239
 240 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 241
 242         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 243
 244 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 245             Ed Satterthwaite  <ehs@broadcom.com>
 246
 247         * mips.igen (mdmx): New (pseudo-)model.
 248         * mdmx.c, mdmx.igen: New files.
 249         * Makefile.in (SIM_OBJS): Add mdmx.o.
 250         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 251         New typedefs.
 252         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 253         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 254         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 255         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 256         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 257         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 258         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 259         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 260         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 261         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 262         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 263         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 264         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 265         (qh_fmtsel): New macros.
 266         (_sim_cpu): New member "acc".
 267         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 268         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 269
 270 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 271
 272         * interp.c: Use 'deprecated' rather than 'depreciated.'
 273         * sim-main.h: Likewise.
 274
 275 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 276
 277         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 278         which wouldn't compile anyway.
 279         * sim-main.h (unpredictable_action): New function prototype.
 280         (Unpredictable): Define to call igen function unpredictable().
 281         (NotWordValue): New macro to call igen function not_word_value().
 282         (UndefinedResult): Remove.
 283         * interp.c (undefined_result): Remove.
 284         (unpredictable_action): New function.
 285         * mips.igen (not_word_value, unpredictable): New functions.
 286         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 287         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 288         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 289         NotWordValue() to check for unpredictable inputs, then
 290         Unpredictable() to handle them.
 291
 292 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 293
 294         * mips.igen: Fix formatting of calls to Unpredictable().
 295
 296 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 297
 298         * interp.c (sim_open): Revert previous change.
 299
 300 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 301
 302         * interp.c (sim_open): Disable chunk of code that wrote code in
 303         vector table entries.
 304
 305 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 306
 307         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 308         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 309         unused definitions.
 310
 311 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 312
 313         * cp1.c: Fix many formatting issues.
 314
 315 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 316
 317         * cp1.c (fpu_format_name): New function to replace...
 318         (DOFMT): This.  Delete, and update all callers.
 319         (fpu_rounding_mode_name): New function to replace...
 320         (RMMODE): This.  Delete, and update all callers.
 321
 322 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 323
 324         * interp.c: Move FPU support routines from here to...
 325         * cp1.c: Here.  New file.
 326         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 327         (cp1.o): New target.
 328
 329 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 330
 331         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 332         * mips.igen (mips32, mips64): New models, add to all instructions
 333         and functions as appropriate.
 334         (loadstore_ea, check_u64): New variant for model mips64.
 335         (check_fmt_p): New variant for models mipsV and mips64, remove
 336         mipsV model marking fro other variant.
 337         (SLL) Rename to...
 338         (SLLa) this.
 339         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 340         for mips32 and mips64.
 341         (DCLO, DCLZ): New instructions for mips64.
 342
 343 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 344
 345         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 346         immediate or code as a hex value with the "%#lx" format.
 347         (ANDI): Likewise, and fix printed instruction name.
 348
 349 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 350
 351         * sim-main.h (UndefinedResult, Unpredictable): New macros
 352         which currently do nothing.
 353
 354 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 355
 356         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 357         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 358         (status_CU3): New definitions.
 359
 360         * sim-main.h (ExceptionCause): Add new values for MIPS32
 361         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 362         for DebugBreakPoint and NMIReset to note their status in
 363         MIPS32 and MIPS64.
 364         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 365         (SignalExceptionCacheErr): New exception macros.
 366
 367 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 368
 369         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 370         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 371         is always enabled.
 372         (SignalExceptionCoProcessorUnusable): Take as argument the
 373         unusable coprocessor number.
 374
 375 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 376
 377         * mips.igen: Fix formatting of all SignalException calls.
 378
 379 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 380
 381         * sim-main.h (SIGNEXTEND): Remove.
 382
 383 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 384
 385         * mips.igen: Remove gencode comment from top of file, fix
 386         spelling in another comment.
 387
 388 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 389
 390         * mips.igen (check_fmt, check_fmt_p): New functions to check
 391         whether specific floating point formats are usable.
 392         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 393         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 394         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 395         Use the new functions.
 396         (do_c_cond_fmt): Remove format checks...
 397         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 398
 399 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 400
 401         * mips.igen: Fix formatting of check_fpu calls.
 402
 403 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 404
 405         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 406
 407 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 408
 409         * mips.igen: Remove whitespace at end of lines.
 410
 411 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 412
 413         * mips.igen (loadstore_ea): New function to do effective
 414         address calculations.
 415         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 416         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 417         CACHE): Use loadstore_ea to do effective address computations.
 418
 419 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 420
 421         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 422         * mips.igen (LL, CxC1, MxC1): Likewise.
 423
 424 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 425
 426         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 427         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 428         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 429         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 430         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 431         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 432         Don't split opcode fields by hand, use the opcode field values
 433         provided by igen.
 434
 435 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 436
 437         * mips.igen (do_divu): Fix spacing.
 438
 439         * mips.igen (do_dsllv): Move to be right before DSLLV,
 440         to match the rest of the do_<shift> functions.
 441
 442 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 443
 444         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 445         DSRL32, do_dsrlv): Trace inputs and results.
 446
 447 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 448
 449         * mips.igen (CACHE): Provide instruction-printing string.
 450
 451         * interp.c (signal_exception): Comment tokens after #endif.
 452
 453 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 454
 455         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 456         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 457         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 458         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 459         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 460         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 461         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 462         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 463
 464 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 465
 466         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 467         instruction-printing string.
 468         (LWU): Use '64' as the filter flag.
 469
 470 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 471
 472         * mips.igen (SDXC1): Fix instruction-printing string.
 473
 474 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 475
 476         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 477         filter flags "32,f".
 478
 479 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 480
 481         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 482         as the filter flag.
 483
 484 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 485
 486         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 487         add a comma) so that it more closely match the MIPS ISA
 488         documentation opcode partitioning.
 489         (PREF): Put useful names on opcode fields, and include
 490         instruction-printing string.
 491
 492 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 493
 494         * mips.igen (check_u64): New function which in the future will
 495         check whether 64-bit instructions are usable and signal an
 496         exception if not.  Currently a no-op.
 497         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 498         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 499         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 500         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 501
 502         * mips.igen (check_fpu): New function which in the future will
 503         check whether FPU instructions are usable and signal an exception
 504         if not.  Currently a no-op.
 505         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 506         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 507         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 508         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 509         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 510         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 511         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 512         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 513
 514 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 515
 516         * mips.igen (do_load_left, do_load_right): Move to be immediately
 517         following do_load.
 518         (do_store_left, do_store_right): Move to be immediately following
 519         do_store.
 520
 521 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 522
 523         * mips.igen (mipsV): New model name.  Also, add it to
 524         all instructions and functions where it is appropriate.
 525
 526 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 527
 528         * mips.igen: For all functions and instructions, list model
 529         names that support that instruction one per line.
 530
 531 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 532
 533         * mips.igen: Add some additional comments about supported
 534         models, and about which instructions go where.
 535         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 536         order as is used in the rest of the file.
 537
 538 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 539
 540         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 541         indicating that ALU32_END or ALU64_END are there to check
 542         for overflow.
 543         (DADD): Likewise, but also remove previous comment about
 544         overflow checking.
 545
 546 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 547
 548         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 549         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 550         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 551         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 552         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 553         fields (i.e., add and move commas) so that they more closely
 554         match the MIPS ISA documentation opcode partitioning.
 555
 556 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 557
 558         * mips.igen (ADDI): Print immediate value.
 559         (BREAK): Print code.
 560         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 561         (SLL): Print "nop" specially, and don't run the code
 562         that does the shift for the "nop" case.
 563
 564 2001-11-17  Fred Fish  <fnf@redhat.com>
 565
 566         * sim-main.h (float_operation): Move enum declaration outside
 567         of _sim_cpu struct declaration.
 568
 569 2001-04-12  Jim Blandy  <jimb@redhat.com>
 570
 571         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 572         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 573         set of the FCSR.
 574         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 575         PENDING_FILL, and you can get the intended effect gracefully by
 576         calling PENDING_SCHED directly.
 577
 578 2001-02-23  Ben Elliston  <bje@redhat.com>
 579
 580         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 581         already defined elsewhere.
 582
 583 2001-02-19  Ben Elliston  <bje@redhat.com>
 584
 585         * sim-main.h (sim_monitor): Return an int.
 586         * interp.c (sim_monitor): Add return values.
 587         (signal_exception): Handle error conditions from sim_monitor.
 588
 589 2001-02-08  Ben Elliston  <bje@redhat.com>
 590
 591         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 592         (store_memory): Likewise, pass cia to sim_core_write*.
 593
 594 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 595
 596         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 597         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 598
 599 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 600
 601         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 602         * Makefile.in: Don't delete *.igen when cleaning directory.
 603
 604 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 605
 606         * m16.igen (break): Call SignalException not sim_engine_halt.
 607
 608 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 609
 610         From Jason Eckhardt:
 611         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 612
 613 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 614
 615         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 616
 617 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 618
 619         * mips.igen (do_dmultx): Fix typo.
 620
 621 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 622
 623         * configure: Regenerated to track ../common/aclocal.m4 changes.
 624
 625 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 626
 627         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 628
 629 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 630
 631         * sim-main.h (GPR_CLEAR): Define macro.
 632
 633 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 634
 635         * interp.c (decode_coproc): Output long using %lx and not %s.
 636
 637 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 638
 639         * interp.c (sim_open): Sort & extend dummy memory regions for
 640         --board=jmr3904 for eCos.
 641
 642 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 643
 644         * configure: Regenerated.
 645
 646 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 647
 648         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 649         calls, conditional on the simulator being in verbose mode.
 650
 651 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 652
 653         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 654         cache don't get ReservedInstruction traps.
 655
 656 1999-11-29  Mark Salter  <msalter@cygnus.com>
 657
 658         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 659         to clear status bits in sdisr register. This is how the hardware works.
 660
 661         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 662         being used by cygmon.
 663
 664 1999-11-11  Andrew Haley  <aph@cygnus.com>
 665
 666         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 667         instructions.
 668
 669 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 670
 671         * mips.igen (MULT): Correct previous mis-applied patch.
 672
 673 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 674
 675         * mips.igen (delayslot32): Handle sequence like
 676         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 677         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 678         (MULT): Actually pass the third register...
 679
 680 1999-09-03  Mark Salter  <msalter@cygnus.com>
 681
 682         * interp.c (sim_open): Added more memory aliases for additional
 683         hardware being touched by cygmon on jmr3904 board.
 684
 685 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 686
 687         * configure: Regenerated to track ../common/aclocal.m4 changes.
 688
 689 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 690
 691         * interp.c (sim_store_register): Handle case where client - GDB -
 692         specifies that a 4 byte register is 8 bytes in size.
 693         (sim_fetch_register): Ditto.
 694
 695 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 696
 697         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 698         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 699         (idt_monitor_base): Base address for IDT monitor traps.
 700         (pmon_monitor_base): Ditto for PMON.
 701         (lsipmon_monitor_base): Ditto for LSI PMON.
 702         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 703         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 704         (sim_firmware_command): New function.
 705         (mips_option_handler): Call it for OPTION_FIRMWARE.
 706         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 707         option was given, add no monitor by default.  Add BREAK hooks only if
 708         monitors are also there.
 709
 710 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 711
 712         * interp.c (sim_monitor): Flush output before reading input.
 713
 714 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 715
 716         * tconfig.in (SIM_HANDLES_LMA): Always define.
 717
 718 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 719
 720         From Mark Salter <msalter@cygnus.com>:
 721         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 722         (sim_open): Add setup for BSP board.
 723
 724 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 725
 726         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 727         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 728         them as unimplemented.
 729
 730 1999-05-08  Felix Lee  <flee@cygnus.com>
 731
 732         * configure: Regenerated to track ../common/aclocal.m4 changes.
 733
 734 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 735
 736         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 737
 738 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 739
 740         * configure.in: Any mips64vr5*-*-* target should have
 741         -DTARGET_ENABLE_FR=1.
 742         (default_endian): Any mips64vr*el-*-* target should default to
 743         LITTLE_ENDIAN.
 744         * configure: Re-generate.
 745
 746 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 747
 748         * mips.igen (ldl): Extend from _16_, not 32.
 749
 750 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 751
 752         * interp.c (sim_store_register): Force registers written to by GDB
 753         into an un-interpreted state.
 754
 755 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 756
 757         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 758         CPU, start periodic background I/O polls.
 759         (tx3904sio_poll): New function: periodic I/O poller.
 760
 761 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 762
 763         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 764
 765 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 766
 767         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 768         case statement.
 769
 770 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 771
 772         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 773         (load_word): Call SIM_CORE_SIGNAL hook on error.
 774         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 775         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 776         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 777         * sim-main.h (COP0_BADVADDR): Define.
 778         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 779         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 780         (_sim_cpu): Add exc_* fields to store register value snapshots.
 781         * mips.igen (*): Replace memory-related SignalException* calls
 782         with references to SIM_CORE_SIGNAL hook.
 783
 784         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 785         fix.
 786         * sim-main.c (*): Minor warning cleanups.
 787
 788 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 789
 790         * m16.igen (DADDIU5): Correct type-o.
 791
 792 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 793
 794         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 795         variables.
 796
 797 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 798
 799         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 800         to include path.
 801         (interp.o): Add dependency on itable.h
 802         (oengine.c, gencode): Delete remaining references.
 803         (BUILT_SRC_FROM_GEN): Clean up.
 804
 805 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 806
 807         * vr4run.c: New.
 808         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 809         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 810         tmp-run-hack) : New.
 811         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 812         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 813         Drop the "64" qualifier to get the HACK generator working.
 814         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 815         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 816         qualifier to get the hack generator working.
 817         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 818         (DSLL): Use do_dsll.
 819         (DSLLV): Use do_dsllv.
 820         (DSRA): Use do_dsra.
 821         (DSRL): Use do_dsrl.
 822         (DSRLV): Use do_dsrlv.
 823         (BC1): Move *vr4100 to get the HACK generator working.
 824         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 825         get the HACK generator working.
 826         (MACC) Rename to get the HACK generator working.
 827         (DMACC,MACCS,DMACCS): Add the 64.
 828
 829 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 830
 831         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 832         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 833
 834 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 835
 836     * mips/interp.c (DEBUG): Cleanups.
 837
 838 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 839
 840         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 841         (tx3904sio_tickle): fflush after a stdout character output.
 842
 843 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 844
 845         * interp.c (sim_close): Uninstall modules.
 846
 847 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 848
 849         * sim-main.h, interp.c (sim_monitor): Change to global
 850         function.
 851
 852 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 853
 854         * configure.in (vr4100): Only include vr4100 instructions in
 855         simulator.
 856         * configure: Re-generate.
 857         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 858
 859 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 860
 861         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 862         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 863         true alternative.
 864
 865         * configure.in (sim_default_gen, sim_use_gen): Replace with
 866         sim_gen.
 867         (--enable-sim-igen): Delete config option. Always using IGEN.
 868         * configure: Re-generate.
 869
 870         * Makefile.in (gencode): Kill, kill, kill.
 871         * gencode.c: Ditto.
 872
 873 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 874
 875         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 876         bit mips16 igen simulator.
 877         * configure: Re-generate.
 878
 879         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 880         as part of vr4100 ISA.
 881         * vr.igen: Mark all instructions as 64 bit only.
 882
 883 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 884
 885         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 886         Pacify GCC.
 887
 888 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 889
 890         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 891         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 892         * configure: Re-generate.
 893
 894         * m16.igen (BREAK): Define breakpoint instruction.
 895         (JALX32): Mark instruction as mips16 and not r3900.
 896         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 897
 898         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 899
 900 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 901
 902         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 903         insn as a debug breakpoint.
 904
 905         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 906         pending.slot_size.
 907         (PENDING_SCHED): Clean up trace statement.
 908         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 909         (PENDING_FILL): Delay write by only one cycle.
 910         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 911
 912         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 913         of pending writes.
 914         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 915         32 & 64.
 916         (pending_tick): Move incrementing of index to FOR statement.
 917         (pending_tick): Only update PENDING_OUT after a write has occured.
 918
 919         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 920         build simulator.
 921         * configure: Re-generate.
 922
 923         * interp.c (sim_engine_run OLD): Delete explicit call to
 924         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 925
 926 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 927
 928         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 929         interrupt level number to match changed SignalExceptionInterrupt
 930         macro.
 931
 932 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 933
 934         * interp.c: #include "itable.h" if WITH_IGEN.
 935         (get_insn_name): New function.
 936         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 937         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 938
 939 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 940
 941         * configure: Rebuilt to inhale new common/aclocal.m4.
 942
 943 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 944
 945         * dv-tx3904sio.c: Include sim-assert.h.
 946
 947 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 948
 949         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 950         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 951         Reorganize target-specific sim-hardware checks.
 952         * configure: rebuilt.
 953         * interp.c (sim_open): For tx39 target boards, set
 954         OPERATING_ENVIRONMENT, add tx3904sio devices.
 955         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 956         ROM executables.  Install dv-sockser into sim-modules list.
 957
 958         * dv-tx3904irc.c: Compiler warning clean-up.
 959         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 960         frequent hw-trace messages.
 961
 962 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 963
 964         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 965
 966 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 967
 968         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 969
 970         * vr.igen: New file.
 971         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 972         * mips.igen: Define vr4100 model. Include vr.igen.
 973 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 974
 975         * mips.igen (check_mf_hilo): Correct check.
 976
 977 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 978
 979         * sim-main.h (interrupt_event): Add prototype.
 980
 981         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 982         register_ptr, register_value.
 983         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 984
 985         * sim-main.h (tracefh): Make extern.
 986
 987 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 988
 989         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 990         Reduce unnecessarily high timer event frequency.
 991         * dv-tx3904cpu.c: Ditto for interrupt event.
 992
 993 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 994
 995         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 996         to allay warnings.
 997         (interrupt_event): Made non-static.
 998
 999         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1000         interchange of configuration values for external vs. internal
1001         clock dividers.
1002
1003 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1004
1005         * mips.igen (BREAK): Moved code to here for
1006         simulator-reserved break instructions.
1007         * gencode.c (build_instruction): Ditto.
1008         * interp.c (signal_exception): Code moved from here.  Non-
1009         reserved instructions now use exception vector, rather
1010         than halting sim.
1011         * sim-main.h: Moved magic constants to here.
1012
1013 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1014
1015         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1016         register upon non-zero interrupt event level, clear upon zero
1017         event value.
1018         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1019         by passing zero event value.
1020         (*_io_{read,write}_buffer): Endianness fixes.
1021         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1022         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1023
1024         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1025         serial I/O and timer module at base address 0xFFFF0000.
1026
1027 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1028
1029         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1030         and BigEndianCPU.
1031
1032 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1033
1034         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1035         parts.
1036         * configure: Update.
1037
1038 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1039
1040         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1041         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1042         * configure.in: Include tx3904tmr in hw_device list.
1043         * configure: Rebuilt.
1044         * interp.c (sim_open): Instantiate three timer instances.
1045         Fix address typo of tx3904irc instance.
1046
1047 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1048
1049         * interp.c (signal_exception): SystemCall exception now uses
1050         the exception vector.
1051
1052 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1053
1054         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1055         to allay warnings.
1056
1057 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1058
1059         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1060
1061 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1062
1063         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1064
1065         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1066         sim-main.h. Declare a struct hw_descriptor instead of struct
1067         hw_device_descriptor.
1068
1069 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1070
1071         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1072         right bits and then re-align left hand bytes to correct byte
1073         lanes.  Fix incorrect computation in do_store_left when loading
1074         bytes from second word.
1075
1076 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1077
1078         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1079         * interp.c (sim_open): Only create a device tree when HW is
1080         enabled.
1081
1082         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1083         * interp.c (signal_exception): Ditto.
1084
1085 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1086
1087         * gencode.c: Mark BEGEZALL as LIKELY.
1088
1089 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1090
1091         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1092         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1093
1094 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1095
1096         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1097         modules.  Recognize TX39 target with "mips*tx39" pattern.
1098         * configure: Rebuilt.
1099         * sim-main.h (*): Added many macros defining bits in
1100         TX39 control registers.
1101         (SignalInterrupt): Send actual PC instead of NULL.
1102         (SignalNMIReset): New exception type.
1103         * interp.c (board): New variable for future use to identify
1104         a particular board being simulated.
1105         (mips_option_handler,mips_options): Added "--board" option.
1106         (interrupt_event): Send actual PC.
1107         (sim_open): Make memory layout conditional on board setting.
1108         (signal_exception): Initial implementation of hardware interrupt
1109         handling.  Accept another break instruction variant for simulator
1110         exit.
1111         (decode_coproc): Implement RFE instruction for TX39.
1112         (mips.igen): Decode RFE instruction as such.
1113         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1114         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1115         bbegin to implement memory map.
1116         * dv-tx3904cpu.c: New file.
1117         * dv-tx3904irc.c: New file.
1118
1119 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1120
1121         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1122
1123 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1124
1125         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1126         with calls to check_div_hilo.
1127
1128 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1129
1130         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1131         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1132         Add special r3900 version of do_mult_hilo.
1133         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1134         with calls to check_mult_hilo.
1135         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1136         with calls to check_div_hilo.
1137
1138 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1139
1140         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1141         Document a replacement.
1142
1143 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1144
1145         * interp.c (sim_monitor): Make mon_printf work.
1146
1147 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1148
1149         * sim-main.h (INSN_NAME): New arg `cpu'.
1150
1151 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1152
1153         * configure: Regenerated to track ../common/aclocal.m4 changes.
1154
1155 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1156
1157         * configure: Regenerated to track ../common/aclocal.m4 changes.
1158         * config.in: Ditto.
1159
1160 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1161
1162         * acconfig.h: New file.
1163         * configure.in: Reverted change of Apr 24; use sinclude again.
1164
1165 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1166
1167         * configure: Regenerated to track ../common/aclocal.m4 changes.
1168         * config.in: Ditto.
1169
1170 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1171
1172         * configure.in: Don't call sinclude.
1173
1174 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1175
1176         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1177
1178 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1179
1180         * mips.igen (ERET): Implement.
1181
1182         * interp.c (decode_coproc): Return sign-extended EPC.
1183
1184         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1185
1186         * interp.c (signal_exception): Do not ignore Trap.
1187         (signal_exception): On TRAP, restart at exception address.
1188         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1189         (signal_exception): Update.
1190         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1191         so that TRAP instructions are caught.
1192
1193 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1194
1195         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1196         contains HI/LO access history.
1197         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1198         (HIACCESS, LOACCESS): Delete, replace with
1199         (HIHISTORY, LOHISTORY): New macros.
1200         (CHECKHILO): Delete all, moved to mips.igen
1201
1202         * gencode.c (build_instruction): Do not generate checks for
1203         correct HI/LO register usage.
1204
1205         * interp.c (old_engine_run): Delete checks for correct HI/LO
1206         register usage.
1207
1208         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1209         check_mf_cycles): New functions.
1210         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1211         do_divu, domultx, do_mult, do_multu): Use.
1212
1213         * tx.igen ("madd", "maddu"): Use.
1214
1215 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1216
1217         * mips.igen (DSRAV): Use function do_dsrav.
1218         (SRAV): Use new function do_srav.
1219
1220         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1221         (B): Sign extend 11 bit immediate.
1222         (EXT-B*): Shift 16 bit immediate left by 1.
1223         (ADDIU*): Don't sign extend immediate value.
1224
1225 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1226
1227         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1228
1229         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1230         functions.
1231
1232         * mips.igen (delayslot32, nullify_next_insn): New functions.
1233         (m16.igen): Always include.
1234         (do_*): Add more tracing.
1235
1236         * m16.igen (delayslot16): Add NIA argument, could be called by a
1237         32 bit MIPS16 instruction.
1238
1239         * interp.c (ifetch16): Move function from here.
1240         * sim-main.c (ifetch16): To here.
1241
1242         * sim-main.c (ifetch16, ifetch32): Update to match current
1243         implementations of LH, LW.
1244         (signal_exception): Don't print out incorrect hex value of illegal
1245         instruction.
1246
1247 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1248
1249         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1250         instruction.
1251
1252         * m16.igen: Implement MIPS16 instructions.
1253
1254         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1255         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1256         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1257         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1258         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1259         bodies of corresponding code from 32 bit insn to these.  Also used
1260         by MIPS16 versions of functions.
1261
1262         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1263         (IMEM16): Drop NR argument from macro.
1264
1265 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1266
1267         * Makefile.in (SIM_OBJS): Add sim-main.o.
1268
1269         * sim-main.h (address_translation, load_memory, store_memory,
1270         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1271         as INLINE_SIM_MAIN.
1272         (pr_addr, pr_uword64): Declare.
1273         (sim-main.c): Include when H_REVEALS_MODULE_P.
1274
1275         * interp.c (address_translation, load_memory, store_memory,
1276         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1277         from here.
1278         * sim-main.c: To here. Fix compilation problems.
1279
1280         * configure.in: Enable inlining.
1281         * configure: Re-config.
1282
1283 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1284
1285         * configure: Regenerated to track ../common/aclocal.m4 changes.
1286
1287 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1288
1289         * mips.igen: Include tx.igen.
1290         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1291         * tx.igen: New file, contains MADD and MADDU.
1292
1293         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1294         the hardwired constant `7'.
1295         (store_memory): Ditto.
1296         (LOADDRMASK): Move definition to sim-main.h.
1297
1298         mips.igen (MTC0): Enable for r3900.
1299         (ADDU): Add trace.
1300
1301         mips.igen (do_load_byte): Delete.
1302         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1303         do_store_right): New functions.
1304         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1305
1306         configure.in: Let the tx39 use igen again.
1307         configure: Update.
1308
1309 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1310
1311         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1312         not an address sized quantity.  Return zero for cache sizes.
1313
1314 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1315
1316         * mips.igen (r3900): r3900 does not support 64 bit integer
1317         operations.
1318
1319 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1320
1321         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1322         than igen one.
1323         * configure : Rebuild.
1324
1325 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1326
1327         * configure: Regenerated to track ../common/aclocal.m4 changes.
1328
1329 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1330
1331         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1332
1333 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1334
1335         * configure: Regenerated to track ../common/aclocal.m4 changes.
1336         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1337
1338 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1339
1340         * configure: Regenerated to track ../common/aclocal.m4 changes.
1341
1342 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1343
1344         * interp.c (Max, Min): Comment out functions. Not yet used.
1345
1346 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1347
1348         * configure: Regenerated to track ../common/aclocal.m4 changes.
1349
1350 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1351
1352         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1353         configurable settings for stand-alone simulator.
1354
1355         * configure.in: Added X11 search, just in case.
1356
1357         * configure: Regenerated.
1358
1359 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1360
1361         * interp.c (sim_write, sim_read, load_memory, store_memory):
1362         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1363
1364 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1365
1366         * sim-main.h (GETFCC): Return an unsigned value.
1367
1368 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1369
1370         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1371         (DADD): Result destination is RD not RT.
1372
1373 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1374
1375         * sim-main.h (HIACCESS, LOACCESS): Always define.
1376
1377         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1378
1379         * interp.c (sim_info): Delete.
1380
1381 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1382
1383         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1384         (mips_option_handler): New argument `cpu'.
1385         (sim_open): Update call to sim_add_option_table.
1386
1387 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1388
1389         * mips.igen (CxC1): Add tracing.
1390
1391 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1392
1393         * sim-main.h (Max, Min): Declare.
1394
1395         * interp.c (Max, Min): New functions.
1396
1397         * mips.igen (BC1): Add tracing.
1398
1399 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1400
1401         * interp.c Added memory map for stack in vr4100
1402
1403 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1404
1405         * interp.c (load_memory): Add missing "break"'s.
1406
1407 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1408
1409         * interp.c (sim_store_register, sim_fetch_register): Pass in
1410         length parameter.  Return -1.
1411
1412 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1413
1414         * interp.c: Added hardware init hook, fixed warnings.
1415
1416 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1417
1418         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1419
1420 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1421
1422         * interp.c (ifetch16): New function.
1423
1424         * sim-main.h (IMEM32): Rename IMEM.
1425         (IMEM16_IMMED): Define.
1426         (IMEM16): Define.
1427         (DELAY_SLOT): Update.
1428
1429         * m16run.c (sim_engine_run): New file.
1430
1431         * m16.igen: All instructions except LB.
1432         (LB): Call do_load_byte.
1433         * mips.igen (do_load_byte): New function.
1434         (LB): Call do_load_byte.
1435
1436         * mips.igen: Move spec for insn bit size and high bit from here.
1437         * Makefile.in (tmp-igen, tmp-m16): To here.
1438
1439         * m16.dc: New file, decode mips16 instructions.
1440
1441         * Makefile.in (SIM_NO_ALL): Define.
1442         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1443
1444 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1445
1446         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1447         point unit to 32 bit registers.
1448         * configure: Re-generate.
1449
1450 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1451
1452         * configure.in (sim_use_gen): Make IGEN the default simulator
1453         generator for generic 32 and 64 bit mips targets.
1454         * configure: Re-generate.
1455
1456 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1457
1458         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1459         bitsize.
1460
1461         * interp.c (sim_fetch_register, sim_store_register): Read/write
1462         FGR from correct location.
1463         (sim_open): Set size of FGR's according to
1464         WITH_TARGET_FLOATING_POINT_BITSIZE.
1465
1466         * sim-main.h (FGR): Store floating point registers in a separate
1467         array.
1468
1469 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1470
1471         * configure: Regenerated to track ../common/aclocal.m4 changes.
1472
1473 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1474
1475         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1476
1477         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1478
1479         * interp.c (pending_tick): New function.  Deliver pending writes.
1480
1481         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1482         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1483         it can handle mixed sized quantites and single bits.
1484
1485 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1486
1487         * interp.c (oengine.h): Do not include when building with IGEN.
1488         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1489         (sim_info): Ditto for PROCESSOR_64BIT.
1490         (sim_monitor): Replace ut_reg with unsigned_word.
1491         (*): Ditto for t_reg.
1492         (LOADDRMASK): Define.
1493         (sim_open): Remove defunct check that host FP is IEEE compliant,
1494         using software to emulate floating point.
1495         (value_fpr, ...): Always compile, was conditional on HASFPU.
1496
1497 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1498
1499         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1500         size.
1501
1502         * interp.c (SD, CPU): Define.
1503         (mips_option_handler): Set flags in each CPU.
1504         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1505         (sim_close): Do not clear STATE, deleted anyway.
1506         (sim_write, sim_read): Assume CPU zero's vm should be used for
1507         data transfers.
1508         (sim_create_inferior): Set the PC for all processors.
1509         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1510         argument.
1511         (mips16_entry): Pass correct nr of args to store_word, load_word.
1512         (ColdReset): Cold reset all cpu's.
1513         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1514         (sim_monitor, load_memory, store_memory, signal_exception): Use
1515         `CPU' instead of STATE_CPU.
1516
1517
1518         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1519         SD or CPU_.
1520
1521         * sim-main.h (signal_exception): Add sim_cpu arg.
1522         (SignalException*): Pass both SD and CPU to signal_exception.
1523         * interp.c (signal_exception): Update.
1524
1525         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1526         Ditto
1527         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1528         address_translation): Ditto
1529         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1530
1531 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1532
1533         * configure: Regenerated to track ../common/aclocal.m4 changes.
1534
1535 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1536
1537         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1538
1539         * mips.igen (model): Map processor names onto BFD name.
1540
1541         * sim-main.h (CPU_CIA): Delete.
1542         (SET_CIA, GET_CIA): Define
1543
1544 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1545
1546         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1547         regiser.
1548
1549         * configure.in (default_endian): Configure a big-endian simulator
1550         by default.
1551         * configure: Re-generate.
1552
1553 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1554
1555         * configure: Regenerated to track ../common/aclocal.m4 changes.
1556
1557 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1558
1559         * interp.c (sim_monitor): Handle Densan monitor outbyte
1560         and inbyte functions.
1561
1562 1997-12-29  Felix Lee  <flee@cygnus.com>
1563
1564         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1565
1566 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1567
1568         * Makefile.in (tmp-igen): Arrange for $zero to always be
1569         reset to zero after every instruction.
1570
1571 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1572
1573         * configure: Regenerated to track ../common/aclocal.m4 changes.
1574         * config.in: Ditto.
1575
1576 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1577
1578         * mips.igen (MSUB): Fix to work like MADD.
1579         * gencode.c (MSUB): Similarly.
1580
1581 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1582
1583         * configure: Regenerated to track ../common/aclocal.m4 changes.
1584
1585 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1586
1587         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1588
1589 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1590
1591         * sim-main.h (sim-fpu.h): Include.
1592
1593         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1594         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1595         using host independant sim_fpu module.
1596
1597 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1598
1599         * interp.c (signal_exception): Report internal errors with SIGABRT
1600         not SIGQUIT.
1601
1602         * sim-main.h (C0_CONFIG): New register.
1603         (signal.h): No longer include.
1604
1605         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1606
1607 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1608
1609         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1610
1611 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1612
1613         * mips.igen: Tag vr5000 instructions.
1614         (ANDI): Was missing mipsIV model, fix assembler syntax.
1615         (do_c_cond_fmt): New function.
1616         (C.cond.fmt): Handle mips I-III which do not support CC field
1617         separatly.
1618         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1619         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1620         in IV3.2 spec.
1621         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1622         vr5000 which saves LO in a GPR separatly.
1623
1624         * configure.in (enable-sim-igen): For vr5000, select vr5000
1625         specific instructions.
1626         * configure: Re-generate.
1627
1628 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1629
1630         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1631
1632         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1633         fmt_uninterpreted_64 bit cases to switch.  Convert to
1634         fmt_formatted,
1635
1636         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1637
1638         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1639         as specified in IV3.2 spec.
1640         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1641
1642 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1643
1644         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1645         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1646         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1647         PENDING_FILL versions of instructions.  Simplify.
1648         (X): New function.
1649         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1650         instructions.
1651         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1652         a signed value.
1653         (MTHI, MFHI): Disable code checking HI-LO.
1654
1655         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1656         global.
1657         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1658
1659 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1660
1661         * gencode.c (build_mips16_operands): Replace IPC with cia.
1662
1663         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1664         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1665         IPC to `cia'.
1666         (UndefinedResult): Replace function with macro/function
1667         combination.
1668         (sim_engine_run): Don't save PC in IPC.
1669
1670         * sim-main.h (IPC): Delete.
1671
1672
1673         * interp.c (signal_exception, store_word, load_word,
1674         address_translation, load_memory, store_memory, cache_op,
1675         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1676         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1677         current instruction address - cia - argument.
1678         (sim_read, sim_write): Call address_translation directly.
1679         (sim_engine_run): Rename variable vaddr to cia.
1680         (signal_exception): Pass cia to sim_monitor
1681
1682         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1683         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1684         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1685
1686         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1687         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1688         SIM_ASSERT.
1689
1690         * interp.c (signal_exception): Pass restart address to
1691         sim_engine_restart.
1692
1693         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1694         idecode.o): Add dependency.
1695
1696         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1697         Delete definitions
1698         (DELAY_SLOT): Update NIA not PC with branch address.
1699         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1700
1701         * mips.igen: Use CIA not PC in branch calculations.
1702         (illegal): Call SignalException.
1703         (BEQ, ADDIU): Fix assembler.
1704
1705 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1706
1707         * m16.igen (JALX): Was missing.
1708
1709         * configure.in (enable-sim-igen): New configuration option.
1710         * configure: Re-generate.
1711
1712         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1713
1714         * interp.c (load_memory, store_memory): Delete parameter RAW.
1715         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1716         bypassing {load,store}_memory.
1717
1718         * sim-main.h (ByteSwapMem): Delete definition.
1719
1720         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1721
1722         * interp.c (sim_do_command, sim_commands): Delete mips specific
1723         commands.  Handled by module sim-options.
1724
1725         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1726         (WITH_MODULO_MEMORY): Define.
1727
1728         * interp.c (sim_info): Delete code printing memory size.
1729
1730         * interp.c (mips_size): Nee sim_size, delete function.
1731         (power2): Delete.
1732         (monitor, monitor_base, monitor_size): Delete global variables.
1733         (sim_open, sim_close): Delete code creating monitor and other
1734         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1735         manage memory regions.
1736         (load_memory, store_memory): Use sim-core for memory model.
1737
1738         * interp.c (address_translation): Delete all memory map code
1739         except line forcing 32 bit addresses.
1740
1741 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1742
1743         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1744         trace options.
1745
1746         * interp.c (logfh, logfile): Delete globals.
1747         (sim_open, sim_close): Delete code opening & closing log file.
1748         (mips_option_handler): Delete -l and -n options.
1749         (OPTION mips_options): Ditto.
1750
1751         * interp.c (OPTION mips_options): Rename option trace to dinero.
1752         (mips_option_handler): Update.
1753
1754 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1755
1756         * interp.c (fetch_str): New function.
1757         (sim_monitor): Rewrite using sim_read & sim_write.
1758         (sim_open): Check magic number.
1759         (sim_open): Write monitor vectors into memory using sim_write.
1760         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1761         (sim_read, sim_write): Simplify - transfer data one byte at a
1762         time.
1763         (load_memory, store_memory): Clarify meaning of parameter RAW.
1764
1765         * sim-main.h (isHOST): Defete definition.
1766         (isTARGET): Mark as depreciated.
1767         (address_translation): Delete parameter HOST.
1768
1769         * interp.c (address_translation): Delete parameter HOST.
1770
1771 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1772
1773         * mips.igen:
1774
1775         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1776         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1777
1778 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1779
1780         * mips.igen: Add model filter field to records.
1781
1782 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1783
1784         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1785
1786         interp.c (sim_engine_run): Do not compile function sim_engine_run
1787         when WITH_IGEN == 1.
1788
1789         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1790         target architecture.
1791
1792         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1793         igen. Replace with configuration variables sim_igen_flags /
1794         sim_m16_flags.
1795
1796         * m16.igen: New file.  Copy mips16 insns here.
1797         * mips.igen: From here.
1798
1799 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1800
1801         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1802         to top.
1803         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1804
1805 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1806
1807         * gencode.c (build_instruction): Follow sim_write's lead in using
1808         BigEndianMem instead of !ByteSwapMem.
1809
1810 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1811
1812         * configure.in (sim_gen): Dependent on target, select type of
1813         generator.  Always select old style generator.
1814
1815         configure: Re-generate.
1816
1817         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1818         targets.
1819         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1820         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1821         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1822         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1823         SIM_@sim_gen@_*, set by autoconf.
1824
1825 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1826
1827         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1828
1829         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1830         CURRENT_FLOATING_POINT instead.
1831
1832         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1833         (address_translation): Raise exception InstructionFetch when
1834         translation fails and isINSTRUCTION.
1835
1836         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1837         sim_engine_run): Change type of of vaddr and paddr to
1838         address_word.
1839         (address_translation, prefetch, load_memory, store_memory,
1840         cache_op): Change type of vAddr and pAddr to address_word.
1841
1842         * gencode.c (build_instruction): Change type of vaddr and paddr to
1843         address_word.
1844
1845 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1846
1847         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1848         macro to obtain result of ALU op.
1849
1850 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1851
1852         * interp.c (sim_info): Call profile_print.
1853
1854 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1855
1856         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1857
1858         * sim-main.h (WITH_PROFILE): Do not define, defined in
1859         common/sim-config.h.  Use sim-profile module.
1860         (simPROFILE): Delete defintion.
1861
1862         * interp.c (PROFILE): Delete definition.
1863         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1864         (sim_close): Delete code writing profile histogram.
1865         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1866         Delete.
1867         (sim_engine_run): Delete code profiling the PC.
1868
1869 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1870
1871         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1872
1873         * interp.c (sim_monitor): Make register pointers of type
1874         unsigned_word*.
1875
1876         * sim-main.h: Make registers of type unsigned_word not
1877         signed_word.
1878
1879 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1880
1881         * interp.c (sync_operation): Rename from SyncOperation, make
1882         global, add SD argument.
1883         (prefetch): Rename from Prefetch, make global, add SD argument.
1884         (decode_coproc): Make global.
1885
1886         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1887
1888         * gencode.c (build_instruction): Generate DecodeCoproc not
1889         decode_coproc calls.
1890
1891         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1892         (SizeFGR): Move to sim-main.h
1893         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1894         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1895         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1896         sim-main.h.
1897         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1898         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1899         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1900         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1901         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1902         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1903
1904         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1905         exception.
1906         (sim-alu.h): Include.
1907         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1908         (sim_cia): Typedef to instruction_address.
1909
1910 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1911
1912         * Makefile.in (interp.o): Rename generated file engine.c to
1913         oengine.c.
1914
1915         * interp.c: Update.
1916
1917 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1918
1919         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1920
1921 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1922
1923         * gencode.c (build_instruction): For "FPSQRT", output correct
1924         number of arguments to Recip.
1925
1926 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1927
1928         * Makefile.in (interp.o): Depends on sim-main.h
1929
1930         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1931
1932         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1933         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1934         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1935         STATE, DSSTATE): Define
1936         (GPR, FGRIDX, ..): Define.
1937
1938         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1939         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1940         (GPR, FGRIDX, ...): Delete macros.
1941
1942         * interp.c: Update names to match defines from sim-main.h
1943
1944 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1945
1946         * interp.c (sim_monitor): Add SD argument.
1947         (sim_warning): Delete.  Replace calls with calls to
1948         sim_io_eprintf.
1949         (sim_error): Delete. Replace calls with sim_io_error.
1950         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1951         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1952         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1953         argument.
1954         (mips_size): Rename from sim_size. Add SD argument.
1955
1956         * interp.c (simulator): Delete global variable.
1957         (callback): Delete global variable.
1958         (mips_option_handler, sim_open, sim_write, sim_read,
1959         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1960         sim_size,sim_monitor): Use sim_io_* not callback->*.
1961         (sim_open): ZALLOC simulator struct.
1962         (PROFILE): Do not define.
1963
1964 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1965
1966         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1967         support.h with corresponding code.
1968
1969         * sim-main.h (word64, uword64), support.h: Move definition to
1970         sim-main.h.
1971         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1972
1973         * support.h: Delete
1974         * Makefile.in: Update dependencies
1975         * interp.c: Do not include.
1976
1977 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1978
1979         * interp.c (address_translation, load_memory, store_memory,
1980         cache_op): Rename to from AddressTranslation et.al., make global,
1981         add SD argument
1982
1983         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1984         CacheOp): Define.
1985
1986         * interp.c (SignalException): Rename to signal_exception, make
1987         global.
1988
1989         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1990
1991         * sim-main.h (SignalException, SignalExceptionInterrupt,
1992         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1993         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1994         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1995         Define.
1996
1997         * interp.c, support.h: Use.
1998
1999 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2000
2001         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2002         to value_fpr / store_fpr. Add SD argument.
2003         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2004         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2005
2006         * sim-main.h (ValueFPR, StoreFPR): Define.
2007
2008 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2009
2010         * interp.c (sim_engine_run): Check consistency between configure
2011         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2012         and HASFPU.
2013
2014         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2015         (mips_fpu): Configure WITH_FLOATING_POINT.
2016         (mips_endian): Configure WITH_TARGET_ENDIAN.
2017         * configure: Update.
2018
2019 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2020
2021         * configure: Regenerated to track ../common/aclocal.m4 changes.
2022
2023 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2024
2025         * configure: Regenerated.
2026
2027 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2028
2029         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2030
2031 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2032
2033         * gencode.c (print_igen_insn_models): Assume certain architectures
2034         include all mips* instructions.
2035         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2036         instruction.
2037
2038         * Makefile.in (tmp.igen): Add target. Generate igen input from
2039         gencode file.
2040
2041         * gencode.c (FEATURE_IGEN): Define.
2042         (main): Add --igen option.  Generate output in igen format.
2043         (process_instructions): Format output according to igen option.
2044         (print_igen_insn_format): New function.
2045         (print_igen_insn_models): New function.
2046         (process_instructions): Only issue warnings and ignore
2047         instructions when no FEATURE_IGEN.
2048
2049 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2050
2051         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2052         MIPS targets.
2053
2054 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2055
2056         * configure: Regenerated to track ../common/aclocal.m4 changes.
2057
2058 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2059
2060         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2061         SIM_RESERVED_BITS): Delete, moved to common.
2062         (SIM_EXTRA_CFLAGS): Update.
2063
2064 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2065
2066         * configure.in: Configure non-strict memory alignment.
2067         * configure: Regenerated to track ../common/aclocal.m4 changes.
2068
2069 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2070
2071         * configure: Regenerated to track ../common/aclocal.m4 changes.
2072
2073 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2074
2075         * gencode.c (SDBBP,DERET): Added (3900) insns.
2076         (RFE): Turn on for 3900.
2077         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2078         (dsstate): Made global.
2079         (SUBTARGET_R3900): Added.
2080         (CANCELDELAYSLOT): New.
2081         (SignalException): Ignore SystemCall rather than ignore and
2082         terminate.  Add DebugBreakPoint handling.
2083         (decode_coproc): New insns RFE, DERET; and new registers Debug
2084         and DEPC protected by SUBTARGET_R3900.
2085         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2086         bits explicitly.
2087         * Makefile.in,configure.in: Add mips subtarget option.
2088         * configure: Update.
2089
2090 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2091
2092         * gencode.c: Add r3900 (tx39).
2093
2094
2095 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2096
2097         * gencode.c (build_instruction): Don't need to subtract 4 for
2098         JALR, just 2.
2099
2100 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2101
2102         * interp.c: Correct some HASFPU problems.
2103
2104 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2105
2106         * configure: Regenerated to track ../common/aclocal.m4 changes.
2107
2108 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2109
2110         * interp.c (mips_options): Fix samples option short form, should
2111         be `x'.
2112
2113 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2114
2115         * interp.c (sim_info): Enable info code.  Was just returning.
2116
2117 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2118
2119         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2120         MFC0.
2121
2122 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2123
2124         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2125         constants.
2126         (build_instruction): Ditto for LL.
2127
2128 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2129
2130         * configure: Regenerated to track ../common/aclocal.m4 changes.
2131
2132 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2133
2134         * configure: Regenerated to track ../common/aclocal.m4 changes.
2135         * config.in: Ditto.
2136
2137 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2138
2139         * interp.c (sim_open): Add call to sim_analyze_program, update
2140         call to sim_config.
2141
2142 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2143
2144         * interp.c (sim_kill): Delete.
2145         (sim_create_inferior): Add ABFD argument. Set PC from same.
2146         (sim_load): Move code initializing trap handlers from here.
2147         (sim_open): To here.
2148         (sim_load): Delete, use sim-hload.c.
2149
2150         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2151
2152 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2153
2154         * configure: Regenerated to track ../common/aclocal.m4 changes.
2155         * config.in: Ditto.
2156
2157 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2158
2159         * interp.c (sim_open): Add ABFD argument.
2160         (sim_load): Move call to sim_config from here.
2161         (sim_open): To here.  Check return status.
2162
2163 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2164
2165         * gencode.c (build_instruction): Two arg MADD should
2166         not assign result to $0.
2167
2168 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2169
2170         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2171         * sim/mips/configure.in: Regenerate.
2172
2173 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2174
2175         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2176         signed8, unsigned8 et.al. types.
2177
2178         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2179         hosts when selecting subreg.
2180
2181 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2182
2183         * interp.c (sim_engine_run): Reset the ZERO register to zero
2184         regardless of FEATURE_WARN_ZERO.
2185         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2186
2187 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2188
2189         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2190         (SignalException): For BreakPoints ignore any mode bits and just
2191         save the PC.
2192         (SignalException): Always set the CAUSE register.
2193
2194 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2195
2196         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2197         exception has been taken.
2198
2199         * interp.c: Implement the ERET and mt/f sr instructions.
2200
2201 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2202
2203         * interp.c (SignalException): Don't bother restarting an
2204         interrupt.
2205
2206 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2207
2208         * interp.c (SignalException): Really take an interrupt.
2209         (interrupt_event): Only deliver interrupts when enabled.
2210
2211 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2212
2213         * interp.c (sim_info): Only print info when verbose.
2214         (sim_info) Use sim_io_printf for output.
2215
2216 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2217
2218         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2219         mips architectures.
2220
2221 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2222
2223         * interp.c (sim_do_command): Check for common commands if a
2224         simulator specific command fails.
2225
2226 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2227
2228         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2229         and simBE when DEBUG is defined.
2230
2231 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2232
2233         * interp.c (interrupt_event): New function.  Pass exception event
2234         onto exception handler.
2235
2236         * configure.in: Check for stdlib.h.
2237         * configure: Regenerate.
2238
2239         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2240         variable declaration.
2241         (build_instruction): Initialize memval1.
2242         (build_instruction): Add UNUSED attribute to byte, bigend,
2243         reverse.
2244         (build_operands): Ditto.
2245
2246         * interp.c: Fix GCC warnings.
2247         (sim_get_quit_code): Delete.
2248
2249         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2250         * Makefile.in: Ditto.
2251         * configure: Re-generate.
2252
2253         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2254
2255 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2256
2257         * interp.c (mips_option_handler): New function parse argumes using
2258         sim-options.
2259         (myname): Replace with STATE_MY_NAME.
2260         (sim_open): Delete check for host endianness - performed by
2261         sim_config.
2262         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2263         (sim_open): Move much of the initialization from here.
2264         (sim_load): To here.  After the image has been loaded and
2265         endianness set.
2266         (sim_open): Move ColdReset from here.
2267         (sim_create_inferior): To here.
2268         (sim_open): Make FP check less dependant on host endianness.
2269
2270         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2271         run.
2272         * interp.c (sim_set_callbacks): Delete.
2273
2274         * interp.c (membank, membank_base, membank_size): Replace with
2275         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2276         (sim_open): Remove call to callback->init. gdb/run do this.
2277
2278         * interp.c: Update
2279
2280         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2281
2282         * interp.c (big_endian_p): Delete, replaced by
2283         current_target_byte_order.
2284
2285 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2286
2287         * interp.c (host_read_long, host_read_word, host_swap_word,
2288         host_swap_long): Delete. Using common sim-endian.
2289         (sim_fetch_register, sim_store_register): Use H2T.
2290         (pipeline_ticks): Delete.  Handled by sim-events.
2291         (sim_info): Update.
2292         (sim_engine_run): Update.
2293
2294 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2295
2296         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2297         reason from here.
2298         (SignalException): To here. Signal using sim_engine_halt.
2299         (sim_stop_reason): Delete, moved to common.
2300
2301 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2302
2303         * interp.c (sim_open): Add callback argument.
2304         (sim_set_callbacks): Delete SIM_DESC argument.
2305         (sim_size): Ditto.
2306
2307 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2308
2309         * Makefile.in (SIM_OBJS): Add common modules.
2310
2311         * interp.c (sim_set_callbacks): Also set SD callback.
2312         (set_endianness, xfer_*, swap_*): Delete.
2313         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2314         Change to functions using sim-endian macros.
2315         (control_c, sim_stop): Delete, use common version.
2316         (simulate): Convert into.
2317         (sim_engine_run): This function.
2318         (sim_resume): Delete.
2319
2320         * interp.c (simulation): New variable - the simulator object.
2321         (sim_kind): Delete global - merged into simulation.
2322         (sim_load): Cleanup.  Move PC assignment from here.
2323         (sim_create_inferior): To here.
2324
2325         * sim-main.h: New file.
2326         * interp.c (sim-main.h): Include.
2327
2328 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2329
2330         * configure: Regenerated to track ../common/aclocal.m4 changes.
2331
2332 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2333
2334         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2335
2336 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2337
2338         * gencode.c (build_instruction): DIV instructions: check
2339         for division by zero and integer overflow before using
2340         host's division operation.
2341
2342 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2343
2344         * Makefile.in (SIM_OBJS): Add sim-load.o.
2345         * interp.c: #include bfd.h.
2346         (target_byte_order): Delete.
2347         (sim_kind, myname, big_endian_p): New static locals.
2348         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2349         after argument parsing.  Recognize -E arg, set endianness accordingly.
2350         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2351         load file into simulator.  Set PC from bfd.
2352         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2353         (set_endianness): Use big_endian_p instead of target_byte_order.
2354
2355 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2356
2357         * interp.c (sim_size): Delete prototype - conflicts with
2358         definition in remote-sim.h.  Correct definition.
2359
2360 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2361
2362         * configure: Regenerated to track ../common/aclocal.m4 changes.
2363         * config.in: Ditto.
2364
2365 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2366
2367         * interp.c (sim_open): New arg `kind'.
2368
2369         * configure: Regenerated to track ../common/aclocal.m4 changes.
2370
2371 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2372
2373         * configure: Regenerated to track ../common/aclocal.m4 changes.
2374
2375 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2376
2377         * interp.c (sim_open): Set optind to 0 before calling getopt.
2378
2379 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2380
2381         * configure: Regenerated to track ../common/aclocal.m4 changes.
2382
2383 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2384
2385         * interp.c : Replace uses of pr_addr with pr_uword64
2386         where the bit length is always 64 independent of SIM_ADDR.
2387         (pr_uword64) : added.
2388
2389 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2390
2391         * configure: Re-generate.
2392
2393 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2394
2395         * configure: Regenerate to track ../common/aclocal.m4 changes.
2396
2397 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2398
2399         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2400         in argv form.
2401         (other sim_*): New SIM_DESC argument.
2402
2403 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2404
2405         * interp.c: Fix printing of addresses for non-64-bit targets.
2406         (pr_addr): Add function to print address based on size.
2407
2408 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2409
2410         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2411
2412 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2413
2414         * gencode.c (build_mips16_operands): Correct computation of base
2415         address for extended PC relative instruction.
2416
2417 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2418
2419         * interp.c (mips16_entry): Add support for floating point cases.
2420         (SignalException): Pass floating point cases to mips16_entry.
2421         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2422         registers.
2423         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2424         or fmt_word.
2425         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2426         and then set the state to fmt_uninterpreted.
2427         (COP_SW): Temporarily set the state to fmt_word while calling
2428         ValueFPR.
2429
2430 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2431
2432         * gencode.c (build_instruction): The high order may be set in the
2433         comparison flags at any ISA level, not just ISA 4.
2434
2435 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2436
2437         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2438         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2439         * configure.in: sinclude ../common/aclocal.m4.
2440         * configure: Regenerated.
2441
2442 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2443
2444         * configure: Rebuild after change to aclocal.m4.
2445
2446 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2447
2448         * configure configure.in Makefile.in:  Update to new configure
2449         scheme which is more compatible with WinGDB builds.
2450         * configure.in:  Improve comment on how to run autoconf.
2451         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2452         * Makefile.in:  Use autoconf substitution to install common
2453         makefile fragment.
2454
2455 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2456
2457         * gencode.c (build_instruction): Use BigEndianCPU instead of
2458         ByteSwapMem.
2459
2460 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2461
2462         * interp.c (sim_monitor): Make output to stdout visible in
2463         wingdb's I/O log window.
2464
2465 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2466
2467         * support.h: Undo previous change to SIGTRAP
2468         and SIGQUIT values.
2469
2470 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2471
2472         * interp.c (store_word, load_word): New static functions.
2473         (mips16_entry): New static function.
2474         (SignalException): Look for mips16 entry and exit instructions.
2475         (simulate): Use the correct index when setting fpr_state after
2476         doing a pending move.
2477
2478 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2479
2480         * interp.c: Fix byte-swapping code throughout to work on
2481         both little- and big-endian hosts.
2482
2483 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2484
2485         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2486         with gdb/config/i386/xm-windows.h.
2487
2488 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2489
2490         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2491         that messes up arithmetic shifts.
2492
2493 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2494
2495         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2496         SIGTRAP and SIGQUIT for _WIN32.
2497
2498 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2499
2500         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2501         force a 64 bit multiplication.
2502         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2503         destination register is 0, since that is the default mips16 nop
2504         instruction.
2505
2506 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2507
2508         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2509         (build_endian_shift): Don't check proc64.
2510         (build_instruction): Always set memval to uword64.  Cast op2 to
2511         uword64 when shifting it left in memory instructions.  Always use
2512         the same code for stores--don't special case proc64.
2513
2514         * gencode.c (build_mips16_operands): Fix base PC value for PC
2515         relative operands.
2516         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2517         jal instruction.
2518         * interp.c (simJALDELAYSLOT): Define.
2519         (JALDELAYSLOT): Define.
2520         (INDELAYSLOT, INJALDELAYSLOT): Define.
2521         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2522
2523 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2524
2525         * interp.c (sim_open): add flush_cache as a PMON routine
2526         (sim_monitor): handle flush_cache by ignoring it
2527
2528 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2529
2530         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2531         BigEndianMem.
2532         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2533         (BigEndianMem): Rename to ByteSwapMem and change sense.
2534         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2535         BigEndianMem references to !ByteSwapMem.
2536         (set_endianness): New function, with prototype.
2537         (sim_open): Call set_endianness.
2538         (sim_info): Use simBE instead of BigEndianMem.
2539         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2540         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2541         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2542         ifdefs, keeping the prototype declaration.
2543         (swap_word): Rewrite correctly.
2544         (ColdReset): Delete references to CONFIG.  Delete endianness related
2545         code; moved to set_endianness.
2546
2547 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2548
2549         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2550         * interp.c (CHECKHILO): Define away.
2551         (simSIGINT): New macro.
2552         (membank_size): Increase from 1MB to 2MB.
2553         (control_c): New function.
2554         (sim_resume): Rename parameter signal to signal_number.  Add local
2555         variable prev.  Call signal before and after simulate.
2556         (sim_stop_reason): Add simSIGINT support.
2557         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2558         functions always.
2559         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2560         if logfh is NULL.
2561         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2562         a call to sim_warning.
2563
2564 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2565
2566         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2567         16 bit instructions.
2568
2569 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2570
2571         Add support for mips16 (16 bit MIPS implementation):
2572         * gencode.c (inst_type): Add mips16 instruction encoding types.
2573         (GETDATASIZEINSN): Define.
2574         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2575         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2576         mtlo.
2577         (MIPS16_DECODE): New table, for mips16 instructions.
2578         (bitmap_val): New static function.
2579         (struct mips16_op): Define.
2580         (mips16_op_table): New table, for mips16 operands.
2581         (build_mips16_operands): New static function.
2582         (process_instructions): If PC is odd, decode a mips16
2583         instruction.  Break out instruction handling into new
2584         build_instruction function.
2585         (build_instruction): New static function, broken out of
2586         process_instructions.  Check modifiers rather than flags for SHIFT
2587         bit count and m[ft]{hi,lo} direction.
2588         (usage): Pass program name to fprintf.
2589         (main): Remove unused variable this_option_optind.  Change
2590         ``*loptarg++'' to ``loptarg++''.
2591         (my_strtoul): Parenthesize && within ||.
2592         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2593         (simulate): If PC is odd, fetch a 16 bit instruction, and
2594         increment PC by 2 rather than 4.
2595         * configure.in: Add case for mips16*-*-*.
2596         * configure: Rebuild.
2597
2598 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2599
2600         * interp.c: Allow -t to enable tracing in standalone simulator.
2601         Fix garbage output in trace file and error messages.
2602
2603 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2604
2605         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2606         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2607         * configure.in: Simplify using macros in ../common/aclocal.m4.
2608         * configure: Regenerated.
2609         * tconfig.in: New file.
2610
2611 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2612
2613         * interp.c: Fix bugs in 64-bit port.
2614         Use ansi function declarations for msvc compiler.
2615         Initialize and test file pointer in trace code.
2616         Prevent duplicate definition of LAST_EMED_REGNUM.
2617
2618 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2619
2620         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2621
2622 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2623
2624         * interp.c (SignalException): Check for explicit terminating
2625         breakpoint value.
2626         * gencode.c: Pass instruction value through SignalException()
2627         calls for Trap, Breakpoint and Syscall.
2628
2629 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2630
2631         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2632         only used on those hosts that provide it.
2633         * configure.in: Add sqrt() to list of functions to be checked for.
2634         * config.in: Re-generated.
2635         * configure: Re-generated.
2636
2637 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2638
2639         * gencode.c (process_instructions): Call build_endian_shift when
2640         expanding STORE RIGHT, to fix swr.
2641         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2642         clear the high bits.
2643         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2644         Fix float to int conversions to produce signed values.
2645
2646 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2647
2648         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2649         (process_instructions): Correct handling of nor instruction.
2650         Correct shift count for 32 bit shift instructions. Correct sign
2651         extension for arithmetic shifts to not shift the number of bits in
2652         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2653         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2654         Fix madd.
2655         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2656         It's OK to have a mult follow a mult.  What's not OK is to have a
2657         mult follow an mfhi.
2658         (Convert): Comment out incorrect rounding code.
2659
2660 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2661
2662         * interp.c (sim_monitor): Improved monitor printf
2663         simulation. Tidied up simulator warnings, and added "--log" option
2664         for directing warning message output.
2665         * gencode.c: Use sim_warning() rather than WARNING macro.
2666
2667 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2668
2669         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2670         getopt1.o, rather than on gencode.c.  Link objects together.
2671         Don't link against -liberty.
2672         (gencode.o, getopt.o, getopt1.o): New targets.
2673         * gencode.c: Include <ctype.h> and "ansidecl.h".
2674         (AND): Undefine after including "ansidecl.h".
2675         (ULONG_MAX): Define if not defined.
2676         (OP_*): Don't define macros; now defined in opcode/mips.h.
2677         (main): Call my_strtoul rather than strtoul.
2678         (my_strtoul): New static function.
2679
2680 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2681
2682         * gencode.c (process_instructions):  Generate word64 and uword64
2683         instead of `long long' and `unsigned long long' data types.
2684         * interp.c:  #include sysdep.h to get signals, and define default
2685         for SIGBUS.
2686         * (Convert):  Work around for Visual-C++ compiler bug with type
2687         conversion.
2688         * support.h:  Make things compile under Visual-C++ by using
2689         __int64 instead of `long long'.  Change many refs to long long
2690         into word64/uword64 typedefs.
2691
2692 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2693
2694         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2695         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2696         (docdir): Removed.
2697         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2698         (AC_PROG_INSTALL): Added.
2699         (AC_PROG_CC): Moved to before configure.host call.
2700         * configure: Rebuilt.
2701
2702 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2703
2704         * configure.in: Define @SIMCONF@ depending on mips target.
2705         * configure: Rebuild.
2706         * Makefile.in (run): Add @SIMCONF@ to control simulator
2707         construction.
2708         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2709         * interp.c: Remove some debugging, provide more detailed error
2710         messages, update memory accesses to use LOADDRMASK.
2711
2712 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2713
2714         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2715         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2716         stamp-h.
2717         * configure: Rebuild.
2718         * config.in: New file, generated by autoheader.
2719         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2720         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2721         HAVE_ANINT and HAVE_AINT, as appropriate.
2722         * Makefile.in (run): Use @LIBS@ rather than -lm.
2723         (interp.o): Depend upon config.h.
2724         (Makefile): Just rebuild Makefile.
2725         (clean): Remove stamp-h.
2726         (mostlyclean): Make the same as clean, not as distclean.
2727         (config.h, stamp-h): New targets.
2728
2729 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2730
2731         * interp.c (ColdReset): Fix boolean test. Make all simulator
2732         globals static.
2733
2734 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2735
2736         * interp.c (xfer_direct_word, xfer_direct_long,
2737         swap_direct_word, swap_direct_long, xfer_big_word,
2738         xfer_big_long, xfer_little_word, xfer_little_long,
2739         swap_word,swap_long): Added.
2740         * interp.c (ColdReset): Provide function indirection to
2741         host<->simulated_target transfer routines.
2742         * interp.c (sim_store_register, sim_fetch_register): Updated to
2743         make use of indirected transfer routines.
2744
2745 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2746
2747         * gencode.c (process_instructions): Ensure FP ABS instruction
2748         recognised.
2749         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2750         system call support.
2751
2752 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2753
2754         * interp.c (sim_do_command): Complain if callback structure not
2755         initialised.
2756
2757 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2758
2759         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2760         support for Sun hosts.
2761         * Makefile.in (gencode): Ensure the host compiler and libraries
2762         used for cross-hosted build.
2763
2764 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2765
2766         * interp.c, gencode.c: Some more (TODO) tidying.
2767
2768 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2769
2770         * gencode.c, interp.c: Replaced explicit long long references with
2771         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2772         * support.h (SET64LO, SET64HI): Macros added.
2773
2774 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2775
2776         * configure: Regenerate with autoconf 2.7.
2777
2778 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2779
2780         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2781         * support.h: Remove superfluous "1" from #if.
2782         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2783
2784 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2785
2786         * interp.c (StoreFPR): Control UndefinedResult() call on
2787         WARN_RESULT manifest.
2788
2789 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2790
2791         * gencode.c: Tidied instruction decoding, and added FP instruction
2792         support.
2793
2794         * interp.c: Added dineroIII, and BSD profiling support. Also
2795         run-time FP handling.
2796
2797 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2798
2799         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2800         gencode.c, interp.c, support.h: created.