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[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
1 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
2
3 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
4 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
5 (idt_monitor_base): Base address for IDT monitor traps.
6 (pmon_monitor_base): Ditto for PMON.
7 (lsipmon_monitor_base): Ditto for LSI PMON.
8 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
9 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
10 (sim_firmware_command): New function.
11 (mips_option_handler): Call it for OPTION_FIRMWARE.
12 (sim_open): Allocate memory for idt_monitor region. If "--board"
13 option was given, add no monitor by default. Add BREAK hooks only if
14 monitors are also there.
15
16 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
17
18 * interp.c (sim_monitor): Flush output before reading input.
19
20 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
21
22 * tconfig.in (SIM_HANDLES_LMA): Always define.
23
24 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
25
26 From Mark Salter <msalter@cygnus.com>:
27 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
28 (sim_open): Add setup for BSP board.
29
30 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
31
32 * mips.igen (MULT, MULTU): Add syntax for two operand version.
33 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
34 them as unimplemented.
35
36 1999-05-08 Felix Lee <flee@cygnus.com>
37
38 * configure: Regenerated to track ../common/aclocal.m4 changes.
39
40 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
41
42 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
43
44 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
45
46 * configure.in: Any mips64vr5*-*-* target should have
47 -DTARGET_ENABLE_FR=1.
48 (default_endian): Any mips64vr*el-*-* target should default to
49 LITTLE_ENDIAN.
50 * configure: Re-generate.
51
52 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
53
54 * mips.igen (ldl): Extend from _16_, not 32.
55
56 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
57
58 * interp.c (sim_store_register): Force registers written to by GDB
59 into an un-interpreted state.
60
61 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
62
63 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
64 CPU, start periodic background I/O polls.
65 (tx3904sio_poll): New function: periodic I/O poller.
66
67 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
68
69 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
70
71 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
72
73 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
74 case statement.
75
76 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
77
78 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
79 (load_word): Call SIM_CORE_SIGNAL hook on error.
80 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
81 starting. For exception dispatching, pass PC instead of NULL_CIA.
82 (decode_coproc): Use COP0_BADVADDR to store faulting address.
83 * sim-main.h (COP0_BADVADDR): Define.
84 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
85 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
86 (_sim_cpu): Add exc_* fields to store register value snapshots.
87 * mips.igen (*): Replace memory-related SignalException* calls
88 with references to SIM_CORE_SIGNAL hook.
89
90 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
91 fix.
92 * sim-main.c (*): Minor warning cleanups.
93
94 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
95
96 * m16.igen (DADDIU5): Correct type-o.
97
98 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
99
100 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
101 variables.
102
103 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
104
105 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
106 to include path.
107 (interp.o): Add dependency on itable.h
108 (oengine.c, gencode): Delete remaining references.
109 (BUILT_SRC_FROM_GEN): Clean up.
110
111 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
112
113 * vr4run.c: New.
114 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
115 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
116 tmp-run-hack) : New.
117 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
118 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
119 Drop the "64" qualifier to get the HACK generator working.
120 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
121 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
122 qualifier to get the hack generator working.
123 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
124 (DSLL): Use do_dsll.
125 (DSLLV): Use do_dsllv.
126 (DSRA): Use do_dsra.
127 (DSRL): Use do_dsrl.
128 (DSRLV): Use do_dsrlv.
129 (BC1): Move *vr4100 to get the HACK generator working.
130 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
131 get the HACK generator working.
132 (MACC) Rename to get the HACK generator working.
133 (DMACC,MACCS,DMACCS): Add the 64.
134
135 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
136
137 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
138 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
139
140 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
141
142 * mips/interp.c (DEBUG): Cleanups.
143
144 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
145
146 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
147 (tx3904sio_tickle): fflush after a stdout character output.
148
149 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
150
151 * interp.c (sim_close): Uninstall modules.
152
153 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
154
155 * sim-main.h, interp.c (sim_monitor): Change to global
156 function.
157
158 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
159
160 * configure.in (vr4100): Only include vr4100 instructions in
161 simulator.
162 * configure: Re-generate.
163 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
164
165 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
166
167 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
168 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
169 true alternative.
170
171 * configure.in (sim_default_gen, sim_use_gen): Replace with
172 sim_gen.
173 (--enable-sim-igen): Delete config option. Always using IGEN.
174 * configure: Re-generate.
175
176 * Makefile.in (gencode): Kill, kill, kill.
177 * gencode.c: Ditto.
178
179 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
180
181 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
182 bit mips16 igen simulator.
183 * configure: Re-generate.
184
185 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
186 as part of vr4100 ISA.
187 * vr.igen: Mark all instructions as 64 bit only.
188
189 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
190
191 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
192 Pacify GCC.
193
194 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
195
196 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
197 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
198 * configure: Re-generate.
199
200 * m16.igen (BREAK): Define breakpoint instruction.
201 (JALX32): Mark instruction as mips16 and not r3900.
202 * mips.igen (C.cond.fmt): Fix typo in instruction format.
203
204 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
205
206 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
207
208 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
209 insn as a debug breakpoint.
210
211 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
212 pending.slot_size.
213 (PENDING_SCHED): Clean up trace statement.
214 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
215 (PENDING_FILL): Delay write by only one cycle.
216 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
217
218 * sim-main.c (pending_tick): Clean up trace statements. Add trace
219 of pending writes.
220 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
221 32 & 64.
222 (pending_tick): Move incrementing of index to FOR statement.
223 (pending_tick): Only update PENDING_OUT after a write has occured.
224
225 * configure.in: Add explicit mips-lsi-* target. Use gencode to
226 build simulator.
227 * configure: Re-generate.
228
229 * interp.c (sim_engine_run OLD): Delete explicit call to
230 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
231
232 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
233
234 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
235 interrupt level number to match changed SignalExceptionInterrupt
236 macro.
237
238 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
239
240 * interp.c: #include "itable.h" if WITH_IGEN.
241 (get_insn_name): New function.
242 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
243 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
244
245 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
246
247 * configure: Rebuilt to inhale new common/aclocal.m4.
248
249 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
250
251 * dv-tx3904sio.c: Include sim-assert.h.
252
253 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
254
255 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
256 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
257 Reorganize target-specific sim-hardware checks.
258 * configure: rebuilt.
259 * interp.c (sim_open): For tx39 target boards, set
260 OPERATING_ENVIRONMENT, add tx3904sio devices.
261 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
262 ROM executables. Install dv-sockser into sim-modules list.
263
264 * dv-tx3904irc.c: Compiler warning clean-up.
265 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
266 frequent hw-trace messages.
267
268 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
269
270 * vr.igen (MulAcc): Identify as a vr4100 specific function.
271
272 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
273
274 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
275
276 * vr.igen: New file.
277 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
278 * mips.igen: Define vr4100 model. Include vr.igen.
279 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
280
281 * mips.igen (check_mf_hilo): Correct check.
282
283 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
284
285 * sim-main.h (interrupt_event): Add prototype.
286
287 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
288 register_ptr, register_value.
289 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
290
291 * sim-main.h (tracefh): Make extern.
292
293 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
294
295 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
296 Reduce unnecessarily high timer event frequency.
297 * dv-tx3904cpu.c: Ditto for interrupt event.
298
299 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
300
301 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
302 to allay warnings.
303 (interrupt_event): Made non-static.
304
305 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
306 interchange of configuration values for external vs. internal
307 clock dividers.
308
309 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
310
311 * mips.igen (BREAK): Moved code to here for
312 simulator-reserved break instructions.
313 * gencode.c (build_instruction): Ditto.
314 * interp.c (signal_exception): Code moved from here. Non-
315 reserved instructions now use exception vector, rather
316 than halting sim.
317 * sim-main.h: Moved magic constants to here.
318
319 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
320
321 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
322 register upon non-zero interrupt event level, clear upon zero
323 event value.
324 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
325 by passing zero event value.
326 (*_io_{read,write}_buffer): Endianness fixes.
327 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
328 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
329
330 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
331 serial I/O and timer module at base address 0xFFFF0000.
332
333 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
334
335 * mips.igen (SWC1) : Correct the handling of ReverseEndian
336 and BigEndianCPU.
337
338 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
339
340 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
341 parts.
342 * configure: Update.
343
344 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
345
346 * dv-tx3904tmr.c: New file - implements tx3904 timer.
347 * dv-tx3904{irc,cpu}.c: Mild reformatting.
348 * configure.in: Include tx3904tmr in hw_device list.
349 * configure: Rebuilt.
350 * interp.c (sim_open): Instantiate three timer instances.
351 Fix address typo of tx3904irc instance.
352
353 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
354
355 * interp.c (signal_exception): SystemCall exception now uses
356 the exception vector.
357
358 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
359
360 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
361 to allay warnings.
362
363 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
364
365 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
366
367 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
368
369 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
370
371 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
372 sim-main.h. Declare a struct hw_descriptor instead of struct
373 hw_device_descriptor.
374
375 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
376
377 * mips.igen (do_store_left, do_load_left): Compute nr of left and
378 right bits and then re-align left hand bytes to correct byte
379 lanes. Fix incorrect computation in do_store_left when loading
380 bytes from second word.
381
382 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
383
384 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
385 * interp.c (sim_open): Only create a device tree when HW is
386 enabled.
387
388 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
389 * interp.c (signal_exception): Ditto.
390
391 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
392
393 * gencode.c: Mark BEGEZALL as LIKELY.
394
395 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
396
397 * sim-main.h (ALU32_END): Sign extend 32 bit results.
398 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
399
400 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
401
402 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
403 modules. Recognize TX39 target with "mips*tx39" pattern.
404 * configure: Rebuilt.
405 * sim-main.h (*): Added many macros defining bits in
406 TX39 control registers.
407 (SignalInterrupt): Send actual PC instead of NULL.
408 (SignalNMIReset): New exception type.
409 * interp.c (board): New variable for future use to identify
410 a particular board being simulated.
411 (mips_option_handler,mips_options): Added "--board" option.
412 (interrupt_event): Send actual PC.
413 (sim_open): Make memory layout conditional on board setting.
414 (signal_exception): Initial implementation of hardware interrupt
415 handling. Accept another break instruction variant for simulator
416 exit.
417 (decode_coproc): Implement RFE instruction for TX39.
418 (mips.igen): Decode RFE instruction as such.
419 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
420 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
421 bbegin to implement memory map.
422 * dv-tx3904cpu.c: New file.
423 * dv-tx3904irc.c: New file.
424
425 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
426
427 * mips.igen (check_mt_hilo): Create a separate r3900 version.
428
429 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
430
431 * tx.igen (madd,maddu): Replace calls to check_op_hilo
432 with calls to check_div_hilo.
433
434 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
435
436 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
437 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
438 Add special r3900 version of do_mult_hilo.
439 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
440 with calls to check_mult_hilo.
441 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
442 with calls to check_div_hilo.
443
444 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
445
446 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
447 Document a replacement.
448
449 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
450
451 * interp.c (sim_monitor): Make mon_printf work.
452
453 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
454
455 * sim-main.h (INSN_NAME): New arg `cpu'.
456
457 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
458
459 * configure: Regenerated to track ../common/aclocal.m4 changes.
460
461 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
462
463 * configure: Regenerated to track ../common/aclocal.m4 changes.
464 * config.in: Ditto.
465
466 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
467
468 * acconfig.h: New file.
469 * configure.in: Reverted change of Apr 24; use sinclude again.
470
471 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
472
473 * configure: Regenerated to track ../common/aclocal.m4 changes.
474 * config.in: Ditto.
475
476 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
477
478 * configure.in: Don't call sinclude.
479
480 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
481
482 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
483
484 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
485
486 * mips.igen (ERET): Implement.
487
488 * interp.c (decode_coproc): Return sign-extended EPC.
489
490 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
491
492 * interp.c (signal_exception): Do not ignore Trap.
493 (signal_exception): On TRAP, restart at exception address.
494 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
495 (signal_exception): Update.
496 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
497 so that TRAP instructions are caught.
498
499 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
500
501 * sim-main.h (struct hilo_access, struct hilo_history): Define,
502 contains HI/LO access history.
503 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
504 (HIACCESS, LOACCESS): Delete, replace with
505 (HIHISTORY, LOHISTORY): New macros.
506 (CHECKHILO): Delete all, moved to mips.igen
507
508 * gencode.c (build_instruction): Do not generate checks for
509 correct HI/LO register usage.
510
511 * interp.c (old_engine_run): Delete checks for correct HI/LO
512 register usage.
513
514 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
515 check_mf_cycles): New functions.
516 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
517 do_divu, domultx, do_mult, do_multu): Use.
518
519 * tx.igen ("madd", "maddu"): Use.
520
521 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
522
523 * mips.igen (DSRAV): Use function do_dsrav.
524 (SRAV): Use new function do_srav.
525
526 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
527 (B): Sign extend 11 bit immediate.
528 (EXT-B*): Shift 16 bit immediate left by 1.
529 (ADDIU*): Don't sign extend immediate value.
530
531 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
532
533 * m16run.c (sim_engine_run): Restore CIA after handling an event.
534
535 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
536 functions.
537
538 * mips.igen (delayslot32, nullify_next_insn): New functions.
539 (m16.igen): Always include.
540 (do_*): Add more tracing.
541
542 * m16.igen (delayslot16): Add NIA argument, could be called by a
543 32 bit MIPS16 instruction.
544
545 * interp.c (ifetch16): Move function from here.
546 * sim-main.c (ifetch16): To here.
547
548 * sim-main.c (ifetch16, ifetch32): Update to match current
549 implementations of LH, LW.
550 (signal_exception): Don't print out incorrect hex value of illegal
551 instruction.
552
553 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
554
555 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
556 instruction.
557
558 * m16.igen: Implement MIPS16 instructions.
559
560 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
561 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
562 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
563 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
564 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
565 bodies of corresponding code from 32 bit insn to these. Also used
566 by MIPS16 versions of functions.
567
568 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
569 (IMEM16): Drop NR argument from macro.
570
571 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
572
573 * Makefile.in (SIM_OBJS): Add sim-main.o.
574
575 * sim-main.h (address_translation, load_memory, store_memory,
576 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
577 as INLINE_SIM_MAIN.
578 (pr_addr, pr_uword64): Declare.
579 (sim-main.c): Include when H_REVEALS_MODULE_P.
580
581 * interp.c (address_translation, load_memory, store_memory,
582 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
583 from here.
584 * sim-main.c: To here. Fix compilation problems.
585
586 * configure.in: Enable inlining.
587 * configure: Re-config.
588
589 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
590
591 * configure: Regenerated to track ../common/aclocal.m4 changes.
592
593 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
594
595 * mips.igen: Include tx.igen.
596 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
597 * tx.igen: New file, contains MADD and MADDU.
598
599 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
600 the hardwired constant `7'.
601 (store_memory): Ditto.
602 (LOADDRMASK): Move definition to sim-main.h.
603
604 mips.igen (MTC0): Enable for r3900.
605 (ADDU): Add trace.
606
607 mips.igen (do_load_byte): Delete.
608 (do_load, do_store, do_load_left, do_load_write, do_store_left,
609 do_store_right): New functions.
610 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
611
612 configure.in: Let the tx39 use igen again.
613 configure: Update.
614
615 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
616
617 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
618 not an address sized quantity. Return zero for cache sizes.
619
620 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
621
622 * mips.igen (r3900): r3900 does not support 64 bit integer
623 operations.
624
625 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
626
627 * configure.in (mipstx39*-*-*): Use gencode simulator rather
628 than igen one.
629 * configure : Rebuild.
630
631 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
632
633 * configure: Regenerated to track ../common/aclocal.m4 changes.
634
635 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
636
637 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
638
639 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
640
641 * configure: Regenerated to track ../common/aclocal.m4 changes.
642 * config.in: Regenerated to track ../common/aclocal.m4 changes.
643
644 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
645
646 * configure: Regenerated to track ../common/aclocal.m4 changes.
647
648 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
649
650 * interp.c (Max, Min): Comment out functions. Not yet used.
651
652 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
653
654 * configure: Regenerated to track ../common/aclocal.m4 changes.
655
656 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
657
658 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
659 configurable settings for stand-alone simulator.
660
661 * configure.in: Added X11 search, just in case.
662
663 * configure: Regenerated.
664
665 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
666
667 * interp.c (sim_write, sim_read, load_memory, store_memory):
668 Replace sim_core_*_map with read_map, write_map, exec_map resp.
669
670 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
671
672 * sim-main.h (GETFCC): Return an unsigned value.
673
674 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
675
676 * mips.igen (DIV): Fix check for -1 / MIN_INT.
677 (DADD): Result destination is RD not RT.
678
679 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
680
681 * sim-main.h (HIACCESS, LOACCESS): Always define.
682
683 * mdmx.igen (Maxi, Mini): Rename Max, Min.
684
685 * interp.c (sim_info): Delete.
686
687 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
688
689 * interp.c (DECLARE_OPTION_HANDLER): Use it.
690 (mips_option_handler): New argument `cpu'.
691 (sim_open): Update call to sim_add_option_table.
692
693 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
694
695 * mips.igen (CxC1): Add tracing.
696
697 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
698
699 * sim-main.h (Max, Min): Declare.
700
701 * interp.c (Max, Min): New functions.
702
703 * mips.igen (BC1): Add tracing.
704
705 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
706
707 * interp.c Added memory map for stack in vr4100
708
709 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
710
711 * interp.c (load_memory): Add missing "break"'s.
712
713 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
714
715 * interp.c (sim_store_register, sim_fetch_register): Pass in
716 length parameter. Return -1.
717
718 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
719
720 * interp.c: Added hardware init hook, fixed warnings.
721
722 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
723
724 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
725
726 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
727
728 * interp.c (ifetch16): New function.
729
730 * sim-main.h (IMEM32): Rename IMEM.
731 (IMEM16_IMMED): Define.
732 (IMEM16): Define.
733 (DELAY_SLOT): Update.
734
735 * m16run.c (sim_engine_run): New file.
736
737 * m16.igen: All instructions except LB.
738 (LB): Call do_load_byte.
739 * mips.igen (do_load_byte): New function.
740 (LB): Call do_load_byte.
741
742 * mips.igen: Move spec for insn bit size and high bit from here.
743 * Makefile.in (tmp-igen, tmp-m16): To here.
744
745 * m16.dc: New file, decode mips16 instructions.
746
747 * Makefile.in (SIM_NO_ALL): Define.
748 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
749
750 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
751
752 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
753 point unit to 32 bit registers.
754 * configure: Re-generate.
755
756 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
757
758 * configure.in (sim_use_gen): Make IGEN the default simulator
759 generator for generic 32 and 64 bit mips targets.
760 * configure: Re-generate.
761
762 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
763
764 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
765 bitsize.
766
767 * interp.c (sim_fetch_register, sim_store_register): Read/write
768 FGR from correct location.
769 (sim_open): Set size of FGR's according to
770 WITH_TARGET_FLOATING_POINT_BITSIZE.
771
772 * sim-main.h (FGR): Store floating point registers in a separate
773 array.
774
775 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
776
777 * configure: Regenerated to track ../common/aclocal.m4 changes.
778
779 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
780
781 * interp.c (ColdReset): Call PENDING_INVALIDATE.
782
783 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
784
785 * interp.c (pending_tick): New function. Deliver pending writes.
786
787 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
788 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
789 it can handle mixed sized quantites and single bits.
790
791 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
792
793 * interp.c (oengine.h): Do not include when building with IGEN.
794 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
795 (sim_info): Ditto for PROCESSOR_64BIT.
796 (sim_monitor): Replace ut_reg with unsigned_word.
797 (*): Ditto for t_reg.
798 (LOADDRMASK): Define.
799 (sim_open): Remove defunct check that host FP is IEEE compliant,
800 using software to emulate floating point.
801 (value_fpr, ...): Always compile, was conditional on HASFPU.
802
803 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
804
805 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
806 size.
807
808 * interp.c (SD, CPU): Define.
809 (mips_option_handler): Set flags in each CPU.
810 (interrupt_event): Assume CPU 0 is the one being iterrupted.
811 (sim_close): Do not clear STATE, deleted anyway.
812 (sim_write, sim_read): Assume CPU zero's vm should be used for
813 data transfers.
814 (sim_create_inferior): Set the PC for all processors.
815 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
816 argument.
817 (mips16_entry): Pass correct nr of args to store_word, load_word.
818 (ColdReset): Cold reset all cpu's.
819 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
820 (sim_monitor, load_memory, store_memory, signal_exception): Use
821 `CPU' instead of STATE_CPU.
822
823
824 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
825 SD or CPU_.
826
827 * sim-main.h (signal_exception): Add sim_cpu arg.
828 (SignalException*): Pass both SD and CPU to signal_exception.
829 * interp.c (signal_exception): Update.
830
831 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
832 Ditto
833 (sync_operation, prefetch, cache_op, store_memory, load_memory,
834 address_translation): Ditto
835 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
836
837 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
838
839 * configure: Regenerated to track ../common/aclocal.m4 changes.
840
841 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
842
843 * interp.c (sim_engine_run): Add `nr_cpus' argument.
844
845 * mips.igen (model): Map processor names onto BFD name.
846
847 * sim-main.h (CPU_CIA): Delete.
848 (SET_CIA, GET_CIA): Define
849
850 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
851
852 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
853 regiser.
854
855 * configure.in (default_endian): Configure a big-endian simulator
856 by default.
857 * configure: Re-generate.
858
859 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
860
861 * configure: Regenerated to track ../common/aclocal.m4 changes.
862
863 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
864
865 * interp.c (sim_monitor): Handle Densan monitor outbyte
866 and inbyte functions.
867
868 1997-12-29 Felix Lee <flee@cygnus.com>
869
870 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
871
872 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
873
874 * Makefile.in (tmp-igen): Arrange for $zero to always be
875 reset to zero after every instruction.
876
877 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
878
879 * configure: Regenerated to track ../common/aclocal.m4 changes.
880 * config.in: Ditto.
881
882 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
883
884 * mips.igen (MSUB): Fix to work like MADD.
885 * gencode.c (MSUB): Similarly.
886
887 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
888
889 * configure: Regenerated to track ../common/aclocal.m4 changes.
890
891 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
892
893 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
894
895 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
896
897 * sim-main.h (sim-fpu.h): Include.
898
899 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
900 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
901 using host independant sim_fpu module.
902
903 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
904
905 * interp.c (signal_exception): Report internal errors with SIGABRT
906 not SIGQUIT.
907
908 * sim-main.h (C0_CONFIG): New register.
909 (signal.h): No longer include.
910
911 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
912
913 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
914
915 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
916
917 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
918
919 * mips.igen: Tag vr5000 instructions.
920 (ANDI): Was missing mipsIV model, fix assembler syntax.
921 (do_c_cond_fmt): New function.
922 (C.cond.fmt): Handle mips I-III which do not support CC field
923 separatly.
924 (bc1): Handle mips IV which do not have a delaed FCC separatly.
925 (SDR): Mask paddr when BigEndianMem, not the converse as specified
926 in IV3.2 spec.
927 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
928 vr5000 which saves LO in a GPR separatly.
929
930 * configure.in (enable-sim-igen): For vr5000, select vr5000
931 specific instructions.
932 * configure: Re-generate.
933
934 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
935
936 * Makefile.in (SIM_OBJS): Add sim-fpu module.
937
938 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
939 fmt_uninterpreted_64 bit cases to switch. Convert to
940 fmt_formatted,
941
942 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
943
944 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
945 as specified in IV3.2 spec.
946 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
947
948 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
949
950 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
951 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
952 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
953 PENDING_FILL versions of instructions. Simplify.
954 (X): New function.
955 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
956 instructions.
957 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
958 a signed value.
959 (MTHI, MFHI): Disable code checking HI-LO.
960
961 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
962 global.
963 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
964
965 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
966
967 * gencode.c (build_mips16_operands): Replace IPC with cia.
968
969 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
970 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
971 IPC to `cia'.
972 (UndefinedResult): Replace function with macro/function
973 combination.
974 (sim_engine_run): Don't save PC in IPC.
975
976 * sim-main.h (IPC): Delete.
977
978
979 * interp.c (signal_exception, store_word, load_word,
980 address_translation, load_memory, store_memory, cache_op,
981 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
982 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
983 current instruction address - cia - argument.
984 (sim_read, sim_write): Call address_translation directly.
985 (sim_engine_run): Rename variable vaddr to cia.
986 (signal_exception): Pass cia to sim_monitor
987
988 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
989 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
990 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
991
992 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
993 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
994 SIM_ASSERT.
995
996 * interp.c (signal_exception): Pass restart address to
997 sim_engine_restart.
998
999 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1000 idecode.o): Add dependency.
1001
1002 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1003 Delete definitions
1004 (DELAY_SLOT): Update NIA not PC with branch address.
1005 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1006
1007 * mips.igen: Use CIA not PC in branch calculations.
1008 (illegal): Call SignalException.
1009 (BEQ, ADDIU): Fix assembler.
1010
1011 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1012
1013 * m16.igen (JALX): Was missing.
1014
1015 * configure.in (enable-sim-igen): New configuration option.
1016 * configure: Re-generate.
1017
1018 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1019
1020 * interp.c (load_memory, store_memory): Delete parameter RAW.
1021 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1022 bypassing {load,store}_memory.
1023
1024 * sim-main.h (ByteSwapMem): Delete definition.
1025
1026 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1027
1028 * interp.c (sim_do_command, sim_commands): Delete mips specific
1029 commands. Handled by module sim-options.
1030
1031 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1032 (WITH_MODULO_MEMORY): Define.
1033
1034 * interp.c (sim_info): Delete code printing memory size.
1035
1036 * interp.c (mips_size): Nee sim_size, delete function.
1037 (power2): Delete.
1038 (monitor, monitor_base, monitor_size): Delete global variables.
1039 (sim_open, sim_close): Delete code creating monitor and other
1040 memory regions. Use sim-memopts module, via sim_do_commandf, to
1041 manage memory regions.
1042 (load_memory, store_memory): Use sim-core for memory model.
1043
1044 * interp.c (address_translation): Delete all memory map code
1045 except line forcing 32 bit addresses.
1046
1047 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1048
1049 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1050 trace options.
1051
1052 * interp.c (logfh, logfile): Delete globals.
1053 (sim_open, sim_close): Delete code opening & closing log file.
1054 (mips_option_handler): Delete -l and -n options.
1055 (OPTION mips_options): Ditto.
1056
1057 * interp.c (OPTION mips_options): Rename option trace to dinero.
1058 (mips_option_handler): Update.
1059
1060 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1061
1062 * interp.c (fetch_str): New function.
1063 (sim_monitor): Rewrite using sim_read & sim_write.
1064 (sim_open): Check magic number.
1065 (sim_open): Write monitor vectors into memory using sim_write.
1066 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1067 (sim_read, sim_write): Simplify - transfer data one byte at a
1068 time.
1069 (load_memory, store_memory): Clarify meaning of parameter RAW.
1070
1071 * sim-main.h (isHOST): Defete definition.
1072 (isTARGET): Mark as depreciated.
1073 (address_translation): Delete parameter HOST.
1074
1075 * interp.c (address_translation): Delete parameter HOST.
1076
1077 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1078
1079 * mips.igen:
1080
1081 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1082 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1083
1084 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1085
1086 * mips.igen: Add model filter field to records.
1087
1088 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1089
1090 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1091
1092 interp.c (sim_engine_run): Do not compile function sim_engine_run
1093 when WITH_IGEN == 1.
1094
1095 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1096 target architecture.
1097
1098 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1099 igen. Replace with configuration variables sim_igen_flags /
1100 sim_m16_flags.
1101
1102 * m16.igen: New file. Copy mips16 insns here.
1103 * mips.igen: From here.
1104
1105 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1106
1107 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1108 to top.
1109 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1110
1111 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1112
1113 * gencode.c (build_instruction): Follow sim_write's lead in using
1114 BigEndianMem instead of !ByteSwapMem.
1115
1116 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1117
1118 * configure.in (sim_gen): Dependent on target, select type of
1119 generator. Always select old style generator.
1120
1121 configure: Re-generate.
1122
1123 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1124 targets.
1125 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1126 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1127 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1128 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1129 SIM_@sim_gen@_*, set by autoconf.
1130
1131 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1132
1133 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1134
1135 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1136 CURRENT_FLOATING_POINT instead.
1137
1138 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1139 (address_translation): Raise exception InstructionFetch when
1140 translation fails and isINSTRUCTION.
1141
1142 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1143 sim_engine_run): Change type of of vaddr and paddr to
1144 address_word.
1145 (address_translation, prefetch, load_memory, store_memory,
1146 cache_op): Change type of vAddr and pAddr to address_word.
1147
1148 * gencode.c (build_instruction): Change type of vaddr and paddr to
1149 address_word.
1150
1151 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1152
1153 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1154 macro to obtain result of ALU op.
1155
1156 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1157
1158 * interp.c (sim_info): Call profile_print.
1159
1160 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1161
1162 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1163
1164 * sim-main.h (WITH_PROFILE): Do not define, defined in
1165 common/sim-config.h. Use sim-profile module.
1166 (simPROFILE): Delete defintion.
1167
1168 * interp.c (PROFILE): Delete definition.
1169 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1170 (sim_close): Delete code writing profile histogram.
1171 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1172 Delete.
1173 (sim_engine_run): Delete code profiling the PC.
1174
1175 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1176
1177 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1178
1179 * interp.c (sim_monitor): Make register pointers of type
1180 unsigned_word*.
1181
1182 * sim-main.h: Make registers of type unsigned_word not
1183 signed_word.
1184
1185 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1186
1187 * interp.c (sync_operation): Rename from SyncOperation, make
1188 global, add SD argument.
1189 (prefetch): Rename from Prefetch, make global, add SD argument.
1190 (decode_coproc): Make global.
1191
1192 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1193
1194 * gencode.c (build_instruction): Generate DecodeCoproc not
1195 decode_coproc calls.
1196
1197 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1198 (SizeFGR): Move to sim-main.h
1199 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1200 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1201 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1202 sim-main.h.
1203 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1204 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1205 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1206 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1207 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1208 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1209
1210 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1211 exception.
1212 (sim-alu.h): Include.
1213 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1214 (sim_cia): Typedef to instruction_address.
1215
1216 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1217
1218 * Makefile.in (interp.o): Rename generated file engine.c to
1219 oengine.c.
1220
1221 * interp.c: Update.
1222
1223 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1224
1225 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1226
1227 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1228
1229 * gencode.c (build_instruction): For "FPSQRT", output correct
1230 number of arguments to Recip.
1231
1232 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1233
1234 * Makefile.in (interp.o): Depends on sim-main.h
1235
1236 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1237
1238 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1239 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1240 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1241 STATE, DSSTATE): Define
1242 (GPR, FGRIDX, ..): Define.
1243
1244 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1245 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1246 (GPR, FGRIDX, ...): Delete macros.
1247
1248 * interp.c: Update names to match defines from sim-main.h
1249
1250 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1251
1252 * interp.c (sim_monitor): Add SD argument.
1253 (sim_warning): Delete. Replace calls with calls to
1254 sim_io_eprintf.
1255 (sim_error): Delete. Replace calls with sim_io_error.
1256 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1257 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1258 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1259 argument.
1260 (mips_size): Rename from sim_size. Add SD argument.
1261
1262 * interp.c (simulator): Delete global variable.
1263 (callback): Delete global variable.
1264 (mips_option_handler, sim_open, sim_write, sim_read,
1265 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1266 sim_size,sim_monitor): Use sim_io_* not callback->*.
1267 (sim_open): ZALLOC simulator struct.
1268 (PROFILE): Do not define.
1269
1270 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1271
1272 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1273 support.h with corresponding code.
1274
1275 * sim-main.h (word64, uword64), support.h: Move definition to
1276 sim-main.h.
1277 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1278
1279 * support.h: Delete
1280 * Makefile.in: Update dependencies
1281 * interp.c: Do not include.
1282
1283 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1284
1285 * interp.c (address_translation, load_memory, store_memory,
1286 cache_op): Rename to from AddressTranslation et.al., make global,
1287 add SD argument
1288
1289 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1290 CacheOp): Define.
1291
1292 * interp.c (SignalException): Rename to signal_exception, make
1293 global.
1294
1295 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1296
1297 * sim-main.h (SignalException, SignalExceptionInterrupt,
1298 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1299 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1300 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1301 Define.
1302
1303 * interp.c, support.h: Use.
1304
1305 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1306
1307 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1308 to value_fpr / store_fpr. Add SD argument.
1309 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1310 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1311
1312 * sim-main.h (ValueFPR, StoreFPR): Define.
1313
1314 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1315
1316 * interp.c (sim_engine_run): Check consistency between configure
1317 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1318 and HASFPU.
1319
1320 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1321 (mips_fpu): Configure WITH_FLOATING_POINT.
1322 (mips_endian): Configure WITH_TARGET_ENDIAN.
1323 * configure: Update.
1324
1325 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1326
1327 * configure: Regenerated to track ../common/aclocal.m4 changes.
1328
1329 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1330
1331 * configure: Regenerated.
1332
1333 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1334
1335 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1336
1337 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1338
1339 * gencode.c (print_igen_insn_models): Assume certain architectures
1340 include all mips* instructions.
1341 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1342 instruction.
1343
1344 * Makefile.in (tmp.igen): Add target. Generate igen input from
1345 gencode file.
1346
1347 * gencode.c (FEATURE_IGEN): Define.
1348 (main): Add --igen option. Generate output in igen format.
1349 (process_instructions): Format output according to igen option.
1350 (print_igen_insn_format): New function.
1351 (print_igen_insn_models): New function.
1352 (process_instructions): Only issue warnings and ignore
1353 instructions when no FEATURE_IGEN.
1354
1355 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1356
1357 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1358 MIPS targets.
1359
1360 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1361
1362 * configure: Regenerated to track ../common/aclocal.m4 changes.
1363
1364 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1365
1366 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1367 SIM_RESERVED_BITS): Delete, moved to common.
1368 (SIM_EXTRA_CFLAGS): Update.
1369
1370 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1371
1372 * configure.in: Configure non-strict memory alignment.
1373 * configure: Regenerated to track ../common/aclocal.m4 changes.
1374
1375 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1376
1377 * configure: Regenerated to track ../common/aclocal.m4 changes.
1378
1379 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1380
1381 * gencode.c (SDBBP,DERET): Added (3900) insns.
1382 (RFE): Turn on for 3900.
1383 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1384 (dsstate): Made global.
1385 (SUBTARGET_R3900): Added.
1386 (CANCELDELAYSLOT): New.
1387 (SignalException): Ignore SystemCall rather than ignore and
1388 terminate. Add DebugBreakPoint handling.
1389 (decode_coproc): New insns RFE, DERET; and new registers Debug
1390 and DEPC protected by SUBTARGET_R3900.
1391 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1392 bits explicitly.
1393 * Makefile.in,configure.in: Add mips subtarget option.
1394 * configure: Update.
1395
1396 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1397
1398 * gencode.c: Add r3900 (tx39).
1399
1400
1401 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1402
1403 * gencode.c (build_instruction): Don't need to subtract 4 for
1404 JALR, just 2.
1405
1406 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1407
1408 * interp.c: Correct some HASFPU problems.
1409
1410 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1411
1412 * configure: Regenerated to track ../common/aclocal.m4 changes.
1413
1414 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1415
1416 * interp.c (mips_options): Fix samples option short form, should
1417 be `x'.
1418
1419 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1420
1421 * interp.c (sim_info): Enable info code. Was just returning.
1422
1423 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1424
1425 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1426 MFC0.
1427
1428 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1429
1430 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1431 constants.
1432 (build_instruction): Ditto for LL.
1433
1434 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1435
1436 * configure: Regenerated to track ../common/aclocal.m4 changes.
1437
1438 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1439
1440 * configure: Regenerated to track ../common/aclocal.m4 changes.
1441 * config.in: Ditto.
1442
1443 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1444
1445 * interp.c (sim_open): Add call to sim_analyze_program, update
1446 call to sim_config.
1447
1448 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1449
1450 * interp.c (sim_kill): Delete.
1451 (sim_create_inferior): Add ABFD argument. Set PC from same.
1452 (sim_load): Move code initializing trap handlers from here.
1453 (sim_open): To here.
1454 (sim_load): Delete, use sim-hload.c.
1455
1456 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1457
1458 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1459
1460 * configure: Regenerated to track ../common/aclocal.m4 changes.
1461 * config.in: Ditto.
1462
1463 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1464
1465 * interp.c (sim_open): Add ABFD argument.
1466 (sim_load): Move call to sim_config from here.
1467 (sim_open): To here. Check return status.
1468
1469 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1470
1471 * gencode.c (build_instruction): Two arg MADD should
1472 not assign result to $0.
1473
1474 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1475
1476 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1477 * sim/mips/configure.in: Regenerate.
1478
1479 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1480
1481 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1482 signed8, unsigned8 et.al. types.
1483
1484 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1485 hosts when selecting subreg.
1486
1487 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1488
1489 * interp.c (sim_engine_run): Reset the ZERO register to zero
1490 regardless of FEATURE_WARN_ZERO.
1491 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1492
1493 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1494
1495 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1496 (SignalException): For BreakPoints ignore any mode bits and just
1497 save the PC.
1498 (SignalException): Always set the CAUSE register.
1499
1500 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1501
1502 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1503 exception has been taken.
1504
1505 * interp.c: Implement the ERET and mt/f sr instructions.
1506
1507 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1508
1509 * interp.c (SignalException): Don't bother restarting an
1510 interrupt.
1511
1512 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1513
1514 * interp.c (SignalException): Really take an interrupt.
1515 (interrupt_event): Only deliver interrupts when enabled.
1516
1517 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1518
1519 * interp.c (sim_info): Only print info when verbose.
1520 (sim_info) Use sim_io_printf for output.
1521
1522 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1523
1524 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1525 mips architectures.
1526
1527 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1528
1529 * interp.c (sim_do_command): Check for common commands if a
1530 simulator specific command fails.
1531
1532 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1533
1534 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1535 and simBE when DEBUG is defined.
1536
1537 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1538
1539 * interp.c (interrupt_event): New function. Pass exception event
1540 onto exception handler.
1541
1542 * configure.in: Check for stdlib.h.
1543 * configure: Regenerate.
1544
1545 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1546 variable declaration.
1547 (build_instruction): Initialize memval1.
1548 (build_instruction): Add UNUSED attribute to byte, bigend,
1549 reverse.
1550 (build_operands): Ditto.
1551
1552 * interp.c: Fix GCC warnings.
1553 (sim_get_quit_code): Delete.
1554
1555 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1556 * Makefile.in: Ditto.
1557 * configure: Re-generate.
1558
1559 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1560
1561 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1562
1563 * interp.c (mips_option_handler): New function parse argumes using
1564 sim-options.
1565 (myname): Replace with STATE_MY_NAME.
1566 (sim_open): Delete check for host endianness - performed by
1567 sim_config.
1568 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1569 (sim_open): Move much of the initialization from here.
1570 (sim_load): To here. After the image has been loaded and
1571 endianness set.
1572 (sim_open): Move ColdReset from here.
1573 (sim_create_inferior): To here.
1574 (sim_open): Make FP check less dependant on host endianness.
1575
1576 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1577 run.
1578 * interp.c (sim_set_callbacks): Delete.
1579
1580 * interp.c (membank, membank_base, membank_size): Replace with
1581 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1582 (sim_open): Remove call to callback->init. gdb/run do this.
1583
1584 * interp.c: Update
1585
1586 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1587
1588 * interp.c (big_endian_p): Delete, replaced by
1589 current_target_byte_order.
1590
1591 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1592
1593 * interp.c (host_read_long, host_read_word, host_swap_word,
1594 host_swap_long): Delete. Using common sim-endian.
1595 (sim_fetch_register, sim_store_register): Use H2T.
1596 (pipeline_ticks): Delete. Handled by sim-events.
1597 (sim_info): Update.
1598 (sim_engine_run): Update.
1599
1600 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1601
1602 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1603 reason from here.
1604 (SignalException): To here. Signal using sim_engine_halt.
1605 (sim_stop_reason): Delete, moved to common.
1606
1607 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1608
1609 * interp.c (sim_open): Add callback argument.
1610 (sim_set_callbacks): Delete SIM_DESC argument.
1611 (sim_size): Ditto.
1612
1613 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1614
1615 * Makefile.in (SIM_OBJS): Add common modules.
1616
1617 * interp.c (sim_set_callbacks): Also set SD callback.
1618 (set_endianness, xfer_*, swap_*): Delete.
1619 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1620 Change to functions using sim-endian macros.
1621 (control_c, sim_stop): Delete, use common version.
1622 (simulate): Convert into.
1623 (sim_engine_run): This function.
1624 (sim_resume): Delete.
1625
1626 * interp.c (simulation): New variable - the simulator object.
1627 (sim_kind): Delete global - merged into simulation.
1628 (sim_load): Cleanup. Move PC assignment from here.
1629 (sim_create_inferior): To here.
1630
1631 * sim-main.h: New file.
1632 * interp.c (sim-main.h): Include.
1633
1634 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1635
1636 * configure: Regenerated to track ../common/aclocal.m4 changes.
1637
1638 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1639
1640 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1641
1642 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1643
1644 * gencode.c (build_instruction): DIV instructions: check
1645 for division by zero and integer overflow before using
1646 host's division operation.
1647
1648 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1649
1650 * Makefile.in (SIM_OBJS): Add sim-load.o.
1651 * interp.c: #include bfd.h.
1652 (target_byte_order): Delete.
1653 (sim_kind, myname, big_endian_p): New static locals.
1654 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1655 after argument parsing. Recognize -E arg, set endianness accordingly.
1656 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1657 load file into simulator. Set PC from bfd.
1658 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1659 (set_endianness): Use big_endian_p instead of target_byte_order.
1660
1661 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1662
1663 * interp.c (sim_size): Delete prototype - conflicts with
1664 definition in remote-sim.h. Correct definition.
1665
1666 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1667
1668 * configure: Regenerated to track ../common/aclocal.m4 changes.
1669 * config.in: Ditto.
1670
1671 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1672
1673 * interp.c (sim_open): New arg `kind'.
1674
1675 * configure: Regenerated to track ../common/aclocal.m4 changes.
1676
1677 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1678
1679 * configure: Regenerated to track ../common/aclocal.m4 changes.
1680
1681 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1682
1683 * interp.c (sim_open): Set optind to 0 before calling getopt.
1684
1685 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1686
1687 * configure: Regenerated to track ../common/aclocal.m4 changes.
1688
1689 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1690
1691 * interp.c : Replace uses of pr_addr with pr_uword64
1692 where the bit length is always 64 independent of SIM_ADDR.
1693 (pr_uword64) : added.
1694
1695 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1696
1697 * configure: Re-generate.
1698
1699 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1700
1701 * configure: Regenerate to track ../common/aclocal.m4 changes.
1702
1703 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1704
1705 * interp.c (sim_open): New SIM_DESC result. Argument is now
1706 in argv form.
1707 (other sim_*): New SIM_DESC argument.
1708
1709 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1710
1711 * interp.c: Fix printing of addresses for non-64-bit targets.
1712 (pr_addr): Add function to print address based on size.
1713
1714 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1715
1716 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1717
1718 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1719
1720 * gencode.c (build_mips16_operands): Correct computation of base
1721 address for extended PC relative instruction.
1722
1723 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1724
1725 * interp.c (mips16_entry): Add support for floating point cases.
1726 (SignalException): Pass floating point cases to mips16_entry.
1727 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1728 registers.
1729 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1730 or fmt_word.
1731 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1732 and then set the state to fmt_uninterpreted.
1733 (COP_SW): Temporarily set the state to fmt_word while calling
1734 ValueFPR.
1735
1736 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1737
1738 * gencode.c (build_instruction): The high order may be set in the
1739 comparison flags at any ISA level, not just ISA 4.
1740
1741 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1742
1743 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1744 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1745 * configure.in: sinclude ../common/aclocal.m4.
1746 * configure: Regenerated.
1747
1748 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1749
1750 * configure: Rebuild after change to aclocal.m4.
1751
1752 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1753
1754 * configure configure.in Makefile.in: Update to new configure
1755 scheme which is more compatible with WinGDB builds.
1756 * configure.in: Improve comment on how to run autoconf.
1757 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1758 * Makefile.in: Use autoconf substitution to install common
1759 makefile fragment.
1760
1761 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1762
1763 * gencode.c (build_instruction): Use BigEndianCPU instead of
1764 ByteSwapMem.
1765
1766 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1767
1768 * interp.c (sim_monitor): Make output to stdout visible in
1769 wingdb's I/O log window.
1770
1771 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1772
1773 * support.h: Undo previous change to SIGTRAP
1774 and SIGQUIT values.
1775
1776 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1777
1778 * interp.c (store_word, load_word): New static functions.
1779 (mips16_entry): New static function.
1780 (SignalException): Look for mips16 entry and exit instructions.
1781 (simulate): Use the correct index when setting fpr_state after
1782 doing a pending move.
1783
1784 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1785
1786 * interp.c: Fix byte-swapping code throughout to work on
1787 both little- and big-endian hosts.
1788
1789 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1790
1791 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1792 with gdb/config/i386/xm-windows.h.
1793
1794 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1795
1796 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1797 that messes up arithmetic shifts.
1798
1799 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1800
1801 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1802 SIGTRAP and SIGQUIT for _WIN32.
1803
1804 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1805
1806 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1807 force a 64 bit multiplication.
1808 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1809 destination register is 0, since that is the default mips16 nop
1810 instruction.
1811
1812 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1813
1814 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1815 (build_endian_shift): Don't check proc64.
1816 (build_instruction): Always set memval to uword64. Cast op2 to
1817 uword64 when shifting it left in memory instructions. Always use
1818 the same code for stores--don't special case proc64.
1819
1820 * gencode.c (build_mips16_operands): Fix base PC value for PC
1821 relative operands.
1822 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1823 jal instruction.
1824 * interp.c (simJALDELAYSLOT): Define.
1825 (JALDELAYSLOT): Define.
1826 (INDELAYSLOT, INJALDELAYSLOT): Define.
1827 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1828
1829 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1830
1831 * interp.c (sim_open): add flush_cache as a PMON routine
1832 (sim_monitor): handle flush_cache by ignoring it
1833
1834 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1835
1836 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1837 BigEndianMem.
1838 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1839 (BigEndianMem): Rename to ByteSwapMem and change sense.
1840 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1841 BigEndianMem references to !ByteSwapMem.
1842 (set_endianness): New function, with prototype.
1843 (sim_open): Call set_endianness.
1844 (sim_info): Use simBE instead of BigEndianMem.
1845 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1846 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1847 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1848 ifdefs, keeping the prototype declaration.
1849 (swap_word): Rewrite correctly.
1850 (ColdReset): Delete references to CONFIG. Delete endianness related
1851 code; moved to set_endianness.
1852
1853 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1854
1855 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1856 * interp.c (CHECKHILO): Define away.
1857 (simSIGINT): New macro.
1858 (membank_size): Increase from 1MB to 2MB.
1859 (control_c): New function.
1860 (sim_resume): Rename parameter signal to signal_number. Add local
1861 variable prev. Call signal before and after simulate.
1862 (sim_stop_reason): Add simSIGINT support.
1863 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1864 functions always.
1865 (sim_warning): Delete call to SignalException. Do call printf_filtered
1866 if logfh is NULL.
1867 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1868 a call to sim_warning.
1869
1870 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1871
1872 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1873 16 bit instructions.
1874
1875 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1876
1877 Add support for mips16 (16 bit MIPS implementation):
1878 * gencode.c (inst_type): Add mips16 instruction encoding types.
1879 (GETDATASIZEINSN): Define.
1880 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1881 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1882 mtlo.
1883 (MIPS16_DECODE): New table, for mips16 instructions.
1884 (bitmap_val): New static function.
1885 (struct mips16_op): Define.
1886 (mips16_op_table): New table, for mips16 operands.
1887 (build_mips16_operands): New static function.
1888 (process_instructions): If PC is odd, decode a mips16
1889 instruction. Break out instruction handling into new
1890 build_instruction function.
1891 (build_instruction): New static function, broken out of
1892 process_instructions. Check modifiers rather than flags for SHIFT
1893 bit count and m[ft]{hi,lo} direction.
1894 (usage): Pass program name to fprintf.
1895 (main): Remove unused variable this_option_optind. Change
1896 ``*loptarg++'' to ``loptarg++''.
1897 (my_strtoul): Parenthesize && within ||.
1898 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1899 (simulate): If PC is odd, fetch a 16 bit instruction, and
1900 increment PC by 2 rather than 4.
1901 * configure.in: Add case for mips16*-*-*.
1902 * configure: Rebuild.
1903
1904 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1905
1906 * interp.c: Allow -t to enable tracing in standalone simulator.
1907 Fix garbage output in trace file and error messages.
1908
1909 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1910
1911 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1912 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1913 * configure.in: Simplify using macros in ../common/aclocal.m4.
1914 * configure: Regenerated.
1915 * tconfig.in: New file.
1916
1917 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1918
1919 * interp.c: Fix bugs in 64-bit port.
1920 Use ansi function declarations for msvc compiler.
1921 Initialize and test file pointer in trace code.
1922 Prevent duplicate definition of LAST_EMED_REGNUM.
1923
1924 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1925
1926 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1927
1928 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1929
1930 * interp.c (SignalException): Check for explicit terminating
1931 breakpoint value.
1932 * gencode.c: Pass instruction value through SignalException()
1933 calls for Trap, Breakpoint and Syscall.
1934
1935 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1936
1937 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1938 only used on those hosts that provide it.
1939 * configure.in: Add sqrt() to list of functions to be checked for.
1940 * config.in: Re-generated.
1941 * configure: Re-generated.
1942
1943 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1944
1945 * gencode.c (process_instructions): Call build_endian_shift when
1946 expanding STORE RIGHT, to fix swr.
1947 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1948 clear the high bits.
1949 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1950 Fix float to int conversions to produce signed values.
1951
1952 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
1953
1954 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1955 (process_instructions): Correct handling of nor instruction.
1956 Correct shift count for 32 bit shift instructions. Correct sign
1957 extension for arithmetic shifts to not shift the number of bits in
1958 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
1959 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
1960 Fix madd.
1961 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
1962 It's OK to have a mult follow a mult. What's not OK is to have a
1963 mult follow an mfhi.
1964 (Convert): Comment out incorrect rounding code.
1965
1966 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
1967
1968 * interp.c (sim_monitor): Improved monitor printf
1969 simulation. Tidied up simulator warnings, and added "--log" option
1970 for directing warning message output.
1971 * gencode.c: Use sim_warning() rather than WARNING macro.
1972
1973 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
1974
1975 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
1976 getopt1.o, rather than on gencode.c. Link objects together.
1977 Don't link against -liberty.
1978 (gencode.o, getopt.o, getopt1.o): New targets.
1979 * gencode.c: Include <ctype.h> and "ansidecl.h".
1980 (AND): Undefine after including "ansidecl.h".
1981 (ULONG_MAX): Define if not defined.
1982 (OP_*): Don't define macros; now defined in opcode/mips.h.
1983 (main): Call my_strtoul rather than strtoul.
1984 (my_strtoul): New static function.
1985
1986 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
1987
1988 * gencode.c (process_instructions): Generate word64 and uword64
1989 instead of `long long' and `unsigned long long' data types.
1990 * interp.c: #include sysdep.h to get signals, and define default
1991 for SIGBUS.
1992 * (Convert): Work around for Visual-C++ compiler bug with type
1993 conversion.
1994 * support.h: Make things compile under Visual-C++ by using
1995 __int64 instead of `long long'. Change many refs to long long
1996 into word64/uword64 typedefs.
1997
1998 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
1999
2000 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2001 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2002 (docdir): Removed.
2003 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2004 (AC_PROG_INSTALL): Added.
2005 (AC_PROG_CC): Moved to before configure.host call.
2006 * configure: Rebuilt.
2007
2008 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2009
2010 * configure.in: Define @SIMCONF@ depending on mips target.
2011 * configure: Rebuild.
2012 * Makefile.in (run): Add @SIMCONF@ to control simulator
2013 construction.
2014 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2015 * interp.c: Remove some debugging, provide more detailed error
2016 messages, update memory accesses to use LOADDRMASK.
2017
2018 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2019
2020 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2021 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2022 stamp-h.
2023 * configure: Rebuild.
2024 * config.in: New file, generated by autoheader.
2025 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2026 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2027 HAVE_ANINT and HAVE_AINT, as appropriate.
2028 * Makefile.in (run): Use @LIBS@ rather than -lm.
2029 (interp.o): Depend upon config.h.
2030 (Makefile): Just rebuild Makefile.
2031 (clean): Remove stamp-h.
2032 (mostlyclean): Make the same as clean, not as distclean.
2033 (config.h, stamp-h): New targets.
2034
2035 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2036
2037 * interp.c (ColdReset): Fix boolean test. Make all simulator
2038 globals static.
2039
2040 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2041
2042 * interp.c (xfer_direct_word, xfer_direct_long,
2043 swap_direct_word, swap_direct_long, xfer_big_word,
2044 xfer_big_long, xfer_little_word, xfer_little_long,
2045 swap_word,swap_long): Added.
2046 * interp.c (ColdReset): Provide function indirection to
2047 host<->simulated_target transfer routines.
2048 * interp.c (sim_store_register, sim_fetch_register): Updated to
2049 make use of indirected transfer routines.
2050
2051 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2052
2053 * gencode.c (process_instructions): Ensure FP ABS instruction
2054 recognised.
2055 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2056 system call support.
2057
2058 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2059
2060 * interp.c (sim_do_command): Complain if callback structure not
2061 initialised.
2062
2063 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2064
2065 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2066 support for Sun hosts.
2067 * Makefile.in (gencode): Ensure the host compiler and libraries
2068 used for cross-hosted build.
2069
2070 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2071
2072 * interp.c, gencode.c: Some more (TODO) tidying.
2073
2074 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2075
2076 * gencode.c, interp.c: Replaced explicit long long references with
2077 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2078 * support.h (SET64LO, SET64HI): Macros added.
2079
2080 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2081
2082 * configure: Regenerate with autoconf 2.7.
2083
2084 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2085
2086 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2087 * support.h: Remove superfluous "1" from #if.
2088 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2089
2090 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2091
2092 * interp.c (StoreFPR): Control UndefinedResult() call on
2093 WARN_RESULT manifest.
2094
2095 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2096
2097 * gencode.c: Tidied instruction decoding, and added FP instruction
2098 support.
2099
2100 * interp.c: Added dineroIII, and BSD profiling support. Also
2101 run-time FP handling.
2102
2103 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2104
2105 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2106 gencode.c, interp.c, support.h: created.
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