sim/mips/ChangeLog

   1 1999-05-08  Felix Lee  <flee@cygnus.com>
   2
   3         * configure: Regenerated to track ../common/aclocal.m4 changes.
   4
   5 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
   6
   7         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
   8
   9 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
  10
  11         * configure.in: Any mips64vr5*-*-* target should have
  12         -DTARGET_ENABLE_FR=1.
  13         (default_endian): Any mips64vr*el-*-* target should default to
  14         LITTLE_ENDIAN.
  15         * configure: Re-generate.
  16
  17 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
  18
  19         * mips.igen (ldl): Extend from _16_, not 32.
  20
  21 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
  22
  23         * interp.c (sim_store_register): Force registers written to by GDB
  24         into an un-interpreted state.
  25
  26 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
  27
  28         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
  29         CPU, start periodic background I/O polls.
  30         (tx3904sio_poll): New function: periodic I/O poller.
  31
  32 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
  33
  34         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
  35
  36 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
  37
  38         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
  39         case statement.
  40
  41 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
  42
  43         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
  44         (load_word): Call SIM_CORE_SIGNAL hook on error.
  45         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
  46         starting.  For exception dispatching, pass PC instead of NULL_CIA.
  47         (decode_coproc): Use COP0_BADVADDR to store faulting address.
  48         * sim-main.h (COP0_BADVADDR): Define.
  49         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
  50         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
  51         (_sim_cpu): Add exc_* fields to store register value snapshots.
  52         * mips.igen (*): Replace memory-related SignalException* calls
  53         with references to SIM_CORE_SIGNAL hook.
  54
  55         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
  56         fix.
  57         * sim-main.c (*): Minor warning cleanups.
  58
  59 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
  60
  61         * m16.igen (DADDIU5): Correct type-o.
  62
  63 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
  64
  65         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
  66         variables.
  67
  68 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
  69
  70         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
  71         to include path.
  72         (interp.o): Add dependency on itable.h
  73         (oengine.c, gencode): Delete remaining references.
  74         (BUILT_SRC_FROM_GEN): Clean up.
  75
  76 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
  77
  78         * vr4run.c: New.
  79         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
  80         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
  81         tmp-run-hack) : New.
  82         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
  83         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
  84         Drop the "64" qualifier to get the HACK generator working.
  85         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
  86         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
  87         qualifier to get the hack generator working.
  88         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
  89         (DSLL): Use do_dsll.
  90         (DSLLV): Use do_dsllv.
  91         (DSRA): Use do_dsra.
  92         (DSRL): Use do_dsrl.
  93         (DSRLV): Use do_dsrlv.
  94         (BC1): Move *vr4100 to get the HACK generator working.
  95         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
  96         get the HACK generator working.
  97         (MACC) Rename to get the HACK generator working.
  98         (DMACC,MACCS,DMACCS): Add the 64.
  99
 100 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 101
 102         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 103         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 104
 105 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 106
 107     * mips/interp.c (DEBUG): Cleanups.
 108
 109 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 110
 111         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 112         (tx3904sio_tickle): fflush after a stdout character output.
 113
 114 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 115
 116         * interp.c (sim_close): Uninstall modules.
 117
 118 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 119
 120         * sim-main.h, interp.c (sim_monitor): Change to global
 121         function.
 122
 123 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 124
 125         * configure.in (vr4100): Only include vr4100 instructions in
 126         simulator.
 127         * configure: Re-generate.
 128         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 129
 130 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 131
 132         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 133         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 134         true alternative.
 135
 136         * configure.in (sim_default_gen, sim_use_gen): Replace with
 137         sim_gen.
 138         (--enable-sim-igen): Delete config option. Always using IGEN.
 139         * configure: Re-generate.
 140
 141         * Makefile.in (gencode): Kill, kill, kill.
 142         * gencode.c: Ditto.
 143
 144 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 145
 146         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 147         bit mips16 igen simulator.
 148         * configure: Re-generate.
 149
 150         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 151         as part of vr4100 ISA.
 152         * vr.igen: Mark all instructions as 64 bit only.
 153
 154 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 155
 156         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 157         Pacify GCC.
 158
 159 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 160
 161         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 162         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 163         * configure: Re-generate.
 164
 165         * m16.igen (BREAK): Define breakpoint instruction.
 166         (JALX32): Mark instruction as mips16 and not r3900.
 167         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 168
 169         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 170
 171 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 172
 173         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 174         insn as a debug breakpoint.
 175
 176         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 177         pending.slot_size.
 178         (PENDING_SCHED): Clean up trace statement.
 179         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 180         (PENDING_FILL): Delay write by only one cycle.
 181         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 182
 183         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 184         of pending writes.
 185         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 186         32 & 64.
 187         (pending_tick): Move incrementing of index to FOR statement.
 188         (pending_tick): Only update PENDING_OUT after a write has occured.
 189
 190         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 191         build simulator.
 192         * configure: Re-generate.
 193
 194         * interp.c (sim_engine_run OLD): Delete explicit call to
 195         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 196
 197 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 198
 199         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 200         interrupt level number to match changed SignalExceptionInterrupt
 201         macro.
 202
 203 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 204
 205         * interp.c: #include "itable.h" if WITH_IGEN.
 206         (get_insn_name): New function.
 207         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 208         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 209
 210 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 211
 212         * configure: Rebuilt to inhale new common/aclocal.m4.
 213
 214 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 215
 216         * dv-tx3904sio.c: Include sim-assert.h.
 217
 218 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 219
 220         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 221         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 222         Reorganize target-specific sim-hardware checks.
 223         * configure: rebuilt.
 224         * interp.c (sim_open): For tx39 target boards, set
 225         OPERATING_ENVIRONMENT, add tx3904sio devices.
 226         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 227         ROM executables.  Install dv-sockser into sim-modules list.
 228
 229         * dv-tx3904irc.c: Compiler warning clean-up.
 230         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 231         frequent hw-trace messages.
 232
 233 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 234
 235         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 236
 237 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 238
 239         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 240
 241         * vr.igen: New file.
 242         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 243         * mips.igen: Define vr4100 model. Include vr.igen.
 244 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 245
 246         * mips.igen (check_mf_hilo): Correct check.
 247
 248 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 249
 250         * sim-main.h (interrupt_event): Add prototype.
 251
 252         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 253         register_ptr, register_value.
 254         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 255
 256         * sim-main.h (tracefh): Make extern.
 257
 258 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 259
 260         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 261         Reduce unnecessarily high timer event frequency.
 262         * dv-tx3904cpu.c: Ditto for interrupt event.
 263
 264 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 265
 266         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 267         to allay warnings.
 268         (interrupt_event): Made non-static.
 269
 270         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 271         interchange of configuration values for external vs. internal
 272         clock dividers.
 273
 274 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 275
 276         * mips.igen (BREAK): Moved code to here for
 277         simulator-reserved break instructions.
 278         * gencode.c (build_instruction): Ditto.
 279         * interp.c (signal_exception): Code moved from here.  Non-
 280         reserved instructions now use exception vector, rather
 281         than halting sim.
 282         * sim-main.h: Moved magic constants to here.
 283
 284 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 285
 286         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 287         register upon non-zero interrupt event level, clear upon zero
 288         event value.
 289         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 290         by passing zero event value.
 291         (*_io_{read,write}_buffer): Endianness fixes.
 292         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 293         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 294
 295         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 296         serial I/O and timer module at base address 0xFFFF0000.
 297
 298 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 299
 300         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 301         and BigEndianCPU.
 302
 303 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 304
 305         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 306         parts.
 307         * configure: Update.
 308
 309 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 310
 311         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 312         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 313         * configure.in: Include tx3904tmr in hw_device list.
 314         * configure: Rebuilt.
 315         * interp.c (sim_open): Instantiate three timer instances.
 316         Fix address typo of tx3904irc instance.
 317
 318 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 319
 320         * interp.c (signal_exception): SystemCall exception now uses
 321         the exception vector.
 322
 323 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 324
 325         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 326         to allay warnings.
 327
 328 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 329
 330         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 331
 332 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 333
 334         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 335
 336         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 337         sim-main.h. Declare a struct hw_descriptor instead of struct
 338         hw_device_descriptor.
 339
 340 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 341
 342         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 343         right bits and then re-align left hand bytes to correct byte
 344         lanes.  Fix incorrect computation in do_store_left when loading
 345         bytes from second word.
 346
 347 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 348
 349         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 350         * interp.c (sim_open): Only create a device tree when HW is
 351         enabled.
 352
 353         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 354         * interp.c (signal_exception): Ditto.
 355
 356 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 357
 358         * gencode.c: Mark BEGEZALL as LIKELY.
 359
 360 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 361
 362         * sim-main.h (ALU32_END): Sign extend 32 bit results.
 363         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
 364
 365 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
 366
 367         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 368         modules.  Recognize TX39 target with "mips*tx39" pattern.
 369         * configure: Rebuilt.
 370         * sim-main.h (*): Added many macros defining bits in
 371         TX39 control registers.
 372         (SignalInterrupt): Send actual PC instead of NULL.
 373         (SignalNMIReset): New exception type.
 374         * interp.c (board): New variable for future use to identify
 375         a particular board being simulated.
 376         (mips_option_handler,mips_options): Added "--board" option.
 377         (interrupt_event): Send actual PC.
 378         (sim_open): Make memory layout conditional on board setting.
 379         (signal_exception): Initial implementation of hardware interrupt
 380         handling.  Accept another break instruction variant for simulator
 381         exit.
 382         (decode_coproc): Implement RFE instruction for TX39.
 383         (mips.igen): Decode RFE instruction as such.
 384         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
 385         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
 386         bbegin to implement memory map.
 387         * dv-tx3904cpu.c: New file.
 388         * dv-tx3904irc.c: New file.
 389
 390 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
 391
 392         * mips.igen (check_mt_hilo): Create a separate r3900 version.
 393
 394 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
 395
 396         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
 397         with calls to check_div_hilo.
 398
 399 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
 400
 401         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
 402         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
 403         Add special r3900 version of do_mult_hilo.
 404         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
 405         with calls to check_mult_hilo.
 406         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
 407         with calls to check_div_hilo.
 408
 409 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 410
 411         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
 412         Document a replacement.
 413
 414 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
 415
 416         * interp.c (sim_monitor): Make mon_printf work.
 417
 418 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
 419
 420         * sim-main.h (INSN_NAME): New arg `cpu'.
 421
 422 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
 423
 424         * configure: Regenerated to track ../common/aclocal.m4 changes.
 425
 426 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
 427
 428         * configure: Regenerated to track ../common/aclocal.m4 changes.
 429         * config.in: Ditto.
 430
 431 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
 432
 433         * acconfig.h: New file.
 434         * configure.in: Reverted change of Apr 24; use sinclude again.
 435
 436 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
 437
 438         * configure: Regenerated to track ../common/aclocal.m4 changes.
 439         * config.in: Ditto.
 440
 441 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
 442
 443         * configure.in: Don't call sinclude.
 444
 445 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
 446
 447         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
 448
 449 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 450
 451         * mips.igen (ERET): Implement.
 452
 453         * interp.c (decode_coproc): Return sign-extended EPC.
 454
 455         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
 456
 457         * interp.c (signal_exception): Do not ignore Trap.
 458         (signal_exception): On TRAP, restart at exception address.
 459         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
 460         (signal_exception): Update.
 461         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
 462         so that TRAP instructions are caught.
 463
 464 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 465
 466         * sim-main.h (struct hilo_access, struct hilo_history): Define,
 467         contains HI/LO access history.
 468         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
 469         (HIACCESS, LOACCESS): Delete, replace with
 470         (HIHISTORY, LOHISTORY): New macros.
 471         (CHECKHILO): Delete all, moved to mips.igen
 472
 473         * gencode.c (build_instruction): Do not generate checks for
 474         correct HI/LO register usage.
 475
 476         * interp.c (old_engine_run): Delete checks for correct HI/LO
 477         register usage.
 478
 479         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
 480         check_mf_cycles): New functions.
 481         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
 482         do_divu, domultx, do_mult, do_multu): Use.
 483
 484         * tx.igen ("madd", "maddu"): Use.
 485
 486 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 487
 488         * mips.igen (DSRAV): Use function do_dsrav.
 489         (SRAV): Use new function do_srav.
 490
 491         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
 492         (B): Sign extend 11 bit immediate.
 493         (EXT-B*): Shift 16 bit immediate left by 1.
 494         (ADDIU*): Don't sign extend immediate value.
 495
 496 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 497
 498         * m16run.c (sim_engine_run): Restore CIA after handling an event.
 499
 500         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
 501         functions.
 502
 503         * mips.igen (delayslot32, nullify_next_insn): New functions.
 504         (m16.igen): Always include.
 505         (do_*): Add more tracing.
 506
 507         * m16.igen (delayslot16): Add NIA argument, could be called by a
 508         32 bit MIPS16 instruction.
 509
 510         * interp.c (ifetch16): Move function from here.
 511         * sim-main.c (ifetch16): To here.
 512
 513         * sim-main.c (ifetch16, ifetch32): Update to match current
 514         implementations of LH, LW.
 515         (signal_exception): Don't print out incorrect hex value of illegal
 516         instruction.
 517
 518 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 519
 520         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
 521         instruction.
 522
 523         * m16.igen: Implement MIPS16 instructions.
 524
 525         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
 526         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
 527         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
 528         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
 529         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
 530         bodies of corresponding code from 32 bit insn to these.  Also used
 531         by MIPS16 versions of functions.
 532
 533         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
 534         (IMEM16): Drop NR argument from macro.
 535
 536 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 537
 538         * Makefile.in (SIM_OBJS): Add sim-main.o.
 539
 540         * sim-main.h (address_translation, load_memory, store_memory,
 541         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
 542         as INLINE_SIM_MAIN.
 543         (pr_addr, pr_uword64): Declare.
 544         (sim-main.c): Include when H_REVEALS_MODULE_P.
 545
 546         * interp.c (address_translation, load_memory, store_memory,
 547         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
 548         from here.
 549         * sim-main.c: To here. Fix compilation problems.
 550
 551         * configure.in: Enable inlining.
 552         * configure: Re-config.
 553
 554 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 555
 556         * configure: Regenerated to track ../common/aclocal.m4 changes.
 557
 558 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 559
 560         * mips.igen: Include tx.igen.
 561         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
 562         * tx.igen: New file, contains MADD and MADDU.
 563
 564         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
 565         the hardwired constant `7'.
 566         (store_memory): Ditto.
 567         (LOADDRMASK): Move definition to sim-main.h.
 568
 569         mips.igen (MTC0): Enable for r3900.
 570         (ADDU): Add trace.
 571
 572         mips.igen (do_load_byte): Delete.
 573         (do_load, do_store, do_load_left, do_load_write, do_store_left,
 574         do_store_right): New functions.
 575         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
 576
 577         configure.in: Let the tx39 use igen again.
 578         configure: Update.
 579
 580 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 581
 582         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
 583         not an address sized quantity.  Return zero for cache sizes.
 584
 585 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 586
 587         * mips.igen (r3900): r3900 does not support 64 bit integer
 588         operations.
 589
 590 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
 591
 592         * configure.in (mipstx39*-*-*): Use gencode simulator rather
 593         than igen one.
 594         * configure : Rebuild.
 595
 596 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 597
 598         * configure: Regenerated to track ../common/aclocal.m4 changes.
 599
 600 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 601
 602         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
 603
 604 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
 605
 606         * configure: Regenerated to track ../common/aclocal.m4 changes.
 607         * config.in: Regenerated to track ../common/aclocal.m4 changes.
 608
 609 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 610
 611         * configure: Regenerated to track ../common/aclocal.m4 changes.
 612
 613 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 614
 615         * interp.c (Max, Min): Comment out functions. Not yet used.
 616
 617 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 618
 619         * configure: Regenerated to track ../common/aclocal.m4 changes.
 620
 621 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
 622
 623         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
 624         configurable settings for stand-alone simulator.
 625
 626         * configure.in: Added X11 search, just in case.
 627
 628         * configure: Regenerated.
 629
 630 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 631
 632         * interp.c (sim_write, sim_read, load_memory, store_memory):
 633         Replace sim_core_*_map with read_map, write_map, exec_map resp.
 634
 635 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 636
 637         * sim-main.h (GETFCC): Return an unsigned value.
 638
 639 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 640
 641         * mips.igen (DIV): Fix check for -1 / MIN_INT.
 642         (DADD): Result destination is RD not RT.
 643
 644 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 645
 646         * sim-main.h (HIACCESS, LOACCESS): Always define.
 647
 648         * mdmx.igen (Maxi, Mini): Rename Max, Min.
 649
 650         * interp.c (sim_info): Delete.
 651
 652 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
 653
 654         * interp.c (DECLARE_OPTION_HANDLER): Use it.
 655         (mips_option_handler): New argument `cpu'.
 656         (sim_open): Update call to sim_add_option_table.
 657
 658 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 659
 660         * mips.igen (CxC1): Add tracing.
 661
 662 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 663
 664         * sim-main.h (Max, Min): Declare.
 665
 666         * interp.c (Max, Min): New functions.
 667
 668         * mips.igen (BC1): Add tracing.
 669
 670 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
 671
 672         * interp.c Added memory map for stack in vr4100
 673
 674 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
 675
 676         * interp.c (load_memory): Add missing "break"'s.
 677
 678 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 679
 680         * interp.c (sim_store_register, sim_fetch_register): Pass in
 681         length parameter.  Return -1.
 682
 683 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
 684
 685         * interp.c: Added hardware init hook, fixed warnings.
 686
 687 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 688
 689         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
 690
 691 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 692
 693         * interp.c (ifetch16): New function.
 694
 695         * sim-main.h (IMEM32): Rename IMEM.
 696         (IMEM16_IMMED): Define.
 697         (IMEM16): Define.
 698         (DELAY_SLOT): Update.
 699
 700         * m16run.c (sim_engine_run): New file.
 701
 702         * m16.igen: All instructions except LB.
 703         (LB): Call do_load_byte.
 704         * mips.igen (do_load_byte): New function.
 705         (LB): Call do_load_byte.
 706
 707         * mips.igen: Move spec for insn bit size and high bit from here.
 708         * Makefile.in (tmp-igen, tmp-m16): To here.
 709
 710         * m16.dc: New file, decode mips16 instructions.
 711
 712         * Makefile.in (SIM_NO_ALL): Define.
 713         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
 714
 715 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 716
 717         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
 718         point unit to 32 bit registers.
 719         * configure: Re-generate.
 720
 721 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 722
 723         * configure.in (sim_use_gen): Make IGEN the default simulator
 724         generator for generic 32 and 64 bit mips targets.
 725         * configure: Re-generate.
 726
 727 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 728
 729         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
 730         bitsize.
 731
 732         * interp.c (sim_fetch_register, sim_store_register): Read/write
 733         FGR from correct location.
 734         (sim_open): Set size of FGR's according to
 735         WITH_TARGET_FLOATING_POINT_BITSIZE.
 736
 737         * sim-main.h (FGR): Store floating point registers in a separate
 738         array.
 739
 740 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 741
 742         * configure: Regenerated to track ../common/aclocal.m4 changes.
 743
 744 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 745
 746         * interp.c (ColdReset): Call PENDING_INVALIDATE.
 747
 748         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
 749
 750         * interp.c (pending_tick): New function.  Deliver pending writes.
 751
 752         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
 753         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
 754         it can handle mixed sized quantites and single bits.
 755
 756 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 757
 758         * interp.c (oengine.h): Do not include when building with IGEN.
 759         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
 760         (sim_info): Ditto for PROCESSOR_64BIT.
 761         (sim_monitor): Replace ut_reg with unsigned_word.
 762         (*): Ditto for t_reg.
 763         (LOADDRMASK): Define.
 764         (sim_open): Remove defunct check that host FP is IEEE compliant,
 765         using software to emulate floating point.
 766         (value_fpr, ...): Always compile, was conditional on HASFPU.
 767
 768 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 769
 770         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
 771         size.
 772
 773         * interp.c (SD, CPU): Define.
 774         (mips_option_handler): Set flags in each CPU.
 775         (interrupt_event): Assume CPU 0 is the one being iterrupted.
 776         (sim_close): Do not clear STATE, deleted anyway.
 777         (sim_write, sim_read): Assume CPU zero's vm should be used for
 778         data transfers.
 779         (sim_create_inferior): Set the PC for all processors.
 780         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
 781         argument.
 782         (mips16_entry): Pass correct nr of args to store_word, load_word.
 783         (ColdReset): Cold reset all cpu's.
 784         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
 785         (sim_monitor, load_memory, store_memory, signal_exception): Use
 786         `CPU' instead of STATE_CPU.
 787
 788
 789         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
 790         SD or CPU_.
 791
 792         * sim-main.h (signal_exception): Add sim_cpu arg.
 793         (SignalException*): Pass both SD and CPU to signal_exception.
 794         * interp.c (signal_exception): Update.
 795
 796         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
 797         Ditto
 798         (sync_operation, prefetch, cache_op, store_memory, load_memory,
 799         address_translation): Ditto
 800         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
 801
 802 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 803
 804         * configure: Regenerated to track ../common/aclocal.m4 changes.
 805
 806 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 807
 808         * interp.c (sim_engine_run): Add `nr_cpus' argument.
 809
 810         * mips.igen (model): Map processor names onto BFD name.
 811
 812         * sim-main.h (CPU_CIA): Delete.
 813         (SET_CIA, GET_CIA): Define
 814
 815 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 816
 817         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
 818         regiser.
 819
 820         * configure.in (default_endian): Configure a big-endian simulator
 821         by default.
 822         * configure: Re-generate.
 823
 824 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
 825
 826         * configure: Regenerated to track ../common/aclocal.m4 changes.
 827
 828 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
 829
 830         * interp.c (sim_monitor): Handle Densan monitor outbyte
 831         and inbyte functions.
 832
 833 1997-12-29  Felix Lee  <flee@cygnus.com>
 834
 835         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
 836
 837 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
 838
 839         * Makefile.in (tmp-igen): Arrange for $zero to always be
 840         reset to zero after every instruction.
 841
 842 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 843
 844         * configure: Regenerated to track ../common/aclocal.m4 changes.
 845         * config.in: Ditto.
 846
 847 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
 848
 849         * mips.igen (MSUB): Fix to work like MADD.
 850         * gencode.c (MSUB): Similarly.
 851
 852 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
 853
 854         * configure: Regenerated to track ../common/aclocal.m4 changes.
 855
 856 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 857
 858         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
 859
 860 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 861
 862         * sim-main.h (sim-fpu.h): Include.
 863
 864         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
 865         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
 866         using host independant sim_fpu module.
 867
 868 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 869
 870         * interp.c (signal_exception): Report internal errors with SIGABRT
 871         not SIGQUIT.
 872
 873         * sim-main.h (C0_CONFIG): New register.
 874         (signal.h): No longer include.
 875
 876         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
 877
 878 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
 879
 880         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
 881
 882 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 883
 884         * mips.igen: Tag vr5000 instructions.
 885         (ANDI): Was missing mipsIV model, fix assembler syntax.
 886         (do_c_cond_fmt): New function.
 887         (C.cond.fmt): Handle mips I-III which do not support CC field
 888         separatly.
 889         (bc1): Handle mips IV which do not have a delaed FCC separatly.
 890         (SDR): Mask paddr when BigEndianMem, not the converse as specified
 891         in IV3.2 spec.
 892         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
 893         vr5000 which saves LO in a GPR separatly.
 894
 895         * configure.in (enable-sim-igen): For vr5000, select vr5000
 896         specific instructions.
 897         * configure: Re-generate.
 898
 899 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 900
 901         * Makefile.in (SIM_OBJS): Add sim-fpu module.
 902
 903         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
 904         fmt_uninterpreted_64 bit cases to switch.  Convert to
 905         fmt_formatted,
 906
 907         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
 908
 909         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
 910         as specified in IV3.2 spec.
 911         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
 912
 913 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 914
 915         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
 916         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
 917         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
 918         PENDING_FILL versions of instructions.  Simplify.
 919         (X): New function.
 920         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
 921         instructions.
 922         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
 923         a signed value.
 924         (MTHI, MFHI): Disable code checking HI-LO.
 925
 926         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
 927         global.
 928         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
 929
 930 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 931
 932         * gencode.c (build_mips16_operands): Replace IPC with cia.
 933
 934         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
 935         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
 936         IPC to `cia'.
 937         (UndefinedResult): Replace function with macro/function
 938         combination.
 939         (sim_engine_run): Don't save PC in IPC.
 940
 941         * sim-main.h (IPC): Delete.
 942
 943
 944         * interp.c (signal_exception, store_word, load_word,
 945         address_translation, load_memory, store_memory, cache_op,
 946         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
 947         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
 948         current instruction address - cia - argument.
 949         (sim_read, sim_write): Call address_translation directly.
 950         (sim_engine_run): Rename variable vaddr to cia.
 951         (signal_exception): Pass cia to sim_monitor
 952
 953         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
 954         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
 955         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
 956
 957         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
 958         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
 959         SIM_ASSERT.
 960
 961         * interp.c (signal_exception): Pass restart address to
 962         sim_engine_restart.
 963
 964         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
 965         idecode.o): Add dependency.
 966
 967         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
 968         Delete definitions
 969         (DELAY_SLOT): Update NIA not PC with branch address.
 970         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
 971
 972         * mips.igen: Use CIA not PC in branch calculations.
 973         (illegal): Call SignalException.
 974         (BEQ, ADDIU): Fix assembler.
 975
 976 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 977
 978         * m16.igen (JALX): Was missing.
 979
 980         * configure.in (enable-sim-igen): New configuration option.
 981         * configure: Re-generate.
 982
 983         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
 984
 985         * interp.c (load_memory, store_memory): Delete parameter RAW.
 986         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
 987         bypassing {load,store}_memory.
 988
 989         * sim-main.h (ByteSwapMem): Delete definition.
 990
 991         * Makefile.in (SIM_OBJS): Add sim-memopt module.
 992
 993         * interp.c (sim_do_command, sim_commands): Delete mips specific
 994         commands.  Handled by module sim-options.
 995
 996         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
 997         (WITH_MODULO_MEMORY): Define.
 998
 999         * interp.c (sim_info): Delete code printing memory size.
1000
1001         * interp.c (mips_size): Nee sim_size, delete function.
1002         (power2): Delete.
1003         (monitor, monitor_base, monitor_size): Delete global variables.
1004         (sim_open, sim_close): Delete code creating monitor and other
1005         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1006         manage memory regions.
1007         (load_memory, store_memory): Use sim-core for memory model.
1008
1009         * interp.c (address_translation): Delete all memory map code
1010         except line forcing 32 bit addresses.
1011
1012 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1013
1014         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1015         trace options.
1016
1017         * interp.c (logfh, logfile): Delete globals.
1018         (sim_open, sim_close): Delete code opening & closing log file.
1019         (mips_option_handler): Delete -l and -n options.
1020         (OPTION mips_options): Ditto.
1021
1022         * interp.c (OPTION mips_options): Rename option trace to dinero.
1023         (mips_option_handler): Update.
1024
1025 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1026
1027         * interp.c (fetch_str): New function.
1028         (sim_monitor): Rewrite using sim_read & sim_write.
1029         (sim_open): Check magic number.
1030         (sim_open): Write monitor vectors into memory using sim_write.
1031         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1032         (sim_read, sim_write): Simplify - transfer data one byte at a
1033         time.
1034         (load_memory, store_memory): Clarify meaning of parameter RAW.
1035
1036         * sim-main.h (isHOST): Defete definition.
1037         (isTARGET): Mark as depreciated.
1038         (address_translation): Delete parameter HOST.
1039
1040         * interp.c (address_translation): Delete parameter HOST.
1041
1042 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1043
1044         * mips.igen:
1045
1046         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1047         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1048
1049 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1050
1051         * mips.igen: Add model filter field to records.
1052
1053 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1054
1055         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1056
1057         interp.c (sim_engine_run): Do not compile function sim_engine_run
1058         when WITH_IGEN == 1.
1059
1060         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1061         target architecture.
1062
1063         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1064         igen. Replace with configuration variables sim_igen_flags /
1065         sim_m16_flags.
1066
1067         * m16.igen: New file.  Copy mips16 insns here.
1068         * mips.igen: From here.
1069
1070 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1071
1072         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1073         to top.
1074         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1075
1076 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1077
1078         * gencode.c (build_instruction): Follow sim_write's lead in using
1079         BigEndianMem instead of !ByteSwapMem.
1080
1081 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1082
1083         * configure.in (sim_gen): Dependent on target, select type of
1084         generator.  Always select old style generator.
1085
1086         configure: Re-generate.
1087
1088         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1089         targets.
1090         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1091         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1092         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1093         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1094         SIM_@sim_gen@_*, set by autoconf.
1095
1096 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1097
1098         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1099
1100         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1101         CURRENT_FLOATING_POINT instead.
1102
1103         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1104         (address_translation): Raise exception InstructionFetch when
1105         translation fails and isINSTRUCTION.
1106
1107         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1108         sim_engine_run): Change type of of vaddr and paddr to
1109         address_word.
1110         (address_translation, prefetch, load_memory, store_memory,
1111         cache_op): Change type of vAddr and pAddr to address_word.
1112
1113         * gencode.c (build_instruction): Change type of vaddr and paddr to
1114         address_word.
1115
1116 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1117
1118         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1119         macro to obtain result of ALU op.
1120
1121 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1122
1123         * interp.c (sim_info): Call profile_print.
1124
1125 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1126
1127         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1128
1129         * sim-main.h (WITH_PROFILE): Do not define, defined in
1130         common/sim-config.h.  Use sim-profile module.
1131         (simPROFILE): Delete defintion.
1132
1133         * interp.c (PROFILE): Delete definition.
1134         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1135         (sim_close): Delete code writing profile histogram.
1136         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1137         Delete.
1138         (sim_engine_run): Delete code profiling the PC.
1139
1140 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1141
1142         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1143
1144         * interp.c (sim_monitor): Make register pointers of type
1145         unsigned_word*.
1146
1147         * sim-main.h: Make registers of type unsigned_word not
1148         signed_word.
1149
1150 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1151
1152         * interp.c (sync_operation): Rename from SyncOperation, make
1153         global, add SD argument.
1154         (prefetch): Rename from Prefetch, make global, add SD argument.
1155         (decode_coproc): Make global.
1156
1157         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1158
1159         * gencode.c (build_instruction): Generate DecodeCoproc not
1160         decode_coproc calls.
1161
1162         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1163         (SizeFGR): Move to sim-main.h
1164         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1165         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1166         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1167         sim-main.h.
1168         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1169         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1170         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1171         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1172         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1173         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1174
1175         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1176         exception.
1177         (sim-alu.h): Include.
1178         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1179         (sim_cia): Typedef to instruction_address.
1180
1181 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1182
1183         * Makefile.in (interp.o): Rename generated file engine.c to
1184         oengine.c.
1185
1186         * interp.c: Update.
1187
1188 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1189
1190         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1191
1192 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1193
1194         * gencode.c (build_instruction): For "FPSQRT", output correct
1195         number of arguments to Recip.
1196
1197 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1198
1199         * Makefile.in (interp.o): Depends on sim-main.h
1200
1201         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1202
1203         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1204         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1205         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1206         STATE, DSSTATE): Define
1207         (GPR, FGRIDX, ..): Define.
1208
1209         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1210         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1211         (GPR, FGRIDX, ...): Delete macros.
1212
1213         * interp.c: Update names to match defines from sim-main.h
1214
1215 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1216
1217         * interp.c (sim_monitor): Add SD argument.
1218         (sim_warning): Delete.  Replace calls with calls to
1219         sim_io_eprintf.
1220         (sim_error): Delete. Replace calls with sim_io_error.
1221         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1222         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1223         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1224         argument.
1225         (mips_size): Rename from sim_size. Add SD argument.
1226
1227         * interp.c (simulator): Delete global variable.
1228         (callback): Delete global variable.
1229         (mips_option_handler, sim_open, sim_write, sim_read,
1230         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1231         sim_size,sim_monitor): Use sim_io_* not callback->*.
1232         (sim_open): ZALLOC simulator struct.
1233         (PROFILE): Do not define.
1234
1235 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1236
1237         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1238         support.h with corresponding code.
1239
1240         * sim-main.h (word64, uword64), support.h: Move definition to
1241         sim-main.h.
1242         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1243
1244         * support.h: Delete
1245         * Makefile.in: Update dependencies
1246         * interp.c: Do not include.
1247
1248 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1249
1250         * interp.c (address_translation, load_memory, store_memory,
1251         cache_op): Rename to from AddressTranslation et.al., make global,
1252         add SD argument
1253
1254         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1255         CacheOp): Define.
1256
1257         * interp.c (SignalException): Rename to signal_exception, make
1258         global.
1259
1260         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1261
1262         * sim-main.h (SignalException, SignalExceptionInterrupt,
1263         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1264         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1265         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1266         Define.
1267
1268         * interp.c, support.h: Use.
1269
1270 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1271
1272         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1273         to value_fpr / store_fpr. Add SD argument.
1274         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1275         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1276
1277         * sim-main.h (ValueFPR, StoreFPR): Define.
1278
1279 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1280
1281         * interp.c (sim_engine_run): Check consistency between configure
1282         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1283         and HASFPU.
1284
1285         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1286         (mips_fpu): Configure WITH_FLOATING_POINT.
1287         (mips_endian): Configure WITH_TARGET_ENDIAN.
1288         * configure: Update.
1289
1290 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1291
1292         * configure: Regenerated to track ../common/aclocal.m4 changes.
1293
1294 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1295
1296         * configure: Regenerated.
1297
1298 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1299
1300         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1301
1302 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1303
1304         * gencode.c (print_igen_insn_models): Assume certain architectures
1305         include all mips* instructions.
1306         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1307         instruction.
1308
1309         * Makefile.in (tmp.igen): Add target. Generate igen input from
1310         gencode file.
1311
1312         * gencode.c (FEATURE_IGEN): Define.
1313         (main): Add --igen option.  Generate output in igen format.
1314         (process_instructions): Format output according to igen option.
1315         (print_igen_insn_format): New function.
1316         (print_igen_insn_models): New function.
1317         (process_instructions): Only issue warnings and ignore
1318         instructions when no FEATURE_IGEN.
1319
1320 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1321
1322         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1323         MIPS targets.
1324
1325 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1326
1327         * configure: Regenerated to track ../common/aclocal.m4 changes.
1328
1329 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1330
1331         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1332         SIM_RESERVED_BITS): Delete, moved to common.
1333         (SIM_EXTRA_CFLAGS): Update.
1334
1335 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1336
1337         * configure.in: Configure non-strict memory alignment.
1338         * configure: Regenerated to track ../common/aclocal.m4 changes.
1339
1340 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1341
1342         * configure: Regenerated to track ../common/aclocal.m4 changes.
1343
1344 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1345
1346         * gencode.c (SDBBP,DERET): Added (3900) insns.
1347         (RFE): Turn on for 3900.
1348         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1349         (dsstate): Made global.
1350         (SUBTARGET_R3900): Added.
1351         (CANCELDELAYSLOT): New.
1352         (SignalException): Ignore SystemCall rather than ignore and
1353         terminate.  Add DebugBreakPoint handling.
1354         (decode_coproc): New insns RFE, DERET; and new registers Debug
1355         and DEPC protected by SUBTARGET_R3900.
1356         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1357         bits explicitly.
1358         * Makefile.in,configure.in: Add mips subtarget option.
1359         * configure: Update.
1360
1361 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
1362
1363         * gencode.c: Add r3900 (tx39).
1364
1365
1366 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
1367
1368         * gencode.c (build_instruction): Don't need to subtract 4 for
1369         JALR, just 2.
1370
1371 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
1372
1373         * interp.c: Correct some HASFPU problems.
1374
1375 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1376
1377         * configure: Regenerated to track ../common/aclocal.m4 changes.
1378
1379 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1380
1381         * interp.c (mips_options): Fix samples option short form, should
1382         be `x'.
1383
1384 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1385
1386         * interp.c (sim_info): Enable info code.  Was just returning.
1387
1388 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1389
1390         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1391         MFC0.
1392
1393 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1394
1395         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1396         constants.
1397         (build_instruction): Ditto for LL.
1398
1399 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
1400
1401         * configure: Regenerated to track ../common/aclocal.m4 changes.
1402
1403 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1404
1405         * configure: Regenerated to track ../common/aclocal.m4 changes.
1406         * config.in: Ditto.
1407
1408 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1409
1410         * interp.c (sim_open): Add call to sim_analyze_program, update
1411         call to sim_config.
1412
1413 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1414
1415         * interp.c (sim_kill): Delete.
1416         (sim_create_inferior): Add ABFD argument. Set PC from same.
1417         (sim_load): Move code initializing trap handlers from here.
1418         (sim_open): To here.
1419         (sim_load): Delete, use sim-hload.c.
1420
1421         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1422
1423 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1424
1425         * configure: Regenerated to track ../common/aclocal.m4 changes.
1426         * config.in: Ditto.
1427
1428 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1429
1430         * interp.c (sim_open): Add ABFD argument.
1431         (sim_load): Move call to sim_config from here.
1432         (sim_open): To here.  Check return status.
1433
1434 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
1435
1436         * gencode.c (build_instruction): Two arg MADD should
1437         not assign result to $0.
1438
1439 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
1440
1441         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1442         * sim/mips/configure.in: Regenerate.
1443
1444 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
1445
1446         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1447         signed8, unsigned8 et.al. types.
1448
1449         * interp.c (SUB_REG_FETCH): Handle both little and big endian
1450         hosts when selecting subreg.
1451
1452 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
1453
1454         * interp.c (sim_engine_run): Reset the ZERO register to zero
1455         regardless of FEATURE_WARN_ZERO.
1456         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1457
1458 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1459
1460         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1461         (SignalException): For BreakPoints ignore any mode bits and just
1462         save the PC.
1463         (SignalException): Always set the CAUSE register.
1464
1465 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1466
1467         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1468         exception has been taken.
1469
1470         * interp.c: Implement the ERET and mt/f sr instructions.
1471
1472 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1473
1474         * interp.c (SignalException): Don't bother restarting an
1475         interrupt.
1476
1477 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1478
1479         * interp.c (SignalException): Really take an interrupt.
1480         (interrupt_event): Only deliver interrupts when enabled.
1481
1482 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1483
1484         * interp.c (sim_info): Only print info when verbose.
1485         (sim_info) Use sim_io_printf for output.
1486
1487 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1488
1489         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1490         mips architectures.
1491
1492 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1493
1494         * interp.c (sim_do_command): Check for common commands if a
1495         simulator specific command fails.
1496
1497 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
1498
1499         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1500         and simBE when DEBUG is defined.
1501
1502 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1503
1504         * interp.c (interrupt_event): New function.  Pass exception event
1505         onto exception handler.
1506
1507         * configure.in: Check for stdlib.h.
1508         * configure: Regenerate.
1509
1510         * gencode.c (build_instruction): Add UNUSED attribute to tempS
1511         variable declaration.
1512         (build_instruction): Initialize memval1.
1513         (build_instruction): Add UNUSED attribute to byte, bigend,
1514         reverse.
1515         (build_operands): Ditto.
1516
1517         * interp.c: Fix GCC warnings.
1518         (sim_get_quit_code): Delete.
1519
1520         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1521         * Makefile.in: Ditto.
1522         * configure: Re-generate.
1523
1524         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1525
1526 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1527
1528         * interp.c (mips_option_handler): New function parse argumes using
1529         sim-options.
1530         (myname): Replace with STATE_MY_NAME.
1531         (sim_open): Delete check for host endianness - performed by
1532         sim_config.
1533         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1534         (sim_open): Move much of the initialization from here.
1535         (sim_load): To here.  After the image has been loaded and
1536         endianness set.
1537         (sim_open): Move ColdReset from here.
1538         (sim_create_inferior): To here.
1539         (sim_open): Make FP check less dependant on host endianness.
1540
1541         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1542         run.
1543         * interp.c (sim_set_callbacks): Delete.
1544
1545         * interp.c (membank, membank_base, membank_size): Replace with
1546         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1547         (sim_open): Remove call to callback->init. gdb/run do this.
1548
1549         * interp.c: Update
1550
1551         * sim-main.h (SIM_HAVE_FLATMEM): Define.
1552
1553         * interp.c (big_endian_p): Delete, replaced by
1554         current_target_byte_order.
1555
1556 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1557
1558         * interp.c (host_read_long, host_read_word, host_swap_word,
1559         host_swap_long): Delete. Using common sim-endian.
1560         (sim_fetch_register, sim_store_register): Use H2T.
1561         (pipeline_ticks): Delete.  Handled by sim-events.
1562         (sim_info): Update.
1563         (sim_engine_run): Update.
1564
1565 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1566
1567         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1568         reason from here.
1569         (SignalException): To here. Signal using sim_engine_halt.
1570         (sim_stop_reason): Delete, moved to common.
1571
1572 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
1573
1574         * interp.c (sim_open): Add callback argument.
1575         (sim_set_callbacks): Delete SIM_DESC argument.
1576         (sim_size): Ditto.
1577
1578 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1579
1580         * Makefile.in (SIM_OBJS): Add common modules.
1581
1582         * interp.c (sim_set_callbacks): Also set SD callback.
1583         (set_endianness, xfer_*, swap_*): Delete.
1584         (host_read_word, host_read_long, host_swap_word, host_swap_long):
1585         Change to functions using sim-endian macros.
1586         (control_c, sim_stop): Delete, use common version.
1587         (simulate): Convert into.
1588         (sim_engine_run): This function.
1589         (sim_resume): Delete.
1590
1591         * interp.c (simulation): New variable - the simulator object.
1592         (sim_kind): Delete global - merged into simulation.
1593         (sim_load): Cleanup.  Move PC assignment from here.
1594         (sim_create_inferior): To here.
1595
1596         * sim-main.h: New file.
1597         * interp.c (sim-main.h): Include.
1598
1599 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
1600
1601         * configure: Regenerated to track ../common/aclocal.m4 changes.
1602
1603 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
1604
1605         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1606
1607 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
1608
1609         * gencode.c (build_instruction): DIV instructions: check
1610         for division by zero and integer overflow before using
1611         host's division operation.
1612
1613 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
1614
1615         * Makefile.in (SIM_OBJS): Add sim-load.o.
1616         * interp.c: #include bfd.h.
1617         (target_byte_order): Delete.
1618         (sim_kind, myname, big_endian_p): New static locals.
1619         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
1620         after argument parsing.  Recognize -E arg, set endianness accordingly.
1621         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
1622         load file into simulator.  Set PC from bfd.
1623         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
1624         (set_endianness): Use big_endian_p instead of target_byte_order.
1625
1626 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1627
1628         * interp.c (sim_size): Delete prototype - conflicts with
1629         definition in remote-sim.h.  Correct definition.
1630
1631 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1632
1633         * configure: Regenerated to track ../common/aclocal.m4 changes.
1634         * config.in: Ditto.
1635
1636 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
1637
1638         * interp.c (sim_open): New arg `kind'.
1639
1640         * configure: Regenerated to track ../common/aclocal.m4 changes.
1641
1642 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1643
1644         * configure: Regenerated to track ../common/aclocal.m4 changes.
1645
1646 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
1647
1648         * interp.c (sim_open): Set optind to 0 before calling getopt.
1649
1650 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1651
1652         * configure: Regenerated to track ../common/aclocal.m4 changes.
1653
1654 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
1655
1656         * interp.c : Replace uses of pr_addr with pr_uword64
1657         where the bit length is always 64 independent of SIM_ADDR.
1658         (pr_uword64) : added.
1659
1660 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1661
1662         * configure: Re-generate.
1663
1664 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
1665
1666         * configure: Regenerate to track ../common/aclocal.m4 changes.
1667
1668 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
1669
1670         * interp.c (sim_open): New SIM_DESC result.  Argument is now
1671         in argv form.
1672         (other sim_*): New SIM_DESC argument.
1673
1674 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
1675
1676         * interp.c: Fix printing of addresses for non-64-bit targets.
1677         (pr_addr): Add function to print address based on size.
1678
1679 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
1680
1681         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1682
1683 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
1684
1685         * gencode.c (build_mips16_operands): Correct computation of base
1686         address for extended PC relative instruction.
1687
1688 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
1689
1690         * interp.c (mips16_entry): Add support for floating point cases.
1691         (SignalException): Pass floating point cases to mips16_entry.
1692         (ValueFPR): Don't restrict fmt_single and fmt_word to even
1693         registers.
1694         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
1695         or fmt_word.
1696         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1697         and then set the state to fmt_uninterpreted.
1698         (COP_SW): Temporarily set the state to fmt_word while calling
1699         ValueFPR.
1700
1701 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
1702
1703         * gencode.c (build_instruction): The high order may be set in the
1704         comparison flags at any ISA level, not just ISA 4.
1705
1706 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
1707
1708         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1709         COMMON_{PRE,POST}_CONFIG_FRAG instead.
1710         * configure.in: sinclude ../common/aclocal.m4.
1711         * configure: Regenerated.
1712
1713 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
1714
1715         * configure: Rebuild after change to aclocal.m4.
1716
1717 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
1718
1719         * configure configure.in Makefile.in:  Update to new configure
1720         scheme which is more compatible with WinGDB builds.
1721         * configure.in:  Improve comment on how to run autoconf.
1722         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
1723         * Makefile.in:  Use autoconf substitution to install common
1724         makefile fragment.
1725
1726 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
1727
1728         * gencode.c (build_instruction): Use BigEndianCPU instead of
1729         ByteSwapMem.
1730
1731 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
1732
1733         * interp.c (sim_monitor): Make output to stdout visible in
1734         wingdb's I/O log window.
1735
1736 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
1737
1738         * support.h: Undo previous change to SIGTRAP
1739         and SIGQUIT values.
1740
1741 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
1742
1743         * interp.c (store_word, load_word): New static functions.
1744         (mips16_entry): New static function.
1745         (SignalException): Look for mips16 entry and exit instructions.
1746         (simulate): Use the correct index when setting fpr_state after
1747         doing a pending move.
1748
1749 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
1750
1751         * interp.c: Fix byte-swapping code throughout to work on
1752         both little- and big-endian hosts.
1753
1754 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
1755
1756         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1757         with gdb/config/i386/xm-windows.h.
1758
1759 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
1760
1761         * gencode.c (build_instruction): Work around MSVC++ code gen bug
1762         that messes up arithmetic shifts.
1763
1764 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
1765
1766         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
1767         SIGTRAP and SIGQUIT for _WIN32.
1768
1769 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
1770
1771         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1772         force a 64 bit multiplication.
1773         (build_instruction) [OR]: In mips16 mode, don't do anything if the
1774         destination register is 0, since that is the default mips16 nop
1775         instruction.
1776
1777 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
1778
1779         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1780         (build_endian_shift): Don't check proc64.
1781         (build_instruction): Always set memval to uword64.  Cast op2 to
1782         uword64 when shifting it left in memory instructions.  Always use
1783         the same code for stores--don't special case proc64.
1784
1785         * gencode.c (build_mips16_operands): Fix base PC value for PC
1786         relative operands.
1787         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1788         jal instruction.
1789         * interp.c (simJALDELAYSLOT): Define.
1790         (JALDELAYSLOT): Define.
1791         (INDELAYSLOT, INJALDELAYSLOT): Define.
1792         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1793
1794 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
1795
1796         * interp.c (sim_open): add flush_cache as a PMON routine
1797         (sim_monitor): handle flush_cache by ignoring it
1798
1799 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
1800
1801         * gencode.c (build_instruction): Use !ByteSwapMem instead of
1802         BigEndianMem.
1803         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1804         (BigEndianMem): Rename to ByteSwapMem and change sense.
1805         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1806         BigEndianMem references to !ByteSwapMem.
1807         (set_endianness): New function, with prototype.
1808         (sim_open): Call set_endianness.
1809         (sim_info): Use simBE instead of BigEndianMem.
1810         (xfer_direct_word, xfer_direct_long, swap_direct_word,
1811         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1812         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1813         ifdefs, keeping the prototype declaration.
1814         (swap_word): Rewrite correctly.
1815         (ColdReset): Delete references to CONFIG.  Delete endianness related
1816         code; moved to set_endianness.
1817
1818 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
1819
1820         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1821         * interp.c (CHECKHILO): Define away.
1822         (simSIGINT): New macro.
1823         (membank_size): Increase from 1MB to 2MB.
1824         (control_c): New function.
1825         (sim_resume): Rename parameter signal to signal_number.  Add local
1826         variable prev.  Call signal before and after simulate.
1827         (sim_stop_reason): Add simSIGINT support.
1828         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1829         functions always.
1830         (sim_warning): Delete call to SignalException.  Do call printf_filtered
1831         if logfh is NULL.
1832         (AddressTranslation): Add #ifdef DEBUG around debugging message and
1833         a call to sim_warning.
1834
1835 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
1836
1837         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1838         16 bit instructions.
1839
1840 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
1841
1842         Add support for mips16 (16 bit MIPS implementation):
1843         * gencode.c (inst_type): Add mips16 instruction encoding types.
1844         (GETDATASIZEINSN): Define.
1845         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
1846         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
1847         mtlo.
1848         (MIPS16_DECODE): New table, for mips16 instructions.
1849         (bitmap_val): New static function.
1850         (struct mips16_op): Define.
1851         (mips16_op_table): New table, for mips16 operands.
1852         (build_mips16_operands): New static function.
1853         (process_instructions): If PC is odd, decode a mips16
1854         instruction.  Break out instruction handling into new
1855         build_instruction function.
1856         (build_instruction): New static function, broken out of
1857         process_instructions.  Check modifiers rather than flags for SHIFT
1858         bit count and m[ft]{hi,lo} direction.
1859         (usage): Pass program name to fprintf.
1860         (main): Remove unused variable this_option_optind.  Change
1861         ``*loptarg++'' to ``loptarg++''.
1862         (my_strtoul): Parenthesize && within ||.
1863         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1864         (simulate): If PC is odd, fetch a 16 bit instruction, and
1865         increment PC by 2 rather than 4.
1866         * configure.in: Add case for mips16*-*-*.
1867         * configure: Rebuild.
1868
1869 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
1870
1871         * interp.c: Allow -t to enable tracing in standalone simulator.
1872         Fix garbage output in trace file and error messages.
1873
1874 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
1875
1876         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1877         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1878         * configure.in: Simplify using macros in ../common/aclocal.m4.
1879         * configure: Regenerated.
1880         * tconfig.in: New file.
1881
1882 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
1883
1884         * interp.c: Fix bugs in 64-bit port.
1885         Use ansi function declarations for msvc compiler.
1886         Initialize and test file pointer in trace code.
1887         Prevent duplicate definition of LAST_EMED_REGNUM.
1888
1889 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
1890
1891         * interp.c (xfer_big_long): Prevent unwanted sign extension.
1892
1893 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
1894
1895         * interp.c (SignalException): Check for explicit terminating
1896         breakpoint value.
1897         * gencode.c: Pass instruction value through SignalException()
1898         calls for Trap, Breakpoint and Syscall.
1899
1900 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
1901
1902         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1903         only used on those hosts that provide it.
1904         * configure.in: Add sqrt() to list of functions to be checked for.
1905         * config.in: Re-generated.
1906         * configure: Re-generated.
1907
1908 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
1909
1910         * gencode.c (process_instructions): Call build_endian_shift when
1911         expanding STORE RIGHT, to fix swr.
1912         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1913         clear the high bits.
1914         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1915         Fix float to int conversions to produce signed values.
1916
1917 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
1918
1919         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1920         (process_instructions): Correct handling of nor instruction.
1921         Correct shift count for 32 bit shift instructions. Correct sign
1922         extension for arithmetic shifts to not shift the number of bits in
1923         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
1924         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
1925         Fix madd.
1926         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
1927         It's OK to have a mult follow a mult.  What's not OK is to have a
1928         mult follow an mfhi.
1929         (Convert): Comment out incorrect rounding code.
1930
1931 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
1932
1933         * interp.c (sim_monitor): Improved monitor printf
1934         simulation. Tidied up simulator warnings, and added "--log" option
1935         for directing warning message output.
1936         * gencode.c: Use sim_warning() rather than WARNING macro.
1937
1938 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
1939
1940         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
1941         getopt1.o, rather than on gencode.c.  Link objects together.
1942         Don't link against -liberty.
1943         (gencode.o, getopt.o, getopt1.o): New targets.
1944         * gencode.c: Include <ctype.h> and "ansidecl.h".
1945         (AND): Undefine after including "ansidecl.h".
1946         (ULONG_MAX): Define if not defined.
1947         (OP_*): Don't define macros; now defined in opcode/mips.h.
1948         (main): Call my_strtoul rather than strtoul.
1949         (my_strtoul): New static function.
1950
1951 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
1952
1953         * gencode.c (process_instructions):  Generate word64 and uword64
1954         instead of `long long' and `unsigned long long' data types.
1955         * interp.c:  #include sysdep.h to get signals, and define default
1956         for SIGBUS.
1957         * (Convert):  Work around for Visual-C++ compiler bug with type
1958         conversion.
1959         * support.h:  Make things compile under Visual-C++ by using
1960         __int64 instead of `long long'.  Change many refs to long long
1961         into word64/uword64 typedefs.
1962
1963 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
1964
1965         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
1966         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
1967         (docdir): Removed.
1968         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
1969         (AC_PROG_INSTALL): Added.
1970         (AC_PROG_CC): Moved to before configure.host call.
1971         * configure: Rebuilt.
1972
1973 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
1974
1975         * configure.in: Define @SIMCONF@ depending on mips target.
1976         * configure: Rebuild.
1977         * Makefile.in (run): Add @SIMCONF@ to control simulator
1978         construction.
1979         * gencode.c: Change LOADDRMASK to 64bit memory model only.
1980         * interp.c: Remove some debugging, provide more detailed error
1981         messages, update memory accesses to use LOADDRMASK.
1982
1983 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
1984
1985         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
1986         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
1987         stamp-h.
1988         * configure: Rebuild.
1989         * config.in: New file, generated by autoheader.
1990         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
1991         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
1992         HAVE_ANINT and HAVE_AINT, as appropriate.
1993         * Makefile.in (run): Use @LIBS@ rather than -lm.
1994         (interp.o): Depend upon config.h.
1995         (Makefile): Just rebuild Makefile.
1996         (clean): Remove stamp-h.
1997         (mostlyclean): Make the same as clean, not as distclean.
1998         (config.h, stamp-h): New targets.
1999
2000 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2001
2002         * interp.c (ColdReset): Fix boolean test. Make all simulator
2003         globals static.
2004
2005 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2006
2007         * interp.c (xfer_direct_word, xfer_direct_long,
2008         swap_direct_word, swap_direct_long, xfer_big_word,
2009         xfer_big_long, xfer_little_word, xfer_little_long,
2010         swap_word,swap_long): Added.
2011         * interp.c (ColdReset): Provide function indirection to
2012         host<->simulated_target transfer routines.
2013         * interp.c (sim_store_register, sim_fetch_register): Updated to
2014         make use of indirected transfer routines.
2015
2016 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2017
2018         * gencode.c (process_instructions): Ensure FP ABS instruction
2019         recognised.
2020         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2021         system call support.
2022
2023 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2024
2025         * interp.c (sim_do_command): Complain if callback structure not
2026         initialised.
2027
2028 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2029
2030         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2031         support for Sun hosts.
2032         * Makefile.in (gencode): Ensure the host compiler and libraries
2033         used for cross-hosted build.
2034
2035 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2036
2037         * interp.c, gencode.c: Some more (TODO) tidying.
2038
2039 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2040
2041         * gencode.c, interp.c: Replaced explicit long long references with
2042         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2043         * support.h (SET64LO, SET64HI): Macros added.
2044
2045 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2046
2047         * configure: Regenerate with autoconf 2.7.
2048
2049 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2050
2051         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2052         * support.h: Remove superfluous "1" from #if.
2053         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2054
2055 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2056
2057         * interp.c (StoreFPR): Control UndefinedResult() call on
2058         WARN_RESULT manifest.
2059
2060 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2061
2062         * gencode.c: Tidied instruction decoding, and added FP instruction
2063         support.
2064
2065         * interp.c: Added dineroIII, and BSD profiling support. Also
2066         run-time FP handling.
2067
2068 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2069
2070         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2071         gencode.c, interp.c, support.h: created.