sim/mips/ChangeLog

   1 2006-08-29  Thiemo Seufer  <ths@mips.com>
   2             David Ung  <davidu@mips.com>
   3
   4         * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
   5         mips3264r2.igen. Add missing dependency rules.
   6         * m16e.igen: Support for mips16e save/restore instructions.
   7
   8 2006-06-13  Richard Earnshaw  <rearnsha@arm.com>
   9
  10         * configure: Regenerated.
  11
  12 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
  13
  14         * configure: Regenerated.
  15
  16 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
  17
  18         * configure: Regenerated.
  19
  20 2006-05-15 Chao-ying Fu  <fu@mips.com>
  21
  22         * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
  23
  24 2006-04-18  Nick Clifton  <nickc@redhat.com>
  25
  26         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
  27         statement.
  28
  29 2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
  30
  31         * configure: Regenerate.
  32
  33 2005-12-14  Chao-ying Fu  <fu@mips.com>
  34
  35         * Makefile.in (SIM_OBJS): Add dsp.o.
  36         (dsp.o): New dependency.
  37         (IGEN_INCLUDE): Add dsp.igen.
  38         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
  39         mipsisa64*-*-*): Add dsp to sim_igen_machine.
  40         * configure: Regenerate.
  41         * mips.igen: Add dsp model and include dsp.igen.
  42         (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
  43         because these instructions are extended in DSP ASE.
  44         * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
  45         adding 6 DSP accumulator registers and 1 DSP control register.
  46         (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
  47         AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
  48         DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
  49         DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
  50         DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
  51         DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
  52         DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
  53         DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
  54         DSPCR_CCOND_SMASK): New define.
  55         (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
  56         * dsp.c, dsp.igen: New files for MIPS DSP ASE.
  57
  58 2005-07-08  Ian Lance Taylor  <ian@airs.com>
  59
  60         * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
  61
  62 2005-06-16  David Ung  <davidu@mips.com>
  63             Nigel Stephens  <nigel@mips.com>
  64
  65         * mips.igen: New mips16e model and include m16e.igen.
  66         (check_u64): Add mips16e tag.
  67         * m16e.igen: New file for MIPS16e instructions.
  68         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
  69         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
  70         models.
  71         * configure: Regenerate.
  72
  73 2005-05-26  David Ung  <davidu@mips.com>
  74
  75         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
  76         tags to all instructions which are applicable to the new ISAs.
  77         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
  78         vr.igen.
  79         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
  80         instructions.
  81         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
  82         to mips.igen.
  83         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
  84         * configure: Regenerate.
  85
  86 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
  87
  88         * configure: Regenerate.
  89
  90 2005-01-14  Andrew Cagney  <cagney@gnu.org>
  91
  92         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
  93         explicit call to AC_CONFIG_HEADER.
  94         * configure: Regenerate.
  95
  96 2005-01-12  Andrew Cagney  <cagney@gnu.org>
  97
  98         * configure.ac: Update to use ../common/common.m4.
  99         * configure: Re-generate.
 100
 101 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
 102
 103         * configure: Regenerated to track ../common/aclocal.m4 changes.
 104
 105 2005-01-07  Andrew Cagney  <cagney@gnu.org>
 106
 107         * configure.ac: Rename configure.in, require autoconf 2.59.
 108         * configure: Re-generate.
 109
 110 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
 111
 112         * configure: Regenerate for ../common/aclocal.m4 update.
 113
 114 2004-09-24  Monika Chaddha  <monika@acmet.com>
 115
 116         Committed by Andrew Cagney.
 117         * m16.igen (CMP, CMPI): Fix assembler.
 118
 119 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
 120
 121         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
 122         * configure: Regenerate.
 123
 124 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
 125
 126         * configure.in (sim_m16_machine): Include mipsIII.
 127         * configure: Regenerate.
 128
 129 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 130
 131         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
 132         from COP0_BADVADDR.
 133         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
 134
 135 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 136
 137         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
 138
 139 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 140
 141         * mips.igen (check_fmt): Remove.
 142         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
 143         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
 144         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
 145         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
 146         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
 147         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
 148         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 149         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
 150         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
 151         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
 152
 153 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 154
 155         * sb1.igen (check_sbx): New function.
 156         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
 157
 158 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
 159             Richard Sandiford  <rsandifo@redhat.com>
 160
 161         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 162         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 163         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 164         separate implementations for mipsIV and mipsV.  Use new macros to
 165         determine whether the restrictions apply.
 166
 167 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 168
 169         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 170         (check_mult_hilo): Improve comments.
 171         (check_div_hilo): Likewise.  Also, fork off a new version
 172         to handle mips32/mips64 (since there are no hazards to check
 173         in MIPS32/MIPS64).
 174
 175 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 176
 177         * mips.igen (do_dmultx): Fix check for negative operands.
 178
 179 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 180
 181         * Makefile.in (SHELL): Make sure this is defined.
 182         (various): Use $(SHELL) whenever we invoke move-if-change.
 183
 184 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 185
 186         * cp1.c: Tweak attribution slightly.
 187         * cp1.h: Likewise.
 188         * mdmx.c: Likewise.
 189         * mdmx.igen: Likewise.
 190         * mips3d.igen: Likewise.
 191         * sb1.igen: Likewise.
 192
 193 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 194
 195         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 196         unsigned operands.
 197
 198 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 199
 200         * interp.c (sim_open): Rename _bfd to bfd.
 201         (sim_create_inferior): Ditto.
 202
 203 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 204
 205         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 206
 207 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 208
 209         * mips.igen (EI, DI): Remove.
 210
 211 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 212
 213         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 214
 215 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 216             Andrew Cagney  <ac131313@redhat.com>
 217             Gavin Romig-Koch  <gavin@redhat.com>
 218             Graydon Hoare  <graydon@redhat.com>
 219             Aldy Hernandez  <aldyh@redhat.com>
 220             Dave Brolley  <brolley@redhat.com>
 221             Chris Demetriou  <cgd@broadcom.com>
 222
 223         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 224         (sim_mach_default): New variable.
 225         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 226         Add a new simulator generator, MULTI.
 227         * configure: Regenerate.
 228         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 229         (multi-run.o): New dependency.
 230         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 231         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 232         (tmp-multi): Combine them.
 233         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 234         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 235         (distclean-extra): New rule.
 236         * sim-main.h: Include bfd.h.
 237         (MIPS_MACH): New macro.
 238         * mips.igen (vr4120, vr5400, vr5500): New models.
 239         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 240         * vr.igen: Replace with new version.
 241
 242 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 243
 244         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 245         * configure: Regenerate.
 246
 247 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 248
 249         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 250         * mips.igen: Remove all invocations of check_branch_bug and
 251         mark_branch_bug.
 252
 253 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 254
 255         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 256
 257 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 258
 259         * mips.igen (do_load_double, do_store_double): New functions.
 260         (LDC1, SDC1): Rename to...
 261         (LDC1b, SDC1b): respectively.
 262         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 263
 264 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 265
 266         * cp1.c (fp_recip2): Modify initialization expression so that
 267         GCC will recognize it as constant.
 268
 269 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 270
 271         * mdmx.c (SD_): Delete.
 272         (Unpredictable): Re-define, for now, to directly invoke
 273         unpredictable_action().
 274         (mdmx_acc_op): Fix error in .ob immediate handling.
 275
 276 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 277
 278         * interp.c (sim_firmware_command): Initialize `address'.
 279
 280 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 281
 282         * configure: Regenerated to track ../common/aclocal.m4 changes.
 283
 284 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 285             Ed Satterthwaite  <ehs@broadcom.com>
 286
 287         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 288         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 289         * mips.igen: Include mips3d.igen.
 290         (mips3d): New model name for MIPS-3D ASE instructions.
 291         (CVT.W.fmt): Don't use this instruction for word (source) format
 292         instructions.
 293         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 294         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 295         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 296         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 297         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 298         (RSquareRoot1, RSquareRoot2): New macros.
 299         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 300         (fp_rsqrt2): New functions.
 301         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 302         * configure: Regenerate.
 303
 304 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 305             Ed Satterthwaite  <ehs@broadcom.com>
 306
 307         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 308         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 309         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 310         (convert): Note that this function is not used for paired-single
 311         format conversions.
 312         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 313         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 314         (check_fmt_p): Enable paired-single support.
 315         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 316         (PUU.PS): New instructions.
 317         (CVT.S.fmt): Don't use this instruction for paired-single format
 318         destinations.
 319         * sim-main.h (FP_formats): New value 'fmt_ps.'
 320         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 321         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 322
 323 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 324
 325         * mips.igen: Fix formatting of function calls in
 326         many FP operations.
 327
 328 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 329
 330         * mips.igen (MOVN, MOVZ): Trace result.
 331         (TNEI): Print "tnei" as the opcode name in traces.
 332         (CEIL.W): Add disassembly string for traces.
 333         (RSQRT.fmt): Make location of disassembly string consistent
 334         with other instructions.
 335
 336 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 337
 338         * mips.igen (X): Delete unused function.
 339
 340 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 341
 342         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 343
 344 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 345             Ed Satterthwaite  <ehs@broadcom.com>
 346
 347         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 348         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 349         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 350         (fp_nmsub): New prototypes.
 351         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 352         (NegMultiplySub): New defines.
 353         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 354         (MADD.D, MADD.S): Replace with...
 355         (MADD.fmt): New instruction.
 356         (MSUB.D, MSUB.S): Replace with...
 357         (MSUB.fmt): New instruction.
 358         (NMADD.D, NMADD.S): Replace with...
 359         (NMADD.fmt): New instruction.
 360         (NMSUB.D, MSUB.S): Replace with...
 361         (NMSUB.fmt): New instruction.
 362
 363 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 364             Ed Satterthwaite  <ehs@broadcom.com>
 365
 366         * cp1.c: Fix more comment spelling and formatting.
 367         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 368         (denorm_mode): New function.
 369         (fpu_unary, fpu_binary): Round results after operation, collect
 370         status from rounding operations, and update the FCSR.
 371         (convert): Collect status from integer conversions and rounding
 372         operations, and update the FCSR.  Adjust NaN values that result
 373         from conversions.  Convert to use sim_io_eprintf rather than
 374         fprintf, and remove some debugging code.
 375         * cp1.h (fenr_FS): New define.
 376
 377 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 378
 379         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 380         rounding mode to sim FP rounding mode flag conversion code into...
 381         (rounding_mode): New function.
 382
 383 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 384
 385         * cp1.c: Clean up formatting of a few comments.
 386         (value_fpr): Reformat switch statement.
 387
 388 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 389             Ed Satterthwaite  <ehs@broadcom.com>
 390
 391         * cp1.h: New file.
 392         * sim-main.h: Include cp1.h.
 393         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 394         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 395         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 396         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 397         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 398         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 399         * cp1.c: Don't include sim-fpu.h; already included by
 400         sim-main.h.  Clean up formatting of some comments.
 401         (NaN, Equal, Less): Remove.
 402         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 403         (fp_cmp): New functions.
 404         * mips.igen (do_c_cond_fmt): Remove.
 405         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 406         Compare.  Add result tracing.
 407         (CxC1): Remove, replace with...
 408         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 409         (DMxC1): Remove, replace with...
 410         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 411         (MxC1): Remove, replace with...
 412         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 413
 414 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 415
 416         * sim-main.h (FGRIDX): Remove, replace all uses with...
 417         (FGR_BASE): New macro.
 418         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 419         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 420         (NR_FGR, FGR): Likewise.
 421         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 422         * mips.igen: Likewise.
 423
 424 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 425
 426         * cp1.c: Add an FSF Copyright notice to this file.
 427
 428 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 429             Ed Satterthwaite  <ehs@broadcom.com>
 430
 431         * cp1.c (Infinity): Remove.
 432         * sim-main.h (Infinity): Likewise.
 433
 434         * cp1.c (fp_unary, fp_binary): New functions.
 435         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 436         (fp_sqrt): New functions, implemented in terms of the above.
 437         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 438         (Recip, SquareRoot): Remove (replaced by functions above).
 439         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 440         (fp_recip, fp_sqrt): New prototypes.
 441         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 442         (Recip, SquareRoot): Replace prototypes with #defines which
 443         invoke the functions above.
 444
 445 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 446
 447         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 448         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 449         file, remove PARAMS from prototypes.
 450         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 451         simulator state arguments.
 452         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 453         pass simulator state arguments.
 454         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 455         (store_fpr, convert): Remove 'sd' argument.
 456         (value_fpr): Likewise.  Convert to use 'SD' instead.
 457
 458 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 459
 460         * cp1.c (Min, Max): Remove #if 0'd functions.
 461         * sim-main.h (Min, Max): Remove.
 462
 463 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 464
 465         * cp1.c: fix formatting of switch case and default labels.
 466         * interp.c: Likewise.
 467         * sim-main.c: Likewise.
 468
 469 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 470
 471         * cp1.c: Clean up comments which describe FP formats.
 472          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 473
 474 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 475             Ed Satterthwaite  <ehs@broadcom.com>
 476
 477         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 478         Broadcom SiByte SB-1 processor configurations.
 479         * configure: Regenerate.
 480         * sb1.igen: New file.
 481         * mips.igen: Include sb1.igen.
 482         (sb1): New model.
 483         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 484         * mdmx.igen: Add "sb1" model to all appropriate functions and
 485         instructions.
 486         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 487         (ob_func, ob_acc): Reference the above.
 488         (qh_acc): Adjust to keep the same size as ob_acc.
 489         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 490         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 491
 492 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 493
 494         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 495
 496 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 497             Ed Satterthwaite  <ehs@broadcom.com>
 498
 499         * mips.igen (mdmx): New (pseudo-)model.
 500         * mdmx.c, mdmx.igen: New files.
 501         * Makefile.in (SIM_OBJS): Add mdmx.o.
 502         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 503         New typedefs.
 504         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 505         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 506         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 507         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 508         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 509         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 510         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 511         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 512         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 513         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 514         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 515         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 516         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 517         (qh_fmtsel): New macros.
 518         (_sim_cpu): New member "acc".
 519         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 520         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 521
 522 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 523
 524         * interp.c: Use 'deprecated' rather than 'depreciated.'
 525         * sim-main.h: Likewise.
 526
 527 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 528
 529         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 530         which wouldn't compile anyway.
 531         * sim-main.h (unpredictable_action): New function prototype.
 532         (Unpredictable): Define to call igen function unpredictable().
 533         (NotWordValue): New macro to call igen function not_word_value().
 534         (UndefinedResult): Remove.
 535         * interp.c (undefined_result): Remove.
 536         (unpredictable_action): New function.
 537         * mips.igen (not_word_value, unpredictable): New functions.
 538         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 539         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 540         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 541         NotWordValue() to check for unpredictable inputs, then
 542         Unpredictable() to handle them.
 543
 544 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 545
 546         * mips.igen: Fix formatting of calls to Unpredictable().
 547
 548 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 549
 550         * interp.c (sim_open): Revert previous change.
 551
 552 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 553
 554         * interp.c (sim_open): Disable chunk of code that wrote code in
 555         vector table entries.
 556
 557 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 558
 559         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 560         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 561         unused definitions.
 562
 563 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 564
 565         * cp1.c: Fix many formatting issues.
 566
 567 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 568
 569         * cp1.c (fpu_format_name): New function to replace...
 570         (DOFMT): This.  Delete, and update all callers.
 571         (fpu_rounding_mode_name): New function to replace...
 572         (RMMODE): This.  Delete, and update all callers.
 573
 574 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 575
 576         * interp.c: Move FPU support routines from here to...
 577         * cp1.c: Here.  New file.
 578         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 579         (cp1.o): New target.
 580
 581 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 582
 583         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 584         * mips.igen (mips32, mips64): New models, add to all instructions
 585         and functions as appropriate.
 586         (loadstore_ea, check_u64): New variant for model mips64.
 587         (check_fmt_p): New variant for models mipsV and mips64, remove
 588         mipsV model marking fro other variant.
 589         (SLL) Rename to...
 590         (SLLa) this.
 591         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 592         for mips32 and mips64.
 593         (DCLO, DCLZ): New instructions for mips64.
 594
 595 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 596
 597         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 598         immediate or code as a hex value with the "%#lx" format.
 599         (ANDI): Likewise, and fix printed instruction name.
 600
 601 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 602
 603         * sim-main.h (UndefinedResult, Unpredictable): New macros
 604         which currently do nothing.
 605
 606 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 607
 608         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 609         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 610         (status_CU3): New definitions.
 611
 612         * sim-main.h (ExceptionCause): Add new values for MIPS32
 613         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 614         for DebugBreakPoint and NMIReset to note their status in
 615         MIPS32 and MIPS64.
 616         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 617         (SignalExceptionCacheErr): New exception macros.
 618
 619 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 620
 621         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 622         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 623         is always enabled.
 624         (SignalExceptionCoProcessorUnusable): Take as argument the
 625         unusable coprocessor number.
 626
 627 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 628
 629         * mips.igen: Fix formatting of all SignalException calls.
 630
 631 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 632
 633         * sim-main.h (SIGNEXTEND): Remove.
 634
 635 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 636
 637         * mips.igen: Remove gencode comment from top of file, fix
 638         spelling in another comment.
 639
 640 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 641
 642         * mips.igen (check_fmt, check_fmt_p): New functions to check
 643         whether specific floating point formats are usable.
 644         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 645         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 646         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 647         Use the new functions.
 648         (do_c_cond_fmt): Remove format checks...
 649         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 650
 651 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 652
 653         * mips.igen: Fix formatting of check_fpu calls.
 654
 655 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 656
 657         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 658
 659 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 660
 661         * mips.igen: Remove whitespace at end of lines.
 662
 663 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 664
 665         * mips.igen (loadstore_ea): New function to do effective
 666         address calculations.
 667         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 668         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 669         CACHE): Use loadstore_ea to do effective address computations.
 670
 671 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 672
 673         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 674         * mips.igen (LL, CxC1, MxC1): Likewise.
 675
 676 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 677
 678         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 679         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 680         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 681         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 682         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 683         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 684         Don't split opcode fields by hand, use the opcode field values
 685         provided by igen.
 686
 687 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 688
 689         * mips.igen (do_divu): Fix spacing.
 690
 691         * mips.igen (do_dsllv): Move to be right before DSLLV,
 692         to match the rest of the do_<shift> functions.
 693
 694 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 695
 696         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 697         DSRL32, do_dsrlv): Trace inputs and results.
 698
 699 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 700
 701         * mips.igen (CACHE): Provide instruction-printing string.
 702
 703         * interp.c (signal_exception): Comment tokens after #endif.
 704
 705 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 706
 707         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 708         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 709         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 710         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 711         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 712         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 713         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 714         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 715
 716 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 717
 718         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 719         instruction-printing string.
 720         (LWU): Use '64' as the filter flag.
 721
 722 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 723
 724         * mips.igen (SDXC1): Fix instruction-printing string.
 725
 726 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 727
 728         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 729         filter flags "32,f".
 730
 731 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 732
 733         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 734         as the filter flag.
 735
 736 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 737
 738         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 739         add a comma) so that it more closely match the MIPS ISA
 740         documentation opcode partitioning.
 741         (PREF): Put useful names on opcode fields, and include
 742         instruction-printing string.
 743
 744 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 745
 746         * mips.igen (check_u64): New function which in the future will
 747         check whether 64-bit instructions are usable and signal an
 748         exception if not.  Currently a no-op.
 749         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 750         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 751         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 752         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 753
 754         * mips.igen (check_fpu): New function which in the future will
 755         check whether FPU instructions are usable and signal an exception
 756         if not.  Currently a no-op.
 757         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 758         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 759         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 760         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 761         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 762         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 763         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 764         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 765
 766 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 767
 768         * mips.igen (do_load_left, do_load_right): Move to be immediately
 769         following do_load.
 770         (do_store_left, do_store_right): Move to be immediately following
 771         do_store.
 772
 773 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 774
 775         * mips.igen (mipsV): New model name.  Also, add it to
 776         all instructions and functions where it is appropriate.
 777
 778 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 779
 780         * mips.igen: For all functions and instructions, list model
 781         names that support that instruction one per line.
 782
 783 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 784
 785         * mips.igen: Add some additional comments about supported
 786         models, and about which instructions go where.
 787         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 788         order as is used in the rest of the file.
 789
 790 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 791
 792         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 793         indicating that ALU32_END or ALU64_END are there to check
 794         for overflow.
 795         (DADD): Likewise, but also remove previous comment about
 796         overflow checking.
 797
 798 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 799
 800         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 801         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 802         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 803         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 804         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 805         fields (i.e., add and move commas) so that they more closely
 806         match the MIPS ISA documentation opcode partitioning.
 807
 808 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 809
 810         * mips.igen (ADDI): Print immediate value.
 811         (BREAK): Print code.
 812         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 813         (SLL): Print "nop" specially, and don't run the code
 814         that does the shift for the "nop" case.
 815
 816 2001-11-17  Fred Fish  <fnf@redhat.com>
 817
 818         * sim-main.h (float_operation): Move enum declaration outside
 819         of _sim_cpu struct declaration.
 820
 821 2001-04-12  Jim Blandy  <jimb@redhat.com>
 822
 823         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 824         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 825         set of the FCSR.
 826         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 827         PENDING_FILL, and you can get the intended effect gracefully by
 828         calling PENDING_SCHED directly.
 829
 830 2001-02-23  Ben Elliston  <bje@redhat.com>
 831
 832         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 833         already defined elsewhere.
 834
 835 2001-02-19  Ben Elliston  <bje@redhat.com>
 836
 837         * sim-main.h (sim_monitor): Return an int.
 838         * interp.c (sim_monitor): Add return values.
 839         (signal_exception): Handle error conditions from sim_monitor.
 840
 841 2001-02-08  Ben Elliston  <bje@redhat.com>
 842
 843         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 844         (store_memory): Likewise, pass cia to sim_core_write*.
 845
 846 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 847
 848         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 849         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 850
 851 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 852
 853         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 854         * Makefile.in: Don't delete *.igen when cleaning directory.
 855
 856 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 857
 858         * m16.igen (break): Call SignalException not sim_engine_halt.
 859
 860 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 861
 862         From Jason Eckhardt:
 863         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 864
 865 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 866
 867         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 868
 869 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 870
 871         * mips.igen (do_dmultx): Fix typo.
 872
 873 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 874
 875         * configure: Regenerated to track ../common/aclocal.m4 changes.
 876
 877 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 878
 879         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 880
 881 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 882
 883         * sim-main.h (GPR_CLEAR): Define macro.
 884
 885 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 886
 887         * interp.c (decode_coproc): Output long using %lx and not %s.
 888
 889 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 890
 891         * interp.c (sim_open): Sort & extend dummy memory regions for
 892         --board=jmr3904 for eCos.
 893
 894 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 895
 896         * configure: Regenerated.
 897
 898 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 899
 900         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 901         calls, conditional on the simulator being in verbose mode.
 902
 903 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 904
 905         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 906         cache don't get ReservedInstruction traps.
 907
 908 1999-11-29  Mark Salter  <msalter@cygnus.com>
 909
 910         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 911         to clear status bits in sdisr register. This is how the hardware works.
 912
 913         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 914         being used by cygmon.
 915
 916 1999-11-11  Andrew Haley  <aph@cygnus.com>
 917
 918         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 919         instructions.
 920
 921 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 922
 923         * mips.igen (MULT): Correct previous mis-applied patch.
 924
 925 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 926
 927         * mips.igen (delayslot32): Handle sequence like
 928         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 929         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 930         (MULT): Actually pass the third register...
 931
 932 1999-09-03  Mark Salter  <msalter@cygnus.com>
 933
 934         * interp.c (sim_open): Added more memory aliases for additional
 935         hardware being touched by cygmon on jmr3904 board.
 936
 937 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 938
 939         * configure: Regenerated to track ../common/aclocal.m4 changes.
 940
 941 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 942
 943         * interp.c (sim_store_register): Handle case where client - GDB -
 944         specifies that a 4 byte register is 8 bytes in size.
 945         (sim_fetch_register): Ditto.
 946
 947 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 948
 949         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 950         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 951         (idt_monitor_base): Base address for IDT monitor traps.
 952         (pmon_monitor_base): Ditto for PMON.
 953         (lsipmon_monitor_base): Ditto for LSI PMON.
 954         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 955         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 956         (sim_firmware_command): New function.
 957         (mips_option_handler): Call it for OPTION_FIRMWARE.
 958         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 959         option was given, add no monitor by default.  Add BREAK hooks only if
 960         monitors are also there.
 961
 962 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 963
 964         * interp.c (sim_monitor): Flush output before reading input.
 965
 966 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 967
 968         * tconfig.in (SIM_HANDLES_LMA): Always define.
 969
 970 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 971
 972         From Mark Salter <msalter@cygnus.com>:
 973         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 974         (sim_open): Add setup for BSP board.
 975
 976 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 977
 978         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 979         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 980         them as unimplemented.
 981
 982 1999-05-08  Felix Lee  <flee@cygnus.com>
 983
 984         * configure: Regenerated to track ../common/aclocal.m4 changes.
 985
 986 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 987
 988         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 989
 990 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 991
 992         * configure.in: Any mips64vr5*-*-* target should have
 993         -DTARGET_ENABLE_FR=1.
 994         (default_endian): Any mips64vr*el-*-* target should default to
 995         LITTLE_ENDIAN.
 996         * configure: Re-generate.
 997
 998 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 999
1000         * mips.igen (ldl): Extend from _16_, not 32.
1001
1002 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
1003
1004         * interp.c (sim_store_register): Force registers written to by GDB
1005         into an un-interpreted state.
1006
1007 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
1008
1009         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1010         CPU, start periodic background I/O polls.
1011         (tx3904sio_poll): New function: periodic I/O poller.
1012
1013 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
1014
1015         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1016
1017 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
1018
1019         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1020         case statement.
1021
1022 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
1023
1024         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1025         (load_word): Call SIM_CORE_SIGNAL hook on error.
1026         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1027         starting.  For exception dispatching, pass PC instead of NULL_CIA.
1028         (decode_coproc): Use COP0_BADVADDR to store faulting address.
1029         * sim-main.h (COP0_BADVADDR): Define.
1030         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1031         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1032         (_sim_cpu): Add exc_* fields to store register value snapshots.
1033         * mips.igen (*): Replace memory-related SignalException* calls
1034         with references to SIM_CORE_SIGNAL hook.
1035
1036         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1037         fix.
1038         * sim-main.c (*): Minor warning cleanups.
1039
1040 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
1041
1042         * m16.igen (DADDIU5): Correct type-o.
1043
1044 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
1045
1046         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1047         variables.
1048
1049 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
1050
1051         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1052         to include path.
1053         (interp.o): Add dependency on itable.h
1054         (oengine.c, gencode): Delete remaining references.
1055         (BUILT_SRC_FROM_GEN): Clean up.
1056
1057 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
1058
1059         * vr4run.c: New.
1060         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1061         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1062         tmp-run-hack) : New.
1063         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1064         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1065         Drop the "64" qualifier to get the HACK generator working.
1066         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1067         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1068         qualifier to get the hack generator working.
1069         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1070         (DSLL): Use do_dsll.
1071         (DSLLV): Use do_dsllv.
1072         (DSRA): Use do_dsra.
1073         (DSRL): Use do_dsrl.
1074         (DSRLV): Use do_dsrlv.
1075         (BC1): Move *vr4100 to get the HACK generator working.
1076         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1077         get the HACK generator working.
1078         (MACC) Rename to get the HACK generator working.
1079         (DMACC,MACCS,DMACCS): Add the 64.
1080
1081 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1082
1083         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1084         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1085
1086 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1087
1088     * mips/interp.c (DEBUG): Cleanups.
1089
1090 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1091
1092         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1093         (tx3904sio_tickle): fflush after a stdout character output.
1094
1095 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1096
1097         * interp.c (sim_close): Uninstall modules.
1098
1099 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1100
1101         * sim-main.h, interp.c (sim_monitor): Change to global
1102         function.
1103
1104 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1105
1106         * configure.in (vr4100): Only include vr4100 instructions in
1107         simulator.
1108         * configure: Re-generate.
1109         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1110
1111 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1112
1113         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1114         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1115         true alternative.
1116
1117         * configure.in (sim_default_gen, sim_use_gen): Replace with
1118         sim_gen.
1119         (--enable-sim-igen): Delete config option. Always using IGEN.
1120         * configure: Re-generate.
1121
1122         * Makefile.in (gencode): Kill, kill, kill.
1123         * gencode.c: Ditto.
1124
1125 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1126
1127         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1128         bit mips16 igen simulator.
1129         * configure: Re-generate.
1130
1131         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1132         as part of vr4100 ISA.
1133         * vr.igen: Mark all instructions as 64 bit only.
1134
1135 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1136
1137         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1138         Pacify GCC.
1139
1140 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1141
1142         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1143         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1144         * configure: Re-generate.
1145
1146         * m16.igen (BREAK): Define breakpoint instruction.
1147         (JALX32): Mark instruction as mips16 and not r3900.
1148         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1149
1150         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1151
1152 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1153
1154         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1155         insn as a debug breakpoint.
1156
1157         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1158         pending.slot_size.
1159         (PENDING_SCHED): Clean up trace statement.
1160         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1161         (PENDING_FILL): Delay write by only one cycle.
1162         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1163
1164         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1165         of pending writes.
1166         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1167         32 & 64.
1168         (pending_tick): Move incrementing of index to FOR statement.
1169         (pending_tick): Only update PENDING_OUT after a write has occured.
1170
1171         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1172         build simulator.
1173         * configure: Re-generate.
1174
1175         * interp.c (sim_engine_run OLD): Delete explicit call to
1176         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1177
1178 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1179
1180         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1181         interrupt level number to match changed SignalExceptionInterrupt
1182         macro.
1183
1184 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1185
1186         * interp.c: #include "itable.h" if WITH_IGEN.
1187         (get_insn_name): New function.
1188         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1189         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1190
1191 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1192
1193         * configure: Rebuilt to inhale new common/aclocal.m4.
1194
1195 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1196
1197         * dv-tx3904sio.c: Include sim-assert.h.
1198
1199 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1200
1201         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1202         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1203         Reorganize target-specific sim-hardware checks.
1204         * configure: rebuilt.
1205         * interp.c (sim_open): For tx39 target boards, set
1206         OPERATING_ENVIRONMENT, add tx3904sio devices.
1207         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1208         ROM executables.  Install dv-sockser into sim-modules list.
1209
1210         * dv-tx3904irc.c: Compiler warning clean-up.
1211         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1212         frequent hw-trace messages.
1213
1214 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1215
1216         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1217
1218 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1219
1220         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1221
1222         * vr.igen: New file.
1223         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1224         * mips.igen: Define vr4100 model. Include vr.igen.
1225 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1226
1227         * mips.igen (check_mf_hilo): Correct check.
1228
1229 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1230
1231         * sim-main.h (interrupt_event): Add prototype.
1232
1233         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1234         register_ptr, register_value.
1235         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1236
1237         * sim-main.h (tracefh): Make extern.
1238
1239 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1240
1241         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1242         Reduce unnecessarily high timer event frequency.
1243         * dv-tx3904cpu.c: Ditto for interrupt event.
1244
1245 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1246
1247         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1248         to allay warnings.
1249         (interrupt_event): Made non-static.
1250
1251         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1252         interchange of configuration values for external vs. internal
1253         clock dividers.
1254
1255 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1256
1257         * mips.igen (BREAK): Moved code to here for
1258         simulator-reserved break instructions.
1259         * gencode.c (build_instruction): Ditto.
1260         * interp.c (signal_exception): Code moved from here.  Non-
1261         reserved instructions now use exception vector, rather
1262         than halting sim.
1263         * sim-main.h: Moved magic constants to here.
1264
1265 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1266
1267         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1268         register upon non-zero interrupt event level, clear upon zero
1269         event value.
1270         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1271         by passing zero event value.
1272         (*_io_{read,write}_buffer): Endianness fixes.
1273         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1274         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1275
1276         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1277         serial I/O and timer module at base address 0xFFFF0000.
1278
1279 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1280
1281         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1282         and BigEndianCPU.
1283
1284 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1285
1286         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1287         parts.
1288         * configure: Update.
1289
1290 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1291
1292         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1293         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1294         * configure.in: Include tx3904tmr in hw_device list.
1295         * configure: Rebuilt.
1296         * interp.c (sim_open): Instantiate three timer instances.
1297         Fix address typo of tx3904irc instance.
1298
1299 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1300
1301         * interp.c (signal_exception): SystemCall exception now uses
1302         the exception vector.
1303
1304 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1305
1306         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1307         to allay warnings.
1308
1309 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1310
1311         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1312
1313 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1314
1315         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1316
1317         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1318         sim-main.h. Declare a struct hw_descriptor instead of struct
1319         hw_device_descriptor.
1320
1321 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1322
1323         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1324         right bits and then re-align left hand bytes to correct byte
1325         lanes.  Fix incorrect computation in do_store_left when loading
1326         bytes from second word.
1327
1328 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1329
1330         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1331         * interp.c (sim_open): Only create a device tree when HW is
1332         enabled.
1333
1334         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1335         * interp.c (signal_exception): Ditto.
1336
1337 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1338
1339         * gencode.c: Mark BEGEZALL as LIKELY.
1340
1341 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1342
1343         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1344         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1345
1346 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1347
1348         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1349         modules.  Recognize TX39 target with "mips*tx39" pattern.
1350         * configure: Rebuilt.
1351         * sim-main.h (*): Added many macros defining bits in
1352         TX39 control registers.
1353         (SignalInterrupt): Send actual PC instead of NULL.
1354         (SignalNMIReset): New exception type.
1355         * interp.c (board): New variable for future use to identify
1356         a particular board being simulated.
1357         (mips_option_handler,mips_options): Added "--board" option.
1358         (interrupt_event): Send actual PC.
1359         (sim_open): Make memory layout conditional on board setting.
1360         (signal_exception): Initial implementation of hardware interrupt
1361         handling.  Accept another break instruction variant for simulator
1362         exit.
1363         (decode_coproc): Implement RFE instruction for TX39.
1364         (mips.igen): Decode RFE instruction as such.
1365         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1366         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1367         bbegin to implement memory map.
1368         * dv-tx3904cpu.c: New file.
1369         * dv-tx3904irc.c: New file.
1370
1371 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1372
1373         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1374
1375 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1376
1377         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1378         with calls to check_div_hilo.
1379
1380 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1381
1382         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1383         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1384         Add special r3900 version of do_mult_hilo.
1385         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1386         with calls to check_mult_hilo.
1387         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1388         with calls to check_div_hilo.
1389
1390 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1391
1392         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1393         Document a replacement.
1394
1395 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1396
1397         * interp.c (sim_monitor): Make mon_printf work.
1398
1399 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1400
1401         * sim-main.h (INSN_NAME): New arg `cpu'.
1402
1403 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1404
1405         * configure: Regenerated to track ../common/aclocal.m4 changes.
1406
1407 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1408
1409         * configure: Regenerated to track ../common/aclocal.m4 changes.
1410         * config.in: Ditto.
1411
1412 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1413
1414         * acconfig.h: New file.
1415         * configure.in: Reverted change of Apr 24; use sinclude again.
1416
1417 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1418
1419         * configure: Regenerated to track ../common/aclocal.m4 changes.
1420         * config.in: Ditto.
1421
1422 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1423
1424         * configure.in: Don't call sinclude.
1425
1426 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1427
1428         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1429
1430 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1431
1432         * mips.igen (ERET): Implement.
1433
1434         * interp.c (decode_coproc): Return sign-extended EPC.
1435
1436         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1437
1438         * interp.c (signal_exception): Do not ignore Trap.
1439         (signal_exception): On TRAP, restart at exception address.
1440         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1441         (signal_exception): Update.
1442         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1443         so that TRAP instructions are caught.
1444
1445 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1446
1447         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1448         contains HI/LO access history.
1449         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1450         (HIACCESS, LOACCESS): Delete, replace with
1451         (HIHISTORY, LOHISTORY): New macros.
1452         (CHECKHILO): Delete all, moved to mips.igen
1453
1454         * gencode.c (build_instruction): Do not generate checks for
1455         correct HI/LO register usage.
1456
1457         * interp.c (old_engine_run): Delete checks for correct HI/LO
1458         register usage.
1459
1460         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1461         check_mf_cycles): New functions.
1462         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1463         do_divu, domultx, do_mult, do_multu): Use.
1464
1465         * tx.igen ("madd", "maddu"): Use.
1466
1467 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1468
1469         * mips.igen (DSRAV): Use function do_dsrav.
1470         (SRAV): Use new function do_srav.
1471
1472         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1473         (B): Sign extend 11 bit immediate.
1474         (EXT-B*): Shift 16 bit immediate left by 1.
1475         (ADDIU*): Don't sign extend immediate value.
1476
1477 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1478
1479         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1480
1481         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1482         functions.
1483
1484         * mips.igen (delayslot32, nullify_next_insn): New functions.
1485         (m16.igen): Always include.
1486         (do_*): Add more tracing.
1487
1488         * m16.igen (delayslot16): Add NIA argument, could be called by a
1489         32 bit MIPS16 instruction.
1490
1491         * interp.c (ifetch16): Move function from here.
1492         * sim-main.c (ifetch16): To here.
1493
1494         * sim-main.c (ifetch16, ifetch32): Update to match current
1495         implementations of LH, LW.
1496         (signal_exception): Don't print out incorrect hex value of illegal
1497         instruction.
1498
1499 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1500
1501         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1502         instruction.
1503
1504         * m16.igen: Implement MIPS16 instructions.
1505
1506         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1507         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1508         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1509         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1510         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1511         bodies of corresponding code from 32 bit insn to these.  Also used
1512         by MIPS16 versions of functions.
1513
1514         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1515         (IMEM16): Drop NR argument from macro.
1516
1517 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1518
1519         * Makefile.in (SIM_OBJS): Add sim-main.o.
1520
1521         * sim-main.h (address_translation, load_memory, store_memory,
1522         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1523         as INLINE_SIM_MAIN.
1524         (pr_addr, pr_uword64): Declare.
1525         (sim-main.c): Include when H_REVEALS_MODULE_P.
1526
1527         * interp.c (address_translation, load_memory, store_memory,
1528         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1529         from here.
1530         * sim-main.c: To here. Fix compilation problems.
1531
1532         * configure.in: Enable inlining.
1533         * configure: Re-config.
1534
1535 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1536
1537         * configure: Regenerated to track ../common/aclocal.m4 changes.
1538
1539 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1540
1541         * mips.igen: Include tx.igen.
1542         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1543         * tx.igen: New file, contains MADD and MADDU.
1544
1545         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1546         the hardwired constant `7'.
1547         (store_memory): Ditto.
1548         (LOADDRMASK): Move definition to sim-main.h.
1549
1550         mips.igen (MTC0): Enable for r3900.
1551         (ADDU): Add trace.
1552
1553         mips.igen (do_load_byte): Delete.
1554         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1555         do_store_right): New functions.
1556         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1557
1558         configure.in: Let the tx39 use igen again.
1559         configure: Update.
1560
1561 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1562
1563         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1564         not an address sized quantity.  Return zero for cache sizes.
1565
1566 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1567
1568         * mips.igen (r3900): r3900 does not support 64 bit integer
1569         operations.
1570
1571 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1572
1573         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1574         than igen one.
1575         * configure : Rebuild.
1576
1577 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1578
1579         * configure: Regenerated to track ../common/aclocal.m4 changes.
1580
1581 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1582
1583         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1584
1585 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1586
1587         * configure: Regenerated to track ../common/aclocal.m4 changes.
1588         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1589
1590 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1591
1592         * configure: Regenerated to track ../common/aclocal.m4 changes.
1593
1594 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1595
1596         * interp.c (Max, Min): Comment out functions. Not yet used.
1597
1598 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1599
1600         * configure: Regenerated to track ../common/aclocal.m4 changes.
1601
1602 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1603
1604         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1605         configurable settings for stand-alone simulator.
1606
1607         * configure.in: Added X11 search, just in case.
1608
1609         * configure: Regenerated.
1610
1611 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1612
1613         * interp.c (sim_write, sim_read, load_memory, store_memory):
1614         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1615
1616 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1617
1618         * sim-main.h (GETFCC): Return an unsigned value.
1619
1620 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1621
1622         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1623         (DADD): Result destination is RD not RT.
1624
1625 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1626
1627         * sim-main.h (HIACCESS, LOACCESS): Always define.
1628
1629         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1630
1631         * interp.c (sim_info): Delete.
1632
1633 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1634
1635         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1636         (mips_option_handler): New argument `cpu'.
1637         (sim_open): Update call to sim_add_option_table.
1638
1639 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1640
1641         * mips.igen (CxC1): Add tracing.
1642
1643 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1644
1645         * sim-main.h (Max, Min): Declare.
1646
1647         * interp.c (Max, Min): New functions.
1648
1649         * mips.igen (BC1): Add tracing.
1650
1651 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1652
1653         * interp.c Added memory map for stack in vr4100
1654
1655 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1656
1657         * interp.c (load_memory): Add missing "break"'s.
1658
1659 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1660
1661         * interp.c (sim_store_register, sim_fetch_register): Pass in
1662         length parameter.  Return -1.
1663
1664 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1665
1666         * interp.c: Added hardware init hook, fixed warnings.
1667
1668 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1669
1670         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1671
1672 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1673
1674         * interp.c (ifetch16): New function.
1675
1676         * sim-main.h (IMEM32): Rename IMEM.
1677         (IMEM16_IMMED): Define.
1678         (IMEM16): Define.
1679         (DELAY_SLOT): Update.
1680
1681         * m16run.c (sim_engine_run): New file.
1682
1683         * m16.igen: All instructions except LB.
1684         (LB): Call do_load_byte.
1685         * mips.igen (do_load_byte): New function.
1686         (LB): Call do_load_byte.
1687
1688         * mips.igen: Move spec for insn bit size and high bit from here.
1689         * Makefile.in (tmp-igen, tmp-m16): To here.
1690
1691         * m16.dc: New file, decode mips16 instructions.
1692
1693         * Makefile.in (SIM_NO_ALL): Define.
1694         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1695
1696 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1697
1698         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1699         point unit to 32 bit registers.
1700         * configure: Re-generate.
1701
1702 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1703
1704         * configure.in (sim_use_gen): Make IGEN the default simulator
1705         generator for generic 32 and 64 bit mips targets.
1706         * configure: Re-generate.
1707
1708 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1709
1710         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1711         bitsize.
1712
1713         * interp.c (sim_fetch_register, sim_store_register): Read/write
1714         FGR from correct location.
1715         (sim_open): Set size of FGR's according to
1716         WITH_TARGET_FLOATING_POINT_BITSIZE.
1717
1718         * sim-main.h (FGR): Store floating point registers in a separate
1719         array.
1720
1721 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1722
1723         * configure: Regenerated to track ../common/aclocal.m4 changes.
1724
1725 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1726
1727         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1728
1729         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1730
1731         * interp.c (pending_tick): New function.  Deliver pending writes.
1732
1733         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1734         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1735         it can handle mixed sized quantites and single bits.
1736
1737 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1738
1739         * interp.c (oengine.h): Do not include when building with IGEN.
1740         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1741         (sim_info): Ditto for PROCESSOR_64BIT.
1742         (sim_monitor): Replace ut_reg with unsigned_word.
1743         (*): Ditto for t_reg.
1744         (LOADDRMASK): Define.
1745         (sim_open): Remove defunct check that host FP is IEEE compliant,
1746         using software to emulate floating point.
1747         (value_fpr, ...): Always compile, was conditional on HASFPU.
1748
1749 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1750
1751         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1752         size.
1753
1754         * interp.c (SD, CPU): Define.
1755         (mips_option_handler): Set flags in each CPU.
1756         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1757         (sim_close): Do not clear STATE, deleted anyway.
1758         (sim_write, sim_read): Assume CPU zero's vm should be used for
1759         data transfers.
1760         (sim_create_inferior): Set the PC for all processors.
1761         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1762         argument.
1763         (mips16_entry): Pass correct nr of args to store_word, load_word.
1764         (ColdReset): Cold reset all cpu's.
1765         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1766         (sim_monitor, load_memory, store_memory, signal_exception): Use
1767         `CPU' instead of STATE_CPU.
1768
1769
1770         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1771         SD or CPU_.
1772
1773         * sim-main.h (signal_exception): Add sim_cpu arg.
1774         (SignalException*): Pass both SD and CPU to signal_exception.
1775         * interp.c (signal_exception): Update.
1776
1777         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1778         Ditto
1779         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1780         address_translation): Ditto
1781         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1782
1783 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1784
1785         * configure: Regenerated to track ../common/aclocal.m4 changes.
1786
1787 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1788
1789         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1790
1791         * mips.igen (model): Map processor names onto BFD name.
1792
1793         * sim-main.h (CPU_CIA): Delete.
1794         (SET_CIA, GET_CIA): Define
1795
1796 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1797
1798         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1799         regiser.
1800
1801         * configure.in (default_endian): Configure a big-endian simulator
1802         by default.
1803         * configure: Re-generate.
1804
1805 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1806
1807         * configure: Regenerated to track ../common/aclocal.m4 changes.
1808
1809 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1810
1811         * interp.c (sim_monitor): Handle Densan monitor outbyte
1812         and inbyte functions.
1813
1814 1997-12-29  Felix Lee  <flee@cygnus.com>
1815
1816         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1817
1818 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1819
1820         * Makefile.in (tmp-igen): Arrange for $zero to always be
1821         reset to zero after every instruction.
1822
1823 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1824
1825         * configure: Regenerated to track ../common/aclocal.m4 changes.
1826         * config.in: Ditto.
1827
1828 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1829
1830         * mips.igen (MSUB): Fix to work like MADD.
1831         * gencode.c (MSUB): Similarly.
1832
1833 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1834
1835         * configure: Regenerated to track ../common/aclocal.m4 changes.
1836
1837 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1838
1839         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1840
1841 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1842
1843         * sim-main.h (sim-fpu.h): Include.
1844
1845         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1846         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1847         using host independant sim_fpu module.
1848
1849 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1850
1851         * interp.c (signal_exception): Report internal errors with SIGABRT
1852         not SIGQUIT.
1853
1854         * sim-main.h (C0_CONFIG): New register.
1855         (signal.h): No longer include.
1856
1857         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1858
1859 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1860
1861         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1862
1863 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1864
1865         * mips.igen: Tag vr5000 instructions.
1866         (ANDI): Was missing mipsIV model, fix assembler syntax.
1867         (do_c_cond_fmt): New function.
1868         (C.cond.fmt): Handle mips I-III which do not support CC field
1869         separatly.
1870         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1871         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1872         in IV3.2 spec.
1873         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1874         vr5000 which saves LO in a GPR separatly.
1875
1876         * configure.in (enable-sim-igen): For vr5000, select vr5000
1877         specific instructions.
1878         * configure: Re-generate.
1879
1880 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1881
1882         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1883
1884         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1885         fmt_uninterpreted_64 bit cases to switch.  Convert to
1886         fmt_formatted,
1887
1888         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1889
1890         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1891         as specified in IV3.2 spec.
1892         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1893
1894 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1895
1896         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1897         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1898         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1899         PENDING_FILL versions of instructions.  Simplify.
1900         (X): New function.
1901         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1902         instructions.
1903         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1904         a signed value.
1905         (MTHI, MFHI): Disable code checking HI-LO.
1906
1907         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1908         global.
1909         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1910
1911 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1912
1913         * gencode.c (build_mips16_operands): Replace IPC with cia.
1914
1915         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1916         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1917         IPC to `cia'.
1918         (UndefinedResult): Replace function with macro/function
1919         combination.
1920         (sim_engine_run): Don't save PC in IPC.
1921
1922         * sim-main.h (IPC): Delete.
1923
1924
1925         * interp.c (signal_exception, store_word, load_word,
1926         address_translation, load_memory, store_memory, cache_op,
1927         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1928         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1929         current instruction address - cia - argument.
1930         (sim_read, sim_write): Call address_translation directly.
1931         (sim_engine_run): Rename variable vaddr to cia.
1932         (signal_exception): Pass cia to sim_monitor
1933
1934         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1935         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1936         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1937
1938         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1939         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1940         SIM_ASSERT.
1941
1942         * interp.c (signal_exception): Pass restart address to
1943         sim_engine_restart.
1944
1945         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1946         idecode.o): Add dependency.
1947
1948         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1949         Delete definitions
1950         (DELAY_SLOT): Update NIA not PC with branch address.
1951         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1952
1953         * mips.igen: Use CIA not PC in branch calculations.
1954         (illegal): Call SignalException.
1955         (BEQ, ADDIU): Fix assembler.
1956
1957 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1958
1959         * m16.igen (JALX): Was missing.
1960
1961         * configure.in (enable-sim-igen): New configuration option.
1962         * configure: Re-generate.
1963
1964         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1965
1966         * interp.c (load_memory, store_memory): Delete parameter RAW.
1967         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1968         bypassing {load,store}_memory.
1969
1970         * sim-main.h (ByteSwapMem): Delete definition.
1971
1972         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1973
1974         * interp.c (sim_do_command, sim_commands): Delete mips specific
1975         commands.  Handled by module sim-options.
1976
1977         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1978         (WITH_MODULO_MEMORY): Define.
1979
1980         * interp.c (sim_info): Delete code printing memory size.
1981
1982         * interp.c (mips_size): Nee sim_size, delete function.
1983         (power2): Delete.
1984         (monitor, monitor_base, monitor_size): Delete global variables.
1985         (sim_open, sim_close): Delete code creating monitor and other
1986         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1987         manage memory regions.
1988         (load_memory, store_memory): Use sim-core for memory model.
1989
1990         * interp.c (address_translation): Delete all memory map code
1991         except line forcing 32 bit addresses.
1992
1993 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1994
1995         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1996         trace options.
1997
1998         * interp.c (logfh, logfile): Delete globals.
1999         (sim_open, sim_close): Delete code opening & closing log file.
2000         (mips_option_handler): Delete -l and -n options.
2001         (OPTION mips_options): Ditto.
2002
2003         * interp.c (OPTION mips_options): Rename option trace to dinero.
2004         (mips_option_handler): Update.
2005
2006 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2007
2008         * interp.c (fetch_str): New function.
2009         (sim_monitor): Rewrite using sim_read & sim_write.
2010         (sim_open): Check magic number.
2011         (sim_open): Write monitor vectors into memory using sim_write.
2012         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2013         (sim_read, sim_write): Simplify - transfer data one byte at a
2014         time.
2015         (load_memory, store_memory): Clarify meaning of parameter RAW.
2016
2017         * sim-main.h (isHOST): Defete definition.
2018         (isTARGET): Mark as depreciated.
2019         (address_translation): Delete parameter HOST.
2020
2021         * interp.c (address_translation): Delete parameter HOST.
2022
2023 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2024
2025         * mips.igen:
2026
2027         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2028         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2029
2030 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2031
2032         * mips.igen: Add model filter field to records.
2033
2034 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2035
2036         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
2037
2038         interp.c (sim_engine_run): Do not compile function sim_engine_run
2039         when WITH_IGEN == 1.
2040
2041         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2042         target architecture.
2043
2044         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2045         igen. Replace with configuration variables sim_igen_flags /
2046         sim_m16_flags.
2047
2048         * m16.igen: New file.  Copy mips16 insns here.
2049         * mips.igen: From here.
2050
2051 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2052
2053         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2054         to top.
2055         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2056
2057 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
2058
2059         * gencode.c (build_instruction): Follow sim_write's lead in using
2060         BigEndianMem instead of !ByteSwapMem.
2061
2062 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2063
2064         * configure.in (sim_gen): Dependent on target, select type of
2065         generator.  Always select old style generator.
2066
2067         configure: Re-generate.
2068
2069         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2070         targets.
2071         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2072         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2073         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2074         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2075         SIM_@sim_gen@_*, set by autoconf.
2076
2077 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2078
2079         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2080
2081         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2082         CURRENT_FLOATING_POINT instead.
2083
2084         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2085         (address_translation): Raise exception InstructionFetch when
2086         translation fails and isINSTRUCTION.
2087
2088         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2089         sim_engine_run): Change type of of vaddr and paddr to
2090         address_word.
2091         (address_translation, prefetch, load_memory, store_memory,
2092         cache_op): Change type of vAddr and pAddr to address_word.
2093
2094         * gencode.c (build_instruction): Change type of vaddr and paddr to
2095         address_word.
2096
2097 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2098
2099         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2100         macro to obtain result of ALU op.
2101
2102 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2103
2104         * interp.c (sim_info): Call profile_print.
2105
2106 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2107
2108         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2109
2110         * sim-main.h (WITH_PROFILE): Do not define, defined in
2111         common/sim-config.h.  Use sim-profile module.
2112         (simPROFILE): Delete defintion.
2113
2114         * interp.c (PROFILE): Delete definition.
2115         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2116         (sim_close): Delete code writing profile histogram.
2117         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2118         Delete.
2119         (sim_engine_run): Delete code profiling the PC.
2120
2121 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2122
2123         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2124
2125         * interp.c (sim_monitor): Make register pointers of type
2126         unsigned_word*.
2127
2128         * sim-main.h: Make registers of type unsigned_word not
2129         signed_word.
2130
2131 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2132
2133         * interp.c (sync_operation): Rename from SyncOperation, make
2134         global, add SD argument.
2135         (prefetch): Rename from Prefetch, make global, add SD argument.
2136         (decode_coproc): Make global.
2137
2138         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2139
2140         * gencode.c (build_instruction): Generate DecodeCoproc not
2141         decode_coproc calls.
2142
2143         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2144         (SizeFGR): Move to sim-main.h
2145         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2146         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2147         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2148         sim-main.h.
2149         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2150         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2151         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2152         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2153         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2154         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2155
2156         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2157         exception.
2158         (sim-alu.h): Include.
2159         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2160         (sim_cia): Typedef to instruction_address.
2161
2162 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2163
2164         * Makefile.in (interp.o): Rename generated file engine.c to
2165         oengine.c.
2166
2167         * interp.c: Update.
2168
2169 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2170
2171         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2172
2173 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2174
2175         * gencode.c (build_instruction): For "FPSQRT", output correct
2176         number of arguments to Recip.
2177
2178 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2179
2180         * Makefile.in (interp.o): Depends on sim-main.h
2181
2182         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2183
2184         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2185         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2186         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2187         STATE, DSSTATE): Define
2188         (GPR, FGRIDX, ..): Define.
2189
2190         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2191         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2192         (GPR, FGRIDX, ...): Delete macros.
2193
2194         * interp.c: Update names to match defines from sim-main.h
2195
2196 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2197
2198         * interp.c (sim_monitor): Add SD argument.
2199         (sim_warning): Delete.  Replace calls with calls to
2200         sim_io_eprintf.
2201         (sim_error): Delete. Replace calls with sim_io_error.
2202         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2203         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2204         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2205         argument.
2206         (mips_size): Rename from sim_size. Add SD argument.
2207
2208         * interp.c (simulator): Delete global variable.
2209         (callback): Delete global variable.
2210         (mips_option_handler, sim_open, sim_write, sim_read,
2211         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2212         sim_size,sim_monitor): Use sim_io_* not callback->*.
2213         (sim_open): ZALLOC simulator struct.
2214         (PROFILE): Do not define.
2215
2216 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2217
2218         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2219         support.h with corresponding code.
2220
2221         * sim-main.h (word64, uword64), support.h: Move definition to
2222         sim-main.h.
2223         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2224
2225         * support.h: Delete
2226         * Makefile.in: Update dependencies
2227         * interp.c: Do not include.
2228
2229 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2230
2231         * interp.c (address_translation, load_memory, store_memory,
2232         cache_op): Rename to from AddressTranslation et.al., make global,
2233         add SD argument
2234
2235         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2236         CacheOp): Define.
2237
2238         * interp.c (SignalException): Rename to signal_exception, make
2239         global.
2240
2241         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2242
2243         * sim-main.h (SignalException, SignalExceptionInterrupt,
2244         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2245         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2246         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2247         Define.
2248
2249         * interp.c, support.h: Use.
2250
2251 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2252
2253         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2254         to value_fpr / store_fpr. Add SD argument.
2255         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2256         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2257
2258         * sim-main.h (ValueFPR, StoreFPR): Define.
2259
2260 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2261
2262         * interp.c (sim_engine_run): Check consistency between configure
2263         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2264         and HASFPU.
2265
2266         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2267         (mips_fpu): Configure WITH_FLOATING_POINT.
2268         (mips_endian): Configure WITH_TARGET_ENDIAN.
2269         * configure: Update.
2270
2271 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2272
2273         * configure: Regenerated to track ../common/aclocal.m4 changes.
2274
2275 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2276
2277         * configure: Regenerated.
2278
2279 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2280
2281         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2282
2283 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2284
2285         * gencode.c (print_igen_insn_models): Assume certain architectures
2286         include all mips* instructions.
2287         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2288         instruction.
2289
2290         * Makefile.in (tmp.igen): Add target. Generate igen input from
2291         gencode file.
2292
2293         * gencode.c (FEATURE_IGEN): Define.
2294         (main): Add --igen option.  Generate output in igen format.
2295         (process_instructions): Format output according to igen option.
2296         (print_igen_insn_format): New function.
2297         (print_igen_insn_models): New function.
2298         (process_instructions): Only issue warnings and ignore
2299         instructions when no FEATURE_IGEN.
2300
2301 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2302
2303         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2304         MIPS targets.
2305
2306 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2307
2308         * configure: Regenerated to track ../common/aclocal.m4 changes.
2309
2310 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2311
2312         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2313         SIM_RESERVED_BITS): Delete, moved to common.
2314         (SIM_EXTRA_CFLAGS): Update.
2315
2316 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2317
2318         * configure.in: Configure non-strict memory alignment.
2319         * configure: Regenerated to track ../common/aclocal.m4 changes.
2320
2321 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2322
2323         * configure: Regenerated to track ../common/aclocal.m4 changes.
2324
2325 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2326
2327         * gencode.c (SDBBP,DERET): Added (3900) insns.
2328         (RFE): Turn on for 3900.
2329         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2330         (dsstate): Made global.
2331         (SUBTARGET_R3900): Added.
2332         (CANCELDELAYSLOT): New.
2333         (SignalException): Ignore SystemCall rather than ignore and
2334         terminate.  Add DebugBreakPoint handling.
2335         (decode_coproc): New insns RFE, DERET; and new registers Debug
2336         and DEPC protected by SUBTARGET_R3900.
2337         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2338         bits explicitly.
2339         * Makefile.in,configure.in: Add mips subtarget option.
2340         * configure: Update.
2341
2342 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2343
2344         * gencode.c: Add r3900 (tx39).
2345
2346
2347 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2348
2349         * gencode.c (build_instruction): Don't need to subtract 4 for
2350         JALR, just 2.
2351
2352 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2353
2354         * interp.c: Correct some HASFPU problems.
2355
2356 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2357
2358         * configure: Regenerated to track ../common/aclocal.m4 changes.
2359
2360 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2361
2362         * interp.c (mips_options): Fix samples option short form, should
2363         be `x'.
2364
2365 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2366
2367         * interp.c (sim_info): Enable info code.  Was just returning.
2368
2369 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2370
2371         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2372         MFC0.
2373
2374 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2375
2376         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2377         constants.
2378         (build_instruction): Ditto for LL.
2379
2380 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2381
2382         * configure: Regenerated to track ../common/aclocal.m4 changes.
2383
2384 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2385
2386         * configure: Regenerated to track ../common/aclocal.m4 changes.
2387         * config.in: Ditto.
2388
2389 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2390
2391         * interp.c (sim_open): Add call to sim_analyze_program, update
2392         call to sim_config.
2393
2394 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2395
2396         * interp.c (sim_kill): Delete.
2397         (sim_create_inferior): Add ABFD argument. Set PC from same.
2398         (sim_load): Move code initializing trap handlers from here.
2399         (sim_open): To here.
2400         (sim_load): Delete, use sim-hload.c.
2401
2402         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2403
2404 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2405
2406         * configure: Regenerated to track ../common/aclocal.m4 changes.
2407         * config.in: Ditto.
2408
2409 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2410
2411         * interp.c (sim_open): Add ABFD argument.
2412         (sim_load): Move call to sim_config from here.
2413         (sim_open): To here.  Check return status.
2414
2415 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2416
2417         * gencode.c (build_instruction): Two arg MADD should
2418         not assign result to $0.
2419
2420 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2421
2422         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2423         * sim/mips/configure.in: Regenerate.
2424
2425 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2426
2427         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2428         signed8, unsigned8 et.al. types.
2429
2430         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2431         hosts when selecting subreg.
2432
2433 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2434
2435         * interp.c (sim_engine_run): Reset the ZERO register to zero
2436         regardless of FEATURE_WARN_ZERO.
2437         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2438
2439 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2440
2441         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2442         (SignalException): For BreakPoints ignore any mode bits and just
2443         save the PC.
2444         (SignalException): Always set the CAUSE register.
2445
2446 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2447
2448         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2449         exception has been taken.
2450
2451         * interp.c: Implement the ERET and mt/f sr instructions.
2452
2453 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2454
2455         * interp.c (SignalException): Don't bother restarting an
2456         interrupt.
2457
2458 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2459
2460         * interp.c (SignalException): Really take an interrupt.
2461         (interrupt_event): Only deliver interrupts when enabled.
2462
2463 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2464
2465         * interp.c (sim_info): Only print info when verbose.
2466         (sim_info) Use sim_io_printf for output.
2467
2468 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2469
2470         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2471         mips architectures.
2472
2473 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2474
2475         * interp.c (sim_do_command): Check for common commands if a
2476         simulator specific command fails.
2477
2478 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2479
2480         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2481         and simBE when DEBUG is defined.
2482
2483 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2484
2485         * interp.c (interrupt_event): New function.  Pass exception event
2486         onto exception handler.
2487
2488         * configure.in: Check for stdlib.h.
2489         * configure: Regenerate.
2490
2491         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2492         variable declaration.
2493         (build_instruction): Initialize memval1.
2494         (build_instruction): Add UNUSED attribute to byte, bigend,
2495         reverse.
2496         (build_operands): Ditto.
2497
2498         * interp.c: Fix GCC warnings.
2499         (sim_get_quit_code): Delete.
2500
2501         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2502         * Makefile.in: Ditto.
2503         * configure: Re-generate.
2504
2505         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2506
2507 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2508
2509         * interp.c (mips_option_handler): New function parse argumes using
2510         sim-options.
2511         (myname): Replace with STATE_MY_NAME.
2512         (sim_open): Delete check for host endianness - performed by
2513         sim_config.
2514         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2515         (sim_open): Move much of the initialization from here.
2516         (sim_load): To here.  After the image has been loaded and
2517         endianness set.
2518         (sim_open): Move ColdReset from here.
2519         (sim_create_inferior): To here.
2520         (sim_open): Make FP check less dependant on host endianness.
2521
2522         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2523         run.
2524         * interp.c (sim_set_callbacks): Delete.
2525
2526         * interp.c (membank, membank_base, membank_size): Replace with
2527         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2528         (sim_open): Remove call to callback->init. gdb/run do this.
2529
2530         * interp.c: Update
2531
2532         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2533
2534         * interp.c (big_endian_p): Delete, replaced by
2535         current_target_byte_order.
2536
2537 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2538
2539         * interp.c (host_read_long, host_read_word, host_swap_word,
2540         host_swap_long): Delete. Using common sim-endian.
2541         (sim_fetch_register, sim_store_register): Use H2T.
2542         (pipeline_ticks): Delete.  Handled by sim-events.
2543         (sim_info): Update.
2544         (sim_engine_run): Update.
2545
2546 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2547
2548         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2549         reason from here.
2550         (SignalException): To here. Signal using sim_engine_halt.
2551         (sim_stop_reason): Delete, moved to common.
2552
2553 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2554
2555         * interp.c (sim_open): Add callback argument.
2556         (sim_set_callbacks): Delete SIM_DESC argument.
2557         (sim_size): Ditto.
2558
2559 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2560
2561         * Makefile.in (SIM_OBJS): Add common modules.
2562
2563         * interp.c (sim_set_callbacks): Also set SD callback.
2564         (set_endianness, xfer_*, swap_*): Delete.
2565         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2566         Change to functions using sim-endian macros.
2567         (control_c, sim_stop): Delete, use common version.
2568         (simulate): Convert into.
2569         (sim_engine_run): This function.
2570         (sim_resume): Delete.
2571
2572         * interp.c (simulation): New variable - the simulator object.
2573         (sim_kind): Delete global - merged into simulation.
2574         (sim_load): Cleanup.  Move PC assignment from here.
2575         (sim_create_inferior): To here.
2576
2577         * sim-main.h: New file.
2578         * interp.c (sim-main.h): Include.
2579
2580 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2581
2582         * configure: Regenerated to track ../common/aclocal.m4 changes.
2583
2584 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2585
2586         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2587
2588 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2589
2590         * gencode.c (build_instruction): DIV instructions: check
2591         for division by zero and integer overflow before using
2592         host's division operation.
2593
2594 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2595
2596         * Makefile.in (SIM_OBJS): Add sim-load.o.
2597         * interp.c: #include bfd.h.
2598         (target_byte_order): Delete.
2599         (sim_kind, myname, big_endian_p): New static locals.
2600         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2601         after argument parsing.  Recognize -E arg, set endianness accordingly.
2602         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2603         load file into simulator.  Set PC from bfd.
2604         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2605         (set_endianness): Use big_endian_p instead of target_byte_order.
2606
2607 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2608
2609         * interp.c (sim_size): Delete prototype - conflicts with
2610         definition in remote-sim.h.  Correct definition.
2611
2612 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2613
2614         * configure: Regenerated to track ../common/aclocal.m4 changes.
2615         * config.in: Ditto.
2616
2617 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2618
2619         * interp.c (sim_open): New arg `kind'.
2620
2621         * configure: Regenerated to track ../common/aclocal.m4 changes.
2622
2623 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2624
2625         * configure: Regenerated to track ../common/aclocal.m4 changes.
2626
2627 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2628
2629         * interp.c (sim_open): Set optind to 0 before calling getopt.
2630
2631 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2632
2633         * configure: Regenerated to track ../common/aclocal.m4 changes.
2634
2635 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2636
2637         * interp.c : Replace uses of pr_addr with pr_uword64
2638         where the bit length is always 64 independent of SIM_ADDR.
2639         (pr_uword64) : added.
2640
2641 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2642
2643         * configure: Re-generate.
2644
2645 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2646
2647         * configure: Regenerate to track ../common/aclocal.m4 changes.
2648
2649 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2650
2651         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2652         in argv form.
2653         (other sim_*): New SIM_DESC argument.
2654
2655 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2656
2657         * interp.c: Fix printing of addresses for non-64-bit targets.
2658         (pr_addr): Add function to print address based on size.
2659
2660 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2661
2662         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2663
2664 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2665
2666         * gencode.c (build_mips16_operands): Correct computation of base
2667         address for extended PC relative instruction.
2668
2669 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2670
2671         * interp.c (mips16_entry): Add support for floating point cases.
2672         (SignalException): Pass floating point cases to mips16_entry.
2673         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2674         registers.
2675         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2676         or fmt_word.
2677         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2678         and then set the state to fmt_uninterpreted.
2679         (COP_SW): Temporarily set the state to fmt_word while calling
2680         ValueFPR.
2681
2682 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2683
2684         * gencode.c (build_instruction): The high order may be set in the
2685         comparison flags at any ISA level, not just ISA 4.
2686
2687 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2688
2689         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2690         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2691         * configure.in: sinclude ../common/aclocal.m4.
2692         * configure: Regenerated.
2693
2694 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2695
2696         * configure: Rebuild after change to aclocal.m4.
2697
2698 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2699
2700         * configure configure.in Makefile.in:  Update to new configure
2701         scheme which is more compatible with WinGDB builds.
2702         * configure.in:  Improve comment on how to run autoconf.
2703         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2704         * Makefile.in:  Use autoconf substitution to install common
2705         makefile fragment.
2706
2707 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2708
2709         * gencode.c (build_instruction): Use BigEndianCPU instead of
2710         ByteSwapMem.
2711
2712 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2713
2714         * interp.c (sim_monitor): Make output to stdout visible in
2715         wingdb's I/O log window.
2716
2717 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2718
2719         * support.h: Undo previous change to SIGTRAP
2720         and SIGQUIT values.
2721
2722 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2723
2724         * interp.c (store_word, load_word): New static functions.
2725         (mips16_entry): New static function.
2726         (SignalException): Look for mips16 entry and exit instructions.
2727         (simulate): Use the correct index when setting fpr_state after
2728         doing a pending move.
2729
2730 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2731
2732         * interp.c: Fix byte-swapping code throughout to work on
2733         both little- and big-endian hosts.
2734
2735 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2736
2737         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2738         with gdb/config/i386/xm-windows.h.
2739
2740 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2741
2742         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2743         that messes up arithmetic shifts.
2744
2745 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2746
2747         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2748         SIGTRAP and SIGQUIT for _WIN32.
2749
2750 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2751
2752         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2753         force a 64 bit multiplication.
2754         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2755         destination register is 0, since that is the default mips16 nop
2756         instruction.
2757
2758 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2759
2760         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2761         (build_endian_shift): Don't check proc64.
2762         (build_instruction): Always set memval to uword64.  Cast op2 to
2763         uword64 when shifting it left in memory instructions.  Always use
2764         the same code for stores--don't special case proc64.
2765
2766         * gencode.c (build_mips16_operands): Fix base PC value for PC
2767         relative operands.
2768         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2769         jal instruction.
2770         * interp.c (simJALDELAYSLOT): Define.
2771         (JALDELAYSLOT): Define.
2772         (INDELAYSLOT, INJALDELAYSLOT): Define.
2773         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2774
2775 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2776
2777         * interp.c (sim_open): add flush_cache as a PMON routine
2778         (sim_monitor): handle flush_cache by ignoring it
2779
2780 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2781
2782         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2783         BigEndianMem.
2784         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2785         (BigEndianMem): Rename to ByteSwapMem and change sense.
2786         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2787         BigEndianMem references to !ByteSwapMem.
2788         (set_endianness): New function, with prototype.
2789         (sim_open): Call set_endianness.
2790         (sim_info): Use simBE instead of BigEndianMem.
2791         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2792         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2793         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2794         ifdefs, keeping the prototype declaration.
2795         (swap_word): Rewrite correctly.
2796         (ColdReset): Delete references to CONFIG.  Delete endianness related
2797         code; moved to set_endianness.
2798
2799 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2800
2801         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2802         * interp.c (CHECKHILO): Define away.
2803         (simSIGINT): New macro.
2804         (membank_size): Increase from 1MB to 2MB.
2805         (control_c): New function.
2806         (sim_resume): Rename parameter signal to signal_number.  Add local
2807         variable prev.  Call signal before and after simulate.
2808         (sim_stop_reason): Add simSIGINT support.
2809         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2810         functions always.
2811         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2812         if logfh is NULL.
2813         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2814         a call to sim_warning.
2815
2816 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2817
2818         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2819         16 bit instructions.
2820
2821 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2822
2823         Add support for mips16 (16 bit MIPS implementation):
2824         * gencode.c (inst_type): Add mips16 instruction encoding types.
2825         (GETDATASIZEINSN): Define.
2826         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2827         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2828         mtlo.
2829         (MIPS16_DECODE): New table, for mips16 instructions.
2830         (bitmap_val): New static function.
2831         (struct mips16_op): Define.
2832         (mips16_op_table): New table, for mips16 operands.
2833         (build_mips16_operands): New static function.
2834         (process_instructions): If PC is odd, decode a mips16
2835         instruction.  Break out instruction handling into new
2836         build_instruction function.
2837         (build_instruction): New static function, broken out of
2838         process_instructions.  Check modifiers rather than flags for SHIFT
2839         bit count and m[ft]{hi,lo} direction.
2840         (usage): Pass program name to fprintf.
2841         (main): Remove unused variable this_option_optind.  Change
2842         ``*loptarg++'' to ``loptarg++''.
2843         (my_strtoul): Parenthesize && within ||.
2844         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2845         (simulate): If PC is odd, fetch a 16 bit instruction, and
2846         increment PC by 2 rather than 4.
2847         * configure.in: Add case for mips16*-*-*.
2848         * configure: Rebuild.
2849
2850 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2851
2852         * interp.c: Allow -t to enable tracing in standalone simulator.
2853         Fix garbage output in trace file and error messages.
2854
2855 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2856
2857         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2858         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2859         * configure.in: Simplify using macros in ../common/aclocal.m4.
2860         * configure: Regenerated.
2861         * tconfig.in: New file.
2862
2863 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2864
2865         * interp.c: Fix bugs in 64-bit port.
2866         Use ansi function declarations for msvc compiler.
2867         Initialize and test file pointer in trace code.
2868         Prevent duplicate definition of LAST_EMED_REGNUM.
2869
2870 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2871
2872         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2873
2874 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2875
2876         * interp.c (SignalException): Check for explicit terminating
2877         breakpoint value.
2878         * gencode.c: Pass instruction value through SignalException()
2879         calls for Trap, Breakpoint and Syscall.
2880
2881 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2882
2883         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2884         only used on those hosts that provide it.
2885         * configure.in: Add sqrt() to list of functions to be checked for.
2886         * config.in: Re-generated.
2887         * configure: Re-generated.
2888
2889 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2890
2891         * gencode.c (process_instructions): Call build_endian_shift when
2892         expanding STORE RIGHT, to fix swr.
2893         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2894         clear the high bits.
2895         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2896         Fix float to int conversions to produce signed values.
2897
2898 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2899
2900         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2901         (process_instructions): Correct handling of nor instruction.
2902         Correct shift count for 32 bit shift instructions. Correct sign
2903         extension for arithmetic shifts to not shift the number of bits in
2904         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2905         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2906         Fix madd.
2907         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2908         It's OK to have a mult follow a mult.  What's not OK is to have a
2909         mult follow an mfhi.
2910         (Convert): Comment out incorrect rounding code.
2911
2912 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2913
2914         * interp.c (sim_monitor): Improved monitor printf
2915         simulation. Tidied up simulator warnings, and added "--log" option
2916         for directing warning message output.
2917         * gencode.c: Use sim_warning() rather than WARNING macro.
2918
2919 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2920
2921         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2922         getopt1.o, rather than on gencode.c.  Link objects together.
2923         Don't link against -liberty.
2924         (gencode.o, getopt.o, getopt1.o): New targets.
2925         * gencode.c: Include <ctype.h> and "ansidecl.h".
2926         (AND): Undefine after including "ansidecl.h".
2927         (ULONG_MAX): Define if not defined.
2928         (OP_*): Don't define macros; now defined in opcode/mips.h.
2929         (main): Call my_strtoul rather than strtoul.
2930         (my_strtoul): New static function.
2931
2932 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2933
2934         * gencode.c (process_instructions):  Generate word64 and uword64
2935         instead of `long long' and `unsigned long long' data types.
2936         * interp.c:  #include sysdep.h to get signals, and define default
2937         for SIGBUS.
2938         * (Convert):  Work around for Visual-C++ compiler bug with type
2939         conversion.
2940         * support.h:  Make things compile under Visual-C++ by using
2941         __int64 instead of `long long'.  Change many refs to long long
2942         into word64/uword64 typedefs.
2943
2944 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2945
2946         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2947         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2948         (docdir): Removed.
2949         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2950         (AC_PROG_INSTALL): Added.
2951         (AC_PROG_CC): Moved to before configure.host call.
2952         * configure: Rebuilt.
2953
2954 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2955
2956         * configure.in: Define @SIMCONF@ depending on mips target.
2957         * configure: Rebuild.
2958         * Makefile.in (run): Add @SIMCONF@ to control simulator
2959         construction.
2960         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2961         * interp.c: Remove some debugging, provide more detailed error
2962         messages, update memory accesses to use LOADDRMASK.
2963
2964 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2965
2966         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2967         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2968         stamp-h.
2969         * configure: Rebuild.
2970         * config.in: New file, generated by autoheader.
2971         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2972         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2973         HAVE_ANINT and HAVE_AINT, as appropriate.
2974         * Makefile.in (run): Use @LIBS@ rather than -lm.
2975         (interp.o): Depend upon config.h.
2976         (Makefile): Just rebuild Makefile.
2977         (clean): Remove stamp-h.
2978         (mostlyclean): Make the same as clean, not as distclean.
2979         (config.h, stamp-h): New targets.
2980
2981 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2982
2983         * interp.c (ColdReset): Fix boolean test. Make all simulator
2984         globals static.
2985
2986 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2987
2988         * interp.c (xfer_direct_word, xfer_direct_long,
2989         swap_direct_word, swap_direct_long, xfer_big_word,
2990         xfer_big_long, xfer_little_word, xfer_little_long,
2991         swap_word,swap_long): Added.
2992         * interp.c (ColdReset): Provide function indirection to
2993         host<->simulated_target transfer routines.
2994         * interp.c (sim_store_register, sim_fetch_register): Updated to
2995         make use of indirected transfer routines.
2996
2997 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2998
2999         * gencode.c (process_instructions): Ensure FP ABS instruction
3000         recognised.
3001         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3002         system call support.
3003
3004 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
3005
3006         * interp.c (sim_do_command): Complain if callback structure not
3007         initialised.
3008
3009 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
3010
3011         * interp.c (Convert): Provide round-to-nearest and round-to-zero
3012         support for Sun hosts.
3013         * Makefile.in (gencode): Ensure the host compiler and libraries
3014         used for cross-hosted build.
3015
3016 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
3017
3018         * interp.c, gencode.c: Some more (TODO) tidying.
3019
3020 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
3021
3022         * gencode.c, interp.c: Replaced explicit long long references with
3023         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3024         * support.h (SET64LO, SET64HI): Macros added.
3025
3026 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
3027
3028         * configure: Regenerate with autoconf 2.7.
3029
3030 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
3031
3032         * interp.c (LoadMemory): Enclose text following #endif in /* */.
3033         * support.h: Remove superfluous "1" from #if.
3034         * support.h (CHECKSIM): Remove stray 'a' at end of line.
3035
3036 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
3037
3038         * interp.c (StoreFPR): Control UndefinedResult() call on
3039         WARN_RESULT manifest.
3040
3041 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
3042
3043         * gencode.c: Tidied instruction decoding, and added FP instruction
3044         support.
3045
3046         * interp.c: Added dineroIII, and BSD profiling support. Also
3047         run-time FP handling.
3048
3049 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
3050
3051         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3052         gencode.c, interp.c, support.h: created.