1 2007-02-19 Thiemo Seufer <ths@mips.com>
2 Nigel Stephens <nigel@mips.com>
4 (ColdReset): Set CP0 Config0 to reflect the address size supported
6 (decode_coproc): Recognise additional CP0 Config registers
9 2007-02-19 Thiemo Seufer <ths@mips.com>
10 Nigel Stephens <nigel@mips.com>
11 David Ung <davidu@mips.com>
13 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
14 uninterpreted formats. If fmt is one of the uninterpreted types
15 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
16 fmt_word, and fmt_uninterpreted_64 like fmt_long.
17 (store_fpr): When writing an invalid odd register, set the
18 matching even register to fmt_unknown, not the following register.
19 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
20 the the memory window at offset 0 set by --memory-size command
22 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
24 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
26 (sim_monitor): When returning the memory size to the MIPS
27 application, use the value in STATE_MEM_SIZE, not an arbitrary
29 (cop_lw): Don' mess around with FPR_STATE, just pass
30 fmt_uninterpreted_32 to StoreFPR.
32 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
34 * mips.igen (not_word_value): Single version for mips32, mips64
37 2007-02-19 Thiemo Seufer <ths@mips.com>
38 Nigel Stephens <nigel@mips.com>
40 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
43 2007-02-17 Thiemo Seufer <ths@mips.com>
45 * configure.ac (mips*-sde-elf*): Move in front of generic machine
47 * configure: Regenerate.
49 2007-02-17 Thiemo Seufer <ths@mips.com>
51 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
52 Add mdmx to sim_igen_machine.
53 (mipsisa64*-*-*): Likewise. Remove dsp.
54 (mipsisa32*-*-*): Remove dsp.
55 * configure: Regenerate.
57 2007-02-13 Thiemo Seufer <ths@mips.com>
59 * configure.ac: Add mips*-sde-elf* target.
60 * configure: Regenerate.
62 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
65 * config.in, configure: Regenerate.
67 2006-11-07 Thiemo Seufer <ths@mips.com>
69 * dsp.igen (do_w_op): Fix compiler warning.
71 2006-08-29 Thiemo Seufer <ths@mips.com>
72 David Ung <davidu@mips.com>
74 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
76 * configure: Regenerate.
77 * mips.igen (model): Add smartmips.
78 (MADDU): Increment ACX if carry.
80 (ROR,RORV): Add smartmips.
81 (include): Include smartmips.igen.
82 * sim-main.h (ACX): Set to REGISTERS[89].
83 * smartmips.igen: New file.
85 2006-08-29 Thiemo Seufer <ths@mips.com>
86 David Ung <davidu@mips.com>
88 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
89 mips3264r2.igen. Add missing dependency rules.
90 * m16e.igen: Support for mips16e save/restore instructions.
92 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
94 * configure: Regenerated.
96 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
98 * configure: Regenerated.
100 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
102 * configure: Regenerated.
104 2006-05-15 Chao-ying Fu <fu@mips.com>
106 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
108 2006-04-18 Nick Clifton <nickc@redhat.com>
110 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
113 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
115 * configure: Regenerate.
117 2005-12-14 Chao-ying Fu <fu@mips.com>
119 * Makefile.in (SIM_OBJS): Add dsp.o.
120 (dsp.o): New dependency.
121 (IGEN_INCLUDE): Add dsp.igen.
122 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
123 mipsisa64*-*-*): Add dsp to sim_igen_machine.
124 * configure: Regenerate.
125 * mips.igen: Add dsp model and include dsp.igen.
126 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
127 because these instructions are extended in DSP ASE.
128 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
129 adding 6 DSP accumulator registers and 1 DSP control register.
130 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
131 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
132 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
133 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
134 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
135 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
136 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
137 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
138 DSPCR_CCOND_SMASK): New define.
139 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
140 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
142 2005-07-08 Ian Lance Taylor <ian@airs.com>
144 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
146 2005-06-16 David Ung <davidu@mips.com>
147 Nigel Stephens <nigel@mips.com>
149 * mips.igen: New mips16e model and include m16e.igen.
150 (check_u64): Add mips16e tag.
151 * m16e.igen: New file for MIPS16e instructions.
152 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
153 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
155 * configure: Regenerate.
157 2005-05-26 David Ung <davidu@mips.com>
159 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
160 tags to all instructions which are applicable to the new ISAs.
161 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
163 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
165 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
167 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
168 * configure: Regenerate.
170 2005-03-23 Mark Kettenis <kettenis@gnu.org>
172 * configure: Regenerate.
174 2005-01-14 Andrew Cagney <cagney@gnu.org>
176 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
177 explicit call to AC_CONFIG_HEADER.
178 * configure: Regenerate.
180 2005-01-12 Andrew Cagney <cagney@gnu.org>
182 * configure.ac: Update to use ../common/common.m4.
183 * configure: Re-generate.
185 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
187 * configure: Regenerated to track ../common/aclocal.m4 changes.
189 2005-01-07 Andrew Cagney <cagney@gnu.org>
191 * configure.ac: Rename configure.in, require autoconf 2.59.
192 * configure: Re-generate.
194 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
196 * configure: Regenerate for ../common/aclocal.m4 update.
198 2004-09-24 Monika Chaddha <monika@acmet.com>
200 Committed by Andrew Cagney.
201 * m16.igen (CMP, CMPI): Fix assembler.
203 2004-08-18 Chris Demetriou <cgd@broadcom.com>
205 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
206 * configure: Regenerate.
208 2004-06-25 Chris Demetriou <cgd@broadcom.com>
210 * configure.in (sim_m16_machine): Include mipsIII.
211 * configure: Regenerate.
213 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
215 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
217 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
219 2004-04-10 Chris Demetriou <cgd@broadcom.com>
221 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
223 2004-04-09 Chris Demetriou <cgd@broadcom.com>
225 * mips.igen (check_fmt): Remove.
226 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
227 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
228 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
229 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
230 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
231 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
232 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
233 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
234 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
235 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
237 2004-04-09 Chris Demetriou <cgd@broadcom.com>
239 * sb1.igen (check_sbx): New function.
240 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
242 2004-03-29 Chris Demetriou <cgd@broadcom.com>
243 Richard Sandiford <rsandifo@redhat.com>
245 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
246 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
247 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
248 separate implementations for mipsIV and mipsV. Use new macros to
249 determine whether the restrictions apply.
251 2004-01-19 Chris Demetriou <cgd@broadcom.com>
253 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
254 (check_mult_hilo): Improve comments.
255 (check_div_hilo): Likewise. Also, fork off a new version
256 to handle mips32/mips64 (since there are no hazards to check
259 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
261 * mips.igen (do_dmultx): Fix check for negative operands.
263 2003-05-16 Ian Lance Taylor <ian@airs.com>
265 * Makefile.in (SHELL): Make sure this is defined.
266 (various): Use $(SHELL) whenever we invoke move-if-change.
268 2003-05-03 Chris Demetriou <cgd@broadcom.com>
270 * cp1.c: Tweak attribution slightly.
273 * mdmx.igen: Likewise.
274 * mips3d.igen: Likewise.
275 * sb1.igen: Likewise.
277 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
279 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
282 2003-02-27 Andrew Cagney <cagney@redhat.com>
284 * interp.c (sim_open): Rename _bfd to bfd.
285 (sim_create_inferior): Ditto.
287 2003-01-14 Chris Demetriou <cgd@broadcom.com>
289 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
291 2003-01-14 Chris Demetriou <cgd@broadcom.com>
293 * mips.igen (EI, DI): Remove.
295 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
297 * Makefile.in (tmp-run-multi): Fix mips16 filter.
299 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
300 Andrew Cagney <ac131313@redhat.com>
301 Gavin Romig-Koch <gavin@redhat.com>
302 Graydon Hoare <graydon@redhat.com>
303 Aldy Hernandez <aldyh@redhat.com>
304 Dave Brolley <brolley@redhat.com>
305 Chris Demetriou <cgd@broadcom.com>
307 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
308 (sim_mach_default): New variable.
309 (mips64vr-*-*, mips64vrel-*-*): New configurations.
310 Add a new simulator generator, MULTI.
311 * configure: Regenerate.
312 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
313 (multi-run.o): New dependency.
314 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
315 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
316 (tmp-multi): Combine them.
317 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
318 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
319 (distclean-extra): New rule.
320 * sim-main.h: Include bfd.h.
321 (MIPS_MACH): New macro.
322 * mips.igen (vr4120, vr5400, vr5500): New models.
323 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
324 * vr.igen: Replace with new version.
326 2003-01-04 Chris Demetriou <cgd@broadcom.com>
328 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
329 * configure: Regenerate.
331 2002-12-31 Chris Demetriou <cgd@broadcom.com>
333 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
334 * mips.igen: Remove all invocations of check_branch_bug and
337 2002-12-16 Chris Demetriou <cgd@broadcom.com>
339 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
341 2002-07-30 Chris Demetriou <cgd@broadcom.com>
343 * mips.igen (do_load_double, do_store_double): New functions.
344 (LDC1, SDC1): Rename to...
345 (LDC1b, SDC1b): respectively.
346 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
348 2002-07-29 Michael Snyder <msnyder@redhat.com>
350 * cp1.c (fp_recip2): Modify initialization expression so that
351 GCC will recognize it as constant.
353 2002-06-18 Chris Demetriou <cgd@broadcom.com>
355 * mdmx.c (SD_): Delete.
356 (Unpredictable): Re-define, for now, to directly invoke
357 unpredictable_action().
358 (mdmx_acc_op): Fix error in .ob immediate handling.
360 2002-06-18 Andrew Cagney <cagney@redhat.com>
362 * interp.c (sim_firmware_command): Initialize `address'.
364 2002-06-16 Andrew Cagney <ac131313@redhat.com>
366 * configure: Regenerated to track ../common/aclocal.m4 changes.
368 2002-06-14 Chris Demetriou <cgd@broadcom.com>
369 Ed Satterthwaite <ehs@broadcom.com>
371 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
372 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
373 * mips.igen: Include mips3d.igen.
374 (mips3d): New model name for MIPS-3D ASE instructions.
375 (CVT.W.fmt): Don't use this instruction for word (source) format
377 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
378 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
379 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
380 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
381 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
382 (RSquareRoot1, RSquareRoot2): New macros.
383 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
384 (fp_rsqrt2): New functions.
385 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
386 * configure: Regenerate.
388 2002-06-13 Chris Demetriou <cgd@broadcom.com>
389 Ed Satterthwaite <ehs@broadcom.com>
391 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
392 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
393 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
394 (convert): Note that this function is not used for paired-single
396 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
397 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
398 (check_fmt_p): Enable paired-single support.
399 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
400 (PUU.PS): New instructions.
401 (CVT.S.fmt): Don't use this instruction for paired-single format
403 * sim-main.h (FP_formats): New value 'fmt_ps.'
404 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
405 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
407 2002-06-12 Chris Demetriou <cgd@broadcom.com>
409 * mips.igen: Fix formatting of function calls in
412 2002-06-12 Chris Demetriou <cgd@broadcom.com>
414 * mips.igen (MOVN, MOVZ): Trace result.
415 (TNEI): Print "tnei" as the opcode name in traces.
416 (CEIL.W): Add disassembly string for traces.
417 (RSQRT.fmt): Make location of disassembly string consistent
418 with other instructions.
420 2002-06-12 Chris Demetriou <cgd@broadcom.com>
422 * mips.igen (X): Delete unused function.
424 2002-06-08 Andrew Cagney <cagney@redhat.com>
426 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
428 2002-06-07 Chris Demetriou <cgd@broadcom.com>
429 Ed Satterthwaite <ehs@broadcom.com>
431 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
432 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
433 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
434 (fp_nmsub): New prototypes.
435 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
436 (NegMultiplySub): New defines.
437 * mips.igen (RSQRT.fmt): Use RSquareRoot().
438 (MADD.D, MADD.S): Replace with...
439 (MADD.fmt): New instruction.
440 (MSUB.D, MSUB.S): Replace with...
441 (MSUB.fmt): New instruction.
442 (NMADD.D, NMADD.S): Replace with...
443 (NMADD.fmt): New instruction.
444 (NMSUB.D, MSUB.S): Replace with...
445 (NMSUB.fmt): New instruction.
447 2002-06-07 Chris Demetriou <cgd@broadcom.com>
448 Ed Satterthwaite <ehs@broadcom.com>
450 * cp1.c: Fix more comment spelling and formatting.
451 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
452 (denorm_mode): New function.
453 (fpu_unary, fpu_binary): Round results after operation, collect
454 status from rounding operations, and update the FCSR.
455 (convert): Collect status from integer conversions and rounding
456 operations, and update the FCSR. Adjust NaN values that result
457 from conversions. Convert to use sim_io_eprintf rather than
458 fprintf, and remove some debugging code.
459 * cp1.h (fenr_FS): New define.
461 2002-06-07 Chris Demetriou <cgd@broadcom.com>
463 * cp1.c (convert): Remove unusable debugging code, and move MIPS
464 rounding mode to sim FP rounding mode flag conversion code into...
465 (rounding_mode): New function.
467 2002-06-07 Chris Demetriou <cgd@broadcom.com>
469 * cp1.c: Clean up formatting of a few comments.
470 (value_fpr): Reformat switch statement.
472 2002-06-06 Chris Demetriou <cgd@broadcom.com>
473 Ed Satterthwaite <ehs@broadcom.com>
476 * sim-main.h: Include cp1.h.
477 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
478 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
479 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
480 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
481 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
482 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
483 * cp1.c: Don't include sim-fpu.h; already included by
484 sim-main.h. Clean up formatting of some comments.
485 (NaN, Equal, Less): Remove.
486 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
487 (fp_cmp): New functions.
488 * mips.igen (do_c_cond_fmt): Remove.
489 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
490 Compare. Add result tracing.
491 (CxC1): Remove, replace with...
492 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
493 (DMxC1): Remove, replace with...
494 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
495 (MxC1): Remove, replace with...
496 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
498 2002-06-04 Chris Demetriou <cgd@broadcom.com>
500 * sim-main.h (FGRIDX): Remove, replace all uses with...
501 (FGR_BASE): New macro.
502 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
503 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
504 (NR_FGR, FGR): Likewise.
505 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
506 * mips.igen: Likewise.
508 2002-06-04 Chris Demetriou <cgd@broadcom.com>
510 * cp1.c: Add an FSF Copyright notice to this file.
512 2002-06-04 Chris Demetriou <cgd@broadcom.com>
513 Ed Satterthwaite <ehs@broadcom.com>
515 * cp1.c (Infinity): Remove.
516 * sim-main.h (Infinity): Likewise.
518 * cp1.c (fp_unary, fp_binary): New functions.
519 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
520 (fp_sqrt): New functions, implemented in terms of the above.
521 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
522 (Recip, SquareRoot): Remove (replaced by functions above).
523 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
524 (fp_recip, fp_sqrt): New prototypes.
525 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
526 (Recip, SquareRoot): Replace prototypes with #defines which
527 invoke the functions above.
529 2002-06-03 Chris Demetriou <cgd@broadcom.com>
531 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
532 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
533 file, remove PARAMS from prototypes.
534 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
535 simulator state arguments.
536 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
537 pass simulator state arguments.
538 * cp1.c (SD): Redefine as CPU_STATE(cpu).
539 (store_fpr, convert): Remove 'sd' argument.
540 (value_fpr): Likewise. Convert to use 'SD' instead.
542 2002-06-03 Chris Demetriou <cgd@broadcom.com>
544 * cp1.c (Min, Max): Remove #if 0'd functions.
545 * sim-main.h (Min, Max): Remove.
547 2002-06-03 Chris Demetriou <cgd@broadcom.com>
549 * cp1.c: fix formatting of switch case and default labels.
550 * interp.c: Likewise.
551 * sim-main.c: Likewise.
553 2002-06-03 Chris Demetriou <cgd@broadcom.com>
555 * cp1.c: Clean up comments which describe FP formats.
556 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
558 2002-06-03 Chris Demetriou <cgd@broadcom.com>
559 Ed Satterthwaite <ehs@broadcom.com>
561 * configure.in (mipsisa64sb1*-*-*): New target for supporting
562 Broadcom SiByte SB-1 processor configurations.
563 * configure: Regenerate.
564 * sb1.igen: New file.
565 * mips.igen: Include sb1.igen.
567 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
568 * mdmx.igen: Add "sb1" model to all appropriate functions and
570 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
571 (ob_func, ob_acc): Reference the above.
572 (qh_acc): Adjust to keep the same size as ob_acc.
573 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
574 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
576 2002-06-03 Chris Demetriou <cgd@broadcom.com>
578 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
580 2002-06-02 Chris Demetriou <cgd@broadcom.com>
581 Ed Satterthwaite <ehs@broadcom.com>
583 * mips.igen (mdmx): New (pseudo-)model.
584 * mdmx.c, mdmx.igen: New files.
585 * Makefile.in (SIM_OBJS): Add mdmx.o.
586 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
588 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
589 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
590 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
591 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
592 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
593 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
594 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
595 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
596 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
597 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
598 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
599 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
600 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
601 (qh_fmtsel): New macros.
602 (_sim_cpu): New member "acc".
603 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
604 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
606 2002-05-01 Chris Demetriou <cgd@broadcom.com>
608 * interp.c: Use 'deprecated' rather than 'depreciated.'
609 * sim-main.h: Likewise.
611 2002-05-01 Chris Demetriou <cgd@broadcom.com>
613 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
614 which wouldn't compile anyway.
615 * sim-main.h (unpredictable_action): New function prototype.
616 (Unpredictable): Define to call igen function unpredictable().
617 (NotWordValue): New macro to call igen function not_word_value().
618 (UndefinedResult): Remove.
619 * interp.c (undefined_result): Remove.
620 (unpredictable_action): New function.
621 * mips.igen (not_word_value, unpredictable): New functions.
622 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
623 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
624 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
625 NotWordValue() to check for unpredictable inputs, then
626 Unpredictable() to handle them.
628 2002-02-24 Chris Demetriou <cgd@broadcom.com>
630 * mips.igen: Fix formatting of calls to Unpredictable().
632 2002-04-20 Andrew Cagney <ac131313@redhat.com>
634 * interp.c (sim_open): Revert previous change.
636 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
638 * interp.c (sim_open): Disable chunk of code that wrote code in
639 vector table entries.
641 2002-03-19 Chris Demetriou <cgd@broadcom.com>
643 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
644 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
647 2002-03-19 Chris Demetriou <cgd@broadcom.com>
649 * cp1.c: Fix many formatting issues.
651 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
653 * cp1.c (fpu_format_name): New function to replace...
654 (DOFMT): This. Delete, and update all callers.
655 (fpu_rounding_mode_name): New function to replace...
656 (RMMODE): This. Delete, and update all callers.
658 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
660 * interp.c: Move FPU support routines from here to...
661 * cp1.c: Here. New file.
662 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
665 2002-03-12 Chris Demetriou <cgd@broadcom.com>
667 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
668 * mips.igen (mips32, mips64): New models, add to all instructions
669 and functions as appropriate.
670 (loadstore_ea, check_u64): New variant for model mips64.
671 (check_fmt_p): New variant for models mipsV and mips64, remove
672 mipsV model marking fro other variant.
675 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
676 for mips32 and mips64.
677 (DCLO, DCLZ): New instructions for mips64.
679 2002-03-07 Chris Demetriou <cgd@broadcom.com>
681 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
682 immediate or code as a hex value with the "%#lx" format.
683 (ANDI): Likewise, and fix printed instruction name.
685 2002-03-05 Chris Demetriou <cgd@broadcom.com>
687 * sim-main.h (UndefinedResult, Unpredictable): New macros
688 which currently do nothing.
690 2002-03-05 Chris Demetriou <cgd@broadcom.com>
692 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
693 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
694 (status_CU3): New definitions.
696 * sim-main.h (ExceptionCause): Add new values for MIPS32
697 and MIPS64: MDMX, MCheck, CacheErr. Update comments
698 for DebugBreakPoint and NMIReset to note their status in
700 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
701 (SignalExceptionCacheErr): New exception macros.
703 2002-03-05 Chris Demetriou <cgd@broadcom.com>
705 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
706 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
708 (SignalExceptionCoProcessorUnusable): Take as argument the
709 unusable coprocessor number.
711 2002-03-05 Chris Demetriou <cgd@broadcom.com>
713 * mips.igen: Fix formatting of all SignalException calls.
715 2002-03-05 Chris Demetriou <cgd@broadcom.com>
717 * sim-main.h (SIGNEXTEND): Remove.
719 2002-03-04 Chris Demetriou <cgd@broadcom.com>
721 * mips.igen: Remove gencode comment from top of file, fix
722 spelling in another comment.
724 2002-03-04 Chris Demetriou <cgd@broadcom.com>
726 * mips.igen (check_fmt, check_fmt_p): New functions to check
727 whether specific floating point formats are usable.
728 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
729 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
730 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
731 Use the new functions.
732 (do_c_cond_fmt): Remove format checks...
733 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
735 2002-03-03 Chris Demetriou <cgd@broadcom.com>
737 * mips.igen: Fix formatting of check_fpu calls.
739 2002-03-03 Chris Demetriou <cgd@broadcom.com>
741 * mips.igen (FLOOR.L.fmt): Store correct destination register.
743 2002-03-03 Chris Demetriou <cgd@broadcom.com>
745 * mips.igen: Remove whitespace at end of lines.
747 2002-03-02 Chris Demetriou <cgd@broadcom.com>
749 * mips.igen (loadstore_ea): New function to do effective
750 address calculations.
751 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
752 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
753 CACHE): Use loadstore_ea to do effective address computations.
755 2002-03-02 Chris Demetriou <cgd@broadcom.com>
757 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
758 * mips.igen (LL, CxC1, MxC1): Likewise.
760 2002-03-02 Chris Demetriou <cgd@broadcom.com>
762 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
763 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
764 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
765 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
766 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
767 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
768 Don't split opcode fields by hand, use the opcode field values
771 2002-03-01 Chris Demetriou <cgd@broadcom.com>
773 * mips.igen (do_divu): Fix spacing.
775 * mips.igen (do_dsllv): Move to be right before DSLLV,
776 to match the rest of the do_<shift> functions.
778 2002-03-01 Chris Demetriou <cgd@broadcom.com>
780 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
781 DSRL32, do_dsrlv): Trace inputs and results.
783 2002-03-01 Chris Demetriou <cgd@broadcom.com>
785 * mips.igen (CACHE): Provide instruction-printing string.
787 * interp.c (signal_exception): Comment tokens after #endif.
789 2002-02-28 Chris Demetriou <cgd@broadcom.com>
791 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
792 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
793 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
794 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
795 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
796 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
797 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
798 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
800 2002-02-28 Chris Demetriou <cgd@broadcom.com>
802 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
803 instruction-printing string.
804 (LWU): Use '64' as the filter flag.
806 2002-02-28 Chris Demetriou <cgd@broadcom.com>
808 * mips.igen (SDXC1): Fix instruction-printing string.
810 2002-02-28 Chris Demetriou <cgd@broadcom.com>
812 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
815 2002-02-27 Chris Demetriou <cgd@broadcom.com>
817 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
820 2002-02-27 Chris Demetriou <cgd@broadcom.com>
822 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
823 add a comma) so that it more closely match the MIPS ISA
824 documentation opcode partitioning.
825 (PREF): Put useful names on opcode fields, and include
826 instruction-printing string.
828 2002-02-27 Chris Demetriou <cgd@broadcom.com>
830 * mips.igen (check_u64): New function which in the future will
831 check whether 64-bit instructions are usable and signal an
832 exception if not. Currently a no-op.
833 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
834 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
835 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
836 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
838 * mips.igen (check_fpu): New function which in the future will
839 check whether FPU instructions are usable and signal an exception
840 if not. Currently a no-op.
841 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
842 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
843 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
844 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
845 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
846 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
847 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
848 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
850 2002-02-27 Chris Demetriou <cgd@broadcom.com>
852 * mips.igen (do_load_left, do_load_right): Move to be immediately
854 (do_store_left, do_store_right): Move to be immediately following
857 2002-02-27 Chris Demetriou <cgd@broadcom.com>
859 * mips.igen (mipsV): New model name. Also, add it to
860 all instructions and functions where it is appropriate.
862 2002-02-18 Chris Demetriou <cgd@broadcom.com>
864 * mips.igen: For all functions and instructions, list model
865 names that support that instruction one per line.
867 2002-02-11 Chris Demetriou <cgd@broadcom.com>
869 * mips.igen: Add some additional comments about supported
870 models, and about which instructions go where.
871 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
872 order as is used in the rest of the file.
874 2002-02-11 Chris Demetriou <cgd@broadcom.com>
876 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
877 indicating that ALU32_END or ALU64_END are there to check
879 (DADD): Likewise, but also remove previous comment about
882 2002-02-10 Chris Demetriou <cgd@broadcom.com>
884 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
885 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
886 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
887 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
888 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
889 fields (i.e., add and move commas) so that they more closely
890 match the MIPS ISA documentation opcode partitioning.
892 2002-02-10 Chris Demetriou <cgd@broadcom.com>
894 * mips.igen (ADDI): Print immediate value.
896 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
897 (SLL): Print "nop" specially, and don't run the code
898 that does the shift for the "nop" case.
900 2001-11-17 Fred Fish <fnf@redhat.com>
902 * sim-main.h (float_operation): Move enum declaration outside
903 of _sim_cpu struct declaration.
905 2001-04-12 Jim Blandy <jimb@redhat.com>
907 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
908 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
910 * sim-main.h (COCIDX): Remove definition; this isn't supported by
911 PENDING_FILL, and you can get the intended effect gracefully by
912 calling PENDING_SCHED directly.
914 2001-02-23 Ben Elliston <bje@redhat.com>
916 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
917 already defined elsewhere.
919 2001-02-19 Ben Elliston <bje@redhat.com>
921 * sim-main.h (sim_monitor): Return an int.
922 * interp.c (sim_monitor): Add return values.
923 (signal_exception): Handle error conditions from sim_monitor.
925 2001-02-08 Ben Elliston <bje@redhat.com>
927 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
928 (store_memory): Likewise, pass cia to sim_core_write*.
930 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
932 On advice from Chris G. Demetriou <cgd@sibyte.com>:
933 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
935 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
937 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
938 * Makefile.in: Don't delete *.igen when cleaning directory.
940 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
942 * m16.igen (break): Call SignalException not sim_engine_halt.
944 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
947 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
949 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
951 * mips.igen (MxC1, DMxC1): Fix printf formatting.
953 2000-05-24 Michael Hayes <mhayes@cygnus.com>
955 * mips.igen (do_dmultx): Fix typo.
957 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
959 * configure: Regenerated to track ../common/aclocal.m4 changes.
961 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
963 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
965 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
967 * sim-main.h (GPR_CLEAR): Define macro.
969 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
971 * interp.c (decode_coproc): Output long using %lx and not %s.
973 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
975 * interp.c (sim_open): Sort & extend dummy memory regions for
976 --board=jmr3904 for eCos.
978 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
980 * configure: Regenerated.
982 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
984 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
985 calls, conditional on the simulator being in verbose mode.
987 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
989 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
990 cache don't get ReservedInstruction traps.
992 1999-11-29 Mark Salter <msalter@cygnus.com>
994 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
995 to clear status bits in sdisr register. This is how the hardware works.
997 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
998 being used by cygmon.
1000 1999-11-11 Andrew Haley <aph@cygnus.com>
1002 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1005 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1007 * mips.igen (MULT): Correct previous mis-applied patch.
1009 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1011 * mips.igen (delayslot32): Handle sequence like
1012 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1013 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1014 (MULT): Actually pass the third register...
1016 1999-09-03 Mark Salter <msalter@cygnus.com>
1018 * interp.c (sim_open): Added more memory aliases for additional
1019 hardware being touched by cygmon on jmr3904 board.
1021 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1023 * configure: Regenerated to track ../common/aclocal.m4 changes.
1025 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1027 * interp.c (sim_store_register): Handle case where client - GDB -
1028 specifies that a 4 byte register is 8 bytes in size.
1029 (sim_fetch_register): Ditto.
1031 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1033 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1034 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1035 (idt_monitor_base): Base address for IDT monitor traps.
1036 (pmon_monitor_base): Ditto for PMON.
1037 (lsipmon_monitor_base): Ditto for LSI PMON.
1038 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1039 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1040 (sim_firmware_command): New function.
1041 (mips_option_handler): Call it for OPTION_FIRMWARE.
1042 (sim_open): Allocate memory for idt_monitor region. If "--board"
1043 option was given, add no monitor by default. Add BREAK hooks only if
1044 monitors are also there.
1046 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1048 * interp.c (sim_monitor): Flush output before reading input.
1050 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1052 * tconfig.in (SIM_HANDLES_LMA): Always define.
1054 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1056 From Mark Salter <msalter@cygnus.com>:
1057 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1058 (sim_open): Add setup for BSP board.
1060 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1062 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1063 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1064 them as unimplemented.
1066 1999-05-08 Felix Lee <flee@cygnus.com>
1068 * configure: Regenerated to track ../common/aclocal.m4 changes.
1070 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1072 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1074 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1076 * configure.in: Any mips64vr5*-*-* target should have
1077 -DTARGET_ENABLE_FR=1.
1078 (default_endian): Any mips64vr*el-*-* target should default to
1080 * configure: Re-generate.
1082 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1084 * mips.igen (ldl): Extend from _16_, not 32.
1086 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1088 * interp.c (sim_store_register): Force registers written to by GDB
1089 into an un-interpreted state.
1091 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1093 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1094 CPU, start periodic background I/O polls.
1095 (tx3904sio_poll): New function: periodic I/O poller.
1097 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1099 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1101 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1103 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1106 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1108 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1109 (load_word): Call SIM_CORE_SIGNAL hook on error.
1110 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1111 starting. For exception dispatching, pass PC instead of NULL_CIA.
1112 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1113 * sim-main.h (COP0_BADVADDR): Define.
1114 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1115 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1116 (_sim_cpu): Add exc_* fields to store register value snapshots.
1117 * mips.igen (*): Replace memory-related SignalException* calls
1118 with references to SIM_CORE_SIGNAL hook.
1120 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1122 * sim-main.c (*): Minor warning cleanups.
1124 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1126 * m16.igen (DADDIU5): Correct type-o.
1128 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1130 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1133 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1135 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1137 (interp.o): Add dependency on itable.h
1138 (oengine.c, gencode): Delete remaining references.
1139 (BUILT_SRC_FROM_GEN): Clean up.
1141 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1144 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1145 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1146 tmp-run-hack) : New.
1147 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1148 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1149 Drop the "64" qualifier to get the HACK generator working.
1150 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1151 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1152 qualifier to get the hack generator working.
1153 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1154 (DSLL): Use do_dsll.
1155 (DSLLV): Use do_dsllv.
1156 (DSRA): Use do_dsra.
1157 (DSRL): Use do_dsrl.
1158 (DSRLV): Use do_dsrlv.
1159 (BC1): Move *vr4100 to get the HACK generator working.
1160 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1161 get the HACK generator working.
1162 (MACC) Rename to get the HACK generator working.
1163 (DMACC,MACCS,DMACCS): Add the 64.
1165 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1167 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1168 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1170 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1172 * mips/interp.c (DEBUG): Cleanups.
1174 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1176 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1177 (tx3904sio_tickle): fflush after a stdout character output.
1179 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1181 * interp.c (sim_close): Uninstall modules.
1183 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1185 * sim-main.h, interp.c (sim_monitor): Change to global
1188 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1190 * configure.in (vr4100): Only include vr4100 instructions in
1192 * configure: Re-generate.
1193 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1195 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1197 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1198 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1201 * configure.in (sim_default_gen, sim_use_gen): Replace with
1203 (--enable-sim-igen): Delete config option. Always using IGEN.
1204 * configure: Re-generate.
1206 * Makefile.in (gencode): Kill, kill, kill.
1209 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1211 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1212 bit mips16 igen simulator.
1213 * configure: Re-generate.
1215 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1216 as part of vr4100 ISA.
1217 * vr.igen: Mark all instructions as 64 bit only.
1219 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1221 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1224 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1226 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1227 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1228 * configure: Re-generate.
1230 * m16.igen (BREAK): Define breakpoint instruction.
1231 (JALX32): Mark instruction as mips16 and not r3900.
1232 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1234 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1236 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1238 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1239 insn as a debug breakpoint.
1241 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1243 (PENDING_SCHED): Clean up trace statement.
1244 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1245 (PENDING_FILL): Delay write by only one cycle.
1246 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1248 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1250 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1252 (pending_tick): Move incrementing of index to FOR statement.
1253 (pending_tick): Only update PENDING_OUT after a write has occured.
1255 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1257 * configure: Re-generate.
1259 * interp.c (sim_engine_run OLD): Delete explicit call to
1260 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1262 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1264 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1265 interrupt level number to match changed SignalExceptionInterrupt
1268 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1270 * interp.c: #include "itable.h" if WITH_IGEN.
1271 (get_insn_name): New function.
1272 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1273 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1275 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1277 * configure: Rebuilt to inhale new common/aclocal.m4.
1279 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1281 * dv-tx3904sio.c: Include sim-assert.h.
1283 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1285 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1286 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1287 Reorganize target-specific sim-hardware checks.
1288 * configure: rebuilt.
1289 * interp.c (sim_open): For tx39 target boards, set
1290 OPERATING_ENVIRONMENT, add tx3904sio devices.
1291 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1292 ROM executables. Install dv-sockser into sim-modules list.
1294 * dv-tx3904irc.c: Compiler warning clean-up.
1295 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1296 frequent hw-trace messages.
1298 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1300 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1302 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1304 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1306 * vr.igen: New file.
1307 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1308 * mips.igen: Define vr4100 model. Include vr.igen.
1309 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1311 * mips.igen (check_mf_hilo): Correct check.
1313 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1315 * sim-main.h (interrupt_event): Add prototype.
1317 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1318 register_ptr, register_value.
1319 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1321 * sim-main.h (tracefh): Make extern.
1323 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1325 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1326 Reduce unnecessarily high timer event frequency.
1327 * dv-tx3904cpu.c: Ditto for interrupt event.
1329 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1331 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1333 (interrupt_event): Made non-static.
1335 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1336 interchange of configuration values for external vs. internal
1339 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1341 * mips.igen (BREAK): Moved code to here for
1342 simulator-reserved break instructions.
1343 * gencode.c (build_instruction): Ditto.
1344 * interp.c (signal_exception): Code moved from here. Non-
1345 reserved instructions now use exception vector, rather
1347 * sim-main.h: Moved magic constants to here.
1349 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1351 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1352 register upon non-zero interrupt event level, clear upon zero
1354 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1355 by passing zero event value.
1356 (*_io_{read,write}_buffer): Endianness fixes.
1357 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1358 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1360 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1361 serial I/O and timer module at base address 0xFFFF0000.
1363 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1365 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1368 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1370 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1372 * configure: Update.
1374 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1376 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1377 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1378 * configure.in: Include tx3904tmr in hw_device list.
1379 * configure: Rebuilt.
1380 * interp.c (sim_open): Instantiate three timer instances.
1381 Fix address typo of tx3904irc instance.
1383 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1385 * interp.c (signal_exception): SystemCall exception now uses
1386 the exception vector.
1388 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1390 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1393 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1395 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1397 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1399 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1401 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1402 sim-main.h. Declare a struct hw_descriptor instead of struct
1403 hw_device_descriptor.
1405 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1407 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1408 right bits and then re-align left hand bytes to correct byte
1409 lanes. Fix incorrect computation in do_store_left when loading
1410 bytes from second word.
1412 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1414 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1415 * interp.c (sim_open): Only create a device tree when HW is
1418 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1419 * interp.c (signal_exception): Ditto.
1421 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1423 * gencode.c: Mark BEGEZALL as LIKELY.
1425 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1427 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1428 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1430 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1432 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1433 modules. Recognize TX39 target with "mips*tx39" pattern.
1434 * configure: Rebuilt.
1435 * sim-main.h (*): Added many macros defining bits in
1436 TX39 control registers.
1437 (SignalInterrupt): Send actual PC instead of NULL.
1438 (SignalNMIReset): New exception type.
1439 * interp.c (board): New variable for future use to identify
1440 a particular board being simulated.
1441 (mips_option_handler,mips_options): Added "--board" option.
1442 (interrupt_event): Send actual PC.
1443 (sim_open): Make memory layout conditional on board setting.
1444 (signal_exception): Initial implementation of hardware interrupt
1445 handling. Accept another break instruction variant for simulator
1447 (decode_coproc): Implement RFE instruction for TX39.
1448 (mips.igen): Decode RFE instruction as such.
1449 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1450 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1451 bbegin to implement memory map.
1452 * dv-tx3904cpu.c: New file.
1453 * dv-tx3904irc.c: New file.
1455 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1457 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1459 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1461 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1462 with calls to check_div_hilo.
1464 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1466 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1467 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1468 Add special r3900 version of do_mult_hilo.
1469 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1470 with calls to check_mult_hilo.
1471 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1472 with calls to check_div_hilo.
1474 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1476 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1477 Document a replacement.
1479 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1481 * interp.c (sim_monitor): Make mon_printf work.
1483 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1485 * sim-main.h (INSN_NAME): New arg `cpu'.
1487 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1489 * configure: Regenerated to track ../common/aclocal.m4 changes.
1491 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1493 * configure: Regenerated to track ../common/aclocal.m4 changes.
1496 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1498 * acconfig.h: New file.
1499 * configure.in: Reverted change of Apr 24; use sinclude again.
1501 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1503 * configure: Regenerated to track ../common/aclocal.m4 changes.
1506 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1508 * configure.in: Don't call sinclude.
1510 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1512 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1514 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1516 * mips.igen (ERET): Implement.
1518 * interp.c (decode_coproc): Return sign-extended EPC.
1520 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1522 * interp.c (signal_exception): Do not ignore Trap.
1523 (signal_exception): On TRAP, restart at exception address.
1524 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1525 (signal_exception): Update.
1526 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1527 so that TRAP instructions are caught.
1529 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1531 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1532 contains HI/LO access history.
1533 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1534 (HIACCESS, LOACCESS): Delete, replace with
1535 (HIHISTORY, LOHISTORY): New macros.
1536 (CHECKHILO): Delete all, moved to mips.igen
1538 * gencode.c (build_instruction): Do not generate checks for
1539 correct HI/LO register usage.
1541 * interp.c (old_engine_run): Delete checks for correct HI/LO
1544 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1545 check_mf_cycles): New functions.
1546 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1547 do_divu, domultx, do_mult, do_multu): Use.
1549 * tx.igen ("madd", "maddu"): Use.
1551 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1553 * mips.igen (DSRAV): Use function do_dsrav.
1554 (SRAV): Use new function do_srav.
1556 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1557 (B): Sign extend 11 bit immediate.
1558 (EXT-B*): Shift 16 bit immediate left by 1.
1559 (ADDIU*): Don't sign extend immediate value.
1561 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1563 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1565 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1568 * mips.igen (delayslot32, nullify_next_insn): New functions.
1569 (m16.igen): Always include.
1570 (do_*): Add more tracing.
1572 * m16.igen (delayslot16): Add NIA argument, could be called by a
1573 32 bit MIPS16 instruction.
1575 * interp.c (ifetch16): Move function from here.
1576 * sim-main.c (ifetch16): To here.
1578 * sim-main.c (ifetch16, ifetch32): Update to match current
1579 implementations of LH, LW.
1580 (signal_exception): Don't print out incorrect hex value of illegal
1583 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1585 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1588 * m16.igen: Implement MIPS16 instructions.
1590 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1591 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1592 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1593 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1594 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1595 bodies of corresponding code from 32 bit insn to these. Also used
1596 by MIPS16 versions of functions.
1598 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1599 (IMEM16): Drop NR argument from macro.
1601 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1603 * Makefile.in (SIM_OBJS): Add sim-main.o.
1605 * sim-main.h (address_translation, load_memory, store_memory,
1606 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1608 (pr_addr, pr_uword64): Declare.
1609 (sim-main.c): Include when H_REVEALS_MODULE_P.
1611 * interp.c (address_translation, load_memory, store_memory,
1612 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1614 * sim-main.c: To here. Fix compilation problems.
1616 * configure.in: Enable inlining.
1617 * configure: Re-config.
1619 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1621 * configure: Regenerated to track ../common/aclocal.m4 changes.
1623 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1625 * mips.igen: Include tx.igen.
1626 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1627 * tx.igen: New file, contains MADD and MADDU.
1629 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1630 the hardwired constant `7'.
1631 (store_memory): Ditto.
1632 (LOADDRMASK): Move definition to sim-main.h.
1634 mips.igen (MTC0): Enable for r3900.
1637 mips.igen (do_load_byte): Delete.
1638 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1639 do_store_right): New functions.
1640 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1642 configure.in: Let the tx39 use igen again.
1645 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1647 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1648 not an address sized quantity. Return zero for cache sizes.
1650 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1652 * mips.igen (r3900): r3900 does not support 64 bit integer
1655 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1657 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1659 * configure : Rebuild.
1661 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1663 * configure: Regenerated to track ../common/aclocal.m4 changes.
1665 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1667 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1669 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1671 * configure: Regenerated to track ../common/aclocal.m4 changes.
1672 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1674 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1676 * configure: Regenerated to track ../common/aclocal.m4 changes.
1678 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1680 * interp.c (Max, Min): Comment out functions. Not yet used.
1682 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1684 * configure: Regenerated to track ../common/aclocal.m4 changes.
1686 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1688 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1689 configurable settings for stand-alone simulator.
1691 * configure.in: Added X11 search, just in case.
1693 * configure: Regenerated.
1695 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1697 * interp.c (sim_write, sim_read, load_memory, store_memory):
1698 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1700 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1702 * sim-main.h (GETFCC): Return an unsigned value.
1704 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1706 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1707 (DADD): Result destination is RD not RT.
1709 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1711 * sim-main.h (HIACCESS, LOACCESS): Always define.
1713 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1715 * interp.c (sim_info): Delete.
1717 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1719 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1720 (mips_option_handler): New argument `cpu'.
1721 (sim_open): Update call to sim_add_option_table.
1723 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1725 * mips.igen (CxC1): Add tracing.
1727 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1729 * sim-main.h (Max, Min): Declare.
1731 * interp.c (Max, Min): New functions.
1733 * mips.igen (BC1): Add tracing.
1735 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1737 * interp.c Added memory map for stack in vr4100
1739 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1741 * interp.c (load_memory): Add missing "break"'s.
1743 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1745 * interp.c (sim_store_register, sim_fetch_register): Pass in
1746 length parameter. Return -1.
1748 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1750 * interp.c: Added hardware init hook, fixed warnings.
1752 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1754 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1756 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1758 * interp.c (ifetch16): New function.
1760 * sim-main.h (IMEM32): Rename IMEM.
1761 (IMEM16_IMMED): Define.
1763 (DELAY_SLOT): Update.
1765 * m16run.c (sim_engine_run): New file.
1767 * m16.igen: All instructions except LB.
1768 (LB): Call do_load_byte.
1769 * mips.igen (do_load_byte): New function.
1770 (LB): Call do_load_byte.
1772 * mips.igen: Move spec for insn bit size and high bit from here.
1773 * Makefile.in (tmp-igen, tmp-m16): To here.
1775 * m16.dc: New file, decode mips16 instructions.
1777 * Makefile.in (SIM_NO_ALL): Define.
1778 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1780 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1782 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1783 point unit to 32 bit registers.
1784 * configure: Re-generate.
1786 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1788 * configure.in (sim_use_gen): Make IGEN the default simulator
1789 generator for generic 32 and 64 bit mips targets.
1790 * configure: Re-generate.
1792 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1794 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1797 * interp.c (sim_fetch_register, sim_store_register): Read/write
1798 FGR from correct location.
1799 (sim_open): Set size of FGR's according to
1800 WITH_TARGET_FLOATING_POINT_BITSIZE.
1802 * sim-main.h (FGR): Store floating point registers in a separate
1805 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1807 * configure: Regenerated to track ../common/aclocal.m4 changes.
1809 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1811 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1813 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1815 * interp.c (pending_tick): New function. Deliver pending writes.
1817 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1818 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1819 it can handle mixed sized quantites and single bits.
1821 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1823 * interp.c (oengine.h): Do not include when building with IGEN.
1824 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1825 (sim_info): Ditto for PROCESSOR_64BIT.
1826 (sim_monitor): Replace ut_reg with unsigned_word.
1827 (*): Ditto for t_reg.
1828 (LOADDRMASK): Define.
1829 (sim_open): Remove defunct check that host FP is IEEE compliant,
1830 using software to emulate floating point.
1831 (value_fpr, ...): Always compile, was conditional on HASFPU.
1833 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1835 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1838 * interp.c (SD, CPU): Define.
1839 (mips_option_handler): Set flags in each CPU.
1840 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1841 (sim_close): Do not clear STATE, deleted anyway.
1842 (sim_write, sim_read): Assume CPU zero's vm should be used for
1844 (sim_create_inferior): Set the PC for all processors.
1845 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1847 (mips16_entry): Pass correct nr of args to store_word, load_word.
1848 (ColdReset): Cold reset all cpu's.
1849 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1850 (sim_monitor, load_memory, store_memory, signal_exception): Use
1851 `CPU' instead of STATE_CPU.
1854 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1857 * sim-main.h (signal_exception): Add sim_cpu arg.
1858 (SignalException*): Pass both SD and CPU to signal_exception.
1859 * interp.c (signal_exception): Update.
1861 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1863 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1864 address_translation): Ditto
1865 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1867 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1869 * configure: Regenerated to track ../common/aclocal.m4 changes.
1871 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1873 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1875 * mips.igen (model): Map processor names onto BFD name.
1877 * sim-main.h (CPU_CIA): Delete.
1878 (SET_CIA, GET_CIA): Define
1880 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1882 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1885 * configure.in (default_endian): Configure a big-endian simulator
1887 * configure: Re-generate.
1889 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1891 * configure: Regenerated to track ../common/aclocal.m4 changes.
1893 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1895 * interp.c (sim_monitor): Handle Densan monitor outbyte
1896 and inbyte functions.
1898 1997-12-29 Felix Lee <flee@cygnus.com>
1900 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1902 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1904 * Makefile.in (tmp-igen): Arrange for $zero to always be
1905 reset to zero after every instruction.
1907 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1909 * configure: Regenerated to track ../common/aclocal.m4 changes.
1912 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1914 * mips.igen (MSUB): Fix to work like MADD.
1915 * gencode.c (MSUB): Similarly.
1917 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1919 * configure: Regenerated to track ../common/aclocal.m4 changes.
1921 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1923 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1925 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1927 * sim-main.h (sim-fpu.h): Include.
1929 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1930 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1931 using host independant sim_fpu module.
1933 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1935 * interp.c (signal_exception): Report internal errors with SIGABRT
1938 * sim-main.h (C0_CONFIG): New register.
1939 (signal.h): No longer include.
1941 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1943 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1945 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1947 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1949 * mips.igen: Tag vr5000 instructions.
1950 (ANDI): Was missing mipsIV model, fix assembler syntax.
1951 (do_c_cond_fmt): New function.
1952 (C.cond.fmt): Handle mips I-III which do not support CC field
1954 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1955 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1957 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1958 vr5000 which saves LO in a GPR separatly.
1960 * configure.in (enable-sim-igen): For vr5000, select vr5000
1961 specific instructions.
1962 * configure: Re-generate.
1964 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1966 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1968 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1969 fmt_uninterpreted_64 bit cases to switch. Convert to
1972 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1974 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1975 as specified in IV3.2 spec.
1976 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1978 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1980 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1981 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1982 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1983 PENDING_FILL versions of instructions. Simplify.
1985 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1987 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1989 (MTHI, MFHI): Disable code checking HI-LO.
1991 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1993 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1995 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1997 * gencode.c (build_mips16_operands): Replace IPC with cia.
1999 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2000 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2002 (UndefinedResult): Replace function with macro/function
2004 (sim_engine_run): Don't save PC in IPC.
2006 * sim-main.h (IPC): Delete.
2009 * interp.c (signal_exception, store_word, load_word,
2010 address_translation, load_memory, store_memory, cache_op,
2011 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2012 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2013 current instruction address - cia - argument.
2014 (sim_read, sim_write): Call address_translation directly.
2015 (sim_engine_run): Rename variable vaddr to cia.
2016 (signal_exception): Pass cia to sim_monitor
2018 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2019 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2020 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2022 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2023 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2026 * interp.c (signal_exception): Pass restart address to
2029 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2030 idecode.o): Add dependency.
2032 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2034 (DELAY_SLOT): Update NIA not PC with branch address.
2035 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2037 * mips.igen: Use CIA not PC in branch calculations.
2038 (illegal): Call SignalException.
2039 (BEQ, ADDIU): Fix assembler.
2041 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2043 * m16.igen (JALX): Was missing.
2045 * configure.in (enable-sim-igen): New configuration option.
2046 * configure: Re-generate.
2048 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2050 * interp.c (load_memory, store_memory): Delete parameter RAW.
2051 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2052 bypassing {load,store}_memory.
2054 * sim-main.h (ByteSwapMem): Delete definition.
2056 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2058 * interp.c (sim_do_command, sim_commands): Delete mips specific
2059 commands. Handled by module sim-options.
2061 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2062 (WITH_MODULO_MEMORY): Define.
2064 * interp.c (sim_info): Delete code printing memory size.
2066 * interp.c (mips_size): Nee sim_size, delete function.
2068 (monitor, monitor_base, monitor_size): Delete global variables.
2069 (sim_open, sim_close): Delete code creating monitor and other
2070 memory regions. Use sim-memopts module, via sim_do_commandf, to
2071 manage memory regions.
2072 (load_memory, store_memory): Use sim-core for memory model.
2074 * interp.c (address_translation): Delete all memory map code
2075 except line forcing 32 bit addresses.
2077 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2079 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2082 * interp.c (logfh, logfile): Delete globals.
2083 (sim_open, sim_close): Delete code opening & closing log file.
2084 (mips_option_handler): Delete -l and -n options.
2085 (OPTION mips_options): Ditto.
2087 * interp.c (OPTION mips_options): Rename option trace to dinero.
2088 (mips_option_handler): Update.
2090 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2092 * interp.c (fetch_str): New function.
2093 (sim_monitor): Rewrite using sim_read & sim_write.
2094 (sim_open): Check magic number.
2095 (sim_open): Write monitor vectors into memory using sim_write.
2096 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2097 (sim_read, sim_write): Simplify - transfer data one byte at a
2099 (load_memory, store_memory): Clarify meaning of parameter RAW.
2101 * sim-main.h (isHOST): Defete definition.
2102 (isTARGET): Mark as depreciated.
2103 (address_translation): Delete parameter HOST.
2105 * interp.c (address_translation): Delete parameter HOST.
2107 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2111 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2112 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2114 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2116 * mips.igen: Add model filter field to records.
2118 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2120 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2122 interp.c (sim_engine_run): Do not compile function sim_engine_run
2123 when WITH_IGEN == 1.
2125 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2126 target architecture.
2128 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2129 igen. Replace with configuration variables sim_igen_flags /
2132 * m16.igen: New file. Copy mips16 insns here.
2133 * mips.igen: From here.
2135 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2137 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2139 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2141 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2143 * gencode.c (build_instruction): Follow sim_write's lead in using
2144 BigEndianMem instead of !ByteSwapMem.
2146 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2148 * configure.in (sim_gen): Dependent on target, select type of
2149 generator. Always select old style generator.
2151 configure: Re-generate.
2153 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2155 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2156 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2157 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2158 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2159 SIM_@sim_gen@_*, set by autoconf.
2161 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2163 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2165 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2166 CURRENT_FLOATING_POINT instead.
2168 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2169 (address_translation): Raise exception InstructionFetch when
2170 translation fails and isINSTRUCTION.
2172 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2173 sim_engine_run): Change type of of vaddr and paddr to
2175 (address_translation, prefetch, load_memory, store_memory,
2176 cache_op): Change type of vAddr and pAddr to address_word.
2178 * gencode.c (build_instruction): Change type of vaddr and paddr to
2181 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2183 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2184 macro to obtain result of ALU op.
2186 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2188 * interp.c (sim_info): Call profile_print.
2190 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2192 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2194 * sim-main.h (WITH_PROFILE): Do not define, defined in
2195 common/sim-config.h. Use sim-profile module.
2196 (simPROFILE): Delete defintion.
2198 * interp.c (PROFILE): Delete definition.
2199 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2200 (sim_close): Delete code writing profile histogram.
2201 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2203 (sim_engine_run): Delete code profiling the PC.
2205 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2207 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2209 * interp.c (sim_monitor): Make register pointers of type
2212 * sim-main.h: Make registers of type unsigned_word not
2215 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2217 * interp.c (sync_operation): Rename from SyncOperation, make
2218 global, add SD argument.
2219 (prefetch): Rename from Prefetch, make global, add SD argument.
2220 (decode_coproc): Make global.
2222 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2224 * gencode.c (build_instruction): Generate DecodeCoproc not
2225 decode_coproc calls.
2227 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2228 (SizeFGR): Move to sim-main.h
2229 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2230 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2231 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2233 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2234 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2235 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2236 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2237 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2238 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2240 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2242 (sim-alu.h): Include.
2243 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2244 (sim_cia): Typedef to instruction_address.
2246 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2248 * Makefile.in (interp.o): Rename generated file engine.c to
2253 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2255 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2257 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2259 * gencode.c (build_instruction): For "FPSQRT", output correct
2260 number of arguments to Recip.
2262 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2264 * Makefile.in (interp.o): Depends on sim-main.h
2266 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2268 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2269 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2270 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2271 STATE, DSSTATE): Define
2272 (GPR, FGRIDX, ..): Define.
2274 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2275 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2276 (GPR, FGRIDX, ...): Delete macros.
2278 * interp.c: Update names to match defines from sim-main.h
2280 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2282 * interp.c (sim_monitor): Add SD argument.
2283 (sim_warning): Delete. Replace calls with calls to
2285 (sim_error): Delete. Replace calls with sim_io_error.
2286 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2287 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2288 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2290 (mips_size): Rename from sim_size. Add SD argument.
2292 * interp.c (simulator): Delete global variable.
2293 (callback): Delete global variable.
2294 (mips_option_handler, sim_open, sim_write, sim_read,
2295 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2296 sim_size,sim_monitor): Use sim_io_* not callback->*.
2297 (sim_open): ZALLOC simulator struct.
2298 (PROFILE): Do not define.
2300 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2302 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2303 support.h with corresponding code.
2305 * sim-main.h (word64, uword64), support.h: Move definition to
2307 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2310 * Makefile.in: Update dependencies
2311 * interp.c: Do not include.
2313 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2315 * interp.c (address_translation, load_memory, store_memory,
2316 cache_op): Rename to from AddressTranslation et.al., make global,
2319 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2322 * interp.c (SignalException): Rename to signal_exception, make
2325 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2327 * sim-main.h (SignalException, SignalExceptionInterrupt,
2328 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2329 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2330 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2333 * interp.c, support.h: Use.
2335 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2337 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2338 to value_fpr / store_fpr. Add SD argument.
2339 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2340 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2342 * sim-main.h (ValueFPR, StoreFPR): Define.
2344 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2346 * interp.c (sim_engine_run): Check consistency between configure
2347 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2350 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2351 (mips_fpu): Configure WITH_FLOATING_POINT.
2352 (mips_endian): Configure WITH_TARGET_ENDIAN.
2353 * configure: Update.
2355 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2357 * configure: Regenerated to track ../common/aclocal.m4 changes.
2359 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2361 * configure: Regenerated.
2363 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2365 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2367 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2369 * gencode.c (print_igen_insn_models): Assume certain architectures
2370 include all mips* instructions.
2371 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2374 * Makefile.in (tmp.igen): Add target. Generate igen input from
2377 * gencode.c (FEATURE_IGEN): Define.
2378 (main): Add --igen option. Generate output in igen format.
2379 (process_instructions): Format output according to igen option.
2380 (print_igen_insn_format): New function.
2381 (print_igen_insn_models): New function.
2382 (process_instructions): Only issue warnings and ignore
2383 instructions when no FEATURE_IGEN.
2385 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2387 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2390 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2392 * configure: Regenerated to track ../common/aclocal.m4 changes.
2394 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2396 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2397 SIM_RESERVED_BITS): Delete, moved to common.
2398 (SIM_EXTRA_CFLAGS): Update.
2400 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2402 * configure.in: Configure non-strict memory alignment.
2403 * configure: Regenerated to track ../common/aclocal.m4 changes.
2405 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2407 * configure: Regenerated to track ../common/aclocal.m4 changes.
2409 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2411 * gencode.c (SDBBP,DERET): Added (3900) insns.
2412 (RFE): Turn on for 3900.
2413 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2414 (dsstate): Made global.
2415 (SUBTARGET_R3900): Added.
2416 (CANCELDELAYSLOT): New.
2417 (SignalException): Ignore SystemCall rather than ignore and
2418 terminate. Add DebugBreakPoint handling.
2419 (decode_coproc): New insns RFE, DERET; and new registers Debug
2420 and DEPC protected by SUBTARGET_R3900.
2421 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2423 * Makefile.in,configure.in: Add mips subtarget option.
2424 * configure: Update.
2426 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2428 * gencode.c: Add r3900 (tx39).
2431 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2433 * gencode.c (build_instruction): Don't need to subtract 4 for
2436 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2438 * interp.c: Correct some HASFPU problems.
2440 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2442 * configure: Regenerated to track ../common/aclocal.m4 changes.
2444 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2446 * interp.c (mips_options): Fix samples option short form, should
2449 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2451 * interp.c (sim_info): Enable info code. Was just returning.
2453 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2455 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2458 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2460 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2462 (build_instruction): Ditto for LL.
2464 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2466 * configure: Regenerated to track ../common/aclocal.m4 changes.
2468 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2470 * configure: Regenerated to track ../common/aclocal.m4 changes.
2473 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2475 * interp.c (sim_open): Add call to sim_analyze_program, update
2478 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2480 * interp.c (sim_kill): Delete.
2481 (sim_create_inferior): Add ABFD argument. Set PC from same.
2482 (sim_load): Move code initializing trap handlers from here.
2483 (sim_open): To here.
2484 (sim_load): Delete, use sim-hload.c.
2486 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2488 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2490 * configure: Regenerated to track ../common/aclocal.m4 changes.
2493 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2495 * interp.c (sim_open): Add ABFD argument.
2496 (sim_load): Move call to sim_config from here.
2497 (sim_open): To here. Check return status.
2499 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2501 * gencode.c (build_instruction): Two arg MADD should
2502 not assign result to $0.
2504 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2506 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2507 * sim/mips/configure.in: Regenerate.
2509 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2511 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2512 signed8, unsigned8 et.al. types.
2514 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2515 hosts when selecting subreg.
2517 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2519 * interp.c (sim_engine_run): Reset the ZERO register to zero
2520 regardless of FEATURE_WARN_ZERO.
2521 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2523 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2525 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2526 (SignalException): For BreakPoints ignore any mode bits and just
2528 (SignalException): Always set the CAUSE register.
2530 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2532 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2533 exception has been taken.
2535 * interp.c: Implement the ERET and mt/f sr instructions.
2537 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2539 * interp.c (SignalException): Don't bother restarting an
2542 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2544 * interp.c (SignalException): Really take an interrupt.
2545 (interrupt_event): Only deliver interrupts when enabled.
2547 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2549 * interp.c (sim_info): Only print info when verbose.
2550 (sim_info) Use sim_io_printf for output.
2552 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2554 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2557 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2559 * interp.c (sim_do_command): Check for common commands if a
2560 simulator specific command fails.
2562 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2564 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2565 and simBE when DEBUG is defined.
2567 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2569 * interp.c (interrupt_event): New function. Pass exception event
2570 onto exception handler.
2572 * configure.in: Check for stdlib.h.
2573 * configure: Regenerate.
2575 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2576 variable declaration.
2577 (build_instruction): Initialize memval1.
2578 (build_instruction): Add UNUSED attribute to byte, bigend,
2580 (build_operands): Ditto.
2582 * interp.c: Fix GCC warnings.
2583 (sim_get_quit_code): Delete.
2585 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2586 * Makefile.in: Ditto.
2587 * configure: Re-generate.
2589 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2591 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2593 * interp.c (mips_option_handler): New function parse argumes using
2595 (myname): Replace with STATE_MY_NAME.
2596 (sim_open): Delete check for host endianness - performed by
2598 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2599 (sim_open): Move much of the initialization from here.
2600 (sim_load): To here. After the image has been loaded and
2602 (sim_open): Move ColdReset from here.
2603 (sim_create_inferior): To here.
2604 (sim_open): Make FP check less dependant on host endianness.
2606 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2608 * interp.c (sim_set_callbacks): Delete.
2610 * interp.c (membank, membank_base, membank_size): Replace with
2611 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2612 (sim_open): Remove call to callback->init. gdb/run do this.
2616 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2618 * interp.c (big_endian_p): Delete, replaced by
2619 current_target_byte_order.
2621 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2623 * interp.c (host_read_long, host_read_word, host_swap_word,
2624 host_swap_long): Delete. Using common sim-endian.
2625 (sim_fetch_register, sim_store_register): Use H2T.
2626 (pipeline_ticks): Delete. Handled by sim-events.
2628 (sim_engine_run): Update.
2630 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2632 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2634 (SignalException): To here. Signal using sim_engine_halt.
2635 (sim_stop_reason): Delete, moved to common.
2637 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2639 * interp.c (sim_open): Add callback argument.
2640 (sim_set_callbacks): Delete SIM_DESC argument.
2643 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2645 * Makefile.in (SIM_OBJS): Add common modules.
2647 * interp.c (sim_set_callbacks): Also set SD callback.
2648 (set_endianness, xfer_*, swap_*): Delete.
2649 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2650 Change to functions using sim-endian macros.
2651 (control_c, sim_stop): Delete, use common version.
2652 (simulate): Convert into.
2653 (sim_engine_run): This function.
2654 (sim_resume): Delete.
2656 * interp.c (simulation): New variable - the simulator object.
2657 (sim_kind): Delete global - merged into simulation.
2658 (sim_load): Cleanup. Move PC assignment from here.
2659 (sim_create_inferior): To here.
2661 * sim-main.h: New file.
2662 * interp.c (sim-main.h): Include.
2664 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2666 * configure: Regenerated to track ../common/aclocal.m4 changes.
2668 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2670 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2672 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2674 * gencode.c (build_instruction): DIV instructions: check
2675 for division by zero and integer overflow before using
2676 host's division operation.
2678 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2680 * Makefile.in (SIM_OBJS): Add sim-load.o.
2681 * interp.c: #include bfd.h.
2682 (target_byte_order): Delete.
2683 (sim_kind, myname, big_endian_p): New static locals.
2684 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2685 after argument parsing. Recognize -E arg, set endianness accordingly.
2686 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2687 load file into simulator. Set PC from bfd.
2688 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2689 (set_endianness): Use big_endian_p instead of target_byte_order.
2691 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2693 * interp.c (sim_size): Delete prototype - conflicts with
2694 definition in remote-sim.h. Correct definition.
2696 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2698 * configure: Regenerated to track ../common/aclocal.m4 changes.
2701 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2703 * interp.c (sim_open): New arg `kind'.
2705 * configure: Regenerated to track ../common/aclocal.m4 changes.
2707 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2709 * configure: Regenerated to track ../common/aclocal.m4 changes.
2711 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2713 * interp.c (sim_open): Set optind to 0 before calling getopt.
2715 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2717 * configure: Regenerated to track ../common/aclocal.m4 changes.
2719 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2721 * interp.c : Replace uses of pr_addr with pr_uword64
2722 where the bit length is always 64 independent of SIM_ADDR.
2723 (pr_uword64) : added.
2725 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2727 * configure: Re-generate.
2729 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2731 * configure: Regenerate to track ../common/aclocal.m4 changes.
2733 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2735 * interp.c (sim_open): New SIM_DESC result. Argument is now
2737 (other sim_*): New SIM_DESC argument.
2739 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2741 * interp.c: Fix printing of addresses for non-64-bit targets.
2742 (pr_addr): Add function to print address based on size.
2744 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2746 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2748 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2750 * gencode.c (build_mips16_operands): Correct computation of base
2751 address for extended PC relative instruction.
2753 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2755 * interp.c (mips16_entry): Add support for floating point cases.
2756 (SignalException): Pass floating point cases to mips16_entry.
2757 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2759 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2761 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2762 and then set the state to fmt_uninterpreted.
2763 (COP_SW): Temporarily set the state to fmt_word while calling
2766 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2768 * gencode.c (build_instruction): The high order may be set in the
2769 comparison flags at any ISA level, not just ISA 4.
2771 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2773 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2774 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2775 * configure.in: sinclude ../common/aclocal.m4.
2776 * configure: Regenerated.
2778 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2780 * configure: Rebuild after change to aclocal.m4.
2782 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2784 * configure configure.in Makefile.in: Update to new configure
2785 scheme which is more compatible with WinGDB builds.
2786 * configure.in: Improve comment on how to run autoconf.
2787 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2788 * Makefile.in: Use autoconf substitution to install common
2791 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2793 * gencode.c (build_instruction): Use BigEndianCPU instead of
2796 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2798 * interp.c (sim_monitor): Make output to stdout visible in
2799 wingdb's I/O log window.
2801 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2803 * support.h: Undo previous change to SIGTRAP
2806 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2808 * interp.c (store_word, load_word): New static functions.
2809 (mips16_entry): New static function.
2810 (SignalException): Look for mips16 entry and exit instructions.
2811 (simulate): Use the correct index when setting fpr_state after
2812 doing a pending move.
2814 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2816 * interp.c: Fix byte-swapping code throughout to work on
2817 both little- and big-endian hosts.
2819 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2821 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2822 with gdb/config/i386/xm-windows.h.
2824 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2826 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2827 that messes up arithmetic shifts.
2829 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2831 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2832 SIGTRAP and SIGQUIT for _WIN32.
2834 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2836 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2837 force a 64 bit multiplication.
2838 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2839 destination register is 0, since that is the default mips16 nop
2842 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2844 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2845 (build_endian_shift): Don't check proc64.
2846 (build_instruction): Always set memval to uword64. Cast op2 to
2847 uword64 when shifting it left in memory instructions. Always use
2848 the same code for stores--don't special case proc64.
2850 * gencode.c (build_mips16_operands): Fix base PC value for PC
2852 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2854 * interp.c (simJALDELAYSLOT): Define.
2855 (JALDELAYSLOT): Define.
2856 (INDELAYSLOT, INJALDELAYSLOT): Define.
2857 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2859 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2861 * interp.c (sim_open): add flush_cache as a PMON routine
2862 (sim_monitor): handle flush_cache by ignoring it
2864 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2866 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2868 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2869 (BigEndianMem): Rename to ByteSwapMem and change sense.
2870 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2871 BigEndianMem references to !ByteSwapMem.
2872 (set_endianness): New function, with prototype.
2873 (sim_open): Call set_endianness.
2874 (sim_info): Use simBE instead of BigEndianMem.
2875 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2876 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2877 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2878 ifdefs, keeping the prototype declaration.
2879 (swap_word): Rewrite correctly.
2880 (ColdReset): Delete references to CONFIG. Delete endianness related
2881 code; moved to set_endianness.
2883 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2885 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2886 * interp.c (CHECKHILO): Define away.
2887 (simSIGINT): New macro.
2888 (membank_size): Increase from 1MB to 2MB.
2889 (control_c): New function.
2890 (sim_resume): Rename parameter signal to signal_number. Add local
2891 variable prev. Call signal before and after simulate.
2892 (sim_stop_reason): Add simSIGINT support.
2893 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2895 (sim_warning): Delete call to SignalException. Do call printf_filtered
2897 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2898 a call to sim_warning.
2900 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2902 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2903 16 bit instructions.
2905 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2907 Add support for mips16 (16 bit MIPS implementation):
2908 * gencode.c (inst_type): Add mips16 instruction encoding types.
2909 (GETDATASIZEINSN): Define.
2910 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2911 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2913 (MIPS16_DECODE): New table, for mips16 instructions.
2914 (bitmap_val): New static function.
2915 (struct mips16_op): Define.
2916 (mips16_op_table): New table, for mips16 operands.
2917 (build_mips16_operands): New static function.
2918 (process_instructions): If PC is odd, decode a mips16
2919 instruction. Break out instruction handling into new
2920 build_instruction function.
2921 (build_instruction): New static function, broken out of
2922 process_instructions. Check modifiers rather than flags for SHIFT
2923 bit count and m[ft]{hi,lo} direction.
2924 (usage): Pass program name to fprintf.
2925 (main): Remove unused variable this_option_optind. Change
2926 ``*loptarg++'' to ``loptarg++''.
2927 (my_strtoul): Parenthesize && within ||.
2928 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2929 (simulate): If PC is odd, fetch a 16 bit instruction, and
2930 increment PC by 2 rather than 4.
2931 * configure.in: Add case for mips16*-*-*.
2932 * configure: Rebuild.
2934 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2936 * interp.c: Allow -t to enable tracing in standalone simulator.
2937 Fix garbage output in trace file and error messages.
2939 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2941 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2942 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2943 * configure.in: Simplify using macros in ../common/aclocal.m4.
2944 * configure: Regenerated.
2945 * tconfig.in: New file.
2947 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2949 * interp.c: Fix bugs in 64-bit port.
2950 Use ansi function declarations for msvc compiler.
2951 Initialize and test file pointer in trace code.
2952 Prevent duplicate definition of LAST_EMED_REGNUM.
2954 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2956 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2958 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2960 * interp.c (SignalException): Check for explicit terminating
2962 * gencode.c: Pass instruction value through SignalException()
2963 calls for Trap, Breakpoint and Syscall.
2965 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2967 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2968 only used on those hosts that provide it.
2969 * configure.in: Add sqrt() to list of functions to be checked for.
2970 * config.in: Re-generated.
2971 * configure: Re-generated.
2973 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2975 * gencode.c (process_instructions): Call build_endian_shift when
2976 expanding STORE RIGHT, to fix swr.
2977 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2978 clear the high bits.
2979 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2980 Fix float to int conversions to produce signed values.
2982 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2984 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2985 (process_instructions): Correct handling of nor instruction.
2986 Correct shift count for 32 bit shift instructions. Correct sign
2987 extension for arithmetic shifts to not shift the number of bits in
2988 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2989 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2991 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2992 It's OK to have a mult follow a mult. What's not OK is to have a
2993 mult follow an mfhi.
2994 (Convert): Comment out incorrect rounding code.
2996 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2998 * interp.c (sim_monitor): Improved monitor printf
2999 simulation. Tidied up simulator warnings, and added "--log" option
3000 for directing warning message output.
3001 * gencode.c: Use sim_warning() rather than WARNING macro.
3003 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3005 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3006 getopt1.o, rather than on gencode.c. Link objects together.
3007 Don't link against -liberty.
3008 (gencode.o, getopt.o, getopt1.o): New targets.
3009 * gencode.c: Include <ctype.h> and "ansidecl.h".
3010 (AND): Undefine after including "ansidecl.h".
3011 (ULONG_MAX): Define if not defined.
3012 (OP_*): Don't define macros; now defined in opcode/mips.h.
3013 (main): Call my_strtoul rather than strtoul.
3014 (my_strtoul): New static function.
3016 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3018 * gencode.c (process_instructions): Generate word64 and uword64
3019 instead of `long long' and `unsigned long long' data types.
3020 * interp.c: #include sysdep.h to get signals, and define default
3022 * (Convert): Work around for Visual-C++ compiler bug with type
3024 * support.h: Make things compile under Visual-C++ by using
3025 __int64 instead of `long long'. Change many refs to long long
3026 into word64/uword64 typedefs.
3028 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3030 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3031 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3033 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3034 (AC_PROG_INSTALL): Added.
3035 (AC_PROG_CC): Moved to before configure.host call.
3036 * configure: Rebuilt.
3038 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3040 * configure.in: Define @SIMCONF@ depending on mips target.
3041 * configure: Rebuild.
3042 * Makefile.in (run): Add @SIMCONF@ to control simulator
3044 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3045 * interp.c: Remove some debugging, provide more detailed error
3046 messages, update memory accesses to use LOADDRMASK.
3048 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3050 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3051 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3053 * configure: Rebuild.
3054 * config.in: New file, generated by autoheader.
3055 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3056 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3057 HAVE_ANINT and HAVE_AINT, as appropriate.
3058 * Makefile.in (run): Use @LIBS@ rather than -lm.
3059 (interp.o): Depend upon config.h.
3060 (Makefile): Just rebuild Makefile.
3061 (clean): Remove stamp-h.
3062 (mostlyclean): Make the same as clean, not as distclean.
3063 (config.h, stamp-h): New targets.
3065 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3067 * interp.c (ColdReset): Fix boolean test. Make all simulator
3070 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3072 * interp.c (xfer_direct_word, xfer_direct_long,
3073 swap_direct_word, swap_direct_long, xfer_big_word,
3074 xfer_big_long, xfer_little_word, xfer_little_long,
3075 swap_word,swap_long): Added.
3076 * interp.c (ColdReset): Provide function indirection to
3077 host<->simulated_target transfer routines.
3078 * interp.c (sim_store_register, sim_fetch_register): Updated to
3079 make use of indirected transfer routines.
3081 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3083 * gencode.c (process_instructions): Ensure FP ABS instruction
3085 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3086 system call support.
3088 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3090 * interp.c (sim_do_command): Complain if callback structure not
3093 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3095 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3096 support for Sun hosts.
3097 * Makefile.in (gencode): Ensure the host compiler and libraries
3098 used for cross-hosted build.
3100 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3102 * interp.c, gencode.c: Some more (TODO) tidying.
3104 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3106 * gencode.c, interp.c: Replaced explicit long long references with
3107 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3108 * support.h (SET64LO, SET64HI): Macros added.
3110 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3112 * configure: Regenerate with autoconf 2.7.
3114 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3116 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3117 * support.h: Remove superfluous "1" from #if.
3118 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3120 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3122 * interp.c (StoreFPR): Control UndefinedResult() call on
3123 WARN_RESULT manifest.
3125 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3127 * gencode.c: Tidied instruction decoding, and added FP instruction
3130 * interp.c: Added dineroIII, and BSD profiling support. Also
3131 run-time FP handling.
3133 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3135 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3136 gencode.c, interp.c, support.h: created.