1 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
3 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
7 Mon Jun 1 10:28:25 1998 Jeffrey A Law (law@cygnus.com)
9 * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1.
13 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
15 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
18 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
20 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
22 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
23 sim-main.h. Declare a struct hw_descriptor instead of struct
27 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
29 * mips.igen (do_store_left, do_load_left): Compute nr of left and
30 right bits and then re-align left hand bytes to correct byte
31 lanes. Fix incorrect computation in do_store_left when loading
32 bytes from second word.
35 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
37 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
38 * interp.c (sim_open): Only create a device tree when HW is
41 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
42 * interp.c (signal_exception): Ditto.
45 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
47 * gencode.c: Mark BEGEZALL as LIKELY.
49 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
51 * sim-main.h (ALU32_END): Sign extend 32 bit results.
52 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
55 Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
57 * interp.c (sim_fetch_register): Convert internal r5900 regs to
61 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
63 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
64 modules. Recognize TX39 target with "mips*tx39" pattern.
66 * sim-main.h (*): Added many macros defining bits in
67 TX39 control registers.
68 (SignalInterrupt): Send actual PC instead of NULL.
69 (SignalNMIReset): New exception type.
70 * interp.c (board): New variable for future use to identify
71 a particular board being simulated.
72 (mips_option_handler,mips_options): Added "--board" option.
73 (interrupt_event): Send actual PC.
74 (sim_open): Make memory layout conditional on board setting.
75 (signal_exception): Initial implementation of hardware interrupt
76 handling. Accept another break instruction variant for simulator
78 (decode_coproc): Implement RFE instruction for TX39.
79 (mips.igen): Decode RFE instruction as such.
81 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
82 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
83 bbegin to implement memory map.
84 * dv-tx3904cpu.c: New file.
85 * dv-tx3904irc.c: New file.
88 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
90 * mips.igen (check_mt_hilo): Create a separate r3900 version.
93 Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
95 * r5900.igen: Replace the calls and the definition of the
96 function check_op_hilo_hi1lo1 with the pair
97 check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
100 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
102 * tx.igen (madd,maddu): Replace calls to check_op_hilo
103 with calls to check_div_hilo.
105 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
107 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
108 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
109 Add special r3900 version of do_mult_hilo.
110 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
111 with calls to check_mult_hilo.
112 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
113 with calls to check_div_hilo.
115 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
117 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
118 Document a replacement.
120 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
122 * interp.c (sim_monitor): Make mon_printf work.
124 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
126 * sim-main.h (INSN_NAME): New arg `cpu'.
129 Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com>
131 * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
136 Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
138 * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
139 * r5900.igen (r59fp_overflow): Use.
141 * r5900.igen (r59fp_op3): Rename to
142 (r59fp_mula): This, delete opm argument.
143 (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
144 (r59fp_mula): Overflowing product propogates through to result.
145 (r59fp_mula): ACC to the MAX propogates to result.
146 (r59fp_mula): Underflow during multiply only sets SU.
149 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
151 * configure: Regenerated to track ../common/aclocal.m4 changes.
153 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
155 * configure: Regenerated to track ../common/aclocal.m4 changes.
158 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
160 * acconfig.h: New file.
161 * configure.in: Reverted change of Apr 24; use sinclude again.
163 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
165 * configure: Regenerated to track ../common/aclocal.m4 changes.
168 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
170 * configure.in: Don't call sinclude.
172 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
174 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
176 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
178 * mips.igen (ERET): Implement.
180 * interp.c (decode_coproc): Return sign-extended EPC.
182 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
184 * interp.c (signal_exception): Do not ignore Trap.
185 (signal_exception): On TRAP, restart at exception address.
186 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
187 (signal_exception): Update.
188 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
189 so that TRAP instructions are caught.
191 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
193 * sim-main.h (struct hilo_access, struct hilo_history): Define,
194 contains HI/LO access history.
195 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
196 (HIACCESS, LOACCESS): Delete, replace with
197 (HIHISTORY, LOHISTORY): New macros.
198 (start-sanitize-r5900):
199 (struct sim_5900_cpu): Make hi1access, lo1access of type
201 (HI1ACCESS, LO1ACCESS): Delete, replace with
202 (HI1HISTORY, LO1HISTORY): New macros.
203 (end-sanitize-r5900):
204 (CHECKHILO): Delete all, moved to mips.igen
206 * gencode.c (build_instruction): Do not generate checks for
207 correct HI/LO register usage.
209 * interp.c (old_engine_run): Delete checks for correct HI/LO
212 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
213 check_mf_cycles): New functions.
214 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
215 do_divu, domultx, do_mult, do_multu): Use.
217 * tx.igen ("madd", "maddu"): Use.
218 (start-sanitize-r5900):
220 r5900.igen: Update all HI/LO checks.
221 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
222 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
223 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
224 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
225 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
227 (end-sanitize-r5900):
230 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
232 * interp.c (decode_coproc): Correct CMFC2/QMTC2
235 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
236 instead of a single 128-bit access.
240 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
242 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
243 * interp.c (cop_[ls]q): Fixes corresponding to above.
247 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
249 * interp.c (decode_coproc): Adapt COP2 micro interlock to
250 clarified specs. Reset "M" bit; exit also on "E" bit.
254 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
256 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
257 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
259 * r5900.igen (r59fp_unpack): New function.
260 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
261 RSQRT.S, SQRT.S): Use.
262 (r59fp_zero): New function.
263 (r59fp_overflow): Generate r5900 specific overflow value.
264 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
266 (CVT.S.W, CVT.W.S): Exchange implementations.
268 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
272 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
274 * configure.in (tx19, sim_use_gen): Switch to igen.
275 * configure: Re-build.
279 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
281 * interp.c (decode_coproc): Make COP2 branch code compile after
282 igen signature changes.
285 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
287 * mips.igen (DSRAV): Use function do_dsrav.
288 (SRAV): Use new function do_srav.
290 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
291 (B): Sign extend 11 bit immediate.
292 (EXT-B*): Shift 16 bit immediate left by 1.
293 (ADDIU*): Don't sign extend immediate value.
295 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
297 * m16run.c (sim_engine_run): Restore CIA after handling an event.
300 * mips.igen (mtc0): Valid tx19 instruction.
303 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
306 * mips.igen (delayslot32, nullify_next_insn): New functions.
307 (m16.igen): Always include.
308 (do_*): Add more tracing.
310 * m16.igen (delayslot16): Add NIA argument, could be called by a
311 32 bit MIPS16 instruction.
313 * interp.c (ifetch16): Move function from here.
314 * sim-main.c (ifetch16): To here.
316 * sim-main.c (ifetch16, ifetch32): Update to match current
317 implementations of LH, LW.
318 (signal_exception): Don't print out incorrect hex value of illegal
321 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
323 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
326 * m16.igen: Implement MIPS16 instructions.
328 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
329 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
330 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
331 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
332 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
333 bodies of corresponding code from 32 bit insn to these. Also used
334 by MIPS16 versions of functions.
336 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
337 (IMEM16): Drop NR argument from macro.
340 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
342 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
343 of VU lower instruction.
347 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
349 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
352 * sim-main.h: Removed attempt at allowing 128-bit access.
356 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
358 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
360 * interp.c (decode_coproc): Refer to VU CIA as a "special"
361 register, not as a "misc" register. Aha. Add activity
362 assertions after VCALLMS* instructions.
366 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
368 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
369 to upper code of generated VU instruction.
373 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
375 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
377 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
380 * r5900.igen (SQC2): Thinko.
384 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
386 * interp.c (*): Adapt code to merged VU device & state structs.
387 (decode_coproc): Execute COP2 each macroinstruction without
388 pipelining, by stepping VU to completion state. Adapted to
389 read_vu_*_reg style of register access.
391 * mips.igen ([SL]QC2): Removed these COP2 instructions.
393 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
395 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
398 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
400 * Makefile.in (SIM_OBJS): Add sim-main.o.
402 * sim-main.h (address_translation, load_memory, store_memory,
403 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
405 (pr_addr, pr_uword64): Declare.
406 (sim-main.c): Include when H_REVEALS_MODULE_P.
408 * interp.c (address_translation, load_memory, store_memory,
409 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
411 * sim-main.c: To here. Fix compilation problems.
413 * configure.in: Enable inlining.
414 * configure: Re-config.
416 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
418 * configure: Regenerated to track ../common/aclocal.m4 changes.
420 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
422 * mips.igen: Include tx.igen.
423 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
424 * tx.igen: New file, contains MADD and MADDU.
426 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
427 the hardwired constant `7'.
428 (store_memory): Ditto.
429 (LOADDRMASK): Move definition to sim-main.h.
431 mips.igen (MTC0): Enable for r3900.
434 mips.igen (do_load_byte): Delete.
435 (do_load, do_store, do_load_left, do_load_write, do_store_left,
436 do_store_right): New functions.
437 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
439 configure.in: Let the tx39 use igen again.
442 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
444 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
445 not an address sized quantity. Return zero for cache sizes.
447 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
449 * mips.igen (r3900): r3900 does not support 64 bit integer
453 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
455 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
459 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
461 * interp.c (decode_coproc): Continuing COP2 work.
462 (cop_[ls]q): Make sky-target-only.
464 * sim-main.h (COP_[LS]Q): Make sky-target-only.
466 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
468 * configure.in (mipstx39*-*-*): Use gencode simulator rather
470 * configure : Rebuild.
473 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
475 * interp.c (decode_coproc): Added a missing TARGET_SKY check
476 around COP2 implementation skeleton.
480 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
482 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
484 * interp.c (sim_{load,store}_register): Use new vu[01]_device
485 static to access VU registers.
486 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
487 decoding. Work in progress.
489 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
490 overlapping/redundant bit pattern.
491 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
494 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
497 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
498 access to coprocessor registers.
500 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
502 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
504 * configure: Regenerated to track ../common/aclocal.m4 changes.
506 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
508 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
510 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
512 * configure: Regenerated to track ../common/aclocal.m4 changes.
513 * config.in: Regenerated to track ../common/aclocal.m4 changes.
515 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
517 * configure: Regenerated to track ../common/aclocal.m4 changes.
519 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
521 * interp.c (Max, Min): Comment out functions. Not yet used.
523 start-sanitize-vr4320
524 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
526 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
529 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
531 * configure: Regenerated to track ../common/aclocal.m4 changes.
533 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
535 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
536 configurable settings for stand-alone simulator.
539 * configure.in: Added --with-sim-gpu2 option to specify path of
540 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
541 links/compiles stand-alone simulator with this library.
543 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
545 * configure.in: Added X11 search, just in case.
547 * configure: Regenerated.
549 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
551 * interp.c (sim_write, sim_read, load_memory, store_memory):
552 Replace sim_core_*_map with read_map, write_map, exec_map resp.
554 start-sanitize-vr4320
555 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
557 * vr4320.igen (clz,dclz) : Added.
558 (dmac): Replaced 99, with LO.
561 start-sanitize-vr5400
562 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
564 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
567 start-sanitize-vr4320
568 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
570 * vr4320.igen: New file.
571 * Makefile.in (vr4320.igen) : Added.
572 * configure.in (mips64vr4320-*-*): Added.
573 * configure : Rebuilt.
574 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
575 Add the vr4320 model entry and mark the vr4320 insn as necessary.
578 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
580 * sim-main.h (GETFCC): Return an unsigned value.
583 * r5900.igen: Use an unsigned array index variable `i'.
584 (QFSRV): Ditto for variable bytes.
587 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
589 * mips.igen (DIV): Fix check for -1 / MIN_INT.
590 (DADD): Result destination is RD not RT.
593 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
594 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
598 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
600 * sim-main.h (HIACCESS, LOACCESS): Always define.
602 * mdmx.igen (Maxi, Mini): Rename Max, Min.
604 * interp.c (sim_info): Delete.
606 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
608 * interp.c (DECLARE_OPTION_HANDLER): Use it.
609 (mips_option_handler): New argument `cpu'.
610 (sim_open): Update call to sim_add_option_table.
612 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
614 * mips.igen (CxC1): Add tracing.
617 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
619 * r5900.igen (StoreFP): Delete.
620 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
622 (rsqrt.s, sqrt.s): Implement.
623 (r59cond): New function.
624 (C.COND.S): Call r59cond in assembler line.
625 (cvt.w.s, cvt.s.w): Implement.
627 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
630 * sim-main.h: Define an enum of r5900 FCSR bit fields.
634 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
636 * r5900.igen: Add tracing to all p* instructions.
638 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
640 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
641 to get gdb talking to re-aranged sim_cpu register structure.
644 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
646 * sim-main.h (Max, Min): Declare.
648 * interp.c (Max, Min): New functions.
650 * mips.igen (BC1): Add tracing.
652 start-sanitize-vr5400
653 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
655 * mdmx.igen: Tag all functions as requiring either with mdmx or
660 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
662 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
664 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
666 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
668 * r5900.igen: Rewrite.
670 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
672 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
673 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
676 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
678 * interp.c Added memory map for stack in vr4100
680 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
682 * interp.c (load_memory): Add missing "break"'s.
684 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
686 * interp.c (sim_store_register, sim_fetch_register): Pass in
687 length parameter. Return -1.
689 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
691 * interp.c: Added hardware init hook, fixed warnings.
693 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
695 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
697 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
699 * interp.c (ifetch16): New function.
701 * sim-main.h (IMEM32): Rename IMEM.
702 (IMEM16_IMMED): Define.
704 (DELAY_SLOT): Update.
706 * m16run.c (sim_engine_run): New file.
708 * m16.igen: All instructions except LB.
709 (LB): Call do_load_byte.
710 * mips.igen (do_load_byte): New function.
711 (LB): Call do_load_byte.
713 * mips.igen: Move spec for insn bit size and high bit from here.
714 * Makefile.in (tmp-igen, tmp-m16): To here.
716 * m16.dc: New file, decode mips16 instructions.
718 * Makefile.in (SIM_NO_ALL): Define.
719 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
722 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
726 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
728 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
729 point unit to 32 bit registers.
730 * configure: Re-generate.
732 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
734 * configure.in (sim_use_gen): Make IGEN the default simulator
735 generator for generic 32 and 64 bit mips targets.
736 * configure: Re-generate.
738 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
740 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
743 * interp.c (sim_fetch_register, sim_store_register): Read/write
744 FGR from correct location.
745 (sim_open): Set size of FGR's according to
746 WITH_TARGET_FLOATING_POINT_BITSIZE.
748 * sim-main.h (FGR): Store floating point registers in a separate
751 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
753 * configure: Regenerated to track ../common/aclocal.m4 changes.
755 start-sanitize-vr5400
756 * mdmx.igen: Mark all instructions as 64bit/fp specific.
759 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
761 * interp.c (ColdReset): Call PENDING_INVALIDATE.
763 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
765 * interp.c (pending_tick): New function. Deliver pending writes.
767 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
768 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
769 it can handle mixed sized quantites and single bits.
771 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
773 * interp.c (oengine.h): Do not include when building with IGEN.
774 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
775 (sim_info): Ditto for PROCESSOR_64BIT.
776 (sim_monitor): Replace ut_reg with unsigned_word.
777 (*): Ditto for t_reg.
778 (LOADDRMASK): Define.
779 (sim_open): Remove defunct check that host FP is IEEE compliant,
780 using software to emulate floating point.
781 (value_fpr, ...): Always compile, was conditional on HASFPU.
783 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
785 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
788 * interp.c (SD, CPU): Define.
789 (mips_option_handler): Set flags in each CPU.
790 (interrupt_event): Assume CPU 0 is the one being iterrupted.
791 (sim_close): Do not clear STATE, deleted anyway.
792 (sim_write, sim_read): Assume CPU zero's vm should be used for
794 (sim_create_inferior): Set the PC for all processors.
795 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
797 (mips16_entry): Pass correct nr of args to store_word, load_word.
798 (ColdReset): Cold reset all cpu's.
799 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
800 (sim_monitor, load_memory, store_memory, signal_exception): Use
801 `CPU' instead of STATE_CPU.
804 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
807 * sim-main.h (signal_exception): Add sim_cpu arg.
808 (SignalException*): Pass both SD and CPU to signal_exception.
809 * interp.c (signal_exception): Update.
811 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
813 (sync_operation, prefetch, cache_op, store_memory, load_memory,
814 address_translation): Ditto
815 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
817 start-sanitize-vr5400
818 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
820 (ByteAlign): Use StoreFPR, pass args in correct order.
824 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
826 * configure.in (sim_igen_filter): For r5900, configure as SMP.
829 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
831 * configure: Regenerated to track ../common/aclocal.m4 changes.
833 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
836 * configure.in (sim_igen_filter): For r5900, use igen.
837 * configure: Re-generate.
840 * interp.c (sim_engine_run): Add `nr_cpus' argument.
842 * mips.igen (model): Map processor names onto BFD name.
844 * sim-main.h (CPU_CIA): Delete.
845 (SET_CIA, GET_CIA): Define
847 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
849 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
852 * configure.in (default_endian): Configure a big-endian simulator
854 * configure: Re-generate.
856 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
858 * configure: Regenerated to track ../common/aclocal.m4 changes.
860 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
862 * interp.c (sim_monitor): Handle Densan monitor outbyte
863 and inbyte functions.
865 1997-12-29 Felix Lee <flee@cygnus.com>
867 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
869 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
871 * Makefile.in (tmp-igen): Arrange for $zero to always be
872 reset to zero after every instruction.
874 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
876 * configure: Regenerated to track ../common/aclocal.m4 changes.
879 start-sanitize-vr5400
880 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
882 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
886 start-sanitize-vr5400
887 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
889 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
890 vr5400 with the vr5000 as the default.
893 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
895 * mips.igen (MSUB): Fix to work like MADD.
896 * gencode.c (MSUB): Similarly.
898 start-sanitize-vr5400
899 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
901 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
905 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
907 * configure: Regenerated to track ../common/aclocal.m4 changes.
909 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
911 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
913 start-sanitize-vr5400
914 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
915 (value_cc, store_cc): Implement.
917 * sim-main.h: Add 8*3*8 bit accumulator.
919 * vr5400.igen: Move mdmx instructins from here
920 * mdmx.igen: To here - new file. Add/fix missing instructions.
921 * mips.igen: Include mdmx.igen.
922 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
925 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
927 * sim-main.h (sim-fpu.h): Include.
929 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
930 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
931 using host independant sim_fpu module.
933 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
935 * interp.c (signal_exception): Report internal errors with SIGABRT
938 * sim-main.h (C0_CONFIG): New register.
939 (signal.h): No longer include.
941 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
943 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
945 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
947 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
949 * mips.igen: Tag vr5000 instructions.
950 (ANDI): Was missing mipsIV model, fix assembler syntax.
951 (do_c_cond_fmt): New function.
952 (C.cond.fmt): Handle mips I-III which do not support CC field
954 (bc1): Handle mips IV which do not have a delaed FCC separatly.
955 (SDR): Mask paddr when BigEndianMem, not the converse as specified
957 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
958 vr5000 which saves LO in a GPR separatly.
960 * configure.in (enable-sim-igen): For vr5000, select vr5000
961 specific instructions.
962 * configure: Re-generate.
964 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
966 * Makefile.in (SIM_OBJS): Add sim-fpu module.
968 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
969 fmt_uninterpreted_64 bit cases to switch. Convert to
972 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
974 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
975 as specified in IV3.2 spec.
976 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
978 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
980 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
981 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
982 (start-sanitize-r5900):
983 (LWXC1, SWXC1): Delete from r5900 instruction set.
984 (end-sanitize-r5900):
985 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
986 PENDING_FILL versions of instructions. Simplify.
988 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
990 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
992 (MTHI, MFHI): Disable code checking HI-LO.
994 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
996 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
998 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1000 * gencode.c (build_mips16_operands): Replace IPC with cia.
1002 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1003 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1005 (UndefinedResult): Replace function with macro/function
1007 (sim_engine_run): Don't save PC in IPC.
1009 * sim-main.h (IPC): Delete.
1011 start-sanitize-vr5400
1012 * vr5400.igen (vr): Add missing cia argument to value_fpr.
1013 (do_select): Rename function select.
1016 * interp.c (signal_exception, store_word, load_word,
1017 address_translation, load_memory, store_memory, cache_op,
1018 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1019 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1020 current instruction address - cia - argument.
1021 (sim_read, sim_write): Call address_translation directly.
1022 (sim_engine_run): Rename variable vaddr to cia.
1023 (signal_exception): Pass cia to sim_monitor
1025 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1026 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1027 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1029 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1030 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1033 * interp.c (signal_exception): Pass restart address to
1036 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1037 idecode.o): Add dependency.
1039 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1041 (DELAY_SLOT): Update NIA not PC with branch address.
1042 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1044 * mips.igen: Use CIA not PC in branch calculations.
1045 (illegal): Call SignalException.
1046 (BEQ, ADDIU): Fix assembler.
1048 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1050 * m16.igen (JALX): Was missing.
1052 * configure.in (enable-sim-igen): New configuration option.
1053 * configure: Re-generate.
1055 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1057 * interp.c (load_memory, store_memory): Delete parameter RAW.
1058 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1059 bypassing {load,store}_memory.
1061 * sim-main.h (ByteSwapMem): Delete definition.
1063 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1065 * interp.c (sim_do_command, sim_commands): Delete mips specific
1066 commands. Handled by module sim-options.
1068 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1069 (WITH_MODULO_MEMORY): Define.
1071 * interp.c (sim_info): Delete code printing memory size.
1073 * interp.c (mips_size): Nee sim_size, delete function.
1075 (monitor, monitor_base, monitor_size): Delete global variables.
1076 (sim_open, sim_close): Delete code creating monitor and other
1077 memory regions. Use sim-memopts module, via sim_do_commandf, to
1078 manage memory regions.
1079 (load_memory, store_memory): Use sim-core for memory model.
1081 * interp.c (address_translation): Delete all memory map code
1082 except line forcing 32 bit addresses.
1084 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1086 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1089 * interp.c (logfh, logfile): Delete globals.
1090 (sim_open, sim_close): Delete code opening & closing log file.
1091 (mips_option_handler): Delete -l and -n options.
1092 (OPTION mips_options): Ditto.
1094 * interp.c (OPTION mips_options): Rename option trace to dinero.
1095 (mips_option_handler): Update.
1097 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1099 * interp.c (fetch_str): New function.
1100 (sim_monitor): Rewrite using sim_read & sim_write.
1101 (sim_open): Check magic number.
1102 (sim_open): Write monitor vectors into memory using sim_write.
1103 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1104 (sim_read, sim_write): Simplify - transfer data one byte at a
1106 (load_memory, store_memory): Clarify meaning of parameter RAW.
1108 * sim-main.h (isHOST): Defete definition.
1109 (isTARGET): Mark as depreciated.
1110 (address_translation): Delete parameter HOST.
1112 * interp.c (address_translation): Delete parameter HOST.
1115 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
1117 * gencode.c: Add tx49 configury and insns.
1118 * configure.in: Add tx49 configury.
1119 * configure: Update.
1122 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1126 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1127 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1129 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1131 * mips.igen: Add model filter field to records.
1133 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1135 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1137 interp.c (sim_engine_run): Do not compile function sim_engine_run
1138 when WITH_IGEN == 1.
1140 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1141 target architecture.
1143 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1144 igen. Replace with configuration variables sim_igen_flags /
1147 start-sanitize-r5900
1148 * r5900.igen: New file. Copy r5900 insns here.
1150 start-sanitize-vr5400
1151 * vr5400.igen: New file.
1153 * m16.igen: New file. Copy mips16 insns here.
1154 * mips.igen: From here.
1156 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1158 start-sanitize-vr5400
1159 * mips.igen: Tag all mipsIV instructions with vr5400 model.
1161 * configure.in: Add mips64vr5400 target.
1162 * configure: Re-generate.
1165 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1167 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1169 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1171 * gencode.c (build_instruction): Follow sim_write's lead in using
1172 BigEndianMem instead of !ByteSwapMem.
1174 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1176 * configure.in (sim_gen): Dependent on target, select type of
1177 generator. Always select old style generator.
1179 configure: Re-generate.
1181 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1183 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1184 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1185 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1186 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1187 SIM_@sim_gen@_*, set by autoconf.
1189 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1191 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1193 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1194 CURRENT_FLOATING_POINT instead.
1196 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1197 (address_translation): Raise exception InstructionFetch when
1198 translation fails and isINSTRUCTION.
1200 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1201 sim_engine_run): Change type of of vaddr and paddr to
1203 (address_translation, prefetch, load_memory, store_memory,
1204 cache_op): Change type of vAddr and pAddr to address_word.
1206 * gencode.c (build_instruction): Change type of vaddr and paddr to
1209 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1211 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1212 macro to obtain result of ALU op.
1214 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1216 * interp.c (sim_info): Call profile_print.
1218 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1220 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1222 * sim-main.h (WITH_PROFILE): Do not define, defined in
1223 common/sim-config.h. Use sim-profile module.
1224 (simPROFILE): Delete defintion.
1226 * interp.c (PROFILE): Delete definition.
1227 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1228 (sim_close): Delete code writing profile histogram.
1229 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1231 (sim_engine_run): Delete code profiling the PC.
1233 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1235 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1237 * interp.c (sim_monitor): Make register pointers of type
1240 * sim-main.h: Make registers of type unsigned_word not
1243 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1245 start-sanitize-r5900
1246 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1247 ...): Move to sim-main.h
1250 * interp.c (sync_operation): Rename from SyncOperation, make
1251 global, add SD argument.
1252 (prefetch): Rename from Prefetch, make global, add SD argument.
1253 (decode_coproc): Make global.
1255 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1257 * gencode.c (build_instruction): Generate DecodeCoproc not
1258 decode_coproc calls.
1260 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1261 (SizeFGR): Move to sim-main.h
1262 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1263 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1264 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1266 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1267 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1268 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1269 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1270 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1271 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1273 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1275 (sim-alu.h): Include.
1276 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1277 (sim_cia): Typedef to instruction_address.
1279 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1281 * Makefile.in (interp.o): Rename generated file engine.c to
1286 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1288 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1290 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1292 * gencode.c (build_instruction): For "FPSQRT", output correct
1293 number of arguments to Recip.
1295 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1297 * Makefile.in (interp.o): Depends on sim-main.h
1299 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1301 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1302 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1303 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1304 STATE, DSSTATE): Define
1305 (GPR, FGRIDX, ..): Define.
1307 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1308 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1309 (GPR, FGRIDX, ...): Delete macros.
1311 * interp.c: Update names to match defines from sim-main.h
1313 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1315 * interp.c (sim_monitor): Add SD argument.
1316 (sim_warning): Delete. Replace calls with calls to
1318 (sim_error): Delete. Replace calls with sim_io_error.
1319 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1320 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1321 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1323 (mips_size): Rename from sim_size. Add SD argument.
1325 * interp.c (simulator): Delete global variable.
1326 (callback): Delete global variable.
1327 (mips_option_handler, sim_open, sim_write, sim_read,
1328 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1329 sim_size,sim_monitor): Use sim_io_* not callback->*.
1330 (sim_open): ZALLOC simulator struct.
1331 (PROFILE): Do not define.
1333 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1335 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1336 support.h with corresponding code.
1338 * sim-main.h (word64, uword64), support.h: Move definition to
1340 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1343 * Makefile.in: Update dependencies
1344 * interp.c: Do not include.
1346 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1348 * interp.c (address_translation, load_memory, store_memory,
1349 cache_op): Rename to from AddressTranslation et.al., make global,
1352 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1355 * interp.c (SignalException): Rename to signal_exception, make
1358 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1360 * sim-main.h (SignalException, SignalExceptionInterrupt,
1361 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1362 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1363 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1366 * interp.c, support.h: Use.
1368 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1370 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1371 to value_fpr / store_fpr. Add SD argument.
1372 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1373 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1375 * sim-main.h (ValueFPR, StoreFPR): Define.
1377 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1379 * interp.c (sim_engine_run): Check consistency between configure
1380 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1383 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1384 (mips_fpu): Configure WITH_FLOATING_POINT.
1385 (mips_endian): Configure WITH_TARGET_ENDIAN.
1386 * configure: Update.
1388 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1390 * configure: Regenerated to track ../common/aclocal.m4 changes.
1392 start-sanitize-r5900
1393 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1395 * interp.c (MAX_REG): Allow up-to 128 registers.
1396 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1397 (REGISTER_SA): Ditto.
1398 (sim_open): Initialize register_widths for r5900 specific
1400 (sim_fetch_register, sim_store_register): Check for request of
1401 r5900 specific SA register. Check for request for hi 64 bits of
1402 r5900 specific registers.
1405 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1407 * configure: Regenerated.
1409 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1411 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1413 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1415 * gencode.c (print_igen_insn_models): Assume certain architectures
1416 include all mips* instructions.
1417 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1420 * Makefile.in (tmp.igen): Add target. Generate igen input from
1423 * gencode.c (FEATURE_IGEN): Define.
1424 (main): Add --igen option. Generate output in igen format.
1425 (process_instructions): Format output according to igen option.
1426 (print_igen_insn_format): New function.
1427 (print_igen_insn_models): New function.
1428 (process_instructions): Only issue warnings and ignore
1429 instructions when no FEATURE_IGEN.
1431 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1433 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1436 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1438 * configure: Regenerated to track ../common/aclocal.m4 changes.
1440 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1442 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1443 SIM_RESERVED_BITS): Delete, moved to common.
1444 (SIM_EXTRA_CFLAGS): Update.
1446 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1448 * configure.in: Configure non-strict memory alignment.
1449 * configure: Regenerated to track ../common/aclocal.m4 changes.
1451 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1453 * configure: Regenerated to track ../common/aclocal.m4 changes.
1455 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1457 * gencode.c (SDBBP,DERET): Added (3900) insns.
1458 (RFE): Turn on for 3900.
1459 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1460 (dsstate): Made global.
1461 (SUBTARGET_R3900): Added.
1462 (CANCELDELAYSLOT): New.
1463 (SignalException): Ignore SystemCall rather than ignore and
1464 terminate. Add DebugBreakPoint handling.
1465 (decode_coproc): New insns RFE, DERET; and new registers Debug
1466 and DEPC protected by SUBTARGET_R3900.
1467 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1469 * Makefile.in,configure.in: Add mips subtarget option.
1470 * configure: Update.
1472 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1474 * gencode.c: Add r3900 (tx39).
1477 * gencode.c: Fix some configuration problems by improving
1478 the relationship between tx19 and tx39.
1481 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1483 * gencode.c (build_instruction): Don't need to subtract 4 for
1486 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1488 * interp.c: Correct some HASFPU problems.
1490 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1492 * configure: Regenerated to track ../common/aclocal.m4 changes.
1494 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1496 * interp.c (mips_options): Fix samples option short form, should
1499 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1501 * interp.c (sim_info): Enable info code. Was just returning.
1503 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1505 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1508 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1510 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1512 (build_instruction): Ditto for LL.
1515 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1517 * mips/configure.in, mips/gencode: Add tx19/r1900.
1520 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1522 * configure: Regenerated to track ../common/aclocal.m4 changes.
1524 start-sanitize-r5900
1525 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1527 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1528 for overflow due to ABS of MININT, set result to MAXINT.
1529 (build_instruction): For "psrlvw", signextend bit 31.
1532 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1534 * configure: Regenerated to track ../common/aclocal.m4 changes.
1537 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1539 * interp.c (sim_open): Add call to sim_analyze_program, update
1542 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1544 * interp.c (sim_kill): Delete.
1545 (sim_create_inferior): Add ABFD argument. Set PC from same.
1546 (sim_load): Move code initializing trap handlers from here.
1547 (sim_open): To here.
1548 (sim_load): Delete, use sim-hload.c.
1550 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1552 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1554 * configure: Regenerated to track ../common/aclocal.m4 changes.
1557 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1559 * interp.c (sim_open): Add ABFD argument.
1560 (sim_load): Move call to sim_config from here.
1561 (sim_open): To here. Check return status.
1563 start-sanitize-r5900
1564 * gencode.c (build_instruction): Do not define x8000000000000000,
1565 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1568 start-sanitize-r5900
1569 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1571 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1572 "pdivuw" check for overflow due to signed divide by -1.
1575 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1577 * gencode.c (build_instruction): Two arg MADD should
1578 not assign result to $0.
1580 start-sanitize-r5900
1581 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1583 * gencode.c (build_instruction): For "ppac5" use unsigned
1584 arrithmetic so that the sign bit doesn't smear when right shifted.
1585 (build_instruction): For "pdiv" perform sign extension when
1586 storing results in HI and LO.
1587 (build_instructions): For "pdiv" and "pdivbw" check for
1589 (build_instruction): For "pmfhl.slw" update hi part of dest
1590 register as well as low part.
1591 (build_instruction): For "pmfhl" portably handle long long values.
1592 (build_instruction): For "pmfhl.sh" correctly negative values.
1593 Store half words 2 and three in the correct place.
1594 (build_instruction): For "psllvw", sign extend value after shift.
1597 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1599 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1600 * sim/mips/configure.in: Regenerate.
1602 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1604 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1605 signed8, unsigned8 et.al. types.
1607 start-sanitize-r5900
1608 * gencode.c (build_instruction): For PMULTU* do not sign extend
1609 registers. Make generated code easier to debug.
1612 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1613 hosts when selecting subreg.
1615 start-sanitize-r5900
1616 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1618 * gencode.c (type_for_data_len): For 32bit operations concerned
1619 with overflow, perform op using 64bits.
1620 (build_instruction): For PADD, always compute operation using type
1621 returned by type_for_data_len.
1622 (build_instruction): For PSUBU, when overflow, saturate to zero as
1626 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1628 start-sanitize-r5900
1629 * gencode.c (build_instruction): Handle "pext5" according to
1630 version 1.95 of the r5900 ISA.
1632 * gencode.c (build_instruction): Handle "ppac5" according to
1633 version 1.95 of the r5900 ISA.
1636 * interp.c (sim_engine_run): Reset the ZERO register to zero
1637 regardless of FEATURE_WARN_ZERO.
1638 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1640 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1642 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1643 (SignalException): For BreakPoints ignore any mode bits and just
1645 (SignalException): Always set the CAUSE register.
1647 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1649 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1650 exception has been taken.
1652 * interp.c: Implement the ERET and mt/f sr instructions.
1654 start-sanitize-r5900
1655 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
1657 * gencode.c (build_instruction): For paddu, extract unsigned
1660 * gencode.c (build_instruction): Saturate padds instead of padd
1664 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1666 * interp.c (SignalException): Don't bother restarting an
1669 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1671 * interp.c (SignalException): Really take an interrupt.
1672 (interrupt_event): Only deliver interrupts when enabled.
1674 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1676 * interp.c (sim_info): Only print info when verbose.
1677 (sim_info) Use sim_io_printf for output.
1679 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1681 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1684 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1686 * interp.c (sim_do_command): Check for common commands if a
1687 simulator specific command fails.
1689 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1691 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1692 and simBE when DEBUG is defined.
1694 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1696 * interp.c (interrupt_event): New function. Pass exception event
1697 onto exception handler.
1699 * configure.in: Check for stdlib.h.
1700 * configure: Regenerate.
1702 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1703 variable declaration.
1704 (build_instruction): Initialize memval1.
1705 (build_instruction): Add UNUSED attribute to byte, bigend,
1707 (build_operands): Ditto.
1709 * interp.c: Fix GCC warnings.
1710 (sim_get_quit_code): Delete.
1712 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1713 * Makefile.in: Ditto.
1714 * configure: Re-generate.
1716 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1718 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1720 * interp.c (mips_option_handler): New function parse argumes using
1722 (myname): Replace with STATE_MY_NAME.
1723 (sim_open): Delete check for host endianness - performed by
1725 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1726 (sim_open): Move much of the initialization from here.
1727 (sim_load): To here. After the image has been loaded and
1729 (sim_open): Move ColdReset from here.
1730 (sim_create_inferior): To here.
1731 (sim_open): Make FP check less dependant on host endianness.
1733 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1735 * interp.c (sim_set_callbacks): Delete.
1737 * interp.c (membank, membank_base, membank_size): Replace with
1738 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1739 (sim_open): Remove call to callback->init. gdb/run do this.
1743 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1745 * interp.c (big_endian_p): Delete, replaced by
1746 current_target_byte_order.
1748 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1750 * interp.c (host_read_long, host_read_word, host_swap_word,
1751 host_swap_long): Delete. Using common sim-endian.
1752 (sim_fetch_register, sim_store_register): Use H2T.
1753 (pipeline_ticks): Delete. Handled by sim-events.
1755 (sim_engine_run): Update.
1757 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1759 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1761 (SignalException): To here. Signal using sim_engine_halt.
1762 (sim_stop_reason): Delete, moved to common.
1764 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1766 * interp.c (sim_open): Add callback argument.
1767 (sim_set_callbacks): Delete SIM_DESC argument.
1770 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1772 * Makefile.in (SIM_OBJS): Add common modules.
1774 * interp.c (sim_set_callbacks): Also set SD callback.
1775 (set_endianness, xfer_*, swap_*): Delete.
1776 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1777 Change to functions using sim-endian macros.
1778 (control_c, sim_stop): Delete, use common version.
1779 (simulate): Convert into.
1780 (sim_engine_run): This function.
1781 (sim_resume): Delete.
1783 * interp.c (simulation): New variable - the simulator object.
1784 (sim_kind): Delete global - merged into simulation.
1785 (sim_load): Cleanup. Move PC assignment from here.
1786 (sim_create_inferior): To here.
1788 * sim-main.h: New file.
1789 * interp.c (sim-main.h): Include.
1791 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1793 * configure: Regenerated to track ../common/aclocal.m4 changes.
1795 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1797 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1799 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1801 * gencode.c (build_instruction): DIV instructions: check
1802 for division by zero and integer overflow before using
1803 host's division operation.
1805 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1807 * Makefile.in (SIM_OBJS): Add sim-load.o.
1808 * interp.c: #include bfd.h.
1809 (target_byte_order): Delete.
1810 (sim_kind, myname, big_endian_p): New static locals.
1811 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1812 after argument parsing. Recognize -E arg, set endianness accordingly.
1813 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1814 load file into simulator. Set PC from bfd.
1815 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1816 (set_endianness): Use big_endian_p instead of target_byte_order.
1818 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1820 * interp.c (sim_size): Delete prototype - conflicts with
1821 definition in remote-sim.h. Correct definition.
1823 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1825 * configure: Regenerated to track ../common/aclocal.m4 changes.
1828 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1830 * interp.c (sim_open): New arg `kind'.
1832 * configure: Regenerated to track ../common/aclocal.m4 changes.
1834 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1836 * configure: Regenerated to track ../common/aclocal.m4 changes.
1838 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1840 * interp.c (sim_open): Set optind to 0 before calling getopt.
1842 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1844 * configure: Regenerated to track ../common/aclocal.m4 changes.
1846 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1848 * interp.c : Replace uses of pr_addr with pr_uword64
1849 where the bit length is always 64 independent of SIM_ADDR.
1850 (pr_uword64) : added.
1852 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1854 * configure: Re-generate.
1856 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1858 * configure: Regenerate to track ../common/aclocal.m4 changes.
1860 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1862 * interp.c (sim_open): New SIM_DESC result. Argument is now
1864 (other sim_*): New SIM_DESC argument.
1866 start-sanitize-r5900
1867 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
1869 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
1870 Change values to avoid overloading DOUBLEWORD which is tested
1872 * gencode.c: reinstate "offending code".
1875 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1877 * interp.c: Fix printing of addresses for non-64-bit targets.
1878 (pr_addr): Add function to print address based on size.
1879 start-sanitize-r5900
1880 * gencode.c: #ifdef out offending code until a permanent fix
1881 can be added. Code is causing build errors for non-5900 mips targets.
1884 start-sanitize-r5900
1885 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
1887 * gencode.c (process_instructions): Correct test for ISA dependent
1888 architecture bits in isa field of MIPS_DECODE.
1891 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1893 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1895 start-sanitize-r5900
1896 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
1898 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
1902 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1904 * gencode.c (build_mips16_operands): Correct computation of base
1905 address for extended PC relative instruction.
1907 start-sanitize-r5900
1908 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
1910 * Makefile.in, configure, configure.in, gencode.c,
1911 interp.c, support.h: add r5900.
1914 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1916 * interp.c (mips16_entry): Add support for floating point cases.
1917 (SignalException): Pass floating point cases to mips16_entry.
1918 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1920 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1922 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1923 and then set the state to fmt_uninterpreted.
1924 (COP_SW): Temporarily set the state to fmt_word while calling
1927 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1929 * gencode.c (build_instruction): The high order may be set in the
1930 comparison flags at any ISA level, not just ISA 4.
1932 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1934 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1935 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1936 * configure.in: sinclude ../common/aclocal.m4.
1937 * configure: Regenerated.
1939 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1941 * configure: Rebuild after change to aclocal.m4.
1943 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1945 * configure configure.in Makefile.in: Update to new configure
1946 scheme which is more compatible with WinGDB builds.
1947 * configure.in: Improve comment on how to run autoconf.
1948 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1949 * Makefile.in: Use autoconf substitution to install common
1952 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1954 * gencode.c (build_instruction): Use BigEndianCPU instead of
1957 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1959 * interp.c (sim_monitor): Make output to stdout visible in
1960 wingdb's I/O log window.
1962 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1964 * support.h: Undo previous change to SIGTRAP
1967 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1969 * interp.c (store_word, load_word): New static functions.
1970 (mips16_entry): New static function.
1971 (SignalException): Look for mips16 entry and exit instructions.
1972 (simulate): Use the correct index when setting fpr_state after
1973 doing a pending move.
1975 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1977 * interp.c: Fix byte-swapping code throughout to work on
1978 both little- and big-endian hosts.
1980 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1982 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1983 with gdb/config/i386/xm-windows.h.
1985 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1987 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1988 that messes up arithmetic shifts.
1990 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1992 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1993 SIGTRAP and SIGQUIT for _WIN32.
1995 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1997 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1998 force a 64 bit multiplication.
1999 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2000 destination register is 0, since that is the default mips16 nop
2003 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2005 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2006 (build_endian_shift): Don't check proc64.
2007 (build_instruction): Always set memval to uword64. Cast op2 to
2008 uword64 when shifting it left in memory instructions. Always use
2009 the same code for stores--don't special case proc64.
2011 * gencode.c (build_mips16_operands): Fix base PC value for PC
2013 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2015 * interp.c (simJALDELAYSLOT): Define.
2016 (JALDELAYSLOT): Define.
2017 (INDELAYSLOT, INJALDELAYSLOT): Define.
2018 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2020 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2022 * interp.c (sim_open): add flush_cache as a PMON routine
2023 (sim_monitor): handle flush_cache by ignoring it
2025 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2027 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2029 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2030 (BigEndianMem): Rename to ByteSwapMem and change sense.
2031 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2032 BigEndianMem references to !ByteSwapMem.
2033 (set_endianness): New function, with prototype.
2034 (sim_open): Call set_endianness.
2035 (sim_info): Use simBE instead of BigEndianMem.
2036 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2037 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2038 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2039 ifdefs, keeping the prototype declaration.
2040 (swap_word): Rewrite correctly.
2041 (ColdReset): Delete references to CONFIG. Delete endianness related
2042 code; moved to set_endianness.
2044 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2046 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2047 * interp.c (CHECKHILO): Define away.
2048 (simSIGINT): New macro.
2049 (membank_size): Increase from 1MB to 2MB.
2050 (control_c): New function.
2051 (sim_resume): Rename parameter signal to signal_number. Add local
2052 variable prev. Call signal before and after simulate.
2053 (sim_stop_reason): Add simSIGINT support.
2054 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2056 (sim_warning): Delete call to SignalException. Do call printf_filtered
2058 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2059 a call to sim_warning.
2061 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2063 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2064 16 bit instructions.
2066 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2068 Add support for mips16 (16 bit MIPS implementation):
2069 * gencode.c (inst_type): Add mips16 instruction encoding types.
2070 (GETDATASIZEINSN): Define.
2071 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2072 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2074 (MIPS16_DECODE): New table, for mips16 instructions.
2075 (bitmap_val): New static function.
2076 (struct mips16_op): Define.
2077 (mips16_op_table): New table, for mips16 operands.
2078 (build_mips16_operands): New static function.
2079 (process_instructions): If PC is odd, decode a mips16
2080 instruction. Break out instruction handling into new
2081 build_instruction function.
2082 (build_instruction): New static function, broken out of
2083 process_instructions. Check modifiers rather than flags for SHIFT
2084 bit count and m[ft]{hi,lo} direction.
2085 (usage): Pass program name to fprintf.
2086 (main): Remove unused variable this_option_optind. Change
2087 ``*loptarg++'' to ``loptarg++''.
2088 (my_strtoul): Parenthesize && within ||.
2089 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2090 (simulate): If PC is odd, fetch a 16 bit instruction, and
2091 increment PC by 2 rather than 4.
2092 * configure.in: Add case for mips16*-*-*.
2093 * configure: Rebuild.
2095 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2097 * interp.c: Allow -t to enable tracing in standalone simulator.
2098 Fix garbage output in trace file and error messages.
2100 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2102 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2103 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2104 * configure.in: Simplify using macros in ../common/aclocal.m4.
2105 * configure: Regenerated.
2106 * tconfig.in: New file.
2108 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2110 * interp.c: Fix bugs in 64-bit port.
2111 Use ansi function declarations for msvc compiler.
2112 Initialize and test file pointer in trace code.
2113 Prevent duplicate definition of LAST_EMED_REGNUM.
2115 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2117 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2119 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2121 * interp.c (SignalException): Check for explicit terminating
2123 * gencode.c: Pass instruction value through SignalException()
2124 calls for Trap, Breakpoint and Syscall.
2126 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2128 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2129 only used on those hosts that provide it.
2130 * configure.in: Add sqrt() to list of functions to be checked for.
2131 * config.in: Re-generated.
2132 * configure: Re-generated.
2134 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2136 * gencode.c (process_instructions): Call build_endian_shift when
2137 expanding STORE RIGHT, to fix swr.
2138 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2139 clear the high bits.
2140 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2141 Fix float to int conversions to produce signed values.
2143 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2145 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2146 (process_instructions): Correct handling of nor instruction.
2147 Correct shift count for 32 bit shift instructions. Correct sign
2148 extension for arithmetic shifts to not shift the number of bits in
2149 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2150 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2152 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2153 It's OK to have a mult follow a mult. What's not OK is to have a
2154 mult follow an mfhi.
2155 (Convert): Comment out incorrect rounding code.
2157 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2159 * interp.c (sim_monitor): Improved monitor printf
2160 simulation. Tidied up simulator warnings, and added "--log" option
2161 for directing warning message output.
2162 * gencode.c: Use sim_warning() rather than WARNING macro.
2164 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2166 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2167 getopt1.o, rather than on gencode.c. Link objects together.
2168 Don't link against -liberty.
2169 (gencode.o, getopt.o, getopt1.o): New targets.
2170 * gencode.c: Include <ctype.h> and "ansidecl.h".
2171 (AND): Undefine after including "ansidecl.h".
2172 (ULONG_MAX): Define if not defined.
2173 (OP_*): Don't define macros; now defined in opcode/mips.h.
2174 (main): Call my_strtoul rather than strtoul.
2175 (my_strtoul): New static function.
2177 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2179 * gencode.c (process_instructions): Generate word64 and uword64
2180 instead of `long long' and `unsigned long long' data types.
2181 * interp.c: #include sysdep.h to get signals, and define default
2183 * (Convert): Work around for Visual-C++ compiler bug with type
2185 * support.h: Make things compile under Visual-C++ by using
2186 __int64 instead of `long long'. Change many refs to long long
2187 into word64/uword64 typedefs.
2189 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2191 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2192 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2194 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2195 (AC_PROG_INSTALL): Added.
2196 (AC_PROG_CC): Moved to before configure.host call.
2197 * configure: Rebuilt.
2199 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2201 * configure.in: Define @SIMCONF@ depending on mips target.
2202 * configure: Rebuild.
2203 * Makefile.in (run): Add @SIMCONF@ to control simulator
2205 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2206 * interp.c: Remove some debugging, provide more detailed error
2207 messages, update memory accesses to use LOADDRMASK.
2209 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2211 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2212 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2214 * configure: Rebuild.
2215 * config.in: New file, generated by autoheader.
2216 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2217 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2218 HAVE_ANINT and HAVE_AINT, as appropriate.
2219 * Makefile.in (run): Use @LIBS@ rather than -lm.
2220 (interp.o): Depend upon config.h.
2221 (Makefile): Just rebuild Makefile.
2222 (clean): Remove stamp-h.
2223 (mostlyclean): Make the same as clean, not as distclean.
2224 (config.h, stamp-h): New targets.
2226 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2228 * interp.c (ColdReset): Fix boolean test. Make all simulator
2231 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2233 * interp.c (xfer_direct_word, xfer_direct_long,
2234 swap_direct_word, swap_direct_long, xfer_big_word,
2235 xfer_big_long, xfer_little_word, xfer_little_long,
2236 swap_word,swap_long): Added.
2237 * interp.c (ColdReset): Provide function indirection to
2238 host<->simulated_target transfer routines.
2239 * interp.c (sim_store_register, sim_fetch_register): Updated to
2240 make use of indirected transfer routines.
2242 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2244 * gencode.c (process_instructions): Ensure FP ABS instruction
2246 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2247 system call support.
2249 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2251 * interp.c (sim_do_command): Complain if callback structure not
2254 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2256 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2257 support for Sun hosts.
2258 * Makefile.in (gencode): Ensure the host compiler and libraries
2259 used for cross-hosted build.
2261 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2263 * interp.c, gencode.c: Some more (TODO) tidying.
2265 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2267 * gencode.c, interp.c: Replaced explicit long long references with
2268 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2269 * support.h (SET64LO, SET64HI): Macros added.
2271 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2273 * configure: Regenerate with autoconf 2.7.
2275 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2277 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2278 * support.h: Remove superfluous "1" from #if.
2279 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2281 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2283 * interp.c (StoreFPR): Control UndefinedResult() call on
2284 WARN_RESULT manifest.
2286 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2288 * gencode.c: Tidied instruction decoding, and added FP instruction
2291 * interp.c: Added dineroIII, and BSD profiling support. Also
2292 run-time FP handling.
2294 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2296 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2297 gencode.c, interp.c, support.h: created.