1 2002-07-30 Chris Demetriou <cgd@broadcom.com>
3 * mips.igen (do_load_double, do_store_double): New functions.
4 (LDC1, SDC1): Rename to...
5 (LDC1b, SDC1b): respectively.
6 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
8 2002-07-29 Michael Snyder <msnyder@redhat.com>
10 * cp1.c (fp_recip2): Modify initialization expression so that
11 GCC will recognize it as constant.
13 2002-06-18 Chris Demetriou <cgd@broadcom.com>
15 * mdmx.c (SD_): Delete.
16 (Unpredictable): Re-define, for now, to directly invoke
17 unpredictable_action().
18 (mdmx_acc_op): Fix error in .ob immediate handling.
20 2002-06-18 Andrew Cagney <cagney@redhat.com>
22 * interp.c (sim_firmware_command): Initialize `address'.
24 2002-06-16 Andrew Cagney <ac131313@redhat.com>
26 * configure: Regenerated to track ../common/aclocal.m4 changes.
28 2002-06-14 Chris Demetriou <cgd@broadcom.com>
29 Ed Satterthwaite <ehs@broadcom.com>
31 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
32 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
33 * mips.igen: Include mips3d.igen.
34 (mips3d): New model name for MIPS-3D ASE instructions.
35 (CVT.W.fmt): Don't use this instruction for word (source) format
37 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
38 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
39 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
40 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
41 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
42 (RSquareRoot1, RSquareRoot2): New macros.
43 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
44 (fp_rsqrt2): New functions.
45 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
46 * configure: Regenerate.
48 2002-06-13 Chris Demetriou <cgd@broadcom.com>
49 Ed Satterthwaite <ehs@broadcom.com>
51 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
52 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
53 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
54 (convert): Note that this function is not used for paired-single
56 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
57 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
58 (check_fmt_p): Enable paired-single support.
59 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
60 (PUU.PS): New instructions.
61 (CVT.S.fmt): Don't use this instruction for paired-single format
63 * sim-main.h (FP_formats): New value 'fmt_ps.'
64 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
65 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
67 2002-06-12 Chris Demetriou <cgd@broadcom.com>
69 * mips.igen: Fix formatting of function calls in
72 2002-06-12 Chris Demetriou <cgd@broadcom.com>
74 * mips.igen (MOVN, MOVZ): Trace result.
75 (TNEI): Print "tnei" as the opcode name in traces.
76 (CEIL.W): Add disassembly string for traces.
77 (RSQRT.fmt): Make location of disassembly string consistent
78 with other instructions.
80 2002-06-12 Chris Demetriou <cgd@broadcom.com>
82 * mips.igen (X): Delete unused function.
84 2002-06-08 Andrew Cagney <cagney@redhat.com>
86 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
88 2002-06-07 Chris Demetriou <cgd@broadcom.com>
89 Ed Satterthwaite <ehs@broadcom.com>
91 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
92 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
93 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
94 (fp_nmsub): New prototypes.
95 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
96 (NegMultiplySub): New defines.
97 * mips.igen (RSQRT.fmt): Use RSquareRoot().
98 (MADD.D, MADD.S): Replace with...
99 (MADD.fmt): New instruction.
100 (MSUB.D, MSUB.S): Replace with...
101 (MSUB.fmt): New instruction.
102 (NMADD.D, NMADD.S): Replace with...
103 (NMADD.fmt): New instruction.
104 (NMSUB.D, MSUB.S): Replace with...
105 (NMSUB.fmt): New instruction.
107 2002-06-07 Chris Demetriou <cgd@broadcom.com>
108 Ed Satterthwaite <ehs@broadcom.com>
110 * cp1.c: Fix more comment spelling and formatting.
111 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
112 (denorm_mode): New function.
113 (fpu_unary, fpu_binary): Round results after operation, collect
114 status from rounding operations, and update the FCSR.
115 (convert): Collect status from integer conversions and rounding
116 operations, and update the FCSR. Adjust NaN values that result
117 from conversions. Convert to use sim_io_eprintf rather than
118 fprintf, and remove some debugging code.
119 * cp1.h (fenr_FS): New define.
121 2002-06-07 Chris Demetriou <cgd@broadcom.com>
123 * cp1.c (convert): Remove unusable debugging code, and move MIPS
124 rounding mode to sim FP rounding mode flag conversion code into...
125 (rounding_mode): New function.
127 2002-06-07 Chris Demetriou <cgd@broadcom.com>
129 * cp1.c: Clean up formatting of a few comments.
130 (value_fpr): Reformat switch statement.
132 2002-06-06 Chris Demetriou <cgd@broadcom.com>
133 Ed Satterthwaite <ehs@broadcom.com>
136 * sim-main.h: Include cp1.h.
137 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
138 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
139 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
140 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
141 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
142 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
143 * cp1.c: Don't include sim-fpu.h; already included by
144 sim-main.h. Clean up formatting of some comments.
145 (NaN, Equal, Less): Remove.
146 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
147 (fp_cmp): New functions.
148 * mips.igen (do_c_cond_fmt): Remove.
149 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
150 Compare. Add result tracing.
151 (CxC1): Remove, replace with...
152 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
153 (DMxC1): Remove, replace with...
154 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
155 (MxC1): Remove, replace with...
156 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
158 2002-06-04 Chris Demetriou <cgd@broadcom.com>
160 * sim-main.h (FGRIDX): Remove, replace all uses with...
161 (FGR_BASE): New macro.
162 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
163 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
164 (NR_FGR, FGR): Likewise.
165 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
166 * mips.igen: Likewise.
168 2002-06-04 Chris Demetriou <cgd@broadcom.com>
170 * cp1.c: Add an FSF Copyright notice to this file.
172 2002-06-04 Chris Demetriou <cgd@broadcom.com>
173 Ed Satterthwaite <ehs@broadcom.com>
175 * cp1.c (Infinity): Remove.
176 * sim-main.h (Infinity): Likewise.
178 * cp1.c (fp_unary, fp_binary): New functions.
179 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
180 (fp_sqrt): New functions, implemented in terms of the above.
181 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
182 (Recip, SquareRoot): Remove (replaced by functions above).
183 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
184 (fp_recip, fp_sqrt): New prototypes.
185 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
186 (Recip, SquareRoot): Replace prototypes with #defines which
187 invoke the functions above.
189 2002-06-03 Chris Demetriou <cgd@broadcom.com>
191 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
192 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
193 file, remove PARAMS from prototypes.
194 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
195 simulator state arguments.
196 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
197 pass simulator state arguments.
198 * cp1.c (SD): Redefine as CPU_STATE(cpu).
199 (store_fpr, convert): Remove 'sd' argument.
200 (value_fpr): Likewise. Convert to use 'SD' instead.
202 2002-06-03 Chris Demetriou <cgd@broadcom.com>
204 * cp1.c (Min, Max): Remove #if 0'd functions.
205 * sim-main.h (Min, Max): Remove.
207 2002-06-03 Chris Demetriou <cgd@broadcom.com>
209 * cp1.c: fix formatting of switch case and default labels.
210 * interp.c: Likewise.
211 * sim-main.c: Likewise.
213 2002-06-03 Chris Demetriou <cgd@broadcom.com>
215 * cp1.c: Clean up comments which describe FP formats.
216 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
218 2002-06-03 Chris Demetriou <cgd@broadcom.com>
219 Ed Satterthwaite <ehs@broadcom.com>
221 * configure.in (mipsisa64sb1*-*-*): New target for supporting
222 Broadcom SiByte SB-1 processor configurations.
223 * configure: Regenerate.
224 * sb1.igen: New file.
225 * mips.igen: Include sb1.igen.
227 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
228 * mdmx.igen: Add "sb1" model to all appropriate functions and
230 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
231 (ob_func, ob_acc): Reference the above.
232 (qh_acc): Adjust to keep the same size as ob_acc.
233 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
234 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
236 2002-06-03 Chris Demetriou <cgd@broadcom.com>
238 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
240 2002-06-02 Chris Demetriou <cgd@broadcom.com>
241 Ed Satterthwaite <ehs@broadcom.com>
243 * mips.igen (mdmx): New (pseudo-)model.
244 * mdmx.c, mdmx.igen: New files.
245 * Makefile.in (SIM_OBJS): Add mdmx.o.
246 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
248 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
249 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
250 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
251 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
252 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
253 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
254 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
255 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
256 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
257 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
258 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
259 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
260 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
261 (qh_fmtsel): New macros.
262 (_sim_cpu): New member "acc".
263 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
264 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
266 2002-05-01 Chris Demetriou <cgd@broadcom.com>
268 * interp.c: Use 'deprecated' rather than 'depreciated.'
269 * sim-main.h: Likewise.
271 2002-05-01 Chris Demetriou <cgd@broadcom.com>
273 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
274 which wouldn't compile anyway.
275 * sim-main.h (unpredictable_action): New function prototype.
276 (Unpredictable): Define to call igen function unpredictable().
277 (NotWordValue): New macro to call igen function not_word_value().
278 (UndefinedResult): Remove.
279 * interp.c (undefined_result): Remove.
280 (unpredictable_action): New function.
281 * mips.igen (not_word_value, unpredictable): New functions.
282 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
283 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
284 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
285 NotWordValue() to check for unpredictable inputs, then
286 Unpredictable() to handle them.
288 2002-02-24 Chris Demetriou <cgd@broadcom.com>
290 * mips.igen: Fix formatting of calls to Unpredictable().
292 2002-04-20 Andrew Cagney <ac131313@redhat.com>
294 * interp.c (sim_open): Revert previous change.
296 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
298 * interp.c (sim_open): Disable chunk of code that wrote code in
299 vector table entries.
301 2002-03-19 Chris Demetriou <cgd@broadcom.com>
303 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
304 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
307 2002-03-19 Chris Demetriou <cgd@broadcom.com>
309 * cp1.c: Fix many formatting issues.
311 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
313 * cp1.c (fpu_format_name): New function to replace...
314 (DOFMT): This. Delete, and update all callers.
315 (fpu_rounding_mode_name): New function to replace...
316 (RMMODE): This. Delete, and update all callers.
318 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
320 * interp.c: Move FPU support routines from here to...
321 * cp1.c: Here. New file.
322 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
325 2002-03-12 Chris Demetriou <cgd@broadcom.com>
327 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
328 * mips.igen (mips32, mips64): New models, add to all instructions
329 and functions as appropriate.
330 (loadstore_ea, check_u64): New variant for model mips64.
331 (check_fmt_p): New variant for models mipsV and mips64, remove
332 mipsV model marking fro other variant.
335 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
336 for mips32 and mips64.
337 (DCLO, DCLZ): New instructions for mips64.
339 2002-03-07 Chris Demetriou <cgd@broadcom.com>
341 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
342 immediate or code as a hex value with the "%#lx" format.
343 (ANDI): Likewise, and fix printed instruction name.
345 2002-03-05 Chris Demetriou <cgd@broadcom.com>
347 * sim-main.h (UndefinedResult, Unpredictable): New macros
348 which currently do nothing.
350 2002-03-05 Chris Demetriou <cgd@broadcom.com>
352 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
353 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
354 (status_CU3): New definitions.
356 * sim-main.h (ExceptionCause): Add new values for MIPS32
357 and MIPS64: MDMX, MCheck, CacheErr. Update comments
358 for DebugBreakPoint and NMIReset to note their status in
360 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
361 (SignalExceptionCacheErr): New exception macros.
363 2002-03-05 Chris Demetriou <cgd@broadcom.com>
365 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
366 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
368 (SignalExceptionCoProcessorUnusable): Take as argument the
369 unusable coprocessor number.
371 2002-03-05 Chris Demetriou <cgd@broadcom.com>
373 * mips.igen: Fix formatting of all SignalException calls.
375 2002-03-05 Chris Demetriou <cgd@broadcom.com>
377 * sim-main.h (SIGNEXTEND): Remove.
379 2002-03-04 Chris Demetriou <cgd@broadcom.com>
381 * mips.igen: Remove gencode comment from top of file, fix
382 spelling in another comment.
384 2002-03-04 Chris Demetriou <cgd@broadcom.com>
386 * mips.igen (check_fmt, check_fmt_p): New functions to check
387 whether specific floating point formats are usable.
388 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
389 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
390 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
391 Use the new functions.
392 (do_c_cond_fmt): Remove format checks...
393 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
395 2002-03-03 Chris Demetriou <cgd@broadcom.com>
397 * mips.igen: Fix formatting of check_fpu calls.
399 2002-03-03 Chris Demetriou <cgd@broadcom.com>
401 * mips.igen (FLOOR.L.fmt): Store correct destination register.
403 2002-03-03 Chris Demetriou <cgd@broadcom.com>
405 * mips.igen: Remove whitespace at end of lines.
407 2002-03-02 Chris Demetriou <cgd@broadcom.com>
409 * mips.igen (loadstore_ea): New function to do effective
410 address calculations.
411 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
412 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
413 CACHE): Use loadstore_ea to do effective address computations.
415 2002-03-02 Chris Demetriou <cgd@broadcom.com>
417 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
418 * mips.igen (LL, CxC1, MxC1): Likewise.
420 2002-03-02 Chris Demetriou <cgd@broadcom.com>
422 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
423 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
424 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
425 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
426 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
427 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
428 Don't split opcode fields by hand, use the opcode field values
431 2002-03-01 Chris Demetriou <cgd@broadcom.com>
433 * mips.igen (do_divu): Fix spacing.
435 * mips.igen (do_dsllv): Move to be right before DSLLV,
436 to match the rest of the do_<shift> functions.
438 2002-03-01 Chris Demetriou <cgd@broadcom.com>
440 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
441 DSRL32, do_dsrlv): Trace inputs and results.
443 2002-03-01 Chris Demetriou <cgd@broadcom.com>
445 * mips.igen (CACHE): Provide instruction-printing string.
447 * interp.c (signal_exception): Comment tokens after #endif.
449 2002-02-28 Chris Demetriou <cgd@broadcom.com>
451 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
452 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
453 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
454 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
455 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
456 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
457 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
458 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
460 2002-02-28 Chris Demetriou <cgd@broadcom.com>
462 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
463 instruction-printing string.
464 (LWU): Use '64' as the filter flag.
466 2002-02-28 Chris Demetriou <cgd@broadcom.com>
468 * mips.igen (SDXC1): Fix instruction-printing string.
470 2002-02-28 Chris Demetriou <cgd@broadcom.com>
472 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
475 2002-02-27 Chris Demetriou <cgd@broadcom.com>
477 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
480 2002-02-27 Chris Demetriou <cgd@broadcom.com>
482 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
483 add a comma) so that it more closely match the MIPS ISA
484 documentation opcode partitioning.
485 (PREF): Put useful names on opcode fields, and include
486 instruction-printing string.
488 2002-02-27 Chris Demetriou <cgd@broadcom.com>
490 * mips.igen (check_u64): New function which in the future will
491 check whether 64-bit instructions are usable and signal an
492 exception if not. Currently a no-op.
493 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
494 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
495 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
496 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
498 * mips.igen (check_fpu): New function which in the future will
499 check whether FPU instructions are usable and signal an exception
500 if not. Currently a no-op.
501 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
502 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
503 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
504 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
505 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
506 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
507 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
508 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
510 2002-02-27 Chris Demetriou <cgd@broadcom.com>
512 * mips.igen (do_load_left, do_load_right): Move to be immediately
514 (do_store_left, do_store_right): Move to be immediately following
517 2002-02-27 Chris Demetriou <cgd@broadcom.com>
519 * mips.igen (mipsV): New model name. Also, add it to
520 all instructions and functions where it is appropriate.
522 2002-02-18 Chris Demetriou <cgd@broadcom.com>
524 * mips.igen: For all functions and instructions, list model
525 names that support that instruction one per line.
527 2002-02-11 Chris Demetriou <cgd@broadcom.com>
529 * mips.igen: Add some additional comments about supported
530 models, and about which instructions go where.
531 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
532 order as is used in the rest of the file.
534 2002-02-11 Chris Demetriou <cgd@broadcom.com>
536 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
537 indicating that ALU32_END or ALU64_END are there to check
539 (DADD): Likewise, but also remove previous comment about
542 2002-02-10 Chris Demetriou <cgd@broadcom.com>
544 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
545 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
546 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
547 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
548 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
549 fields (i.e., add and move commas) so that they more closely
550 match the MIPS ISA documentation opcode partitioning.
552 2002-02-10 Chris Demetriou <cgd@broadcom.com>
554 * mips.igen (ADDI): Print immediate value.
556 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
557 (SLL): Print "nop" specially, and don't run the code
558 that does the shift for the "nop" case.
560 2001-11-17 Fred Fish <fnf@redhat.com>
562 * sim-main.h (float_operation): Move enum declaration outside
563 of _sim_cpu struct declaration.
565 2001-04-12 Jim Blandy <jimb@redhat.com>
567 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
568 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
570 * sim-main.h (COCIDX): Remove definition; this isn't supported by
571 PENDING_FILL, and you can get the intended effect gracefully by
572 calling PENDING_SCHED directly.
574 2001-02-23 Ben Elliston <bje@redhat.com>
576 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
577 already defined elsewhere.
579 2001-02-19 Ben Elliston <bje@redhat.com>
581 * sim-main.h (sim_monitor): Return an int.
582 * interp.c (sim_monitor): Add return values.
583 (signal_exception): Handle error conditions from sim_monitor.
585 2001-02-08 Ben Elliston <bje@redhat.com>
587 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
588 (store_memory): Likewise, pass cia to sim_core_write*.
590 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
592 On advice from Chris G. Demetriou <cgd@sibyte.com>:
593 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
595 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
597 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
598 * Makefile.in: Don't delete *.igen when cleaning directory.
600 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
602 * m16.igen (break): Call SignalException not sim_engine_halt.
604 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
607 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
609 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
611 * mips.igen (MxC1, DMxC1): Fix printf formatting.
613 2000-05-24 Michael Hayes <mhayes@cygnus.com>
615 * mips.igen (do_dmultx): Fix typo.
617 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
619 * configure: Regenerated to track ../common/aclocal.m4 changes.
621 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
623 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
625 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
627 * sim-main.h (GPR_CLEAR): Define macro.
629 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
631 * interp.c (decode_coproc): Output long using %lx and not %s.
633 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
635 * interp.c (sim_open): Sort & extend dummy memory regions for
636 --board=jmr3904 for eCos.
638 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
640 * configure: Regenerated.
642 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
644 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
645 calls, conditional on the simulator being in verbose mode.
647 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
649 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
650 cache don't get ReservedInstruction traps.
652 1999-11-29 Mark Salter <msalter@cygnus.com>
654 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
655 to clear status bits in sdisr register. This is how the hardware works.
657 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
658 being used by cygmon.
660 1999-11-11 Andrew Haley <aph@cygnus.com>
662 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
665 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
667 * mips.igen (MULT): Correct previous mis-applied patch.
669 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
671 * mips.igen (delayslot32): Handle sequence like
672 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
673 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
674 (MULT): Actually pass the third register...
676 1999-09-03 Mark Salter <msalter@cygnus.com>
678 * interp.c (sim_open): Added more memory aliases for additional
679 hardware being touched by cygmon on jmr3904 board.
681 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
683 * configure: Regenerated to track ../common/aclocal.m4 changes.
685 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
687 * interp.c (sim_store_register): Handle case where client - GDB -
688 specifies that a 4 byte register is 8 bytes in size.
689 (sim_fetch_register): Ditto.
691 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
693 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
694 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
695 (idt_monitor_base): Base address for IDT monitor traps.
696 (pmon_monitor_base): Ditto for PMON.
697 (lsipmon_monitor_base): Ditto for LSI PMON.
698 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
699 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
700 (sim_firmware_command): New function.
701 (mips_option_handler): Call it for OPTION_FIRMWARE.
702 (sim_open): Allocate memory for idt_monitor region. If "--board"
703 option was given, add no monitor by default. Add BREAK hooks only if
704 monitors are also there.
706 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
708 * interp.c (sim_monitor): Flush output before reading input.
710 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
712 * tconfig.in (SIM_HANDLES_LMA): Always define.
714 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
716 From Mark Salter <msalter@cygnus.com>:
717 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
718 (sim_open): Add setup for BSP board.
720 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
722 * mips.igen (MULT, MULTU): Add syntax for two operand version.
723 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
724 them as unimplemented.
726 1999-05-08 Felix Lee <flee@cygnus.com>
728 * configure: Regenerated to track ../common/aclocal.m4 changes.
730 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
732 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
734 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
736 * configure.in: Any mips64vr5*-*-* target should have
737 -DTARGET_ENABLE_FR=1.
738 (default_endian): Any mips64vr*el-*-* target should default to
740 * configure: Re-generate.
742 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
744 * mips.igen (ldl): Extend from _16_, not 32.
746 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
748 * interp.c (sim_store_register): Force registers written to by GDB
749 into an un-interpreted state.
751 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
753 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
754 CPU, start periodic background I/O polls.
755 (tx3904sio_poll): New function: periodic I/O poller.
757 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
759 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
761 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
763 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
766 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
768 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
769 (load_word): Call SIM_CORE_SIGNAL hook on error.
770 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
771 starting. For exception dispatching, pass PC instead of NULL_CIA.
772 (decode_coproc): Use COP0_BADVADDR to store faulting address.
773 * sim-main.h (COP0_BADVADDR): Define.
774 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
775 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
776 (_sim_cpu): Add exc_* fields to store register value snapshots.
777 * mips.igen (*): Replace memory-related SignalException* calls
778 with references to SIM_CORE_SIGNAL hook.
780 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
782 * sim-main.c (*): Minor warning cleanups.
784 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
786 * m16.igen (DADDIU5): Correct type-o.
788 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
790 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
793 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
795 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
797 (interp.o): Add dependency on itable.h
798 (oengine.c, gencode): Delete remaining references.
799 (BUILT_SRC_FROM_GEN): Clean up.
801 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
804 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
805 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
807 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
808 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
809 Drop the "64" qualifier to get the HACK generator working.
810 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
811 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
812 qualifier to get the hack generator working.
813 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
815 (DSLLV): Use do_dsllv.
818 (DSRLV): Use do_dsrlv.
819 (BC1): Move *vr4100 to get the HACK generator working.
820 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
821 get the HACK generator working.
822 (MACC) Rename to get the HACK generator working.
823 (DMACC,MACCS,DMACCS): Add the 64.
825 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
827 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
828 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
830 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
832 * mips/interp.c (DEBUG): Cleanups.
834 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
836 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
837 (tx3904sio_tickle): fflush after a stdout character output.
839 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
841 * interp.c (sim_close): Uninstall modules.
843 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
845 * sim-main.h, interp.c (sim_monitor): Change to global
848 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
850 * configure.in (vr4100): Only include vr4100 instructions in
852 * configure: Re-generate.
853 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
855 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
857 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
858 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
861 * configure.in (sim_default_gen, sim_use_gen): Replace with
863 (--enable-sim-igen): Delete config option. Always using IGEN.
864 * configure: Re-generate.
866 * Makefile.in (gencode): Kill, kill, kill.
869 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
871 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
872 bit mips16 igen simulator.
873 * configure: Re-generate.
875 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
876 as part of vr4100 ISA.
877 * vr.igen: Mark all instructions as 64 bit only.
879 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
881 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
884 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
886 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
887 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
888 * configure: Re-generate.
890 * m16.igen (BREAK): Define breakpoint instruction.
891 (JALX32): Mark instruction as mips16 and not r3900.
892 * mips.igen (C.cond.fmt): Fix typo in instruction format.
894 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
896 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
898 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
899 insn as a debug breakpoint.
901 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
903 (PENDING_SCHED): Clean up trace statement.
904 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
905 (PENDING_FILL): Delay write by only one cycle.
906 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
908 * sim-main.c (pending_tick): Clean up trace statements. Add trace
910 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
912 (pending_tick): Move incrementing of index to FOR statement.
913 (pending_tick): Only update PENDING_OUT after a write has occured.
915 * configure.in: Add explicit mips-lsi-* target. Use gencode to
917 * configure: Re-generate.
919 * interp.c (sim_engine_run OLD): Delete explicit call to
920 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
922 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
924 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
925 interrupt level number to match changed SignalExceptionInterrupt
928 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
930 * interp.c: #include "itable.h" if WITH_IGEN.
931 (get_insn_name): New function.
932 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
933 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
935 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
937 * configure: Rebuilt to inhale new common/aclocal.m4.
939 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
941 * dv-tx3904sio.c: Include sim-assert.h.
943 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
945 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
946 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
947 Reorganize target-specific sim-hardware checks.
948 * configure: rebuilt.
949 * interp.c (sim_open): For tx39 target boards, set
950 OPERATING_ENVIRONMENT, add tx3904sio devices.
951 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
952 ROM executables. Install dv-sockser into sim-modules list.
954 * dv-tx3904irc.c: Compiler warning clean-up.
955 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
956 frequent hw-trace messages.
958 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
960 * vr.igen (MulAcc): Identify as a vr4100 specific function.
962 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
964 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
967 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
968 * mips.igen: Define vr4100 model. Include vr.igen.
969 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
971 * mips.igen (check_mf_hilo): Correct check.
973 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
975 * sim-main.h (interrupt_event): Add prototype.
977 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
978 register_ptr, register_value.
979 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
981 * sim-main.h (tracefh): Make extern.
983 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
985 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
986 Reduce unnecessarily high timer event frequency.
987 * dv-tx3904cpu.c: Ditto for interrupt event.
989 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
991 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
993 (interrupt_event): Made non-static.
995 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
996 interchange of configuration values for external vs. internal
999 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1001 * mips.igen (BREAK): Moved code to here for
1002 simulator-reserved break instructions.
1003 * gencode.c (build_instruction): Ditto.
1004 * interp.c (signal_exception): Code moved from here. Non-
1005 reserved instructions now use exception vector, rather
1007 * sim-main.h: Moved magic constants to here.
1009 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1011 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1012 register upon non-zero interrupt event level, clear upon zero
1014 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1015 by passing zero event value.
1016 (*_io_{read,write}_buffer): Endianness fixes.
1017 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1018 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1020 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1021 serial I/O and timer module at base address 0xFFFF0000.
1023 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1025 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1028 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1030 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1032 * configure: Update.
1034 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1036 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1037 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1038 * configure.in: Include tx3904tmr in hw_device list.
1039 * configure: Rebuilt.
1040 * interp.c (sim_open): Instantiate three timer instances.
1041 Fix address typo of tx3904irc instance.
1043 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1045 * interp.c (signal_exception): SystemCall exception now uses
1046 the exception vector.
1048 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1050 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1053 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1055 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1057 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1059 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1061 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1062 sim-main.h. Declare a struct hw_descriptor instead of struct
1063 hw_device_descriptor.
1065 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1067 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1068 right bits and then re-align left hand bytes to correct byte
1069 lanes. Fix incorrect computation in do_store_left when loading
1070 bytes from second word.
1072 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1074 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1075 * interp.c (sim_open): Only create a device tree when HW is
1078 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1079 * interp.c (signal_exception): Ditto.
1081 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1083 * gencode.c: Mark BEGEZALL as LIKELY.
1085 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1087 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1088 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1090 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1092 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1093 modules. Recognize TX39 target with "mips*tx39" pattern.
1094 * configure: Rebuilt.
1095 * sim-main.h (*): Added many macros defining bits in
1096 TX39 control registers.
1097 (SignalInterrupt): Send actual PC instead of NULL.
1098 (SignalNMIReset): New exception type.
1099 * interp.c (board): New variable for future use to identify
1100 a particular board being simulated.
1101 (mips_option_handler,mips_options): Added "--board" option.
1102 (interrupt_event): Send actual PC.
1103 (sim_open): Make memory layout conditional on board setting.
1104 (signal_exception): Initial implementation of hardware interrupt
1105 handling. Accept another break instruction variant for simulator
1107 (decode_coproc): Implement RFE instruction for TX39.
1108 (mips.igen): Decode RFE instruction as such.
1109 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1110 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1111 bbegin to implement memory map.
1112 * dv-tx3904cpu.c: New file.
1113 * dv-tx3904irc.c: New file.
1115 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1117 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1119 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1121 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1122 with calls to check_div_hilo.
1124 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1126 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1127 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1128 Add special r3900 version of do_mult_hilo.
1129 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1130 with calls to check_mult_hilo.
1131 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1132 with calls to check_div_hilo.
1134 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1136 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1137 Document a replacement.
1139 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1141 * interp.c (sim_monitor): Make mon_printf work.
1143 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1145 * sim-main.h (INSN_NAME): New arg `cpu'.
1147 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1149 * configure: Regenerated to track ../common/aclocal.m4 changes.
1151 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1153 * configure: Regenerated to track ../common/aclocal.m4 changes.
1156 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1158 * acconfig.h: New file.
1159 * configure.in: Reverted change of Apr 24; use sinclude again.
1161 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1163 * configure: Regenerated to track ../common/aclocal.m4 changes.
1166 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1168 * configure.in: Don't call sinclude.
1170 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1172 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1174 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1176 * mips.igen (ERET): Implement.
1178 * interp.c (decode_coproc): Return sign-extended EPC.
1180 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1182 * interp.c (signal_exception): Do not ignore Trap.
1183 (signal_exception): On TRAP, restart at exception address.
1184 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1185 (signal_exception): Update.
1186 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1187 so that TRAP instructions are caught.
1189 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1191 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1192 contains HI/LO access history.
1193 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1194 (HIACCESS, LOACCESS): Delete, replace with
1195 (HIHISTORY, LOHISTORY): New macros.
1196 (CHECKHILO): Delete all, moved to mips.igen
1198 * gencode.c (build_instruction): Do not generate checks for
1199 correct HI/LO register usage.
1201 * interp.c (old_engine_run): Delete checks for correct HI/LO
1204 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1205 check_mf_cycles): New functions.
1206 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1207 do_divu, domultx, do_mult, do_multu): Use.
1209 * tx.igen ("madd", "maddu"): Use.
1211 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1213 * mips.igen (DSRAV): Use function do_dsrav.
1214 (SRAV): Use new function do_srav.
1216 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1217 (B): Sign extend 11 bit immediate.
1218 (EXT-B*): Shift 16 bit immediate left by 1.
1219 (ADDIU*): Don't sign extend immediate value.
1221 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1223 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1225 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1228 * mips.igen (delayslot32, nullify_next_insn): New functions.
1229 (m16.igen): Always include.
1230 (do_*): Add more tracing.
1232 * m16.igen (delayslot16): Add NIA argument, could be called by a
1233 32 bit MIPS16 instruction.
1235 * interp.c (ifetch16): Move function from here.
1236 * sim-main.c (ifetch16): To here.
1238 * sim-main.c (ifetch16, ifetch32): Update to match current
1239 implementations of LH, LW.
1240 (signal_exception): Don't print out incorrect hex value of illegal
1243 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1245 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1248 * m16.igen: Implement MIPS16 instructions.
1250 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1251 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1252 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1253 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1254 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1255 bodies of corresponding code from 32 bit insn to these. Also used
1256 by MIPS16 versions of functions.
1258 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1259 (IMEM16): Drop NR argument from macro.
1261 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1263 * Makefile.in (SIM_OBJS): Add sim-main.o.
1265 * sim-main.h (address_translation, load_memory, store_memory,
1266 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1268 (pr_addr, pr_uword64): Declare.
1269 (sim-main.c): Include when H_REVEALS_MODULE_P.
1271 * interp.c (address_translation, load_memory, store_memory,
1272 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1274 * sim-main.c: To here. Fix compilation problems.
1276 * configure.in: Enable inlining.
1277 * configure: Re-config.
1279 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1281 * configure: Regenerated to track ../common/aclocal.m4 changes.
1283 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1285 * mips.igen: Include tx.igen.
1286 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1287 * tx.igen: New file, contains MADD and MADDU.
1289 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1290 the hardwired constant `7'.
1291 (store_memory): Ditto.
1292 (LOADDRMASK): Move definition to sim-main.h.
1294 mips.igen (MTC0): Enable for r3900.
1297 mips.igen (do_load_byte): Delete.
1298 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1299 do_store_right): New functions.
1300 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1302 configure.in: Let the tx39 use igen again.
1305 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1307 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1308 not an address sized quantity. Return zero for cache sizes.
1310 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1312 * mips.igen (r3900): r3900 does not support 64 bit integer
1315 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1317 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1319 * configure : Rebuild.
1321 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1323 * configure: Regenerated to track ../common/aclocal.m4 changes.
1325 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1327 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1329 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1331 * configure: Regenerated to track ../common/aclocal.m4 changes.
1332 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1334 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1336 * configure: Regenerated to track ../common/aclocal.m4 changes.
1338 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1340 * interp.c (Max, Min): Comment out functions. Not yet used.
1342 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1344 * configure: Regenerated to track ../common/aclocal.m4 changes.
1346 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1348 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1349 configurable settings for stand-alone simulator.
1351 * configure.in: Added X11 search, just in case.
1353 * configure: Regenerated.
1355 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1357 * interp.c (sim_write, sim_read, load_memory, store_memory):
1358 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1360 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1362 * sim-main.h (GETFCC): Return an unsigned value.
1364 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1366 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1367 (DADD): Result destination is RD not RT.
1369 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1371 * sim-main.h (HIACCESS, LOACCESS): Always define.
1373 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1375 * interp.c (sim_info): Delete.
1377 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1379 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1380 (mips_option_handler): New argument `cpu'.
1381 (sim_open): Update call to sim_add_option_table.
1383 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1385 * mips.igen (CxC1): Add tracing.
1387 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1389 * sim-main.h (Max, Min): Declare.
1391 * interp.c (Max, Min): New functions.
1393 * mips.igen (BC1): Add tracing.
1395 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1397 * interp.c Added memory map for stack in vr4100
1399 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1401 * interp.c (load_memory): Add missing "break"'s.
1403 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1405 * interp.c (sim_store_register, sim_fetch_register): Pass in
1406 length parameter. Return -1.
1408 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1410 * interp.c: Added hardware init hook, fixed warnings.
1412 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1414 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1416 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1418 * interp.c (ifetch16): New function.
1420 * sim-main.h (IMEM32): Rename IMEM.
1421 (IMEM16_IMMED): Define.
1423 (DELAY_SLOT): Update.
1425 * m16run.c (sim_engine_run): New file.
1427 * m16.igen: All instructions except LB.
1428 (LB): Call do_load_byte.
1429 * mips.igen (do_load_byte): New function.
1430 (LB): Call do_load_byte.
1432 * mips.igen: Move spec for insn bit size and high bit from here.
1433 * Makefile.in (tmp-igen, tmp-m16): To here.
1435 * m16.dc: New file, decode mips16 instructions.
1437 * Makefile.in (SIM_NO_ALL): Define.
1438 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1440 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1442 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1443 point unit to 32 bit registers.
1444 * configure: Re-generate.
1446 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1448 * configure.in (sim_use_gen): Make IGEN the default simulator
1449 generator for generic 32 and 64 bit mips targets.
1450 * configure: Re-generate.
1452 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1454 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1457 * interp.c (sim_fetch_register, sim_store_register): Read/write
1458 FGR from correct location.
1459 (sim_open): Set size of FGR's according to
1460 WITH_TARGET_FLOATING_POINT_BITSIZE.
1462 * sim-main.h (FGR): Store floating point registers in a separate
1465 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1467 * configure: Regenerated to track ../common/aclocal.m4 changes.
1469 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1471 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1473 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1475 * interp.c (pending_tick): New function. Deliver pending writes.
1477 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1478 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1479 it can handle mixed sized quantites and single bits.
1481 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1483 * interp.c (oengine.h): Do not include when building with IGEN.
1484 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1485 (sim_info): Ditto for PROCESSOR_64BIT.
1486 (sim_monitor): Replace ut_reg with unsigned_word.
1487 (*): Ditto for t_reg.
1488 (LOADDRMASK): Define.
1489 (sim_open): Remove defunct check that host FP is IEEE compliant,
1490 using software to emulate floating point.
1491 (value_fpr, ...): Always compile, was conditional on HASFPU.
1493 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1495 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1498 * interp.c (SD, CPU): Define.
1499 (mips_option_handler): Set flags in each CPU.
1500 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1501 (sim_close): Do not clear STATE, deleted anyway.
1502 (sim_write, sim_read): Assume CPU zero's vm should be used for
1504 (sim_create_inferior): Set the PC for all processors.
1505 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1507 (mips16_entry): Pass correct nr of args to store_word, load_word.
1508 (ColdReset): Cold reset all cpu's.
1509 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1510 (sim_monitor, load_memory, store_memory, signal_exception): Use
1511 `CPU' instead of STATE_CPU.
1514 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1517 * sim-main.h (signal_exception): Add sim_cpu arg.
1518 (SignalException*): Pass both SD and CPU to signal_exception.
1519 * interp.c (signal_exception): Update.
1521 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1523 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1524 address_translation): Ditto
1525 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1527 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1529 * configure: Regenerated to track ../common/aclocal.m4 changes.
1531 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1533 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1535 * mips.igen (model): Map processor names onto BFD name.
1537 * sim-main.h (CPU_CIA): Delete.
1538 (SET_CIA, GET_CIA): Define
1540 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1542 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1545 * configure.in (default_endian): Configure a big-endian simulator
1547 * configure: Re-generate.
1549 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1551 * configure: Regenerated to track ../common/aclocal.m4 changes.
1553 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1555 * interp.c (sim_monitor): Handle Densan monitor outbyte
1556 and inbyte functions.
1558 1997-12-29 Felix Lee <flee@cygnus.com>
1560 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1562 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1564 * Makefile.in (tmp-igen): Arrange for $zero to always be
1565 reset to zero after every instruction.
1567 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1569 * configure: Regenerated to track ../common/aclocal.m4 changes.
1572 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1574 * mips.igen (MSUB): Fix to work like MADD.
1575 * gencode.c (MSUB): Similarly.
1577 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1579 * configure: Regenerated to track ../common/aclocal.m4 changes.
1581 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1583 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1585 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1587 * sim-main.h (sim-fpu.h): Include.
1589 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1590 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1591 using host independant sim_fpu module.
1593 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1595 * interp.c (signal_exception): Report internal errors with SIGABRT
1598 * sim-main.h (C0_CONFIG): New register.
1599 (signal.h): No longer include.
1601 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1603 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1605 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1607 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1609 * mips.igen: Tag vr5000 instructions.
1610 (ANDI): Was missing mipsIV model, fix assembler syntax.
1611 (do_c_cond_fmt): New function.
1612 (C.cond.fmt): Handle mips I-III which do not support CC field
1614 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1615 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1617 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1618 vr5000 which saves LO in a GPR separatly.
1620 * configure.in (enable-sim-igen): For vr5000, select vr5000
1621 specific instructions.
1622 * configure: Re-generate.
1624 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1626 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1628 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1629 fmt_uninterpreted_64 bit cases to switch. Convert to
1632 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1634 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1635 as specified in IV3.2 spec.
1636 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1638 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1640 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1641 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1642 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1643 PENDING_FILL versions of instructions. Simplify.
1645 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1647 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1649 (MTHI, MFHI): Disable code checking HI-LO.
1651 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1653 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1655 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1657 * gencode.c (build_mips16_operands): Replace IPC with cia.
1659 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1660 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1662 (UndefinedResult): Replace function with macro/function
1664 (sim_engine_run): Don't save PC in IPC.
1666 * sim-main.h (IPC): Delete.
1669 * interp.c (signal_exception, store_word, load_word,
1670 address_translation, load_memory, store_memory, cache_op,
1671 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1672 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1673 current instruction address - cia - argument.
1674 (sim_read, sim_write): Call address_translation directly.
1675 (sim_engine_run): Rename variable vaddr to cia.
1676 (signal_exception): Pass cia to sim_monitor
1678 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1679 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1680 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1682 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1683 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1686 * interp.c (signal_exception): Pass restart address to
1689 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1690 idecode.o): Add dependency.
1692 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1694 (DELAY_SLOT): Update NIA not PC with branch address.
1695 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1697 * mips.igen: Use CIA not PC in branch calculations.
1698 (illegal): Call SignalException.
1699 (BEQ, ADDIU): Fix assembler.
1701 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1703 * m16.igen (JALX): Was missing.
1705 * configure.in (enable-sim-igen): New configuration option.
1706 * configure: Re-generate.
1708 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1710 * interp.c (load_memory, store_memory): Delete parameter RAW.
1711 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1712 bypassing {load,store}_memory.
1714 * sim-main.h (ByteSwapMem): Delete definition.
1716 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1718 * interp.c (sim_do_command, sim_commands): Delete mips specific
1719 commands. Handled by module sim-options.
1721 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1722 (WITH_MODULO_MEMORY): Define.
1724 * interp.c (sim_info): Delete code printing memory size.
1726 * interp.c (mips_size): Nee sim_size, delete function.
1728 (monitor, monitor_base, monitor_size): Delete global variables.
1729 (sim_open, sim_close): Delete code creating monitor and other
1730 memory regions. Use sim-memopts module, via sim_do_commandf, to
1731 manage memory regions.
1732 (load_memory, store_memory): Use sim-core for memory model.
1734 * interp.c (address_translation): Delete all memory map code
1735 except line forcing 32 bit addresses.
1737 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1739 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1742 * interp.c (logfh, logfile): Delete globals.
1743 (sim_open, sim_close): Delete code opening & closing log file.
1744 (mips_option_handler): Delete -l and -n options.
1745 (OPTION mips_options): Ditto.
1747 * interp.c (OPTION mips_options): Rename option trace to dinero.
1748 (mips_option_handler): Update.
1750 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1752 * interp.c (fetch_str): New function.
1753 (sim_monitor): Rewrite using sim_read & sim_write.
1754 (sim_open): Check magic number.
1755 (sim_open): Write monitor vectors into memory using sim_write.
1756 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1757 (sim_read, sim_write): Simplify - transfer data one byte at a
1759 (load_memory, store_memory): Clarify meaning of parameter RAW.
1761 * sim-main.h (isHOST): Defete definition.
1762 (isTARGET): Mark as depreciated.
1763 (address_translation): Delete parameter HOST.
1765 * interp.c (address_translation): Delete parameter HOST.
1767 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1771 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1772 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1774 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1776 * mips.igen: Add model filter field to records.
1778 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1780 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1782 interp.c (sim_engine_run): Do not compile function sim_engine_run
1783 when WITH_IGEN == 1.
1785 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1786 target architecture.
1788 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1789 igen. Replace with configuration variables sim_igen_flags /
1792 * m16.igen: New file. Copy mips16 insns here.
1793 * mips.igen: From here.
1795 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1797 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1799 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1801 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1803 * gencode.c (build_instruction): Follow sim_write's lead in using
1804 BigEndianMem instead of !ByteSwapMem.
1806 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1808 * configure.in (sim_gen): Dependent on target, select type of
1809 generator. Always select old style generator.
1811 configure: Re-generate.
1813 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1815 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1816 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1817 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1818 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1819 SIM_@sim_gen@_*, set by autoconf.
1821 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1823 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1825 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1826 CURRENT_FLOATING_POINT instead.
1828 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1829 (address_translation): Raise exception InstructionFetch when
1830 translation fails and isINSTRUCTION.
1832 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1833 sim_engine_run): Change type of of vaddr and paddr to
1835 (address_translation, prefetch, load_memory, store_memory,
1836 cache_op): Change type of vAddr and pAddr to address_word.
1838 * gencode.c (build_instruction): Change type of vaddr and paddr to
1841 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1843 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1844 macro to obtain result of ALU op.
1846 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1848 * interp.c (sim_info): Call profile_print.
1850 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1852 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1854 * sim-main.h (WITH_PROFILE): Do not define, defined in
1855 common/sim-config.h. Use sim-profile module.
1856 (simPROFILE): Delete defintion.
1858 * interp.c (PROFILE): Delete definition.
1859 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1860 (sim_close): Delete code writing profile histogram.
1861 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1863 (sim_engine_run): Delete code profiling the PC.
1865 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1867 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1869 * interp.c (sim_monitor): Make register pointers of type
1872 * sim-main.h: Make registers of type unsigned_word not
1875 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1877 * interp.c (sync_operation): Rename from SyncOperation, make
1878 global, add SD argument.
1879 (prefetch): Rename from Prefetch, make global, add SD argument.
1880 (decode_coproc): Make global.
1882 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1884 * gencode.c (build_instruction): Generate DecodeCoproc not
1885 decode_coproc calls.
1887 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1888 (SizeFGR): Move to sim-main.h
1889 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1890 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1891 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1893 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1894 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1895 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1896 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1897 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1898 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1900 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1902 (sim-alu.h): Include.
1903 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1904 (sim_cia): Typedef to instruction_address.
1906 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1908 * Makefile.in (interp.o): Rename generated file engine.c to
1913 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1915 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1917 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1919 * gencode.c (build_instruction): For "FPSQRT", output correct
1920 number of arguments to Recip.
1922 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1924 * Makefile.in (interp.o): Depends on sim-main.h
1926 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1928 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1929 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1930 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1931 STATE, DSSTATE): Define
1932 (GPR, FGRIDX, ..): Define.
1934 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1935 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1936 (GPR, FGRIDX, ...): Delete macros.
1938 * interp.c: Update names to match defines from sim-main.h
1940 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1942 * interp.c (sim_monitor): Add SD argument.
1943 (sim_warning): Delete. Replace calls with calls to
1945 (sim_error): Delete. Replace calls with sim_io_error.
1946 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1947 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1948 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1950 (mips_size): Rename from sim_size. Add SD argument.
1952 * interp.c (simulator): Delete global variable.
1953 (callback): Delete global variable.
1954 (mips_option_handler, sim_open, sim_write, sim_read,
1955 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1956 sim_size,sim_monitor): Use sim_io_* not callback->*.
1957 (sim_open): ZALLOC simulator struct.
1958 (PROFILE): Do not define.
1960 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1962 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1963 support.h with corresponding code.
1965 * sim-main.h (word64, uword64), support.h: Move definition to
1967 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1970 * Makefile.in: Update dependencies
1971 * interp.c: Do not include.
1973 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1975 * interp.c (address_translation, load_memory, store_memory,
1976 cache_op): Rename to from AddressTranslation et.al., make global,
1979 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1982 * interp.c (SignalException): Rename to signal_exception, make
1985 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1987 * sim-main.h (SignalException, SignalExceptionInterrupt,
1988 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1989 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1990 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1993 * interp.c, support.h: Use.
1995 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1997 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1998 to value_fpr / store_fpr. Add SD argument.
1999 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2000 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2002 * sim-main.h (ValueFPR, StoreFPR): Define.
2004 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2006 * interp.c (sim_engine_run): Check consistency between configure
2007 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2010 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2011 (mips_fpu): Configure WITH_FLOATING_POINT.
2012 (mips_endian): Configure WITH_TARGET_ENDIAN.
2013 * configure: Update.
2015 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2017 * configure: Regenerated to track ../common/aclocal.m4 changes.
2019 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2021 * configure: Regenerated.
2023 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2025 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2027 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2029 * gencode.c (print_igen_insn_models): Assume certain architectures
2030 include all mips* instructions.
2031 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2034 * Makefile.in (tmp.igen): Add target. Generate igen input from
2037 * gencode.c (FEATURE_IGEN): Define.
2038 (main): Add --igen option. Generate output in igen format.
2039 (process_instructions): Format output according to igen option.
2040 (print_igen_insn_format): New function.
2041 (print_igen_insn_models): New function.
2042 (process_instructions): Only issue warnings and ignore
2043 instructions when no FEATURE_IGEN.
2045 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2047 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2050 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2052 * configure: Regenerated to track ../common/aclocal.m4 changes.
2054 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2056 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2057 SIM_RESERVED_BITS): Delete, moved to common.
2058 (SIM_EXTRA_CFLAGS): Update.
2060 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2062 * configure.in: Configure non-strict memory alignment.
2063 * configure: Regenerated to track ../common/aclocal.m4 changes.
2065 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2067 * configure: Regenerated to track ../common/aclocal.m4 changes.
2069 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2071 * gencode.c (SDBBP,DERET): Added (3900) insns.
2072 (RFE): Turn on for 3900.
2073 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2074 (dsstate): Made global.
2075 (SUBTARGET_R3900): Added.
2076 (CANCELDELAYSLOT): New.
2077 (SignalException): Ignore SystemCall rather than ignore and
2078 terminate. Add DebugBreakPoint handling.
2079 (decode_coproc): New insns RFE, DERET; and new registers Debug
2080 and DEPC protected by SUBTARGET_R3900.
2081 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2083 * Makefile.in,configure.in: Add mips subtarget option.
2084 * configure: Update.
2086 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2088 * gencode.c: Add r3900 (tx39).
2091 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2093 * gencode.c (build_instruction): Don't need to subtract 4 for
2096 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2098 * interp.c: Correct some HASFPU problems.
2100 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2102 * configure: Regenerated to track ../common/aclocal.m4 changes.
2104 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2106 * interp.c (mips_options): Fix samples option short form, should
2109 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2111 * interp.c (sim_info): Enable info code. Was just returning.
2113 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2115 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2118 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2120 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2122 (build_instruction): Ditto for LL.
2124 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2126 * configure: Regenerated to track ../common/aclocal.m4 changes.
2128 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2130 * configure: Regenerated to track ../common/aclocal.m4 changes.
2133 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2135 * interp.c (sim_open): Add call to sim_analyze_program, update
2138 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2140 * interp.c (sim_kill): Delete.
2141 (sim_create_inferior): Add ABFD argument. Set PC from same.
2142 (sim_load): Move code initializing trap handlers from here.
2143 (sim_open): To here.
2144 (sim_load): Delete, use sim-hload.c.
2146 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2148 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2150 * configure: Regenerated to track ../common/aclocal.m4 changes.
2153 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2155 * interp.c (sim_open): Add ABFD argument.
2156 (sim_load): Move call to sim_config from here.
2157 (sim_open): To here. Check return status.
2159 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2161 * gencode.c (build_instruction): Two arg MADD should
2162 not assign result to $0.
2164 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2166 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2167 * sim/mips/configure.in: Regenerate.
2169 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2171 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2172 signed8, unsigned8 et.al. types.
2174 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2175 hosts when selecting subreg.
2177 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2179 * interp.c (sim_engine_run): Reset the ZERO register to zero
2180 regardless of FEATURE_WARN_ZERO.
2181 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2183 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2185 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2186 (SignalException): For BreakPoints ignore any mode bits and just
2188 (SignalException): Always set the CAUSE register.
2190 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2192 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2193 exception has been taken.
2195 * interp.c: Implement the ERET and mt/f sr instructions.
2197 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2199 * interp.c (SignalException): Don't bother restarting an
2202 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2204 * interp.c (SignalException): Really take an interrupt.
2205 (interrupt_event): Only deliver interrupts when enabled.
2207 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2209 * interp.c (sim_info): Only print info when verbose.
2210 (sim_info) Use sim_io_printf for output.
2212 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2214 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2217 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2219 * interp.c (sim_do_command): Check for common commands if a
2220 simulator specific command fails.
2222 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2224 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2225 and simBE when DEBUG is defined.
2227 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2229 * interp.c (interrupt_event): New function. Pass exception event
2230 onto exception handler.
2232 * configure.in: Check for stdlib.h.
2233 * configure: Regenerate.
2235 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2236 variable declaration.
2237 (build_instruction): Initialize memval1.
2238 (build_instruction): Add UNUSED attribute to byte, bigend,
2240 (build_operands): Ditto.
2242 * interp.c: Fix GCC warnings.
2243 (sim_get_quit_code): Delete.
2245 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2246 * Makefile.in: Ditto.
2247 * configure: Re-generate.
2249 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2251 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2253 * interp.c (mips_option_handler): New function parse argumes using
2255 (myname): Replace with STATE_MY_NAME.
2256 (sim_open): Delete check for host endianness - performed by
2258 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2259 (sim_open): Move much of the initialization from here.
2260 (sim_load): To here. After the image has been loaded and
2262 (sim_open): Move ColdReset from here.
2263 (sim_create_inferior): To here.
2264 (sim_open): Make FP check less dependant on host endianness.
2266 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2268 * interp.c (sim_set_callbacks): Delete.
2270 * interp.c (membank, membank_base, membank_size): Replace with
2271 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2272 (sim_open): Remove call to callback->init. gdb/run do this.
2276 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2278 * interp.c (big_endian_p): Delete, replaced by
2279 current_target_byte_order.
2281 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2283 * interp.c (host_read_long, host_read_word, host_swap_word,
2284 host_swap_long): Delete. Using common sim-endian.
2285 (sim_fetch_register, sim_store_register): Use H2T.
2286 (pipeline_ticks): Delete. Handled by sim-events.
2288 (sim_engine_run): Update.
2290 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2292 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2294 (SignalException): To here. Signal using sim_engine_halt.
2295 (sim_stop_reason): Delete, moved to common.
2297 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2299 * interp.c (sim_open): Add callback argument.
2300 (sim_set_callbacks): Delete SIM_DESC argument.
2303 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2305 * Makefile.in (SIM_OBJS): Add common modules.
2307 * interp.c (sim_set_callbacks): Also set SD callback.
2308 (set_endianness, xfer_*, swap_*): Delete.
2309 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2310 Change to functions using sim-endian macros.
2311 (control_c, sim_stop): Delete, use common version.
2312 (simulate): Convert into.
2313 (sim_engine_run): This function.
2314 (sim_resume): Delete.
2316 * interp.c (simulation): New variable - the simulator object.
2317 (sim_kind): Delete global - merged into simulation.
2318 (sim_load): Cleanup. Move PC assignment from here.
2319 (sim_create_inferior): To here.
2321 * sim-main.h: New file.
2322 * interp.c (sim-main.h): Include.
2324 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2326 * configure: Regenerated to track ../common/aclocal.m4 changes.
2328 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2330 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2332 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2334 * gencode.c (build_instruction): DIV instructions: check
2335 for division by zero and integer overflow before using
2336 host's division operation.
2338 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2340 * Makefile.in (SIM_OBJS): Add sim-load.o.
2341 * interp.c: #include bfd.h.
2342 (target_byte_order): Delete.
2343 (sim_kind, myname, big_endian_p): New static locals.
2344 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2345 after argument parsing. Recognize -E arg, set endianness accordingly.
2346 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2347 load file into simulator. Set PC from bfd.
2348 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2349 (set_endianness): Use big_endian_p instead of target_byte_order.
2351 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2353 * interp.c (sim_size): Delete prototype - conflicts with
2354 definition in remote-sim.h. Correct definition.
2356 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2358 * configure: Regenerated to track ../common/aclocal.m4 changes.
2361 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2363 * interp.c (sim_open): New arg `kind'.
2365 * configure: Regenerated to track ../common/aclocal.m4 changes.
2367 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2369 * configure: Regenerated to track ../common/aclocal.m4 changes.
2371 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2373 * interp.c (sim_open): Set optind to 0 before calling getopt.
2375 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2377 * configure: Regenerated to track ../common/aclocal.m4 changes.
2379 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2381 * interp.c : Replace uses of pr_addr with pr_uword64
2382 where the bit length is always 64 independent of SIM_ADDR.
2383 (pr_uword64) : added.
2385 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2387 * configure: Re-generate.
2389 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2391 * configure: Regenerate to track ../common/aclocal.m4 changes.
2393 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2395 * interp.c (sim_open): New SIM_DESC result. Argument is now
2397 (other sim_*): New SIM_DESC argument.
2399 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2401 * interp.c: Fix printing of addresses for non-64-bit targets.
2402 (pr_addr): Add function to print address based on size.
2404 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2406 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2408 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2410 * gencode.c (build_mips16_operands): Correct computation of base
2411 address for extended PC relative instruction.
2413 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2415 * interp.c (mips16_entry): Add support for floating point cases.
2416 (SignalException): Pass floating point cases to mips16_entry.
2417 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2419 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2421 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2422 and then set the state to fmt_uninterpreted.
2423 (COP_SW): Temporarily set the state to fmt_word while calling
2426 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2428 * gencode.c (build_instruction): The high order may be set in the
2429 comparison flags at any ISA level, not just ISA 4.
2431 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2433 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2434 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2435 * configure.in: sinclude ../common/aclocal.m4.
2436 * configure: Regenerated.
2438 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2440 * configure: Rebuild after change to aclocal.m4.
2442 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2444 * configure configure.in Makefile.in: Update to new configure
2445 scheme which is more compatible with WinGDB builds.
2446 * configure.in: Improve comment on how to run autoconf.
2447 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2448 * Makefile.in: Use autoconf substitution to install common
2451 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2453 * gencode.c (build_instruction): Use BigEndianCPU instead of
2456 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2458 * interp.c (sim_monitor): Make output to stdout visible in
2459 wingdb's I/O log window.
2461 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2463 * support.h: Undo previous change to SIGTRAP
2466 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2468 * interp.c (store_word, load_word): New static functions.
2469 (mips16_entry): New static function.
2470 (SignalException): Look for mips16 entry and exit instructions.
2471 (simulate): Use the correct index when setting fpr_state after
2472 doing a pending move.
2474 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2476 * interp.c: Fix byte-swapping code throughout to work on
2477 both little- and big-endian hosts.
2479 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2481 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2482 with gdb/config/i386/xm-windows.h.
2484 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2486 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2487 that messes up arithmetic shifts.
2489 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2491 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2492 SIGTRAP and SIGQUIT for _WIN32.
2494 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2496 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2497 force a 64 bit multiplication.
2498 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2499 destination register is 0, since that is the default mips16 nop
2502 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2504 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2505 (build_endian_shift): Don't check proc64.
2506 (build_instruction): Always set memval to uword64. Cast op2 to
2507 uword64 when shifting it left in memory instructions. Always use
2508 the same code for stores--don't special case proc64.
2510 * gencode.c (build_mips16_operands): Fix base PC value for PC
2512 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2514 * interp.c (simJALDELAYSLOT): Define.
2515 (JALDELAYSLOT): Define.
2516 (INDELAYSLOT, INJALDELAYSLOT): Define.
2517 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2519 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2521 * interp.c (sim_open): add flush_cache as a PMON routine
2522 (sim_monitor): handle flush_cache by ignoring it
2524 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2526 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2528 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2529 (BigEndianMem): Rename to ByteSwapMem and change sense.
2530 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2531 BigEndianMem references to !ByteSwapMem.
2532 (set_endianness): New function, with prototype.
2533 (sim_open): Call set_endianness.
2534 (sim_info): Use simBE instead of BigEndianMem.
2535 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2536 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2537 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2538 ifdefs, keeping the prototype declaration.
2539 (swap_word): Rewrite correctly.
2540 (ColdReset): Delete references to CONFIG. Delete endianness related
2541 code; moved to set_endianness.
2543 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2545 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2546 * interp.c (CHECKHILO): Define away.
2547 (simSIGINT): New macro.
2548 (membank_size): Increase from 1MB to 2MB.
2549 (control_c): New function.
2550 (sim_resume): Rename parameter signal to signal_number. Add local
2551 variable prev. Call signal before and after simulate.
2552 (sim_stop_reason): Add simSIGINT support.
2553 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2555 (sim_warning): Delete call to SignalException. Do call printf_filtered
2557 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2558 a call to sim_warning.
2560 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2562 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2563 16 bit instructions.
2565 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2567 Add support for mips16 (16 bit MIPS implementation):
2568 * gencode.c (inst_type): Add mips16 instruction encoding types.
2569 (GETDATASIZEINSN): Define.
2570 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2571 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2573 (MIPS16_DECODE): New table, for mips16 instructions.
2574 (bitmap_val): New static function.
2575 (struct mips16_op): Define.
2576 (mips16_op_table): New table, for mips16 operands.
2577 (build_mips16_operands): New static function.
2578 (process_instructions): If PC is odd, decode a mips16
2579 instruction. Break out instruction handling into new
2580 build_instruction function.
2581 (build_instruction): New static function, broken out of
2582 process_instructions. Check modifiers rather than flags for SHIFT
2583 bit count and m[ft]{hi,lo} direction.
2584 (usage): Pass program name to fprintf.
2585 (main): Remove unused variable this_option_optind. Change
2586 ``*loptarg++'' to ``loptarg++''.
2587 (my_strtoul): Parenthesize && within ||.
2588 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2589 (simulate): If PC is odd, fetch a 16 bit instruction, and
2590 increment PC by 2 rather than 4.
2591 * configure.in: Add case for mips16*-*-*.
2592 * configure: Rebuild.
2594 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2596 * interp.c: Allow -t to enable tracing in standalone simulator.
2597 Fix garbage output in trace file and error messages.
2599 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2601 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2602 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2603 * configure.in: Simplify using macros in ../common/aclocal.m4.
2604 * configure: Regenerated.
2605 * tconfig.in: New file.
2607 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2609 * interp.c: Fix bugs in 64-bit port.
2610 Use ansi function declarations for msvc compiler.
2611 Initialize and test file pointer in trace code.
2612 Prevent duplicate definition of LAST_EMED_REGNUM.
2614 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2616 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2618 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2620 * interp.c (SignalException): Check for explicit terminating
2622 * gencode.c: Pass instruction value through SignalException()
2623 calls for Trap, Breakpoint and Syscall.
2625 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2627 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2628 only used on those hosts that provide it.
2629 * configure.in: Add sqrt() to list of functions to be checked for.
2630 * config.in: Re-generated.
2631 * configure: Re-generated.
2633 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2635 * gencode.c (process_instructions): Call build_endian_shift when
2636 expanding STORE RIGHT, to fix swr.
2637 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2638 clear the high bits.
2639 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2640 Fix float to int conversions to produce signed values.
2642 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2644 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2645 (process_instructions): Correct handling of nor instruction.
2646 Correct shift count for 32 bit shift instructions. Correct sign
2647 extension for arithmetic shifts to not shift the number of bits in
2648 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2649 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2651 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2652 It's OK to have a mult follow a mult. What's not OK is to have a
2653 mult follow an mfhi.
2654 (Convert): Comment out incorrect rounding code.
2656 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2658 * interp.c (sim_monitor): Improved monitor printf
2659 simulation. Tidied up simulator warnings, and added "--log" option
2660 for directing warning message output.
2661 * gencode.c: Use sim_warning() rather than WARNING macro.
2663 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2665 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2666 getopt1.o, rather than on gencode.c. Link objects together.
2667 Don't link against -liberty.
2668 (gencode.o, getopt.o, getopt1.o): New targets.
2669 * gencode.c: Include <ctype.h> and "ansidecl.h".
2670 (AND): Undefine after including "ansidecl.h".
2671 (ULONG_MAX): Define if not defined.
2672 (OP_*): Don't define macros; now defined in opcode/mips.h.
2673 (main): Call my_strtoul rather than strtoul.
2674 (my_strtoul): New static function.
2676 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2678 * gencode.c (process_instructions): Generate word64 and uword64
2679 instead of `long long' and `unsigned long long' data types.
2680 * interp.c: #include sysdep.h to get signals, and define default
2682 * (Convert): Work around for Visual-C++ compiler bug with type
2684 * support.h: Make things compile under Visual-C++ by using
2685 __int64 instead of `long long'. Change many refs to long long
2686 into word64/uword64 typedefs.
2688 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2690 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2691 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2693 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2694 (AC_PROG_INSTALL): Added.
2695 (AC_PROG_CC): Moved to before configure.host call.
2696 * configure: Rebuilt.
2698 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2700 * configure.in: Define @SIMCONF@ depending on mips target.
2701 * configure: Rebuild.
2702 * Makefile.in (run): Add @SIMCONF@ to control simulator
2704 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2705 * interp.c: Remove some debugging, provide more detailed error
2706 messages, update memory accesses to use LOADDRMASK.
2708 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2710 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2711 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2713 * configure: Rebuild.
2714 * config.in: New file, generated by autoheader.
2715 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2716 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2717 HAVE_ANINT and HAVE_AINT, as appropriate.
2718 * Makefile.in (run): Use @LIBS@ rather than -lm.
2719 (interp.o): Depend upon config.h.
2720 (Makefile): Just rebuild Makefile.
2721 (clean): Remove stamp-h.
2722 (mostlyclean): Make the same as clean, not as distclean.
2723 (config.h, stamp-h): New targets.
2725 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2727 * interp.c (ColdReset): Fix boolean test. Make all simulator
2730 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2732 * interp.c (xfer_direct_word, xfer_direct_long,
2733 swap_direct_word, swap_direct_long, xfer_big_word,
2734 xfer_big_long, xfer_little_word, xfer_little_long,
2735 swap_word,swap_long): Added.
2736 * interp.c (ColdReset): Provide function indirection to
2737 host<->simulated_target transfer routines.
2738 * interp.c (sim_store_register, sim_fetch_register): Updated to
2739 make use of indirected transfer routines.
2741 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2743 * gencode.c (process_instructions): Ensure FP ABS instruction
2745 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2746 system call support.
2748 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2750 * interp.c (sim_do_command): Complain if callback structure not
2753 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2755 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2756 support for Sun hosts.
2757 * Makefile.in (gencode): Ensure the host compiler and libraries
2758 used for cross-hosted build.
2760 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2762 * interp.c, gencode.c: Some more (TODO) tidying.
2764 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2766 * gencode.c, interp.c: Replaced explicit long long references with
2767 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2768 * support.h (SET64LO, SET64HI): Macros added.
2770 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2772 * configure: Regenerate with autoconf 2.7.
2774 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2776 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2777 * support.h: Remove superfluous "1" from #if.
2778 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2780 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2782 * interp.c (StoreFPR): Control UndefinedResult() call on
2783 WARN_RESULT manifest.
2785 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2787 * gencode.c: Tidied instruction decoding, and added FP instruction
2790 * interp.c: Added dineroIII, and BSD profiling support. Also
2791 run-time FP handling.
2793 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2795 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2796 gencode.c, interp.c, support.h: created.