1 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
3 * configure: Regenerated.
5 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
7 * configure: Regenerated.
9 2006-05-15 Chao-ying Fu <fu@mips.com>
11 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
13 2006-04-18 Nick Clifton <nickc@redhat.com>
15 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
18 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
20 * configure: Regenerate.
22 2005-12-14 Chao-ying Fu <fu@mips.com>
24 * Makefile.in (SIM_OBJS): Add dsp.o.
25 (dsp.o): New dependency.
26 (IGEN_INCLUDE): Add dsp.igen.
27 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
28 mipsisa64*-*-*): Add dsp to sim_igen_machine.
29 * configure: Regenerate.
30 * mips.igen: Add dsp model and include dsp.igen.
31 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
32 because these instructions are extended in DSP ASE.
33 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
34 adding 6 DSP accumulator registers and 1 DSP control register.
35 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
36 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
37 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
38 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
39 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
40 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
41 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
42 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
43 DSPCR_CCOND_SMASK): New define.
44 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
45 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
47 2005-07-08 Ian Lance Taylor <ian@airs.com>
49 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
51 2005-06-16 David Ung <davidu@mips.com>
52 Nigel Stephens <nigel@mips.com>
54 * mips.igen: New mips16e model and include m16e.igen.
55 (check_u64): Add mips16e tag.
56 * m16e.igen: New file for MIPS16e instructions.
57 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
58 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
60 * configure: Regenerate.
62 2005-05-26 David Ung <davidu@mips.com>
64 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
65 tags to all instructions which are applicable to the new ISAs.
66 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
68 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
70 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
72 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
73 * configure: Regenerate.
75 2005-03-23 Mark Kettenis <kettenis@gnu.org>
77 * configure: Regenerate.
79 2005-01-14 Andrew Cagney <cagney@gnu.org>
81 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
82 explicit call to AC_CONFIG_HEADER.
83 * configure: Regenerate.
85 2005-01-12 Andrew Cagney <cagney@gnu.org>
87 * configure.ac: Update to use ../common/common.m4.
88 * configure: Re-generate.
90 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
92 * configure: Regenerated to track ../common/aclocal.m4 changes.
94 2005-01-07 Andrew Cagney <cagney@gnu.org>
96 * configure.ac: Rename configure.in, require autoconf 2.59.
97 * configure: Re-generate.
99 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
101 * configure: Regenerate for ../common/aclocal.m4 update.
103 2004-09-24 Monika Chaddha <monika@acmet.com>
105 Committed by Andrew Cagney.
106 * m16.igen (CMP, CMPI): Fix assembler.
108 2004-08-18 Chris Demetriou <cgd@broadcom.com>
110 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
111 * configure: Regenerate.
113 2004-06-25 Chris Demetriou <cgd@broadcom.com>
115 * configure.in (sim_m16_machine): Include mipsIII.
116 * configure: Regenerate.
118 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
120 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
122 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
124 2004-04-10 Chris Demetriou <cgd@broadcom.com>
126 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
128 2004-04-09 Chris Demetriou <cgd@broadcom.com>
130 * mips.igen (check_fmt): Remove.
131 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
132 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
133 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
134 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
135 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
136 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
137 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
138 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
139 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
140 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
142 2004-04-09 Chris Demetriou <cgd@broadcom.com>
144 * sb1.igen (check_sbx): New function.
145 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
147 2004-03-29 Chris Demetriou <cgd@broadcom.com>
148 Richard Sandiford <rsandifo@redhat.com>
150 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
151 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
152 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
153 separate implementations for mipsIV and mipsV. Use new macros to
154 determine whether the restrictions apply.
156 2004-01-19 Chris Demetriou <cgd@broadcom.com>
158 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
159 (check_mult_hilo): Improve comments.
160 (check_div_hilo): Likewise. Also, fork off a new version
161 to handle mips32/mips64 (since there are no hazards to check
164 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
166 * mips.igen (do_dmultx): Fix check for negative operands.
168 2003-05-16 Ian Lance Taylor <ian@airs.com>
170 * Makefile.in (SHELL): Make sure this is defined.
171 (various): Use $(SHELL) whenever we invoke move-if-change.
173 2003-05-03 Chris Demetriou <cgd@broadcom.com>
175 * cp1.c: Tweak attribution slightly.
178 * mdmx.igen: Likewise.
179 * mips3d.igen: Likewise.
180 * sb1.igen: Likewise.
182 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
184 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
187 2003-02-27 Andrew Cagney <cagney@redhat.com>
189 * interp.c (sim_open): Rename _bfd to bfd.
190 (sim_create_inferior): Ditto.
192 2003-01-14 Chris Demetriou <cgd@broadcom.com>
194 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
196 2003-01-14 Chris Demetriou <cgd@broadcom.com>
198 * mips.igen (EI, DI): Remove.
200 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
202 * Makefile.in (tmp-run-multi): Fix mips16 filter.
204 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
205 Andrew Cagney <ac131313@redhat.com>
206 Gavin Romig-Koch <gavin@redhat.com>
207 Graydon Hoare <graydon@redhat.com>
208 Aldy Hernandez <aldyh@redhat.com>
209 Dave Brolley <brolley@redhat.com>
210 Chris Demetriou <cgd@broadcom.com>
212 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
213 (sim_mach_default): New variable.
214 (mips64vr-*-*, mips64vrel-*-*): New configurations.
215 Add a new simulator generator, MULTI.
216 * configure: Regenerate.
217 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
218 (multi-run.o): New dependency.
219 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
220 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
221 (tmp-multi): Combine them.
222 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
223 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
224 (distclean-extra): New rule.
225 * sim-main.h: Include bfd.h.
226 (MIPS_MACH): New macro.
227 * mips.igen (vr4120, vr5400, vr5500): New models.
228 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
229 * vr.igen: Replace with new version.
231 2003-01-04 Chris Demetriou <cgd@broadcom.com>
233 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
234 * configure: Regenerate.
236 2002-12-31 Chris Demetriou <cgd@broadcom.com>
238 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
239 * mips.igen: Remove all invocations of check_branch_bug and
242 2002-12-16 Chris Demetriou <cgd@broadcom.com>
244 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
246 2002-07-30 Chris Demetriou <cgd@broadcom.com>
248 * mips.igen (do_load_double, do_store_double): New functions.
249 (LDC1, SDC1): Rename to...
250 (LDC1b, SDC1b): respectively.
251 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
253 2002-07-29 Michael Snyder <msnyder@redhat.com>
255 * cp1.c (fp_recip2): Modify initialization expression so that
256 GCC will recognize it as constant.
258 2002-06-18 Chris Demetriou <cgd@broadcom.com>
260 * mdmx.c (SD_): Delete.
261 (Unpredictable): Re-define, for now, to directly invoke
262 unpredictable_action().
263 (mdmx_acc_op): Fix error in .ob immediate handling.
265 2002-06-18 Andrew Cagney <cagney@redhat.com>
267 * interp.c (sim_firmware_command): Initialize `address'.
269 2002-06-16 Andrew Cagney <ac131313@redhat.com>
271 * configure: Regenerated to track ../common/aclocal.m4 changes.
273 2002-06-14 Chris Demetriou <cgd@broadcom.com>
274 Ed Satterthwaite <ehs@broadcom.com>
276 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
277 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
278 * mips.igen: Include mips3d.igen.
279 (mips3d): New model name for MIPS-3D ASE instructions.
280 (CVT.W.fmt): Don't use this instruction for word (source) format
282 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
283 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
284 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
285 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
286 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
287 (RSquareRoot1, RSquareRoot2): New macros.
288 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
289 (fp_rsqrt2): New functions.
290 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
291 * configure: Regenerate.
293 2002-06-13 Chris Demetriou <cgd@broadcom.com>
294 Ed Satterthwaite <ehs@broadcom.com>
296 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
297 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
298 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
299 (convert): Note that this function is not used for paired-single
301 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
302 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
303 (check_fmt_p): Enable paired-single support.
304 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
305 (PUU.PS): New instructions.
306 (CVT.S.fmt): Don't use this instruction for paired-single format
308 * sim-main.h (FP_formats): New value 'fmt_ps.'
309 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
310 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
312 2002-06-12 Chris Demetriou <cgd@broadcom.com>
314 * mips.igen: Fix formatting of function calls in
317 2002-06-12 Chris Demetriou <cgd@broadcom.com>
319 * mips.igen (MOVN, MOVZ): Trace result.
320 (TNEI): Print "tnei" as the opcode name in traces.
321 (CEIL.W): Add disassembly string for traces.
322 (RSQRT.fmt): Make location of disassembly string consistent
323 with other instructions.
325 2002-06-12 Chris Demetriou <cgd@broadcom.com>
327 * mips.igen (X): Delete unused function.
329 2002-06-08 Andrew Cagney <cagney@redhat.com>
331 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
333 2002-06-07 Chris Demetriou <cgd@broadcom.com>
334 Ed Satterthwaite <ehs@broadcom.com>
336 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
337 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
338 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
339 (fp_nmsub): New prototypes.
340 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
341 (NegMultiplySub): New defines.
342 * mips.igen (RSQRT.fmt): Use RSquareRoot().
343 (MADD.D, MADD.S): Replace with...
344 (MADD.fmt): New instruction.
345 (MSUB.D, MSUB.S): Replace with...
346 (MSUB.fmt): New instruction.
347 (NMADD.D, NMADD.S): Replace with...
348 (NMADD.fmt): New instruction.
349 (NMSUB.D, MSUB.S): Replace with...
350 (NMSUB.fmt): New instruction.
352 2002-06-07 Chris Demetriou <cgd@broadcom.com>
353 Ed Satterthwaite <ehs@broadcom.com>
355 * cp1.c: Fix more comment spelling and formatting.
356 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
357 (denorm_mode): New function.
358 (fpu_unary, fpu_binary): Round results after operation, collect
359 status from rounding operations, and update the FCSR.
360 (convert): Collect status from integer conversions and rounding
361 operations, and update the FCSR. Adjust NaN values that result
362 from conversions. Convert to use sim_io_eprintf rather than
363 fprintf, and remove some debugging code.
364 * cp1.h (fenr_FS): New define.
366 2002-06-07 Chris Demetriou <cgd@broadcom.com>
368 * cp1.c (convert): Remove unusable debugging code, and move MIPS
369 rounding mode to sim FP rounding mode flag conversion code into...
370 (rounding_mode): New function.
372 2002-06-07 Chris Demetriou <cgd@broadcom.com>
374 * cp1.c: Clean up formatting of a few comments.
375 (value_fpr): Reformat switch statement.
377 2002-06-06 Chris Demetriou <cgd@broadcom.com>
378 Ed Satterthwaite <ehs@broadcom.com>
381 * sim-main.h: Include cp1.h.
382 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
383 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
384 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
385 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
386 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
387 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
388 * cp1.c: Don't include sim-fpu.h; already included by
389 sim-main.h. Clean up formatting of some comments.
390 (NaN, Equal, Less): Remove.
391 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
392 (fp_cmp): New functions.
393 * mips.igen (do_c_cond_fmt): Remove.
394 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
395 Compare. Add result tracing.
396 (CxC1): Remove, replace with...
397 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
398 (DMxC1): Remove, replace with...
399 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
400 (MxC1): Remove, replace with...
401 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
403 2002-06-04 Chris Demetriou <cgd@broadcom.com>
405 * sim-main.h (FGRIDX): Remove, replace all uses with...
406 (FGR_BASE): New macro.
407 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
408 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
409 (NR_FGR, FGR): Likewise.
410 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
411 * mips.igen: Likewise.
413 2002-06-04 Chris Demetriou <cgd@broadcom.com>
415 * cp1.c: Add an FSF Copyright notice to this file.
417 2002-06-04 Chris Demetriou <cgd@broadcom.com>
418 Ed Satterthwaite <ehs@broadcom.com>
420 * cp1.c (Infinity): Remove.
421 * sim-main.h (Infinity): Likewise.
423 * cp1.c (fp_unary, fp_binary): New functions.
424 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
425 (fp_sqrt): New functions, implemented in terms of the above.
426 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
427 (Recip, SquareRoot): Remove (replaced by functions above).
428 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
429 (fp_recip, fp_sqrt): New prototypes.
430 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
431 (Recip, SquareRoot): Replace prototypes with #defines which
432 invoke the functions above.
434 2002-06-03 Chris Demetriou <cgd@broadcom.com>
436 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
437 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
438 file, remove PARAMS from prototypes.
439 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
440 simulator state arguments.
441 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
442 pass simulator state arguments.
443 * cp1.c (SD): Redefine as CPU_STATE(cpu).
444 (store_fpr, convert): Remove 'sd' argument.
445 (value_fpr): Likewise. Convert to use 'SD' instead.
447 2002-06-03 Chris Demetriou <cgd@broadcom.com>
449 * cp1.c (Min, Max): Remove #if 0'd functions.
450 * sim-main.h (Min, Max): Remove.
452 2002-06-03 Chris Demetriou <cgd@broadcom.com>
454 * cp1.c: fix formatting of switch case and default labels.
455 * interp.c: Likewise.
456 * sim-main.c: Likewise.
458 2002-06-03 Chris Demetriou <cgd@broadcom.com>
460 * cp1.c: Clean up comments which describe FP formats.
461 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
463 2002-06-03 Chris Demetriou <cgd@broadcom.com>
464 Ed Satterthwaite <ehs@broadcom.com>
466 * configure.in (mipsisa64sb1*-*-*): New target for supporting
467 Broadcom SiByte SB-1 processor configurations.
468 * configure: Regenerate.
469 * sb1.igen: New file.
470 * mips.igen: Include sb1.igen.
472 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
473 * mdmx.igen: Add "sb1" model to all appropriate functions and
475 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
476 (ob_func, ob_acc): Reference the above.
477 (qh_acc): Adjust to keep the same size as ob_acc.
478 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
479 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
481 2002-06-03 Chris Demetriou <cgd@broadcom.com>
483 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
485 2002-06-02 Chris Demetriou <cgd@broadcom.com>
486 Ed Satterthwaite <ehs@broadcom.com>
488 * mips.igen (mdmx): New (pseudo-)model.
489 * mdmx.c, mdmx.igen: New files.
490 * Makefile.in (SIM_OBJS): Add mdmx.o.
491 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
493 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
494 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
495 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
496 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
497 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
498 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
499 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
500 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
501 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
502 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
503 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
504 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
505 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
506 (qh_fmtsel): New macros.
507 (_sim_cpu): New member "acc".
508 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
509 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
511 2002-05-01 Chris Demetriou <cgd@broadcom.com>
513 * interp.c: Use 'deprecated' rather than 'depreciated.'
514 * sim-main.h: Likewise.
516 2002-05-01 Chris Demetriou <cgd@broadcom.com>
518 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
519 which wouldn't compile anyway.
520 * sim-main.h (unpredictable_action): New function prototype.
521 (Unpredictable): Define to call igen function unpredictable().
522 (NotWordValue): New macro to call igen function not_word_value().
523 (UndefinedResult): Remove.
524 * interp.c (undefined_result): Remove.
525 (unpredictable_action): New function.
526 * mips.igen (not_word_value, unpredictable): New functions.
527 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
528 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
529 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
530 NotWordValue() to check for unpredictable inputs, then
531 Unpredictable() to handle them.
533 2002-02-24 Chris Demetriou <cgd@broadcom.com>
535 * mips.igen: Fix formatting of calls to Unpredictable().
537 2002-04-20 Andrew Cagney <ac131313@redhat.com>
539 * interp.c (sim_open): Revert previous change.
541 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
543 * interp.c (sim_open): Disable chunk of code that wrote code in
544 vector table entries.
546 2002-03-19 Chris Demetriou <cgd@broadcom.com>
548 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
549 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
552 2002-03-19 Chris Demetriou <cgd@broadcom.com>
554 * cp1.c: Fix many formatting issues.
556 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
558 * cp1.c (fpu_format_name): New function to replace...
559 (DOFMT): This. Delete, and update all callers.
560 (fpu_rounding_mode_name): New function to replace...
561 (RMMODE): This. Delete, and update all callers.
563 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
565 * interp.c: Move FPU support routines from here to...
566 * cp1.c: Here. New file.
567 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
570 2002-03-12 Chris Demetriou <cgd@broadcom.com>
572 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
573 * mips.igen (mips32, mips64): New models, add to all instructions
574 and functions as appropriate.
575 (loadstore_ea, check_u64): New variant for model mips64.
576 (check_fmt_p): New variant for models mipsV and mips64, remove
577 mipsV model marking fro other variant.
580 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
581 for mips32 and mips64.
582 (DCLO, DCLZ): New instructions for mips64.
584 2002-03-07 Chris Demetriou <cgd@broadcom.com>
586 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
587 immediate or code as a hex value with the "%#lx" format.
588 (ANDI): Likewise, and fix printed instruction name.
590 2002-03-05 Chris Demetriou <cgd@broadcom.com>
592 * sim-main.h (UndefinedResult, Unpredictable): New macros
593 which currently do nothing.
595 2002-03-05 Chris Demetriou <cgd@broadcom.com>
597 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
598 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
599 (status_CU3): New definitions.
601 * sim-main.h (ExceptionCause): Add new values for MIPS32
602 and MIPS64: MDMX, MCheck, CacheErr. Update comments
603 for DebugBreakPoint and NMIReset to note their status in
605 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
606 (SignalExceptionCacheErr): New exception macros.
608 2002-03-05 Chris Demetriou <cgd@broadcom.com>
610 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
611 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
613 (SignalExceptionCoProcessorUnusable): Take as argument the
614 unusable coprocessor number.
616 2002-03-05 Chris Demetriou <cgd@broadcom.com>
618 * mips.igen: Fix formatting of all SignalException calls.
620 2002-03-05 Chris Demetriou <cgd@broadcom.com>
622 * sim-main.h (SIGNEXTEND): Remove.
624 2002-03-04 Chris Demetriou <cgd@broadcom.com>
626 * mips.igen: Remove gencode comment from top of file, fix
627 spelling in another comment.
629 2002-03-04 Chris Demetriou <cgd@broadcom.com>
631 * mips.igen (check_fmt, check_fmt_p): New functions to check
632 whether specific floating point formats are usable.
633 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
634 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
635 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
636 Use the new functions.
637 (do_c_cond_fmt): Remove format checks...
638 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
640 2002-03-03 Chris Demetriou <cgd@broadcom.com>
642 * mips.igen: Fix formatting of check_fpu calls.
644 2002-03-03 Chris Demetriou <cgd@broadcom.com>
646 * mips.igen (FLOOR.L.fmt): Store correct destination register.
648 2002-03-03 Chris Demetriou <cgd@broadcom.com>
650 * mips.igen: Remove whitespace at end of lines.
652 2002-03-02 Chris Demetriou <cgd@broadcom.com>
654 * mips.igen (loadstore_ea): New function to do effective
655 address calculations.
656 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
657 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
658 CACHE): Use loadstore_ea to do effective address computations.
660 2002-03-02 Chris Demetriou <cgd@broadcom.com>
662 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
663 * mips.igen (LL, CxC1, MxC1): Likewise.
665 2002-03-02 Chris Demetriou <cgd@broadcom.com>
667 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
668 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
669 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
670 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
671 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
672 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
673 Don't split opcode fields by hand, use the opcode field values
676 2002-03-01 Chris Demetriou <cgd@broadcom.com>
678 * mips.igen (do_divu): Fix spacing.
680 * mips.igen (do_dsllv): Move to be right before DSLLV,
681 to match the rest of the do_<shift> functions.
683 2002-03-01 Chris Demetriou <cgd@broadcom.com>
685 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
686 DSRL32, do_dsrlv): Trace inputs and results.
688 2002-03-01 Chris Demetriou <cgd@broadcom.com>
690 * mips.igen (CACHE): Provide instruction-printing string.
692 * interp.c (signal_exception): Comment tokens after #endif.
694 2002-02-28 Chris Demetriou <cgd@broadcom.com>
696 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
697 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
698 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
699 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
700 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
701 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
702 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
703 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
705 2002-02-28 Chris Demetriou <cgd@broadcom.com>
707 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
708 instruction-printing string.
709 (LWU): Use '64' as the filter flag.
711 2002-02-28 Chris Demetriou <cgd@broadcom.com>
713 * mips.igen (SDXC1): Fix instruction-printing string.
715 2002-02-28 Chris Demetriou <cgd@broadcom.com>
717 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
720 2002-02-27 Chris Demetriou <cgd@broadcom.com>
722 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
725 2002-02-27 Chris Demetriou <cgd@broadcom.com>
727 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
728 add a comma) so that it more closely match the MIPS ISA
729 documentation opcode partitioning.
730 (PREF): Put useful names on opcode fields, and include
731 instruction-printing string.
733 2002-02-27 Chris Demetriou <cgd@broadcom.com>
735 * mips.igen (check_u64): New function which in the future will
736 check whether 64-bit instructions are usable and signal an
737 exception if not. Currently a no-op.
738 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
739 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
740 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
741 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
743 * mips.igen (check_fpu): New function which in the future will
744 check whether FPU instructions are usable and signal an exception
745 if not. Currently a no-op.
746 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
747 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
748 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
749 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
750 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
751 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
752 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
753 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
755 2002-02-27 Chris Demetriou <cgd@broadcom.com>
757 * mips.igen (do_load_left, do_load_right): Move to be immediately
759 (do_store_left, do_store_right): Move to be immediately following
762 2002-02-27 Chris Demetriou <cgd@broadcom.com>
764 * mips.igen (mipsV): New model name. Also, add it to
765 all instructions and functions where it is appropriate.
767 2002-02-18 Chris Demetriou <cgd@broadcom.com>
769 * mips.igen: For all functions and instructions, list model
770 names that support that instruction one per line.
772 2002-02-11 Chris Demetriou <cgd@broadcom.com>
774 * mips.igen: Add some additional comments about supported
775 models, and about which instructions go where.
776 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
777 order as is used in the rest of the file.
779 2002-02-11 Chris Demetriou <cgd@broadcom.com>
781 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
782 indicating that ALU32_END or ALU64_END are there to check
784 (DADD): Likewise, but also remove previous comment about
787 2002-02-10 Chris Demetriou <cgd@broadcom.com>
789 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
790 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
791 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
792 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
793 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
794 fields (i.e., add and move commas) so that they more closely
795 match the MIPS ISA documentation opcode partitioning.
797 2002-02-10 Chris Demetriou <cgd@broadcom.com>
799 * mips.igen (ADDI): Print immediate value.
801 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
802 (SLL): Print "nop" specially, and don't run the code
803 that does the shift for the "nop" case.
805 2001-11-17 Fred Fish <fnf@redhat.com>
807 * sim-main.h (float_operation): Move enum declaration outside
808 of _sim_cpu struct declaration.
810 2001-04-12 Jim Blandy <jimb@redhat.com>
812 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
813 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
815 * sim-main.h (COCIDX): Remove definition; this isn't supported by
816 PENDING_FILL, and you can get the intended effect gracefully by
817 calling PENDING_SCHED directly.
819 2001-02-23 Ben Elliston <bje@redhat.com>
821 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
822 already defined elsewhere.
824 2001-02-19 Ben Elliston <bje@redhat.com>
826 * sim-main.h (sim_monitor): Return an int.
827 * interp.c (sim_monitor): Add return values.
828 (signal_exception): Handle error conditions from sim_monitor.
830 2001-02-08 Ben Elliston <bje@redhat.com>
832 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
833 (store_memory): Likewise, pass cia to sim_core_write*.
835 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
837 On advice from Chris G. Demetriou <cgd@sibyte.com>:
838 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
840 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
842 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
843 * Makefile.in: Don't delete *.igen when cleaning directory.
845 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
847 * m16.igen (break): Call SignalException not sim_engine_halt.
849 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
852 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
854 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
856 * mips.igen (MxC1, DMxC1): Fix printf formatting.
858 2000-05-24 Michael Hayes <mhayes@cygnus.com>
860 * mips.igen (do_dmultx): Fix typo.
862 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
864 * configure: Regenerated to track ../common/aclocal.m4 changes.
866 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
868 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
870 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
872 * sim-main.h (GPR_CLEAR): Define macro.
874 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
876 * interp.c (decode_coproc): Output long using %lx and not %s.
878 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
880 * interp.c (sim_open): Sort & extend dummy memory regions for
881 --board=jmr3904 for eCos.
883 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
885 * configure: Regenerated.
887 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
889 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
890 calls, conditional on the simulator being in verbose mode.
892 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
894 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
895 cache don't get ReservedInstruction traps.
897 1999-11-29 Mark Salter <msalter@cygnus.com>
899 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
900 to clear status bits in sdisr register. This is how the hardware works.
902 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
903 being used by cygmon.
905 1999-11-11 Andrew Haley <aph@cygnus.com>
907 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
910 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
912 * mips.igen (MULT): Correct previous mis-applied patch.
914 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
916 * mips.igen (delayslot32): Handle sequence like
917 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
918 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
919 (MULT): Actually pass the third register...
921 1999-09-03 Mark Salter <msalter@cygnus.com>
923 * interp.c (sim_open): Added more memory aliases for additional
924 hardware being touched by cygmon on jmr3904 board.
926 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
928 * configure: Regenerated to track ../common/aclocal.m4 changes.
930 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
932 * interp.c (sim_store_register): Handle case where client - GDB -
933 specifies that a 4 byte register is 8 bytes in size.
934 (sim_fetch_register): Ditto.
936 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
938 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
939 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
940 (idt_monitor_base): Base address for IDT monitor traps.
941 (pmon_monitor_base): Ditto for PMON.
942 (lsipmon_monitor_base): Ditto for LSI PMON.
943 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
944 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
945 (sim_firmware_command): New function.
946 (mips_option_handler): Call it for OPTION_FIRMWARE.
947 (sim_open): Allocate memory for idt_monitor region. If "--board"
948 option was given, add no monitor by default. Add BREAK hooks only if
949 monitors are also there.
951 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
953 * interp.c (sim_monitor): Flush output before reading input.
955 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
957 * tconfig.in (SIM_HANDLES_LMA): Always define.
959 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
961 From Mark Salter <msalter@cygnus.com>:
962 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
963 (sim_open): Add setup for BSP board.
965 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
967 * mips.igen (MULT, MULTU): Add syntax for two operand version.
968 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
969 them as unimplemented.
971 1999-05-08 Felix Lee <flee@cygnus.com>
973 * configure: Regenerated to track ../common/aclocal.m4 changes.
975 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
977 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
979 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
981 * configure.in: Any mips64vr5*-*-* target should have
982 -DTARGET_ENABLE_FR=1.
983 (default_endian): Any mips64vr*el-*-* target should default to
985 * configure: Re-generate.
987 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
989 * mips.igen (ldl): Extend from _16_, not 32.
991 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
993 * interp.c (sim_store_register): Force registers written to by GDB
994 into an un-interpreted state.
996 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
998 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
999 CPU, start periodic background I/O polls.
1000 (tx3904sio_poll): New function: periodic I/O poller.
1002 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1004 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1006 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1008 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1011 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1013 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1014 (load_word): Call SIM_CORE_SIGNAL hook on error.
1015 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1016 starting. For exception dispatching, pass PC instead of NULL_CIA.
1017 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1018 * sim-main.h (COP0_BADVADDR): Define.
1019 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1020 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1021 (_sim_cpu): Add exc_* fields to store register value snapshots.
1022 * mips.igen (*): Replace memory-related SignalException* calls
1023 with references to SIM_CORE_SIGNAL hook.
1025 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1027 * sim-main.c (*): Minor warning cleanups.
1029 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1031 * m16.igen (DADDIU5): Correct type-o.
1033 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1035 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1038 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1040 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1042 (interp.o): Add dependency on itable.h
1043 (oengine.c, gencode): Delete remaining references.
1044 (BUILT_SRC_FROM_GEN): Clean up.
1046 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1049 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1050 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1051 tmp-run-hack) : New.
1052 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1053 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1054 Drop the "64" qualifier to get the HACK generator working.
1055 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1056 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1057 qualifier to get the hack generator working.
1058 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1059 (DSLL): Use do_dsll.
1060 (DSLLV): Use do_dsllv.
1061 (DSRA): Use do_dsra.
1062 (DSRL): Use do_dsrl.
1063 (DSRLV): Use do_dsrlv.
1064 (BC1): Move *vr4100 to get the HACK generator working.
1065 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1066 get the HACK generator working.
1067 (MACC) Rename to get the HACK generator working.
1068 (DMACC,MACCS,DMACCS): Add the 64.
1070 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1072 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1073 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1075 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1077 * mips/interp.c (DEBUG): Cleanups.
1079 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1081 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1082 (tx3904sio_tickle): fflush after a stdout character output.
1084 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1086 * interp.c (sim_close): Uninstall modules.
1088 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1090 * sim-main.h, interp.c (sim_monitor): Change to global
1093 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1095 * configure.in (vr4100): Only include vr4100 instructions in
1097 * configure: Re-generate.
1098 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1100 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1102 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1103 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1106 * configure.in (sim_default_gen, sim_use_gen): Replace with
1108 (--enable-sim-igen): Delete config option. Always using IGEN.
1109 * configure: Re-generate.
1111 * Makefile.in (gencode): Kill, kill, kill.
1114 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1116 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1117 bit mips16 igen simulator.
1118 * configure: Re-generate.
1120 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1121 as part of vr4100 ISA.
1122 * vr.igen: Mark all instructions as 64 bit only.
1124 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1126 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1129 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1131 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1132 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1133 * configure: Re-generate.
1135 * m16.igen (BREAK): Define breakpoint instruction.
1136 (JALX32): Mark instruction as mips16 and not r3900.
1137 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1139 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1141 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1143 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1144 insn as a debug breakpoint.
1146 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1148 (PENDING_SCHED): Clean up trace statement.
1149 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1150 (PENDING_FILL): Delay write by only one cycle.
1151 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1153 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1155 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1157 (pending_tick): Move incrementing of index to FOR statement.
1158 (pending_tick): Only update PENDING_OUT after a write has occured.
1160 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1162 * configure: Re-generate.
1164 * interp.c (sim_engine_run OLD): Delete explicit call to
1165 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1167 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1169 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1170 interrupt level number to match changed SignalExceptionInterrupt
1173 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1175 * interp.c: #include "itable.h" if WITH_IGEN.
1176 (get_insn_name): New function.
1177 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1178 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1180 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1182 * configure: Rebuilt to inhale new common/aclocal.m4.
1184 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1186 * dv-tx3904sio.c: Include sim-assert.h.
1188 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1190 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1191 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1192 Reorganize target-specific sim-hardware checks.
1193 * configure: rebuilt.
1194 * interp.c (sim_open): For tx39 target boards, set
1195 OPERATING_ENVIRONMENT, add tx3904sio devices.
1196 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1197 ROM executables. Install dv-sockser into sim-modules list.
1199 * dv-tx3904irc.c: Compiler warning clean-up.
1200 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1201 frequent hw-trace messages.
1203 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1205 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1207 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1209 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1211 * vr.igen: New file.
1212 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1213 * mips.igen: Define vr4100 model. Include vr.igen.
1214 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1216 * mips.igen (check_mf_hilo): Correct check.
1218 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1220 * sim-main.h (interrupt_event): Add prototype.
1222 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1223 register_ptr, register_value.
1224 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1226 * sim-main.h (tracefh): Make extern.
1228 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1230 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1231 Reduce unnecessarily high timer event frequency.
1232 * dv-tx3904cpu.c: Ditto for interrupt event.
1234 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1236 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1238 (interrupt_event): Made non-static.
1240 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1241 interchange of configuration values for external vs. internal
1244 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1246 * mips.igen (BREAK): Moved code to here for
1247 simulator-reserved break instructions.
1248 * gencode.c (build_instruction): Ditto.
1249 * interp.c (signal_exception): Code moved from here. Non-
1250 reserved instructions now use exception vector, rather
1252 * sim-main.h: Moved magic constants to here.
1254 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1256 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1257 register upon non-zero interrupt event level, clear upon zero
1259 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1260 by passing zero event value.
1261 (*_io_{read,write}_buffer): Endianness fixes.
1262 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1263 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1265 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1266 serial I/O and timer module at base address 0xFFFF0000.
1268 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1270 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1273 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1275 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1277 * configure: Update.
1279 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1281 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1282 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1283 * configure.in: Include tx3904tmr in hw_device list.
1284 * configure: Rebuilt.
1285 * interp.c (sim_open): Instantiate three timer instances.
1286 Fix address typo of tx3904irc instance.
1288 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1290 * interp.c (signal_exception): SystemCall exception now uses
1291 the exception vector.
1293 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1295 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1298 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1300 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1302 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1304 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1306 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1307 sim-main.h. Declare a struct hw_descriptor instead of struct
1308 hw_device_descriptor.
1310 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1312 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1313 right bits and then re-align left hand bytes to correct byte
1314 lanes. Fix incorrect computation in do_store_left when loading
1315 bytes from second word.
1317 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1319 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1320 * interp.c (sim_open): Only create a device tree when HW is
1323 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1324 * interp.c (signal_exception): Ditto.
1326 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1328 * gencode.c: Mark BEGEZALL as LIKELY.
1330 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1332 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1333 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1335 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1337 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1338 modules. Recognize TX39 target with "mips*tx39" pattern.
1339 * configure: Rebuilt.
1340 * sim-main.h (*): Added many macros defining bits in
1341 TX39 control registers.
1342 (SignalInterrupt): Send actual PC instead of NULL.
1343 (SignalNMIReset): New exception type.
1344 * interp.c (board): New variable for future use to identify
1345 a particular board being simulated.
1346 (mips_option_handler,mips_options): Added "--board" option.
1347 (interrupt_event): Send actual PC.
1348 (sim_open): Make memory layout conditional on board setting.
1349 (signal_exception): Initial implementation of hardware interrupt
1350 handling. Accept another break instruction variant for simulator
1352 (decode_coproc): Implement RFE instruction for TX39.
1353 (mips.igen): Decode RFE instruction as such.
1354 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1355 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1356 bbegin to implement memory map.
1357 * dv-tx3904cpu.c: New file.
1358 * dv-tx3904irc.c: New file.
1360 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1362 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1364 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1366 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1367 with calls to check_div_hilo.
1369 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1371 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1372 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1373 Add special r3900 version of do_mult_hilo.
1374 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1375 with calls to check_mult_hilo.
1376 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1377 with calls to check_div_hilo.
1379 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1381 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1382 Document a replacement.
1384 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1386 * interp.c (sim_monitor): Make mon_printf work.
1388 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1390 * sim-main.h (INSN_NAME): New arg `cpu'.
1392 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1394 * configure: Regenerated to track ../common/aclocal.m4 changes.
1396 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1398 * configure: Regenerated to track ../common/aclocal.m4 changes.
1401 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1403 * acconfig.h: New file.
1404 * configure.in: Reverted change of Apr 24; use sinclude again.
1406 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1408 * configure: Regenerated to track ../common/aclocal.m4 changes.
1411 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1413 * configure.in: Don't call sinclude.
1415 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1417 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1419 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1421 * mips.igen (ERET): Implement.
1423 * interp.c (decode_coproc): Return sign-extended EPC.
1425 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1427 * interp.c (signal_exception): Do not ignore Trap.
1428 (signal_exception): On TRAP, restart at exception address.
1429 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1430 (signal_exception): Update.
1431 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1432 so that TRAP instructions are caught.
1434 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1436 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1437 contains HI/LO access history.
1438 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1439 (HIACCESS, LOACCESS): Delete, replace with
1440 (HIHISTORY, LOHISTORY): New macros.
1441 (CHECKHILO): Delete all, moved to mips.igen
1443 * gencode.c (build_instruction): Do not generate checks for
1444 correct HI/LO register usage.
1446 * interp.c (old_engine_run): Delete checks for correct HI/LO
1449 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1450 check_mf_cycles): New functions.
1451 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1452 do_divu, domultx, do_mult, do_multu): Use.
1454 * tx.igen ("madd", "maddu"): Use.
1456 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1458 * mips.igen (DSRAV): Use function do_dsrav.
1459 (SRAV): Use new function do_srav.
1461 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1462 (B): Sign extend 11 bit immediate.
1463 (EXT-B*): Shift 16 bit immediate left by 1.
1464 (ADDIU*): Don't sign extend immediate value.
1466 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1468 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1470 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1473 * mips.igen (delayslot32, nullify_next_insn): New functions.
1474 (m16.igen): Always include.
1475 (do_*): Add more tracing.
1477 * m16.igen (delayslot16): Add NIA argument, could be called by a
1478 32 bit MIPS16 instruction.
1480 * interp.c (ifetch16): Move function from here.
1481 * sim-main.c (ifetch16): To here.
1483 * sim-main.c (ifetch16, ifetch32): Update to match current
1484 implementations of LH, LW.
1485 (signal_exception): Don't print out incorrect hex value of illegal
1488 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1490 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1493 * m16.igen: Implement MIPS16 instructions.
1495 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1496 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1497 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1498 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1499 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1500 bodies of corresponding code from 32 bit insn to these. Also used
1501 by MIPS16 versions of functions.
1503 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1504 (IMEM16): Drop NR argument from macro.
1506 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1508 * Makefile.in (SIM_OBJS): Add sim-main.o.
1510 * sim-main.h (address_translation, load_memory, store_memory,
1511 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1513 (pr_addr, pr_uword64): Declare.
1514 (sim-main.c): Include when H_REVEALS_MODULE_P.
1516 * interp.c (address_translation, load_memory, store_memory,
1517 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1519 * sim-main.c: To here. Fix compilation problems.
1521 * configure.in: Enable inlining.
1522 * configure: Re-config.
1524 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1526 * configure: Regenerated to track ../common/aclocal.m4 changes.
1528 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1530 * mips.igen: Include tx.igen.
1531 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1532 * tx.igen: New file, contains MADD and MADDU.
1534 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1535 the hardwired constant `7'.
1536 (store_memory): Ditto.
1537 (LOADDRMASK): Move definition to sim-main.h.
1539 mips.igen (MTC0): Enable for r3900.
1542 mips.igen (do_load_byte): Delete.
1543 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1544 do_store_right): New functions.
1545 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1547 configure.in: Let the tx39 use igen again.
1550 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1552 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1553 not an address sized quantity. Return zero for cache sizes.
1555 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1557 * mips.igen (r3900): r3900 does not support 64 bit integer
1560 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1562 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1564 * configure : Rebuild.
1566 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1568 * configure: Regenerated to track ../common/aclocal.m4 changes.
1570 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1572 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1574 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1576 * configure: Regenerated to track ../common/aclocal.m4 changes.
1577 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1579 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1581 * configure: Regenerated to track ../common/aclocal.m4 changes.
1583 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1585 * interp.c (Max, Min): Comment out functions. Not yet used.
1587 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1589 * configure: Regenerated to track ../common/aclocal.m4 changes.
1591 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1593 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1594 configurable settings for stand-alone simulator.
1596 * configure.in: Added X11 search, just in case.
1598 * configure: Regenerated.
1600 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1602 * interp.c (sim_write, sim_read, load_memory, store_memory):
1603 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1605 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1607 * sim-main.h (GETFCC): Return an unsigned value.
1609 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1611 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1612 (DADD): Result destination is RD not RT.
1614 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1616 * sim-main.h (HIACCESS, LOACCESS): Always define.
1618 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1620 * interp.c (sim_info): Delete.
1622 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1624 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1625 (mips_option_handler): New argument `cpu'.
1626 (sim_open): Update call to sim_add_option_table.
1628 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1630 * mips.igen (CxC1): Add tracing.
1632 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1634 * sim-main.h (Max, Min): Declare.
1636 * interp.c (Max, Min): New functions.
1638 * mips.igen (BC1): Add tracing.
1640 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1642 * interp.c Added memory map for stack in vr4100
1644 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1646 * interp.c (load_memory): Add missing "break"'s.
1648 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1650 * interp.c (sim_store_register, sim_fetch_register): Pass in
1651 length parameter. Return -1.
1653 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1655 * interp.c: Added hardware init hook, fixed warnings.
1657 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1659 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1661 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1663 * interp.c (ifetch16): New function.
1665 * sim-main.h (IMEM32): Rename IMEM.
1666 (IMEM16_IMMED): Define.
1668 (DELAY_SLOT): Update.
1670 * m16run.c (sim_engine_run): New file.
1672 * m16.igen: All instructions except LB.
1673 (LB): Call do_load_byte.
1674 * mips.igen (do_load_byte): New function.
1675 (LB): Call do_load_byte.
1677 * mips.igen: Move spec for insn bit size and high bit from here.
1678 * Makefile.in (tmp-igen, tmp-m16): To here.
1680 * m16.dc: New file, decode mips16 instructions.
1682 * Makefile.in (SIM_NO_ALL): Define.
1683 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1685 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1687 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1688 point unit to 32 bit registers.
1689 * configure: Re-generate.
1691 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1693 * configure.in (sim_use_gen): Make IGEN the default simulator
1694 generator for generic 32 and 64 bit mips targets.
1695 * configure: Re-generate.
1697 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1699 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1702 * interp.c (sim_fetch_register, sim_store_register): Read/write
1703 FGR from correct location.
1704 (sim_open): Set size of FGR's according to
1705 WITH_TARGET_FLOATING_POINT_BITSIZE.
1707 * sim-main.h (FGR): Store floating point registers in a separate
1710 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1712 * configure: Regenerated to track ../common/aclocal.m4 changes.
1714 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1716 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1718 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1720 * interp.c (pending_tick): New function. Deliver pending writes.
1722 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1723 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1724 it can handle mixed sized quantites and single bits.
1726 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1728 * interp.c (oengine.h): Do not include when building with IGEN.
1729 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1730 (sim_info): Ditto for PROCESSOR_64BIT.
1731 (sim_monitor): Replace ut_reg with unsigned_word.
1732 (*): Ditto for t_reg.
1733 (LOADDRMASK): Define.
1734 (sim_open): Remove defunct check that host FP is IEEE compliant,
1735 using software to emulate floating point.
1736 (value_fpr, ...): Always compile, was conditional on HASFPU.
1738 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1740 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1743 * interp.c (SD, CPU): Define.
1744 (mips_option_handler): Set flags in each CPU.
1745 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1746 (sim_close): Do not clear STATE, deleted anyway.
1747 (sim_write, sim_read): Assume CPU zero's vm should be used for
1749 (sim_create_inferior): Set the PC for all processors.
1750 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1752 (mips16_entry): Pass correct nr of args to store_word, load_word.
1753 (ColdReset): Cold reset all cpu's.
1754 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1755 (sim_monitor, load_memory, store_memory, signal_exception): Use
1756 `CPU' instead of STATE_CPU.
1759 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1762 * sim-main.h (signal_exception): Add sim_cpu arg.
1763 (SignalException*): Pass both SD and CPU to signal_exception.
1764 * interp.c (signal_exception): Update.
1766 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1768 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1769 address_translation): Ditto
1770 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1772 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1774 * configure: Regenerated to track ../common/aclocal.m4 changes.
1776 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1778 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1780 * mips.igen (model): Map processor names onto BFD name.
1782 * sim-main.h (CPU_CIA): Delete.
1783 (SET_CIA, GET_CIA): Define
1785 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1787 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1790 * configure.in (default_endian): Configure a big-endian simulator
1792 * configure: Re-generate.
1794 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1796 * configure: Regenerated to track ../common/aclocal.m4 changes.
1798 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1800 * interp.c (sim_monitor): Handle Densan monitor outbyte
1801 and inbyte functions.
1803 1997-12-29 Felix Lee <flee@cygnus.com>
1805 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1807 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1809 * Makefile.in (tmp-igen): Arrange for $zero to always be
1810 reset to zero after every instruction.
1812 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1814 * configure: Regenerated to track ../common/aclocal.m4 changes.
1817 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1819 * mips.igen (MSUB): Fix to work like MADD.
1820 * gencode.c (MSUB): Similarly.
1822 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1824 * configure: Regenerated to track ../common/aclocal.m4 changes.
1826 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1828 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1830 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1832 * sim-main.h (sim-fpu.h): Include.
1834 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1835 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1836 using host independant sim_fpu module.
1838 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1840 * interp.c (signal_exception): Report internal errors with SIGABRT
1843 * sim-main.h (C0_CONFIG): New register.
1844 (signal.h): No longer include.
1846 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1848 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1850 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1852 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1854 * mips.igen: Tag vr5000 instructions.
1855 (ANDI): Was missing mipsIV model, fix assembler syntax.
1856 (do_c_cond_fmt): New function.
1857 (C.cond.fmt): Handle mips I-III which do not support CC field
1859 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1860 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1862 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1863 vr5000 which saves LO in a GPR separatly.
1865 * configure.in (enable-sim-igen): For vr5000, select vr5000
1866 specific instructions.
1867 * configure: Re-generate.
1869 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1871 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1873 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1874 fmt_uninterpreted_64 bit cases to switch. Convert to
1877 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1879 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1880 as specified in IV3.2 spec.
1881 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1883 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1885 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1886 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1887 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1888 PENDING_FILL versions of instructions. Simplify.
1890 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1892 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1894 (MTHI, MFHI): Disable code checking HI-LO.
1896 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1898 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1900 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1902 * gencode.c (build_mips16_operands): Replace IPC with cia.
1904 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1905 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1907 (UndefinedResult): Replace function with macro/function
1909 (sim_engine_run): Don't save PC in IPC.
1911 * sim-main.h (IPC): Delete.
1914 * interp.c (signal_exception, store_word, load_word,
1915 address_translation, load_memory, store_memory, cache_op,
1916 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1917 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1918 current instruction address - cia - argument.
1919 (sim_read, sim_write): Call address_translation directly.
1920 (sim_engine_run): Rename variable vaddr to cia.
1921 (signal_exception): Pass cia to sim_monitor
1923 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1924 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1925 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1927 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1928 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1931 * interp.c (signal_exception): Pass restart address to
1934 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1935 idecode.o): Add dependency.
1937 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1939 (DELAY_SLOT): Update NIA not PC with branch address.
1940 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1942 * mips.igen: Use CIA not PC in branch calculations.
1943 (illegal): Call SignalException.
1944 (BEQ, ADDIU): Fix assembler.
1946 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1948 * m16.igen (JALX): Was missing.
1950 * configure.in (enable-sim-igen): New configuration option.
1951 * configure: Re-generate.
1953 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1955 * interp.c (load_memory, store_memory): Delete parameter RAW.
1956 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1957 bypassing {load,store}_memory.
1959 * sim-main.h (ByteSwapMem): Delete definition.
1961 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1963 * interp.c (sim_do_command, sim_commands): Delete mips specific
1964 commands. Handled by module sim-options.
1966 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1967 (WITH_MODULO_MEMORY): Define.
1969 * interp.c (sim_info): Delete code printing memory size.
1971 * interp.c (mips_size): Nee sim_size, delete function.
1973 (monitor, monitor_base, monitor_size): Delete global variables.
1974 (sim_open, sim_close): Delete code creating monitor and other
1975 memory regions. Use sim-memopts module, via sim_do_commandf, to
1976 manage memory regions.
1977 (load_memory, store_memory): Use sim-core for memory model.
1979 * interp.c (address_translation): Delete all memory map code
1980 except line forcing 32 bit addresses.
1982 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1984 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1987 * interp.c (logfh, logfile): Delete globals.
1988 (sim_open, sim_close): Delete code opening & closing log file.
1989 (mips_option_handler): Delete -l and -n options.
1990 (OPTION mips_options): Ditto.
1992 * interp.c (OPTION mips_options): Rename option trace to dinero.
1993 (mips_option_handler): Update.
1995 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1997 * interp.c (fetch_str): New function.
1998 (sim_monitor): Rewrite using sim_read & sim_write.
1999 (sim_open): Check magic number.
2000 (sim_open): Write monitor vectors into memory using sim_write.
2001 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2002 (sim_read, sim_write): Simplify - transfer data one byte at a
2004 (load_memory, store_memory): Clarify meaning of parameter RAW.
2006 * sim-main.h (isHOST): Defete definition.
2007 (isTARGET): Mark as depreciated.
2008 (address_translation): Delete parameter HOST.
2010 * interp.c (address_translation): Delete parameter HOST.
2012 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2016 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2017 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2019 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2021 * mips.igen: Add model filter field to records.
2023 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2025 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2027 interp.c (sim_engine_run): Do not compile function sim_engine_run
2028 when WITH_IGEN == 1.
2030 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2031 target architecture.
2033 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2034 igen. Replace with configuration variables sim_igen_flags /
2037 * m16.igen: New file. Copy mips16 insns here.
2038 * mips.igen: From here.
2040 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2042 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2044 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2046 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2048 * gencode.c (build_instruction): Follow sim_write's lead in using
2049 BigEndianMem instead of !ByteSwapMem.
2051 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2053 * configure.in (sim_gen): Dependent on target, select type of
2054 generator. Always select old style generator.
2056 configure: Re-generate.
2058 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2060 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2061 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2062 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2063 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2064 SIM_@sim_gen@_*, set by autoconf.
2066 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2068 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2070 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2071 CURRENT_FLOATING_POINT instead.
2073 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2074 (address_translation): Raise exception InstructionFetch when
2075 translation fails and isINSTRUCTION.
2077 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2078 sim_engine_run): Change type of of vaddr and paddr to
2080 (address_translation, prefetch, load_memory, store_memory,
2081 cache_op): Change type of vAddr and pAddr to address_word.
2083 * gencode.c (build_instruction): Change type of vaddr and paddr to
2086 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2088 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2089 macro to obtain result of ALU op.
2091 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2093 * interp.c (sim_info): Call profile_print.
2095 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2097 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2099 * sim-main.h (WITH_PROFILE): Do not define, defined in
2100 common/sim-config.h. Use sim-profile module.
2101 (simPROFILE): Delete defintion.
2103 * interp.c (PROFILE): Delete definition.
2104 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2105 (sim_close): Delete code writing profile histogram.
2106 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2108 (sim_engine_run): Delete code profiling the PC.
2110 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2112 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2114 * interp.c (sim_monitor): Make register pointers of type
2117 * sim-main.h: Make registers of type unsigned_word not
2120 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2122 * interp.c (sync_operation): Rename from SyncOperation, make
2123 global, add SD argument.
2124 (prefetch): Rename from Prefetch, make global, add SD argument.
2125 (decode_coproc): Make global.
2127 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2129 * gencode.c (build_instruction): Generate DecodeCoproc not
2130 decode_coproc calls.
2132 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2133 (SizeFGR): Move to sim-main.h
2134 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2135 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2136 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2138 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2139 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2140 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2141 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2142 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2143 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2145 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2147 (sim-alu.h): Include.
2148 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2149 (sim_cia): Typedef to instruction_address.
2151 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2153 * Makefile.in (interp.o): Rename generated file engine.c to
2158 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2160 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2162 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2164 * gencode.c (build_instruction): For "FPSQRT", output correct
2165 number of arguments to Recip.
2167 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2169 * Makefile.in (interp.o): Depends on sim-main.h
2171 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2173 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2174 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2175 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2176 STATE, DSSTATE): Define
2177 (GPR, FGRIDX, ..): Define.
2179 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2180 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2181 (GPR, FGRIDX, ...): Delete macros.
2183 * interp.c: Update names to match defines from sim-main.h
2185 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2187 * interp.c (sim_monitor): Add SD argument.
2188 (sim_warning): Delete. Replace calls with calls to
2190 (sim_error): Delete. Replace calls with sim_io_error.
2191 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2192 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2193 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2195 (mips_size): Rename from sim_size. Add SD argument.
2197 * interp.c (simulator): Delete global variable.
2198 (callback): Delete global variable.
2199 (mips_option_handler, sim_open, sim_write, sim_read,
2200 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2201 sim_size,sim_monitor): Use sim_io_* not callback->*.
2202 (sim_open): ZALLOC simulator struct.
2203 (PROFILE): Do not define.
2205 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2207 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2208 support.h with corresponding code.
2210 * sim-main.h (word64, uword64), support.h: Move definition to
2212 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2215 * Makefile.in: Update dependencies
2216 * interp.c: Do not include.
2218 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2220 * interp.c (address_translation, load_memory, store_memory,
2221 cache_op): Rename to from AddressTranslation et.al., make global,
2224 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2227 * interp.c (SignalException): Rename to signal_exception, make
2230 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2232 * sim-main.h (SignalException, SignalExceptionInterrupt,
2233 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2234 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2235 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2238 * interp.c, support.h: Use.
2240 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2242 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2243 to value_fpr / store_fpr. Add SD argument.
2244 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2245 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2247 * sim-main.h (ValueFPR, StoreFPR): Define.
2249 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2251 * interp.c (sim_engine_run): Check consistency between configure
2252 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2255 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2256 (mips_fpu): Configure WITH_FLOATING_POINT.
2257 (mips_endian): Configure WITH_TARGET_ENDIAN.
2258 * configure: Update.
2260 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2262 * configure: Regenerated to track ../common/aclocal.m4 changes.
2264 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2266 * configure: Regenerated.
2268 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2270 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2272 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2274 * gencode.c (print_igen_insn_models): Assume certain architectures
2275 include all mips* instructions.
2276 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2279 * Makefile.in (tmp.igen): Add target. Generate igen input from
2282 * gencode.c (FEATURE_IGEN): Define.
2283 (main): Add --igen option. Generate output in igen format.
2284 (process_instructions): Format output according to igen option.
2285 (print_igen_insn_format): New function.
2286 (print_igen_insn_models): New function.
2287 (process_instructions): Only issue warnings and ignore
2288 instructions when no FEATURE_IGEN.
2290 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2292 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2295 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2297 * configure: Regenerated to track ../common/aclocal.m4 changes.
2299 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2301 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2302 SIM_RESERVED_BITS): Delete, moved to common.
2303 (SIM_EXTRA_CFLAGS): Update.
2305 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2307 * configure.in: Configure non-strict memory alignment.
2308 * configure: Regenerated to track ../common/aclocal.m4 changes.
2310 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2312 * configure: Regenerated to track ../common/aclocal.m4 changes.
2314 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2316 * gencode.c (SDBBP,DERET): Added (3900) insns.
2317 (RFE): Turn on for 3900.
2318 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2319 (dsstate): Made global.
2320 (SUBTARGET_R3900): Added.
2321 (CANCELDELAYSLOT): New.
2322 (SignalException): Ignore SystemCall rather than ignore and
2323 terminate. Add DebugBreakPoint handling.
2324 (decode_coproc): New insns RFE, DERET; and new registers Debug
2325 and DEPC protected by SUBTARGET_R3900.
2326 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2328 * Makefile.in,configure.in: Add mips subtarget option.
2329 * configure: Update.
2331 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2333 * gencode.c: Add r3900 (tx39).
2336 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2338 * gencode.c (build_instruction): Don't need to subtract 4 for
2341 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2343 * interp.c: Correct some HASFPU problems.
2345 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2347 * configure: Regenerated to track ../common/aclocal.m4 changes.
2349 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2351 * interp.c (mips_options): Fix samples option short form, should
2354 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2356 * interp.c (sim_info): Enable info code. Was just returning.
2358 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2360 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2363 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2365 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2367 (build_instruction): Ditto for LL.
2369 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2371 * configure: Regenerated to track ../common/aclocal.m4 changes.
2373 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2375 * configure: Regenerated to track ../common/aclocal.m4 changes.
2378 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2380 * interp.c (sim_open): Add call to sim_analyze_program, update
2383 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2385 * interp.c (sim_kill): Delete.
2386 (sim_create_inferior): Add ABFD argument. Set PC from same.
2387 (sim_load): Move code initializing trap handlers from here.
2388 (sim_open): To here.
2389 (sim_load): Delete, use sim-hload.c.
2391 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2393 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2395 * configure: Regenerated to track ../common/aclocal.m4 changes.
2398 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2400 * interp.c (sim_open): Add ABFD argument.
2401 (sim_load): Move call to sim_config from here.
2402 (sim_open): To here. Check return status.
2404 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2406 * gencode.c (build_instruction): Two arg MADD should
2407 not assign result to $0.
2409 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2411 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2412 * sim/mips/configure.in: Regenerate.
2414 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2416 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2417 signed8, unsigned8 et.al. types.
2419 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2420 hosts when selecting subreg.
2422 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2424 * interp.c (sim_engine_run): Reset the ZERO register to zero
2425 regardless of FEATURE_WARN_ZERO.
2426 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2428 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2430 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2431 (SignalException): For BreakPoints ignore any mode bits and just
2433 (SignalException): Always set the CAUSE register.
2435 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2437 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2438 exception has been taken.
2440 * interp.c: Implement the ERET and mt/f sr instructions.
2442 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2444 * interp.c (SignalException): Don't bother restarting an
2447 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2449 * interp.c (SignalException): Really take an interrupt.
2450 (interrupt_event): Only deliver interrupts when enabled.
2452 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2454 * interp.c (sim_info): Only print info when verbose.
2455 (sim_info) Use sim_io_printf for output.
2457 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2459 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2462 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2464 * interp.c (sim_do_command): Check for common commands if a
2465 simulator specific command fails.
2467 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2469 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2470 and simBE when DEBUG is defined.
2472 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2474 * interp.c (interrupt_event): New function. Pass exception event
2475 onto exception handler.
2477 * configure.in: Check for stdlib.h.
2478 * configure: Regenerate.
2480 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2481 variable declaration.
2482 (build_instruction): Initialize memval1.
2483 (build_instruction): Add UNUSED attribute to byte, bigend,
2485 (build_operands): Ditto.
2487 * interp.c: Fix GCC warnings.
2488 (sim_get_quit_code): Delete.
2490 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2491 * Makefile.in: Ditto.
2492 * configure: Re-generate.
2494 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2496 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2498 * interp.c (mips_option_handler): New function parse argumes using
2500 (myname): Replace with STATE_MY_NAME.
2501 (sim_open): Delete check for host endianness - performed by
2503 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2504 (sim_open): Move much of the initialization from here.
2505 (sim_load): To here. After the image has been loaded and
2507 (sim_open): Move ColdReset from here.
2508 (sim_create_inferior): To here.
2509 (sim_open): Make FP check less dependant on host endianness.
2511 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2513 * interp.c (sim_set_callbacks): Delete.
2515 * interp.c (membank, membank_base, membank_size): Replace with
2516 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2517 (sim_open): Remove call to callback->init. gdb/run do this.
2521 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2523 * interp.c (big_endian_p): Delete, replaced by
2524 current_target_byte_order.
2526 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2528 * interp.c (host_read_long, host_read_word, host_swap_word,
2529 host_swap_long): Delete. Using common sim-endian.
2530 (sim_fetch_register, sim_store_register): Use H2T.
2531 (pipeline_ticks): Delete. Handled by sim-events.
2533 (sim_engine_run): Update.
2535 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2537 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2539 (SignalException): To here. Signal using sim_engine_halt.
2540 (sim_stop_reason): Delete, moved to common.
2542 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2544 * interp.c (sim_open): Add callback argument.
2545 (sim_set_callbacks): Delete SIM_DESC argument.
2548 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2550 * Makefile.in (SIM_OBJS): Add common modules.
2552 * interp.c (sim_set_callbacks): Also set SD callback.
2553 (set_endianness, xfer_*, swap_*): Delete.
2554 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2555 Change to functions using sim-endian macros.
2556 (control_c, sim_stop): Delete, use common version.
2557 (simulate): Convert into.
2558 (sim_engine_run): This function.
2559 (sim_resume): Delete.
2561 * interp.c (simulation): New variable - the simulator object.
2562 (sim_kind): Delete global - merged into simulation.
2563 (sim_load): Cleanup. Move PC assignment from here.
2564 (sim_create_inferior): To here.
2566 * sim-main.h: New file.
2567 * interp.c (sim-main.h): Include.
2569 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2571 * configure: Regenerated to track ../common/aclocal.m4 changes.
2573 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2575 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2577 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2579 * gencode.c (build_instruction): DIV instructions: check
2580 for division by zero and integer overflow before using
2581 host's division operation.
2583 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2585 * Makefile.in (SIM_OBJS): Add sim-load.o.
2586 * interp.c: #include bfd.h.
2587 (target_byte_order): Delete.
2588 (sim_kind, myname, big_endian_p): New static locals.
2589 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2590 after argument parsing. Recognize -E arg, set endianness accordingly.
2591 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2592 load file into simulator. Set PC from bfd.
2593 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2594 (set_endianness): Use big_endian_p instead of target_byte_order.
2596 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2598 * interp.c (sim_size): Delete prototype - conflicts with
2599 definition in remote-sim.h. Correct definition.
2601 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2603 * configure: Regenerated to track ../common/aclocal.m4 changes.
2606 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2608 * interp.c (sim_open): New arg `kind'.
2610 * configure: Regenerated to track ../common/aclocal.m4 changes.
2612 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2614 * configure: Regenerated to track ../common/aclocal.m4 changes.
2616 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2618 * interp.c (sim_open): Set optind to 0 before calling getopt.
2620 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2622 * configure: Regenerated to track ../common/aclocal.m4 changes.
2624 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2626 * interp.c : Replace uses of pr_addr with pr_uword64
2627 where the bit length is always 64 independent of SIM_ADDR.
2628 (pr_uword64) : added.
2630 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2632 * configure: Re-generate.
2634 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2636 * configure: Regenerate to track ../common/aclocal.m4 changes.
2638 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2640 * interp.c (sim_open): New SIM_DESC result. Argument is now
2642 (other sim_*): New SIM_DESC argument.
2644 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2646 * interp.c: Fix printing of addresses for non-64-bit targets.
2647 (pr_addr): Add function to print address based on size.
2649 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2651 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2653 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2655 * gencode.c (build_mips16_operands): Correct computation of base
2656 address for extended PC relative instruction.
2658 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2660 * interp.c (mips16_entry): Add support for floating point cases.
2661 (SignalException): Pass floating point cases to mips16_entry.
2662 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2664 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2666 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2667 and then set the state to fmt_uninterpreted.
2668 (COP_SW): Temporarily set the state to fmt_word while calling
2671 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2673 * gencode.c (build_instruction): The high order may be set in the
2674 comparison flags at any ISA level, not just ISA 4.
2676 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2678 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2679 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2680 * configure.in: sinclude ../common/aclocal.m4.
2681 * configure: Regenerated.
2683 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2685 * configure: Rebuild after change to aclocal.m4.
2687 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2689 * configure configure.in Makefile.in: Update to new configure
2690 scheme which is more compatible with WinGDB builds.
2691 * configure.in: Improve comment on how to run autoconf.
2692 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2693 * Makefile.in: Use autoconf substitution to install common
2696 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2698 * gencode.c (build_instruction): Use BigEndianCPU instead of
2701 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2703 * interp.c (sim_monitor): Make output to stdout visible in
2704 wingdb's I/O log window.
2706 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2708 * support.h: Undo previous change to SIGTRAP
2711 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2713 * interp.c (store_word, load_word): New static functions.
2714 (mips16_entry): New static function.
2715 (SignalException): Look for mips16 entry and exit instructions.
2716 (simulate): Use the correct index when setting fpr_state after
2717 doing a pending move.
2719 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2721 * interp.c: Fix byte-swapping code throughout to work on
2722 both little- and big-endian hosts.
2724 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2726 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2727 with gdb/config/i386/xm-windows.h.
2729 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2731 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2732 that messes up arithmetic shifts.
2734 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2736 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2737 SIGTRAP and SIGQUIT for _WIN32.
2739 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2741 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2742 force a 64 bit multiplication.
2743 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2744 destination register is 0, since that is the default mips16 nop
2747 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2749 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2750 (build_endian_shift): Don't check proc64.
2751 (build_instruction): Always set memval to uword64. Cast op2 to
2752 uword64 when shifting it left in memory instructions. Always use
2753 the same code for stores--don't special case proc64.
2755 * gencode.c (build_mips16_operands): Fix base PC value for PC
2757 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2759 * interp.c (simJALDELAYSLOT): Define.
2760 (JALDELAYSLOT): Define.
2761 (INDELAYSLOT, INJALDELAYSLOT): Define.
2762 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2764 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2766 * interp.c (sim_open): add flush_cache as a PMON routine
2767 (sim_monitor): handle flush_cache by ignoring it
2769 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2771 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2773 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2774 (BigEndianMem): Rename to ByteSwapMem and change sense.
2775 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2776 BigEndianMem references to !ByteSwapMem.
2777 (set_endianness): New function, with prototype.
2778 (sim_open): Call set_endianness.
2779 (sim_info): Use simBE instead of BigEndianMem.
2780 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2781 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2782 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2783 ifdefs, keeping the prototype declaration.
2784 (swap_word): Rewrite correctly.
2785 (ColdReset): Delete references to CONFIG. Delete endianness related
2786 code; moved to set_endianness.
2788 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2790 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2791 * interp.c (CHECKHILO): Define away.
2792 (simSIGINT): New macro.
2793 (membank_size): Increase from 1MB to 2MB.
2794 (control_c): New function.
2795 (sim_resume): Rename parameter signal to signal_number. Add local
2796 variable prev. Call signal before and after simulate.
2797 (sim_stop_reason): Add simSIGINT support.
2798 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2800 (sim_warning): Delete call to SignalException. Do call printf_filtered
2802 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2803 a call to sim_warning.
2805 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2807 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2808 16 bit instructions.
2810 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2812 Add support for mips16 (16 bit MIPS implementation):
2813 * gencode.c (inst_type): Add mips16 instruction encoding types.
2814 (GETDATASIZEINSN): Define.
2815 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2816 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2818 (MIPS16_DECODE): New table, for mips16 instructions.
2819 (bitmap_val): New static function.
2820 (struct mips16_op): Define.
2821 (mips16_op_table): New table, for mips16 operands.
2822 (build_mips16_operands): New static function.
2823 (process_instructions): If PC is odd, decode a mips16
2824 instruction. Break out instruction handling into new
2825 build_instruction function.
2826 (build_instruction): New static function, broken out of
2827 process_instructions. Check modifiers rather than flags for SHIFT
2828 bit count and m[ft]{hi,lo} direction.
2829 (usage): Pass program name to fprintf.
2830 (main): Remove unused variable this_option_optind. Change
2831 ``*loptarg++'' to ``loptarg++''.
2832 (my_strtoul): Parenthesize && within ||.
2833 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2834 (simulate): If PC is odd, fetch a 16 bit instruction, and
2835 increment PC by 2 rather than 4.
2836 * configure.in: Add case for mips16*-*-*.
2837 * configure: Rebuild.
2839 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2841 * interp.c: Allow -t to enable tracing in standalone simulator.
2842 Fix garbage output in trace file and error messages.
2844 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2846 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2847 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2848 * configure.in: Simplify using macros in ../common/aclocal.m4.
2849 * configure: Regenerated.
2850 * tconfig.in: New file.
2852 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2854 * interp.c: Fix bugs in 64-bit port.
2855 Use ansi function declarations for msvc compiler.
2856 Initialize and test file pointer in trace code.
2857 Prevent duplicate definition of LAST_EMED_REGNUM.
2859 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2861 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2863 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2865 * interp.c (SignalException): Check for explicit terminating
2867 * gencode.c: Pass instruction value through SignalException()
2868 calls for Trap, Breakpoint and Syscall.
2870 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2872 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2873 only used on those hosts that provide it.
2874 * configure.in: Add sqrt() to list of functions to be checked for.
2875 * config.in: Re-generated.
2876 * configure: Re-generated.
2878 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2880 * gencode.c (process_instructions): Call build_endian_shift when
2881 expanding STORE RIGHT, to fix swr.
2882 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2883 clear the high bits.
2884 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2885 Fix float to int conversions to produce signed values.
2887 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2889 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2890 (process_instructions): Correct handling of nor instruction.
2891 Correct shift count for 32 bit shift instructions. Correct sign
2892 extension for arithmetic shifts to not shift the number of bits in
2893 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2894 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2896 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2897 It's OK to have a mult follow a mult. What's not OK is to have a
2898 mult follow an mfhi.
2899 (Convert): Comment out incorrect rounding code.
2901 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2903 * interp.c (sim_monitor): Improved monitor printf
2904 simulation. Tidied up simulator warnings, and added "--log" option
2905 for directing warning message output.
2906 * gencode.c: Use sim_warning() rather than WARNING macro.
2908 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2910 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2911 getopt1.o, rather than on gencode.c. Link objects together.
2912 Don't link against -liberty.
2913 (gencode.o, getopt.o, getopt1.o): New targets.
2914 * gencode.c: Include <ctype.h> and "ansidecl.h".
2915 (AND): Undefine after including "ansidecl.h".
2916 (ULONG_MAX): Define if not defined.
2917 (OP_*): Don't define macros; now defined in opcode/mips.h.
2918 (main): Call my_strtoul rather than strtoul.
2919 (my_strtoul): New static function.
2921 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2923 * gencode.c (process_instructions): Generate word64 and uword64
2924 instead of `long long' and `unsigned long long' data types.
2925 * interp.c: #include sysdep.h to get signals, and define default
2927 * (Convert): Work around for Visual-C++ compiler bug with type
2929 * support.h: Make things compile under Visual-C++ by using
2930 __int64 instead of `long long'. Change many refs to long long
2931 into word64/uword64 typedefs.
2933 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2935 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2936 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2938 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2939 (AC_PROG_INSTALL): Added.
2940 (AC_PROG_CC): Moved to before configure.host call.
2941 * configure: Rebuilt.
2943 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2945 * configure.in: Define @SIMCONF@ depending on mips target.
2946 * configure: Rebuild.
2947 * Makefile.in (run): Add @SIMCONF@ to control simulator
2949 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2950 * interp.c: Remove some debugging, provide more detailed error
2951 messages, update memory accesses to use LOADDRMASK.
2953 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2955 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2956 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2958 * configure: Rebuild.
2959 * config.in: New file, generated by autoheader.
2960 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2961 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2962 HAVE_ANINT and HAVE_AINT, as appropriate.
2963 * Makefile.in (run): Use @LIBS@ rather than -lm.
2964 (interp.o): Depend upon config.h.
2965 (Makefile): Just rebuild Makefile.
2966 (clean): Remove stamp-h.
2967 (mostlyclean): Make the same as clean, not as distclean.
2968 (config.h, stamp-h): New targets.
2970 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2972 * interp.c (ColdReset): Fix boolean test. Make all simulator
2975 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2977 * interp.c (xfer_direct_word, xfer_direct_long,
2978 swap_direct_word, swap_direct_long, xfer_big_word,
2979 xfer_big_long, xfer_little_word, xfer_little_long,
2980 swap_word,swap_long): Added.
2981 * interp.c (ColdReset): Provide function indirection to
2982 host<->simulated_target transfer routines.
2983 * interp.c (sim_store_register, sim_fetch_register): Updated to
2984 make use of indirected transfer routines.
2986 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2988 * gencode.c (process_instructions): Ensure FP ABS instruction
2990 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2991 system call support.
2993 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2995 * interp.c (sim_do_command): Complain if callback structure not
2998 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3000 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3001 support for Sun hosts.
3002 * Makefile.in (gencode): Ensure the host compiler and libraries
3003 used for cross-hosted build.
3005 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3007 * interp.c, gencode.c: Some more (TODO) tidying.
3009 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3011 * gencode.c, interp.c: Replaced explicit long long references with
3012 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3013 * support.h (SET64LO, SET64HI): Macros added.
3015 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3017 * configure: Regenerate with autoconf 2.7.
3019 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3021 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3022 * support.h: Remove superfluous "1" from #if.
3023 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3025 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3027 * interp.c (StoreFPR): Control UndefinedResult() call on
3028 WARN_RESULT manifest.
3030 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3032 * gencode.c: Tidied instruction decoding, and added FP instruction
3035 * interp.c: Added dineroIII, and BSD profiling support. Also
3036 run-time FP handling.
3038 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3040 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3041 gencode.c, interp.c, support.h: created.