sim/mips/ChangeLog

   1 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
   2
   3         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
   4         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
   5         is always enabled.
   6         (SignalExceptionCoProcessorUnusable): Take as argument the
   7         unusable coprocessor number.
   8
   9 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  10
  11         * mips.igen: Fix formatting of all SignalException calls.
  12
  13 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  14
  15         * sim-main.h (SIGNEXTEND): Remove.
  16
  17 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
  18
  19         * mips.igen: Remove gencode comment from top of file, fix
  20         spelling in another comment.
  21
  22 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
  23
  24         * mips.igen (check_fmt, check_fmt_p): New functions to check
  25         whether specific floating point formats are usable.
  26         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
  27         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
  28         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
  29         Use the new functions.
  30         (do_c_cond_fmt): Remove format checks...
  31         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
  32
  33 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
  34
  35         * mips.igen: Fix formatting of check_fpu calls.
  36
  37 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
  38
  39         * mips.igen (FLOOR.L.fmt): Store correct destination register.
  40
  41 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
  42
  43         * mips.igen: Remove whitespace at end of lines.
  44
  45 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
  46
  47         * mips.igen (loadstore_ea): New function to do effective
  48         address calculations.
  49         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
  50         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
  51         CACHE): Use loadstore_ea to do effective address computations.
  52
  53 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
  54
  55         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
  56         * mips.igen (LL, CxC1, MxC1): Likewise.
  57
  58 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
  59
  60         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
  61         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
  62         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
  63         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
  64         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
  65         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
  66         Don't split opcode fields by hand, use the opcode field values
  67         provided by igen.
  68
  69 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
  70
  71         * mips.igen (do_divu): Fix spacing.
  72
  73         * mips.igen (do_dsllv): Move to be right before DSLLV,
  74         to match the rest of the do_<shift> functions.
  75
  76 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
  77
  78         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
  79         DSRL32, do_dsrlv): Trace inputs and results.
  80
  81 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
  82
  83         * mips.igen (CACHE): Provide instruction-printing string.
  84
  85         * interp.c (signal_exception): Comment tokens after #endif.
  86
  87 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
  88
  89         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
  90         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
  91         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
  92         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
  93         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
  94         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
  95         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
  96         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
  97
  98 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
  99
 100         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 101         instruction-printing string.
 102         (LWU): Use '64' as the filter flag.
 103
 104 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 105
 106         * mips.igen (SDXC1): Fix instruction-printing string.
 107
 108 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 109
 110         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 111         filter flags "32,f".
 112
 113 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 114
 115         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 116         as the filter flag.
 117
 118 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 119
 120         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 121         add a comma) so that it more closely match the MIPS ISA
 122         documentation opcode partitioning.
 123         (PREF): Put useful names on opcode fields, and include
 124         instruction-printing string.
 125
 126 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 127
 128         * mips.igen (check_u64): New function which in the future will
 129         check whether 64-bit instructions are usable and signal an
 130         exception if not.  Currently a no-op.
 131         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 132         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 133         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 134         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 135
 136         * mips.igen (check_fpu): New function which in the future will
 137         check whether FPU instructions are usable and signal an exception
 138         if not.  Currently a no-op.
 139         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 140         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 141         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 142         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 143         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 144         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 145         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 146         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 147
 148 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 149
 150         * mips.igen (do_load_left, do_load_right): Move to be immediately
 151         following do_load.
 152         (do_store_left, do_store_right): Move to be immediately following
 153         do_store.
 154
 155 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 156
 157         * mips.igen (mipsV): New model name.  Also, add it to
 158         all instructions and functions where it is appropriate.
 159
 160 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 161
 162         * mips.igen: For all functions and instructions, list model
 163         names that support that instruction one per line.
 164
 165 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 166
 167         * mips.igen: Add some additional comments about supported
 168         models, and about which instructions go where.
 169         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 170         order as is used in the rest of the file.
 171
 172 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 173
 174         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 175         indicating that ALU32_END or ALU64_END are there to check
 176         for overflow.
 177         (DADD): Likewise, but also remove previous comment about
 178         overflow checking.
 179
 180 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 181
 182         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 183         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 184         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 185         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 186         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 187         fields (i.e., add and move commas) so that they more closely
 188         match the MIPS ISA documentation opcode partitioning.
 189
 190 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 191
 192         * mips.igen (ADDI): Print immediate value.
 193         (BREAK): Print code.
 194         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 195         (SLL): Print "nop" specially, and don't run the code
 196         that does the shift for the "nop" case.
 197
 198 2001-11-17  Fred Fish  <fnf@redhat.com>
 199
 200         * sim-main.h (float_operation): Move enum declaration outside
 201         of _sim_cpu struct declaration.
 202
 203 2001-04-12  Jim Blandy  <jimb@redhat.com>
 204
 205         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 206         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 207         set of the FCSR.
 208         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 209         PENDING_FILL, and you can get the intended effect gracefully by
 210         calling PENDING_SCHED directly.
 211
 212 2001-02-23  Ben Elliston  <bje@redhat.com>
 213
 214         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 215         already defined elsewhere.
 216
 217 2001-02-19  Ben Elliston  <bje@redhat.com>
 218
 219         * sim-main.h (sim_monitor): Return an int.
 220         * interp.c (sim_monitor): Add return values.
 221         (signal_exception): Handle error conditions from sim_monitor.
 222
 223 2001-02-08  Ben Elliston  <bje@redhat.com>
 224
 225         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 226         (store_memory): Likewise, pass cia to sim_core_write*.
 227
 228 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 229
 230         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 231         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 232
 233 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 234
 235         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 236         * Makefile.in: Don't delete *.igen when cleaning directory.
 237
 238 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 239
 240         * m16.igen (break): Call SignalException not sim_engine_halt.
 241
 242 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 243
 244         From Jason Eckhardt:
 245         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 246
 247 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 248
 249         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 250
 251 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 252
 253         * mips.igen (do_dmultx): Fix typo.
 254
 255 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 256
 257         * configure: Regenerated to track ../common/aclocal.m4 changes.
 258
 259 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 260
 261         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 262
 263 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 264
 265         * sim-main.h (GPR_CLEAR): Define macro.
 266
 267 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 268
 269         * interp.c (decode_coproc): Output long using %lx and not %s.
 270
 271 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 272
 273         * interp.c (sim_open): Sort & extend dummy memory regions for
 274         --board=jmr3904 for eCos.
 275
 276 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 277
 278         * configure: Regenerated.
 279
 280 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 281
 282         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 283         calls, conditional on the simulator being in verbose mode.
 284
 285 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 286
 287         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 288         cache don't get ReservedInstruction traps.
 289
 290 1999-11-29  Mark Salter  <msalter@cygnus.com>
 291
 292         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 293         to clear status bits in sdisr register. This is how the hardware works.
 294
 295         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 296         being used by cygmon.
 297
 298 1999-11-11  Andrew Haley  <aph@cygnus.com>
 299
 300         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 301         instructions.
 302
 303 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 304
 305         * mips.igen (MULT): Correct previous mis-applied patch.
 306
 307 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 308
 309         * mips.igen (delayslot32): Handle sequence like
 310         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 311         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 312         (MULT): Actually pass the third register...
 313
 314 1999-09-03  Mark Salter  <msalter@cygnus.com>
 315
 316         * interp.c (sim_open): Added more memory aliases for additional
 317         hardware being touched by cygmon on jmr3904 board.
 318
 319 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 320
 321         * configure: Regenerated to track ../common/aclocal.m4 changes.
 322
 323 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 324
 325         * interp.c (sim_store_register): Handle case where client - GDB -
 326         specifies that a 4 byte register is 8 bytes in size.
 327         (sim_fetch_register): Ditto.
 328
 329 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 330
 331         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 332         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 333         (idt_monitor_base): Base address for IDT monitor traps.
 334         (pmon_monitor_base): Ditto for PMON.
 335         (lsipmon_monitor_base): Ditto for LSI PMON.
 336         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 337         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 338         (sim_firmware_command): New function.
 339         (mips_option_handler): Call it for OPTION_FIRMWARE.
 340         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 341         option was given, add no monitor by default.  Add BREAK hooks only if
 342         monitors are also there.
 343
 344 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 345
 346         * interp.c (sim_monitor): Flush output before reading input.
 347
 348 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 349
 350         * tconfig.in (SIM_HANDLES_LMA): Always define.
 351
 352 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 353
 354         From Mark Salter <msalter@cygnus.com>:
 355         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 356         (sim_open): Add setup for BSP board.
 357
 358 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 359
 360         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 361         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 362         them as unimplemented.
 363
 364 1999-05-08  Felix Lee  <flee@cygnus.com>
 365
 366         * configure: Regenerated to track ../common/aclocal.m4 changes.
 367
 368 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 369
 370         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 371
 372 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 373
 374         * configure.in: Any mips64vr5*-*-* target should have
 375         -DTARGET_ENABLE_FR=1.
 376         (default_endian): Any mips64vr*el-*-* target should default to
 377         LITTLE_ENDIAN.
 378         * configure: Re-generate.
 379
 380 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 381
 382         * mips.igen (ldl): Extend from _16_, not 32.
 383
 384 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 385
 386         * interp.c (sim_store_register): Force registers written to by GDB
 387         into an un-interpreted state.
 388
 389 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 390
 391         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 392         CPU, start periodic background I/O polls.
 393         (tx3904sio_poll): New function: periodic I/O poller.
 394
 395 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 396
 397         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 398
 399 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 400
 401         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 402         case statement.
 403
 404 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 405
 406         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 407         (load_word): Call SIM_CORE_SIGNAL hook on error.
 408         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 409         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 410         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 411         * sim-main.h (COP0_BADVADDR): Define.
 412         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 413         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 414         (_sim_cpu): Add exc_* fields to store register value snapshots.
 415         * mips.igen (*): Replace memory-related SignalException* calls
 416         with references to SIM_CORE_SIGNAL hook.
 417
 418         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 419         fix.
 420         * sim-main.c (*): Minor warning cleanups.
 421
 422 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 423
 424         * m16.igen (DADDIU5): Correct type-o.
 425
 426 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 427
 428         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 429         variables.
 430
 431 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 432
 433         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 434         to include path.
 435         (interp.o): Add dependency on itable.h
 436         (oengine.c, gencode): Delete remaining references.
 437         (BUILT_SRC_FROM_GEN): Clean up.
 438
 439 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 440
 441         * vr4run.c: New.
 442         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 443         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 444         tmp-run-hack) : New.
 445         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 446         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 447         Drop the "64" qualifier to get the HACK generator working.
 448         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 449         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 450         qualifier to get the hack generator working.
 451         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 452         (DSLL): Use do_dsll.
 453         (DSLLV): Use do_dsllv.
 454         (DSRA): Use do_dsra.
 455         (DSRL): Use do_dsrl.
 456         (DSRLV): Use do_dsrlv.
 457         (BC1): Move *vr4100 to get the HACK generator working.
 458         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 459         get the HACK generator working.
 460         (MACC) Rename to get the HACK generator working.
 461         (DMACC,MACCS,DMACCS): Add the 64.
 462
 463 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 464
 465         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 466         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 467
 468 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 469
 470     * mips/interp.c (DEBUG): Cleanups.
 471
 472 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 473
 474         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 475         (tx3904sio_tickle): fflush after a stdout character output.
 476
 477 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 478
 479         * interp.c (sim_close): Uninstall modules.
 480
 481 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 482
 483         * sim-main.h, interp.c (sim_monitor): Change to global
 484         function.
 485
 486 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 487
 488         * configure.in (vr4100): Only include vr4100 instructions in
 489         simulator.
 490         * configure: Re-generate.
 491         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 492
 493 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 494
 495         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 496         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 497         true alternative.
 498
 499         * configure.in (sim_default_gen, sim_use_gen): Replace with
 500         sim_gen.
 501         (--enable-sim-igen): Delete config option. Always using IGEN.
 502         * configure: Re-generate.
 503
 504         * Makefile.in (gencode): Kill, kill, kill.
 505         * gencode.c: Ditto.
 506
 507 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 508
 509         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 510         bit mips16 igen simulator.
 511         * configure: Re-generate.
 512
 513         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 514         as part of vr4100 ISA.
 515         * vr.igen: Mark all instructions as 64 bit only.
 516
 517 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 518
 519         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 520         Pacify GCC.
 521
 522 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 523
 524         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 525         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 526         * configure: Re-generate.
 527
 528         * m16.igen (BREAK): Define breakpoint instruction.
 529         (JALX32): Mark instruction as mips16 and not r3900.
 530         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 531
 532         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 533
 534 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 535
 536         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 537         insn as a debug breakpoint.
 538
 539         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 540         pending.slot_size.
 541         (PENDING_SCHED): Clean up trace statement.
 542         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 543         (PENDING_FILL): Delay write by only one cycle.
 544         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 545
 546         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 547         of pending writes.
 548         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 549         32 & 64.
 550         (pending_tick): Move incrementing of index to FOR statement.
 551         (pending_tick): Only update PENDING_OUT after a write has occured.
 552
 553         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 554         build simulator.
 555         * configure: Re-generate.
 556
 557         * interp.c (sim_engine_run OLD): Delete explicit call to
 558         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 559
 560 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 561
 562         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 563         interrupt level number to match changed SignalExceptionInterrupt
 564         macro.
 565
 566 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 567
 568         * interp.c: #include "itable.h" if WITH_IGEN.
 569         (get_insn_name): New function.
 570         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 571         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 572
 573 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 574
 575         * configure: Rebuilt to inhale new common/aclocal.m4.
 576
 577 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 578
 579         * dv-tx3904sio.c: Include sim-assert.h.
 580
 581 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 582
 583         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 584         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 585         Reorganize target-specific sim-hardware checks.
 586         * configure: rebuilt.
 587         * interp.c (sim_open): For tx39 target boards, set
 588         OPERATING_ENVIRONMENT, add tx3904sio devices.
 589         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 590         ROM executables.  Install dv-sockser into sim-modules list.
 591
 592         * dv-tx3904irc.c: Compiler warning clean-up.
 593         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 594         frequent hw-trace messages.
 595
 596 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 597
 598         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 599
 600 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 601
 602         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 603
 604         * vr.igen: New file.
 605         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 606         * mips.igen: Define vr4100 model. Include vr.igen.
 607 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 608
 609         * mips.igen (check_mf_hilo): Correct check.
 610
 611 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 612
 613         * sim-main.h (interrupt_event): Add prototype.
 614
 615         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 616         register_ptr, register_value.
 617         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 618
 619         * sim-main.h (tracefh): Make extern.
 620
 621 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 622
 623         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 624         Reduce unnecessarily high timer event frequency.
 625         * dv-tx3904cpu.c: Ditto for interrupt event.
 626
 627 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 628
 629         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 630         to allay warnings.
 631         (interrupt_event): Made non-static.
 632
 633         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 634         interchange of configuration values for external vs. internal
 635         clock dividers.
 636
 637 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 638
 639         * mips.igen (BREAK): Moved code to here for
 640         simulator-reserved break instructions.
 641         * gencode.c (build_instruction): Ditto.
 642         * interp.c (signal_exception): Code moved from here.  Non-
 643         reserved instructions now use exception vector, rather
 644         than halting sim.
 645         * sim-main.h: Moved magic constants to here.
 646
 647 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 648
 649         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 650         register upon non-zero interrupt event level, clear upon zero
 651         event value.
 652         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 653         by passing zero event value.
 654         (*_io_{read,write}_buffer): Endianness fixes.
 655         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 656         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 657
 658         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 659         serial I/O and timer module at base address 0xFFFF0000.
 660
 661 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 662
 663         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 664         and BigEndianCPU.
 665
 666 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 667
 668         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 669         parts.
 670         * configure: Update.
 671
 672 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 673
 674         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 675         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 676         * configure.in: Include tx3904tmr in hw_device list.
 677         * configure: Rebuilt.
 678         * interp.c (sim_open): Instantiate three timer instances.
 679         Fix address typo of tx3904irc instance.
 680
 681 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 682
 683         * interp.c (signal_exception): SystemCall exception now uses
 684         the exception vector.
 685
 686 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 687
 688         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 689         to allay warnings.
 690
 691 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 692
 693         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 694
 695 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 696
 697         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 698
 699         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 700         sim-main.h. Declare a struct hw_descriptor instead of struct
 701         hw_device_descriptor.
 702
 703 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 704
 705         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 706         right bits and then re-align left hand bytes to correct byte
 707         lanes.  Fix incorrect computation in do_store_left when loading
 708         bytes from second word.
 709
 710 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 711
 712         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 713         * interp.c (sim_open): Only create a device tree when HW is
 714         enabled.
 715
 716         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 717         * interp.c (signal_exception): Ditto.
 718
 719 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 720
 721         * gencode.c: Mark BEGEZALL as LIKELY.
 722
 723 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 724
 725         * sim-main.h (ALU32_END): Sign extend 32 bit results.
 726         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
 727
 728 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
 729
 730         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 731         modules.  Recognize TX39 target with "mips*tx39" pattern.
 732         * configure: Rebuilt.
 733         * sim-main.h (*): Added many macros defining bits in
 734         TX39 control registers.
 735         (SignalInterrupt): Send actual PC instead of NULL.
 736         (SignalNMIReset): New exception type.
 737         * interp.c (board): New variable for future use to identify
 738         a particular board being simulated.
 739         (mips_option_handler,mips_options): Added "--board" option.
 740         (interrupt_event): Send actual PC.
 741         (sim_open): Make memory layout conditional on board setting.
 742         (signal_exception): Initial implementation of hardware interrupt
 743         handling.  Accept another break instruction variant for simulator
 744         exit.
 745         (decode_coproc): Implement RFE instruction for TX39.
 746         (mips.igen): Decode RFE instruction as such.
 747         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
 748         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
 749         bbegin to implement memory map.
 750         * dv-tx3904cpu.c: New file.
 751         * dv-tx3904irc.c: New file.
 752
 753 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
 754
 755         * mips.igen (check_mt_hilo): Create a separate r3900 version.
 756
 757 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
 758
 759         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
 760         with calls to check_div_hilo.
 761
 762 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
 763
 764         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
 765         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
 766         Add special r3900 version of do_mult_hilo.
 767         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
 768         with calls to check_mult_hilo.
 769         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
 770         with calls to check_div_hilo.
 771
 772 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 773
 774         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
 775         Document a replacement.
 776
 777 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
 778
 779         * interp.c (sim_monitor): Make mon_printf work.
 780
 781 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
 782
 783         * sim-main.h (INSN_NAME): New arg `cpu'.
 784
 785 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
 786
 787         * configure: Regenerated to track ../common/aclocal.m4 changes.
 788
 789 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
 790
 791         * configure: Regenerated to track ../common/aclocal.m4 changes.
 792         * config.in: Ditto.
 793
 794 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
 795
 796         * acconfig.h: New file.
 797         * configure.in: Reverted change of Apr 24; use sinclude again.
 798
 799 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
 800
 801         * configure: Regenerated to track ../common/aclocal.m4 changes.
 802         * config.in: Ditto.
 803
 804 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
 805
 806         * configure.in: Don't call sinclude.
 807
 808 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
 809
 810         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
 811
 812 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 813
 814         * mips.igen (ERET): Implement.
 815
 816         * interp.c (decode_coproc): Return sign-extended EPC.
 817
 818         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
 819
 820         * interp.c (signal_exception): Do not ignore Trap.
 821         (signal_exception): On TRAP, restart at exception address.
 822         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
 823         (signal_exception): Update.
 824         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
 825         so that TRAP instructions are caught.
 826
 827 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 828
 829         * sim-main.h (struct hilo_access, struct hilo_history): Define,
 830         contains HI/LO access history.
 831         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
 832         (HIACCESS, LOACCESS): Delete, replace with
 833         (HIHISTORY, LOHISTORY): New macros.
 834         (CHECKHILO): Delete all, moved to mips.igen
 835
 836         * gencode.c (build_instruction): Do not generate checks for
 837         correct HI/LO register usage.
 838
 839         * interp.c (old_engine_run): Delete checks for correct HI/LO
 840         register usage.
 841
 842         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
 843         check_mf_cycles): New functions.
 844         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
 845         do_divu, domultx, do_mult, do_multu): Use.
 846
 847         * tx.igen ("madd", "maddu"): Use.
 848
 849 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 850
 851         * mips.igen (DSRAV): Use function do_dsrav.
 852         (SRAV): Use new function do_srav.
 853
 854         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
 855         (B): Sign extend 11 bit immediate.
 856         (EXT-B*): Shift 16 bit immediate left by 1.
 857         (ADDIU*): Don't sign extend immediate value.
 858
 859 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 860
 861         * m16run.c (sim_engine_run): Restore CIA after handling an event.
 862
 863         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
 864         functions.
 865
 866         * mips.igen (delayslot32, nullify_next_insn): New functions.
 867         (m16.igen): Always include.
 868         (do_*): Add more tracing.
 869
 870         * m16.igen (delayslot16): Add NIA argument, could be called by a
 871         32 bit MIPS16 instruction.
 872
 873         * interp.c (ifetch16): Move function from here.
 874         * sim-main.c (ifetch16): To here.
 875
 876         * sim-main.c (ifetch16, ifetch32): Update to match current
 877         implementations of LH, LW.
 878         (signal_exception): Don't print out incorrect hex value of illegal
 879         instruction.
 880
 881 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 882
 883         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
 884         instruction.
 885
 886         * m16.igen: Implement MIPS16 instructions.
 887
 888         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
 889         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
 890         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
 891         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
 892         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
 893         bodies of corresponding code from 32 bit insn to these.  Also used
 894         by MIPS16 versions of functions.
 895
 896         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
 897         (IMEM16): Drop NR argument from macro.
 898
 899 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 900
 901         * Makefile.in (SIM_OBJS): Add sim-main.o.
 902
 903         * sim-main.h (address_translation, load_memory, store_memory,
 904         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
 905         as INLINE_SIM_MAIN.
 906         (pr_addr, pr_uword64): Declare.
 907         (sim-main.c): Include when H_REVEALS_MODULE_P.
 908
 909         * interp.c (address_translation, load_memory, store_memory,
 910         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
 911         from here.
 912         * sim-main.c: To here. Fix compilation problems.
 913
 914         * configure.in: Enable inlining.
 915         * configure: Re-config.
 916
 917 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 918
 919         * configure: Regenerated to track ../common/aclocal.m4 changes.
 920
 921 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 922
 923         * mips.igen: Include tx.igen.
 924         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
 925         * tx.igen: New file, contains MADD and MADDU.
 926
 927         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
 928         the hardwired constant `7'.
 929         (store_memory): Ditto.
 930         (LOADDRMASK): Move definition to sim-main.h.
 931
 932         mips.igen (MTC0): Enable for r3900.
 933         (ADDU): Add trace.
 934
 935         mips.igen (do_load_byte): Delete.
 936         (do_load, do_store, do_load_left, do_load_write, do_store_left,
 937         do_store_right): New functions.
 938         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
 939
 940         configure.in: Let the tx39 use igen again.
 941         configure: Update.
 942
 943 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 944
 945         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
 946         not an address sized quantity.  Return zero for cache sizes.
 947
 948 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 949
 950         * mips.igen (r3900): r3900 does not support 64 bit integer
 951         operations.
 952
 953 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
 954
 955         * configure.in (mipstx39*-*-*): Use gencode simulator rather
 956         than igen one.
 957         * configure : Rebuild.
 958
 959 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 960
 961         * configure: Regenerated to track ../common/aclocal.m4 changes.
 962
 963 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 964
 965         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
 966
 967 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
 968
 969         * configure: Regenerated to track ../common/aclocal.m4 changes.
 970         * config.in: Regenerated to track ../common/aclocal.m4 changes.
 971
 972 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 973
 974         * configure: Regenerated to track ../common/aclocal.m4 changes.
 975
 976 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 977
 978         * interp.c (Max, Min): Comment out functions. Not yet used.
 979
 980 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 981
 982         * configure: Regenerated to track ../common/aclocal.m4 changes.
 983
 984 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
 985
 986         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
 987         configurable settings for stand-alone simulator.
 988
 989         * configure.in: Added X11 search, just in case.
 990
 991         * configure: Regenerated.
 992
 993 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 994
 995         * interp.c (sim_write, sim_read, load_memory, store_memory):
 996         Replace sim_core_*_map with read_map, write_map, exec_map resp.
 997
 998 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 999
1000         * sim-main.h (GETFCC): Return an unsigned value.
1001
1002 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1003
1004         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1005         (DADD): Result destination is RD not RT.
1006
1007 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1008
1009         * sim-main.h (HIACCESS, LOACCESS): Always define.
1010
1011         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1012
1013         * interp.c (sim_info): Delete.
1014
1015 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1016
1017         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1018         (mips_option_handler): New argument `cpu'.
1019         (sim_open): Update call to sim_add_option_table.
1020
1021 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1022
1023         * mips.igen (CxC1): Add tracing.
1024
1025 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1026
1027         * sim-main.h (Max, Min): Declare.
1028
1029         * interp.c (Max, Min): New functions.
1030
1031         * mips.igen (BC1): Add tracing.
1032
1033 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1034
1035         * interp.c Added memory map for stack in vr4100
1036
1037 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1038
1039         * interp.c (load_memory): Add missing "break"'s.
1040
1041 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1042
1043         * interp.c (sim_store_register, sim_fetch_register): Pass in
1044         length parameter.  Return -1.
1045
1046 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1047
1048         * interp.c: Added hardware init hook, fixed warnings.
1049
1050 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1051
1052         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1053
1054 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1055
1056         * interp.c (ifetch16): New function.
1057
1058         * sim-main.h (IMEM32): Rename IMEM.
1059         (IMEM16_IMMED): Define.
1060         (IMEM16): Define.
1061         (DELAY_SLOT): Update.
1062
1063         * m16run.c (sim_engine_run): New file.
1064
1065         * m16.igen: All instructions except LB.
1066         (LB): Call do_load_byte.
1067         * mips.igen (do_load_byte): New function.
1068         (LB): Call do_load_byte.
1069
1070         * mips.igen: Move spec for insn bit size and high bit from here.
1071         * Makefile.in (tmp-igen, tmp-m16): To here.
1072
1073         * m16.dc: New file, decode mips16 instructions.
1074
1075         * Makefile.in (SIM_NO_ALL): Define.
1076         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1077
1078 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1079
1080         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1081         point unit to 32 bit registers.
1082         * configure: Re-generate.
1083
1084 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1085
1086         * configure.in (sim_use_gen): Make IGEN the default simulator
1087         generator for generic 32 and 64 bit mips targets.
1088         * configure: Re-generate.
1089
1090 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1091
1092         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1093         bitsize.
1094
1095         * interp.c (sim_fetch_register, sim_store_register): Read/write
1096         FGR from correct location.
1097         (sim_open): Set size of FGR's according to
1098         WITH_TARGET_FLOATING_POINT_BITSIZE.
1099
1100         * sim-main.h (FGR): Store floating point registers in a separate
1101         array.
1102
1103 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1104
1105         * configure: Regenerated to track ../common/aclocal.m4 changes.
1106
1107 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1108
1109         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1110
1111         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1112
1113         * interp.c (pending_tick): New function.  Deliver pending writes.
1114
1115         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1116         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1117         it can handle mixed sized quantites and single bits.
1118
1119 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1120
1121         * interp.c (oengine.h): Do not include when building with IGEN.
1122         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1123         (sim_info): Ditto for PROCESSOR_64BIT.
1124         (sim_monitor): Replace ut_reg with unsigned_word.
1125         (*): Ditto for t_reg.
1126         (LOADDRMASK): Define.
1127         (sim_open): Remove defunct check that host FP is IEEE compliant,
1128         using software to emulate floating point.
1129         (value_fpr, ...): Always compile, was conditional on HASFPU.
1130
1131 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1132
1133         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1134         size.
1135
1136         * interp.c (SD, CPU): Define.
1137         (mips_option_handler): Set flags in each CPU.
1138         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1139         (sim_close): Do not clear STATE, deleted anyway.
1140         (sim_write, sim_read): Assume CPU zero's vm should be used for
1141         data transfers.
1142         (sim_create_inferior): Set the PC for all processors.
1143         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1144         argument.
1145         (mips16_entry): Pass correct nr of args to store_word, load_word.
1146         (ColdReset): Cold reset all cpu's.
1147         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1148         (sim_monitor, load_memory, store_memory, signal_exception): Use
1149         `CPU' instead of STATE_CPU.
1150
1151
1152         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1153         SD or CPU_.
1154
1155         * sim-main.h (signal_exception): Add sim_cpu arg.
1156         (SignalException*): Pass both SD and CPU to signal_exception.
1157         * interp.c (signal_exception): Update.
1158
1159         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1160         Ditto
1161         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1162         address_translation): Ditto
1163         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1164
1165 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1166
1167         * configure: Regenerated to track ../common/aclocal.m4 changes.
1168
1169 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1170
1171         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1172
1173         * mips.igen (model): Map processor names onto BFD name.
1174
1175         * sim-main.h (CPU_CIA): Delete.
1176         (SET_CIA, GET_CIA): Define
1177
1178 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1179
1180         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1181         regiser.
1182
1183         * configure.in (default_endian): Configure a big-endian simulator
1184         by default.
1185         * configure: Re-generate.
1186
1187 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1188
1189         * configure: Regenerated to track ../common/aclocal.m4 changes.
1190
1191 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1192
1193         * interp.c (sim_monitor): Handle Densan monitor outbyte
1194         and inbyte functions.
1195
1196 1997-12-29  Felix Lee  <flee@cygnus.com>
1197
1198         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1199
1200 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1201
1202         * Makefile.in (tmp-igen): Arrange for $zero to always be
1203         reset to zero after every instruction.
1204
1205 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1206
1207         * configure: Regenerated to track ../common/aclocal.m4 changes.
1208         * config.in: Ditto.
1209
1210 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1211
1212         * mips.igen (MSUB): Fix to work like MADD.
1213         * gencode.c (MSUB): Similarly.
1214
1215 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1216
1217         * configure: Regenerated to track ../common/aclocal.m4 changes.
1218
1219 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1220
1221         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1222
1223 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1224
1225         * sim-main.h (sim-fpu.h): Include.
1226
1227         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1228         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1229         using host independant sim_fpu module.
1230
1231 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1232
1233         * interp.c (signal_exception): Report internal errors with SIGABRT
1234         not SIGQUIT.
1235
1236         * sim-main.h (C0_CONFIG): New register.
1237         (signal.h): No longer include.
1238
1239         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1240
1241 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1242
1243         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1244
1245 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1246
1247         * mips.igen: Tag vr5000 instructions.
1248         (ANDI): Was missing mipsIV model, fix assembler syntax.
1249         (do_c_cond_fmt): New function.
1250         (C.cond.fmt): Handle mips I-III which do not support CC field
1251         separatly.
1252         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1253         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1254         in IV3.2 spec.
1255         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1256         vr5000 which saves LO in a GPR separatly.
1257
1258         * configure.in (enable-sim-igen): For vr5000, select vr5000
1259         specific instructions.
1260         * configure: Re-generate.
1261
1262 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1263
1264         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1265
1266         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1267         fmt_uninterpreted_64 bit cases to switch.  Convert to
1268         fmt_formatted,
1269
1270         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1271
1272         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1273         as specified in IV3.2 spec.
1274         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1275
1276 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1277
1278         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1279         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1280         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1281         PENDING_FILL versions of instructions.  Simplify.
1282         (X): New function.
1283         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1284         instructions.
1285         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1286         a signed value.
1287         (MTHI, MFHI): Disable code checking HI-LO.
1288
1289         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1290         global.
1291         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1292
1293 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1294
1295         * gencode.c (build_mips16_operands): Replace IPC with cia.
1296
1297         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1298         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1299         IPC to `cia'.
1300         (UndefinedResult): Replace function with macro/function
1301         combination.
1302         (sim_engine_run): Don't save PC in IPC.
1303
1304         * sim-main.h (IPC): Delete.
1305
1306
1307         * interp.c (signal_exception, store_word, load_word,
1308         address_translation, load_memory, store_memory, cache_op,
1309         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1310         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1311         current instruction address - cia - argument.
1312         (sim_read, sim_write): Call address_translation directly.
1313         (sim_engine_run): Rename variable vaddr to cia.
1314         (signal_exception): Pass cia to sim_monitor
1315
1316         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1317         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1318         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1319
1320         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1321         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1322         SIM_ASSERT.
1323
1324         * interp.c (signal_exception): Pass restart address to
1325         sim_engine_restart.
1326
1327         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1328         idecode.o): Add dependency.
1329
1330         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1331         Delete definitions
1332         (DELAY_SLOT): Update NIA not PC with branch address.
1333         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1334
1335         * mips.igen: Use CIA not PC in branch calculations.
1336         (illegal): Call SignalException.
1337         (BEQ, ADDIU): Fix assembler.
1338
1339 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1340
1341         * m16.igen (JALX): Was missing.
1342
1343         * configure.in (enable-sim-igen): New configuration option.
1344         * configure: Re-generate.
1345
1346         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1347
1348         * interp.c (load_memory, store_memory): Delete parameter RAW.
1349         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1350         bypassing {load,store}_memory.
1351
1352         * sim-main.h (ByteSwapMem): Delete definition.
1353
1354         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1355
1356         * interp.c (sim_do_command, sim_commands): Delete mips specific
1357         commands.  Handled by module sim-options.
1358
1359         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1360         (WITH_MODULO_MEMORY): Define.
1361
1362         * interp.c (sim_info): Delete code printing memory size.
1363
1364         * interp.c (mips_size): Nee sim_size, delete function.
1365         (power2): Delete.
1366         (monitor, monitor_base, monitor_size): Delete global variables.
1367         (sim_open, sim_close): Delete code creating monitor and other
1368         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1369         manage memory regions.
1370         (load_memory, store_memory): Use sim-core for memory model.
1371
1372         * interp.c (address_translation): Delete all memory map code
1373         except line forcing 32 bit addresses.
1374
1375 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1376
1377         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1378         trace options.
1379
1380         * interp.c (logfh, logfile): Delete globals.
1381         (sim_open, sim_close): Delete code opening & closing log file.
1382         (mips_option_handler): Delete -l and -n options.
1383         (OPTION mips_options): Ditto.
1384
1385         * interp.c (OPTION mips_options): Rename option trace to dinero.
1386         (mips_option_handler): Update.
1387
1388 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1389
1390         * interp.c (fetch_str): New function.
1391         (sim_monitor): Rewrite using sim_read & sim_write.
1392         (sim_open): Check magic number.
1393         (sim_open): Write monitor vectors into memory using sim_write.
1394         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1395         (sim_read, sim_write): Simplify - transfer data one byte at a
1396         time.
1397         (load_memory, store_memory): Clarify meaning of parameter RAW.
1398
1399         * sim-main.h (isHOST): Defete definition.
1400         (isTARGET): Mark as depreciated.
1401         (address_translation): Delete parameter HOST.
1402
1403         * interp.c (address_translation): Delete parameter HOST.
1404
1405 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1406
1407         * mips.igen:
1408
1409         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1410         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1411
1412 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1413
1414         * mips.igen: Add model filter field to records.
1415
1416 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1417
1418         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1419
1420         interp.c (sim_engine_run): Do not compile function sim_engine_run
1421         when WITH_IGEN == 1.
1422
1423         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1424         target architecture.
1425
1426         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1427         igen. Replace with configuration variables sim_igen_flags /
1428         sim_m16_flags.
1429
1430         * m16.igen: New file.  Copy mips16 insns here.
1431         * mips.igen: From here.
1432
1433 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1434
1435         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1436         to top.
1437         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1438
1439 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1440
1441         * gencode.c (build_instruction): Follow sim_write's lead in using
1442         BigEndianMem instead of !ByteSwapMem.
1443
1444 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1445
1446         * configure.in (sim_gen): Dependent on target, select type of
1447         generator.  Always select old style generator.
1448
1449         configure: Re-generate.
1450
1451         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1452         targets.
1453         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1454         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1455         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1456         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1457         SIM_@sim_gen@_*, set by autoconf.
1458
1459 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1460
1461         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1462
1463         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1464         CURRENT_FLOATING_POINT instead.
1465
1466         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1467         (address_translation): Raise exception InstructionFetch when
1468         translation fails and isINSTRUCTION.
1469
1470         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1471         sim_engine_run): Change type of of vaddr and paddr to
1472         address_word.
1473         (address_translation, prefetch, load_memory, store_memory,
1474         cache_op): Change type of vAddr and pAddr to address_word.
1475
1476         * gencode.c (build_instruction): Change type of vaddr and paddr to
1477         address_word.
1478
1479 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1480
1481         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1482         macro to obtain result of ALU op.
1483
1484 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1485
1486         * interp.c (sim_info): Call profile_print.
1487
1488 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1489
1490         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1491
1492         * sim-main.h (WITH_PROFILE): Do not define, defined in
1493         common/sim-config.h.  Use sim-profile module.
1494         (simPROFILE): Delete defintion.
1495
1496         * interp.c (PROFILE): Delete definition.
1497         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1498         (sim_close): Delete code writing profile histogram.
1499         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1500         Delete.
1501         (sim_engine_run): Delete code profiling the PC.
1502
1503 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1504
1505         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1506
1507         * interp.c (sim_monitor): Make register pointers of type
1508         unsigned_word*.
1509
1510         * sim-main.h: Make registers of type unsigned_word not
1511         signed_word.
1512
1513 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1514
1515         * interp.c (sync_operation): Rename from SyncOperation, make
1516         global, add SD argument.
1517         (prefetch): Rename from Prefetch, make global, add SD argument.
1518         (decode_coproc): Make global.
1519
1520         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1521
1522         * gencode.c (build_instruction): Generate DecodeCoproc not
1523         decode_coproc calls.
1524
1525         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1526         (SizeFGR): Move to sim-main.h
1527         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1528         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1529         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1530         sim-main.h.
1531         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1532         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1533         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1534         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1535         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1536         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1537
1538         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1539         exception.
1540         (sim-alu.h): Include.
1541         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1542         (sim_cia): Typedef to instruction_address.
1543
1544 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1545
1546         * Makefile.in (interp.o): Rename generated file engine.c to
1547         oengine.c.
1548
1549         * interp.c: Update.
1550
1551 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1552
1553         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1554
1555 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1556
1557         * gencode.c (build_instruction): For "FPSQRT", output correct
1558         number of arguments to Recip.
1559
1560 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1561
1562         * Makefile.in (interp.o): Depends on sim-main.h
1563
1564         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1565
1566         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1567         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1568         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1569         STATE, DSSTATE): Define
1570         (GPR, FGRIDX, ..): Define.
1571
1572         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1573         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1574         (GPR, FGRIDX, ...): Delete macros.
1575
1576         * interp.c: Update names to match defines from sim-main.h
1577
1578 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1579
1580         * interp.c (sim_monitor): Add SD argument.
1581         (sim_warning): Delete.  Replace calls with calls to
1582         sim_io_eprintf.
1583         (sim_error): Delete. Replace calls with sim_io_error.
1584         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1585         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1586         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1587         argument.
1588         (mips_size): Rename from sim_size. Add SD argument.
1589
1590         * interp.c (simulator): Delete global variable.
1591         (callback): Delete global variable.
1592         (mips_option_handler, sim_open, sim_write, sim_read,
1593         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1594         sim_size,sim_monitor): Use sim_io_* not callback->*.
1595         (sim_open): ZALLOC simulator struct.
1596         (PROFILE): Do not define.
1597
1598 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1599
1600         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1601         support.h with corresponding code.
1602
1603         * sim-main.h (word64, uword64), support.h: Move definition to
1604         sim-main.h.
1605         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1606
1607         * support.h: Delete
1608         * Makefile.in: Update dependencies
1609         * interp.c: Do not include.
1610
1611 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1612
1613         * interp.c (address_translation, load_memory, store_memory,
1614         cache_op): Rename to from AddressTranslation et.al., make global,
1615         add SD argument
1616
1617         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1618         CacheOp): Define.
1619
1620         * interp.c (SignalException): Rename to signal_exception, make
1621         global.
1622
1623         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1624
1625         * sim-main.h (SignalException, SignalExceptionInterrupt,
1626         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1627         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1628         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1629         Define.
1630
1631         * interp.c, support.h: Use.
1632
1633 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1634
1635         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1636         to value_fpr / store_fpr. Add SD argument.
1637         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1638         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1639
1640         * sim-main.h (ValueFPR, StoreFPR): Define.
1641
1642 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1643
1644         * interp.c (sim_engine_run): Check consistency between configure
1645         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1646         and HASFPU.
1647
1648         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1649         (mips_fpu): Configure WITH_FLOATING_POINT.
1650         (mips_endian): Configure WITH_TARGET_ENDIAN.
1651         * configure: Update.
1652
1653 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1654
1655         * configure: Regenerated to track ../common/aclocal.m4 changes.
1656
1657 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1658
1659         * configure: Regenerated.
1660
1661 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1662
1663         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1664
1665 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1666
1667         * gencode.c (print_igen_insn_models): Assume certain architectures
1668         include all mips* instructions.
1669         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1670         instruction.
1671
1672         * Makefile.in (tmp.igen): Add target. Generate igen input from
1673         gencode file.
1674
1675         * gencode.c (FEATURE_IGEN): Define.
1676         (main): Add --igen option.  Generate output in igen format.
1677         (process_instructions): Format output according to igen option.
1678         (print_igen_insn_format): New function.
1679         (print_igen_insn_models): New function.
1680         (process_instructions): Only issue warnings and ignore
1681         instructions when no FEATURE_IGEN.
1682
1683 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1684
1685         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1686         MIPS targets.
1687
1688 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1689
1690         * configure: Regenerated to track ../common/aclocal.m4 changes.
1691
1692 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1693
1694         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1695         SIM_RESERVED_BITS): Delete, moved to common.
1696         (SIM_EXTRA_CFLAGS): Update.
1697
1698 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1699
1700         * configure.in: Configure non-strict memory alignment.
1701         * configure: Regenerated to track ../common/aclocal.m4 changes.
1702
1703 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1704
1705         * configure: Regenerated to track ../common/aclocal.m4 changes.
1706
1707 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1708
1709         * gencode.c (SDBBP,DERET): Added (3900) insns.
1710         (RFE): Turn on for 3900.
1711         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1712         (dsstate): Made global.
1713         (SUBTARGET_R3900): Added.
1714         (CANCELDELAYSLOT): New.
1715         (SignalException): Ignore SystemCall rather than ignore and
1716         terminate.  Add DebugBreakPoint handling.
1717         (decode_coproc): New insns RFE, DERET; and new registers Debug
1718         and DEPC protected by SUBTARGET_R3900.
1719         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1720         bits explicitly.
1721         * Makefile.in,configure.in: Add mips subtarget option.
1722         * configure: Update.
1723
1724 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
1725
1726         * gencode.c: Add r3900 (tx39).
1727
1728
1729 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
1730
1731         * gencode.c (build_instruction): Don't need to subtract 4 for
1732         JALR, just 2.
1733
1734 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
1735
1736         * interp.c: Correct some HASFPU problems.
1737
1738 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1739
1740         * configure: Regenerated to track ../common/aclocal.m4 changes.
1741
1742 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1743
1744         * interp.c (mips_options): Fix samples option short form, should
1745         be `x'.
1746
1747 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1748
1749         * interp.c (sim_info): Enable info code.  Was just returning.
1750
1751 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1752
1753         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1754         MFC0.
1755
1756 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1757
1758         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1759         constants.
1760         (build_instruction): Ditto for LL.
1761
1762 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
1763
1764         * configure: Regenerated to track ../common/aclocal.m4 changes.
1765
1766 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1767
1768         * configure: Regenerated to track ../common/aclocal.m4 changes.
1769         * config.in: Ditto.
1770
1771 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1772
1773         * interp.c (sim_open): Add call to sim_analyze_program, update
1774         call to sim_config.
1775
1776 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1777
1778         * interp.c (sim_kill): Delete.
1779         (sim_create_inferior): Add ABFD argument. Set PC from same.
1780         (sim_load): Move code initializing trap handlers from here.
1781         (sim_open): To here.
1782         (sim_load): Delete, use sim-hload.c.
1783
1784         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1785
1786 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1787
1788         * configure: Regenerated to track ../common/aclocal.m4 changes.
1789         * config.in: Ditto.
1790
1791 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1792
1793         * interp.c (sim_open): Add ABFD argument.
1794         (sim_load): Move call to sim_config from here.
1795         (sim_open): To here.  Check return status.
1796
1797 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
1798
1799         * gencode.c (build_instruction): Two arg MADD should
1800         not assign result to $0.
1801
1802 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
1803
1804         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1805         * sim/mips/configure.in: Regenerate.
1806
1807 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
1808
1809         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1810         signed8, unsigned8 et.al. types.
1811
1812         * interp.c (SUB_REG_FETCH): Handle both little and big endian
1813         hosts when selecting subreg.
1814
1815 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
1816
1817         * interp.c (sim_engine_run): Reset the ZERO register to zero
1818         regardless of FEATURE_WARN_ZERO.
1819         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1820
1821 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1822
1823         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1824         (SignalException): For BreakPoints ignore any mode bits and just
1825         save the PC.
1826         (SignalException): Always set the CAUSE register.
1827
1828 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1829
1830         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1831         exception has been taken.
1832
1833         * interp.c: Implement the ERET and mt/f sr instructions.
1834
1835 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1836
1837         * interp.c (SignalException): Don't bother restarting an
1838         interrupt.
1839
1840 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1841
1842         * interp.c (SignalException): Really take an interrupt.
1843         (interrupt_event): Only deliver interrupts when enabled.
1844
1845 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1846
1847         * interp.c (sim_info): Only print info when verbose.
1848         (sim_info) Use sim_io_printf for output.
1849
1850 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1851
1852         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1853         mips architectures.
1854
1855 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1856
1857         * interp.c (sim_do_command): Check for common commands if a
1858         simulator specific command fails.
1859
1860 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
1861
1862         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1863         and simBE when DEBUG is defined.
1864
1865 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1866
1867         * interp.c (interrupt_event): New function.  Pass exception event
1868         onto exception handler.
1869
1870         * configure.in: Check for stdlib.h.
1871         * configure: Regenerate.
1872
1873         * gencode.c (build_instruction): Add UNUSED attribute to tempS
1874         variable declaration.
1875         (build_instruction): Initialize memval1.
1876         (build_instruction): Add UNUSED attribute to byte, bigend,
1877         reverse.
1878         (build_operands): Ditto.
1879
1880         * interp.c: Fix GCC warnings.
1881         (sim_get_quit_code): Delete.
1882
1883         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1884         * Makefile.in: Ditto.
1885         * configure: Re-generate.
1886
1887         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1888
1889 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1890
1891         * interp.c (mips_option_handler): New function parse argumes using
1892         sim-options.
1893         (myname): Replace with STATE_MY_NAME.
1894         (sim_open): Delete check for host endianness - performed by
1895         sim_config.
1896         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1897         (sim_open): Move much of the initialization from here.
1898         (sim_load): To here.  After the image has been loaded and
1899         endianness set.
1900         (sim_open): Move ColdReset from here.
1901         (sim_create_inferior): To here.
1902         (sim_open): Make FP check less dependant on host endianness.
1903
1904         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1905         run.
1906         * interp.c (sim_set_callbacks): Delete.
1907
1908         * interp.c (membank, membank_base, membank_size): Replace with
1909         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1910         (sim_open): Remove call to callback->init. gdb/run do this.
1911
1912         * interp.c: Update
1913
1914         * sim-main.h (SIM_HAVE_FLATMEM): Define.
1915
1916         * interp.c (big_endian_p): Delete, replaced by
1917         current_target_byte_order.
1918
1919 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1920
1921         * interp.c (host_read_long, host_read_word, host_swap_word,
1922         host_swap_long): Delete. Using common sim-endian.
1923         (sim_fetch_register, sim_store_register): Use H2T.
1924         (pipeline_ticks): Delete.  Handled by sim-events.
1925         (sim_info): Update.
1926         (sim_engine_run): Update.
1927
1928 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1929
1930         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1931         reason from here.
1932         (SignalException): To here. Signal using sim_engine_halt.
1933         (sim_stop_reason): Delete, moved to common.
1934
1935 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
1936
1937         * interp.c (sim_open): Add callback argument.
1938         (sim_set_callbacks): Delete SIM_DESC argument.
1939         (sim_size): Ditto.
1940
1941 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1942
1943         * Makefile.in (SIM_OBJS): Add common modules.
1944
1945         * interp.c (sim_set_callbacks): Also set SD callback.
1946         (set_endianness, xfer_*, swap_*): Delete.
1947         (host_read_word, host_read_long, host_swap_word, host_swap_long):
1948         Change to functions using sim-endian macros.
1949         (control_c, sim_stop): Delete, use common version.
1950         (simulate): Convert into.
1951         (sim_engine_run): This function.
1952         (sim_resume): Delete.
1953
1954         * interp.c (simulation): New variable - the simulator object.
1955         (sim_kind): Delete global - merged into simulation.
1956         (sim_load): Cleanup.  Move PC assignment from here.
1957         (sim_create_inferior): To here.
1958
1959         * sim-main.h: New file.
1960         * interp.c (sim-main.h): Include.
1961
1962 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
1963
1964         * configure: Regenerated to track ../common/aclocal.m4 changes.
1965
1966 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
1967
1968         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1969
1970 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
1971
1972         * gencode.c (build_instruction): DIV instructions: check
1973         for division by zero and integer overflow before using
1974         host's division operation.
1975
1976 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
1977
1978         * Makefile.in (SIM_OBJS): Add sim-load.o.
1979         * interp.c: #include bfd.h.
1980         (target_byte_order): Delete.
1981         (sim_kind, myname, big_endian_p): New static locals.
1982         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
1983         after argument parsing.  Recognize -E arg, set endianness accordingly.
1984         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
1985         load file into simulator.  Set PC from bfd.
1986         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
1987         (set_endianness): Use big_endian_p instead of target_byte_order.
1988
1989 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1990
1991         * interp.c (sim_size): Delete prototype - conflicts with
1992         definition in remote-sim.h.  Correct definition.
1993
1994 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1995
1996         * configure: Regenerated to track ../common/aclocal.m4 changes.
1997         * config.in: Ditto.
1998
1999 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2000
2001         * interp.c (sim_open): New arg `kind'.
2002
2003         * configure: Regenerated to track ../common/aclocal.m4 changes.
2004
2005 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2006
2007         * configure: Regenerated to track ../common/aclocal.m4 changes.
2008
2009 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2010
2011         * interp.c (sim_open): Set optind to 0 before calling getopt.
2012
2013 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2014
2015         * configure: Regenerated to track ../common/aclocal.m4 changes.
2016
2017 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2018
2019         * interp.c : Replace uses of pr_addr with pr_uword64
2020         where the bit length is always 64 independent of SIM_ADDR.
2021         (pr_uword64) : added.
2022
2023 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2024
2025         * configure: Re-generate.
2026
2027 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2028
2029         * configure: Regenerate to track ../common/aclocal.m4 changes.
2030
2031 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2032
2033         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2034         in argv form.
2035         (other sim_*): New SIM_DESC argument.
2036
2037 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2038
2039         * interp.c: Fix printing of addresses for non-64-bit targets.
2040         (pr_addr): Add function to print address based on size.
2041
2042 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2043
2044         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2045
2046 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2047
2048         * gencode.c (build_mips16_operands): Correct computation of base
2049         address for extended PC relative instruction.
2050
2051 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2052
2053         * interp.c (mips16_entry): Add support for floating point cases.
2054         (SignalException): Pass floating point cases to mips16_entry.
2055         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2056         registers.
2057         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2058         or fmt_word.
2059         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2060         and then set the state to fmt_uninterpreted.
2061         (COP_SW): Temporarily set the state to fmt_word while calling
2062         ValueFPR.
2063
2064 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2065
2066         * gencode.c (build_instruction): The high order may be set in the
2067         comparison flags at any ISA level, not just ISA 4.
2068
2069 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2070
2071         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2072         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2073         * configure.in: sinclude ../common/aclocal.m4.
2074         * configure: Regenerated.
2075
2076 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2077
2078         * configure: Rebuild after change to aclocal.m4.
2079
2080 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2081
2082         * configure configure.in Makefile.in:  Update to new configure
2083         scheme which is more compatible with WinGDB builds.
2084         * configure.in:  Improve comment on how to run autoconf.
2085         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2086         * Makefile.in:  Use autoconf substitution to install common
2087         makefile fragment.
2088
2089 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2090
2091         * gencode.c (build_instruction): Use BigEndianCPU instead of
2092         ByteSwapMem.
2093
2094 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2095
2096         * interp.c (sim_monitor): Make output to stdout visible in
2097         wingdb's I/O log window.
2098
2099 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2100
2101         * support.h: Undo previous change to SIGTRAP
2102         and SIGQUIT values.
2103
2104 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2105
2106         * interp.c (store_word, load_word): New static functions.
2107         (mips16_entry): New static function.
2108         (SignalException): Look for mips16 entry and exit instructions.
2109         (simulate): Use the correct index when setting fpr_state after
2110         doing a pending move.
2111
2112 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2113
2114         * interp.c: Fix byte-swapping code throughout to work on
2115         both little- and big-endian hosts.
2116
2117 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2118
2119         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2120         with gdb/config/i386/xm-windows.h.
2121
2122 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2123
2124         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2125         that messes up arithmetic shifts.
2126
2127 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2128
2129         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2130         SIGTRAP and SIGQUIT for _WIN32.
2131
2132 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2133
2134         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2135         force a 64 bit multiplication.
2136         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2137         destination register is 0, since that is the default mips16 nop
2138         instruction.
2139
2140 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2141
2142         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2143         (build_endian_shift): Don't check proc64.
2144         (build_instruction): Always set memval to uword64.  Cast op2 to
2145         uword64 when shifting it left in memory instructions.  Always use
2146         the same code for stores--don't special case proc64.
2147
2148         * gencode.c (build_mips16_operands): Fix base PC value for PC
2149         relative operands.
2150         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2151         jal instruction.
2152         * interp.c (simJALDELAYSLOT): Define.
2153         (JALDELAYSLOT): Define.
2154         (INDELAYSLOT, INJALDELAYSLOT): Define.
2155         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2156
2157 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2158
2159         * interp.c (sim_open): add flush_cache as a PMON routine
2160         (sim_monitor): handle flush_cache by ignoring it
2161
2162 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2163
2164         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2165         BigEndianMem.
2166         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2167         (BigEndianMem): Rename to ByteSwapMem and change sense.
2168         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2169         BigEndianMem references to !ByteSwapMem.
2170         (set_endianness): New function, with prototype.
2171         (sim_open): Call set_endianness.
2172         (sim_info): Use simBE instead of BigEndianMem.
2173         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2174         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2175         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2176         ifdefs, keeping the prototype declaration.
2177         (swap_word): Rewrite correctly.
2178         (ColdReset): Delete references to CONFIG.  Delete endianness related
2179         code; moved to set_endianness.
2180
2181 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2182
2183         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2184         * interp.c (CHECKHILO): Define away.
2185         (simSIGINT): New macro.
2186         (membank_size): Increase from 1MB to 2MB.
2187         (control_c): New function.
2188         (sim_resume): Rename parameter signal to signal_number.  Add local
2189         variable prev.  Call signal before and after simulate.
2190         (sim_stop_reason): Add simSIGINT support.
2191         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2192         functions always.
2193         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2194         if logfh is NULL.
2195         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2196         a call to sim_warning.
2197
2198 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2199
2200         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2201         16 bit instructions.
2202
2203 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2204
2205         Add support for mips16 (16 bit MIPS implementation):
2206         * gencode.c (inst_type): Add mips16 instruction encoding types.
2207         (GETDATASIZEINSN): Define.
2208         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2209         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2210         mtlo.
2211         (MIPS16_DECODE): New table, for mips16 instructions.
2212         (bitmap_val): New static function.
2213         (struct mips16_op): Define.
2214         (mips16_op_table): New table, for mips16 operands.
2215         (build_mips16_operands): New static function.
2216         (process_instructions): If PC is odd, decode a mips16
2217         instruction.  Break out instruction handling into new
2218         build_instruction function.
2219         (build_instruction): New static function, broken out of
2220         process_instructions.  Check modifiers rather than flags for SHIFT
2221         bit count and m[ft]{hi,lo} direction.
2222         (usage): Pass program name to fprintf.
2223         (main): Remove unused variable this_option_optind.  Change
2224         ``*loptarg++'' to ``loptarg++''.
2225         (my_strtoul): Parenthesize && within ||.
2226         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2227         (simulate): If PC is odd, fetch a 16 bit instruction, and
2228         increment PC by 2 rather than 4.
2229         * configure.in: Add case for mips16*-*-*.
2230         * configure: Rebuild.
2231
2232 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2233
2234         * interp.c: Allow -t to enable tracing in standalone simulator.
2235         Fix garbage output in trace file and error messages.
2236
2237 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2238
2239         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2240         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2241         * configure.in: Simplify using macros in ../common/aclocal.m4.
2242         * configure: Regenerated.
2243         * tconfig.in: New file.
2244
2245 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2246
2247         * interp.c: Fix bugs in 64-bit port.
2248         Use ansi function declarations for msvc compiler.
2249         Initialize and test file pointer in trace code.
2250         Prevent duplicate definition of LAST_EMED_REGNUM.
2251
2252 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2253
2254         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2255
2256 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2257
2258         * interp.c (SignalException): Check for explicit terminating
2259         breakpoint value.
2260         * gencode.c: Pass instruction value through SignalException()
2261         calls for Trap, Breakpoint and Syscall.
2262
2263 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2264
2265         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2266         only used on those hosts that provide it.
2267         * configure.in: Add sqrt() to list of functions to be checked for.
2268         * config.in: Re-generated.
2269         * configure: Re-generated.
2270
2271 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2272
2273         * gencode.c (process_instructions): Call build_endian_shift when
2274         expanding STORE RIGHT, to fix swr.
2275         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2276         clear the high bits.
2277         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2278         Fix float to int conversions to produce signed values.
2279
2280 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2281
2282         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2283         (process_instructions): Correct handling of nor instruction.
2284         Correct shift count for 32 bit shift instructions. Correct sign
2285         extension for arithmetic shifts to not shift the number of bits in
2286         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2287         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2288         Fix madd.
2289         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2290         It's OK to have a mult follow a mult.  What's not OK is to have a
2291         mult follow an mfhi.
2292         (Convert): Comment out incorrect rounding code.
2293
2294 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2295
2296         * interp.c (sim_monitor): Improved monitor printf
2297         simulation. Tidied up simulator warnings, and added "--log" option
2298         for directing warning message output.
2299         * gencode.c: Use sim_warning() rather than WARNING macro.
2300
2301 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2302
2303         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2304         getopt1.o, rather than on gencode.c.  Link objects together.
2305         Don't link against -liberty.
2306         (gencode.o, getopt.o, getopt1.o): New targets.
2307         * gencode.c: Include <ctype.h> and "ansidecl.h".
2308         (AND): Undefine after including "ansidecl.h".
2309         (ULONG_MAX): Define if not defined.
2310         (OP_*): Don't define macros; now defined in opcode/mips.h.
2311         (main): Call my_strtoul rather than strtoul.
2312         (my_strtoul): New static function.
2313
2314 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2315
2316         * gencode.c (process_instructions):  Generate word64 and uword64
2317         instead of `long long' and `unsigned long long' data types.
2318         * interp.c:  #include sysdep.h to get signals, and define default
2319         for SIGBUS.
2320         * (Convert):  Work around for Visual-C++ compiler bug with type
2321         conversion.
2322         * support.h:  Make things compile under Visual-C++ by using
2323         __int64 instead of `long long'.  Change many refs to long long
2324         into word64/uword64 typedefs.
2325
2326 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2327
2328         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2329         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2330         (docdir): Removed.
2331         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2332         (AC_PROG_INSTALL): Added.
2333         (AC_PROG_CC): Moved to before configure.host call.
2334         * configure: Rebuilt.
2335
2336 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2337
2338         * configure.in: Define @SIMCONF@ depending on mips target.
2339         * configure: Rebuild.
2340         * Makefile.in (run): Add @SIMCONF@ to control simulator
2341         construction.
2342         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2343         * interp.c: Remove some debugging, provide more detailed error
2344         messages, update memory accesses to use LOADDRMASK.
2345
2346 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2347
2348         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2349         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2350         stamp-h.
2351         * configure: Rebuild.
2352         * config.in: New file, generated by autoheader.
2353         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2354         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2355         HAVE_ANINT and HAVE_AINT, as appropriate.
2356         * Makefile.in (run): Use @LIBS@ rather than -lm.
2357         (interp.o): Depend upon config.h.
2358         (Makefile): Just rebuild Makefile.
2359         (clean): Remove stamp-h.
2360         (mostlyclean): Make the same as clean, not as distclean.
2361         (config.h, stamp-h): New targets.
2362
2363 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2364
2365         * interp.c (ColdReset): Fix boolean test. Make all simulator
2366         globals static.
2367
2368 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2369
2370         * interp.c (xfer_direct_word, xfer_direct_long,
2371         swap_direct_word, swap_direct_long, xfer_big_word,
2372         xfer_big_long, xfer_little_word, xfer_little_long,
2373         swap_word,swap_long): Added.
2374         * interp.c (ColdReset): Provide function indirection to
2375         host<->simulated_target transfer routines.
2376         * interp.c (sim_store_register, sim_fetch_register): Updated to
2377         make use of indirected transfer routines.
2378
2379 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2380
2381         * gencode.c (process_instructions): Ensure FP ABS instruction
2382         recognised.
2383         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2384         system call support.
2385
2386 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2387
2388         * interp.c (sim_do_command): Complain if callback structure not
2389         initialised.
2390
2391 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2392
2393         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2394         support for Sun hosts.
2395         * Makefile.in (gencode): Ensure the host compiler and libraries
2396         used for cross-hosted build.
2397
2398 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2399
2400         * interp.c, gencode.c: Some more (TODO) tidying.
2401
2402 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2403
2404         * gencode.c, interp.c: Replaced explicit long long references with
2405         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2406         * support.h (SET64LO, SET64HI): Macros added.
2407
2408 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2409
2410         * configure: Regenerate with autoconf 2.7.
2411
2412 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2413
2414         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2415         * support.h: Remove superfluous "1" from #if.
2416         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2417
2418 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2419
2420         * interp.c (StoreFPR): Control UndefinedResult() call on
2421         WARN_RESULT manifest.
2422
2423 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2424
2425         * gencode.c: Tidied instruction decoding, and added FP instruction
2426         support.
2427
2428         * interp.c: Added dineroIII, and BSD profiling support. Also
2429         run-time FP handling.
2430
2431 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2432
2433         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2434         gencode.c, interp.c, support.h: created.