1 2002-02-27 Chris Demetriou <cgd@broadcom.com>
3 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
6 2002-02-27 Chris Demetriou <cgd@broadcom.com>
8 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
9 add a comma) so that it more closely match the MIPS ISA
10 documentation opcode partitioning.
11 (PREF): Put useful names on opcode fields, and include
12 instruction-printing string.
14 2002-02-27 Chris Demetriou <cgd@broadcom.com>
16 * mips.igen (check_u64): New function which in the future will
17 check whether 64-bit instructions are usable and signal an
18 exception if not. Currently a no-op.
19 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
20 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
21 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
22 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
24 * mips.igen (check_fpu): New function which in the future will
25 check whether FPU instructions are usable and signal an exception
26 if not. Currently a no-op.
27 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
28 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
29 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
30 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
31 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
32 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
33 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
34 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
36 2002-02-27 Chris Demetriou <cgd@broadcom.com>
38 * mips.igen (do_load_left, do_load_right): Move to be immediately
40 (do_store_left, do_store_right): Move to be immediately following
43 2002-02-27 Chris Demetriou <cgd@broadcom.com>
45 * mips.igen (mipsV): New model name. Also, add it to
46 all instructions and functions where it is appropriate.
48 2002-02-18 Chris Demetriou <cgd@broadcom.com>
50 * mips.igen: For all functions and instructions, list model
51 names that support that instruction one per line.
53 2002-02-11 Chris Demetriou <cgd@broadcom.com>
55 * mips.igen: Add some additional comments about supported
56 models, and about which instructions go where.
57 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
58 order as is used in the rest of the file.
60 2002-02-11 Chris Demetriou <cgd@broadcom.com>
62 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
63 indicating that ALU32_END or ALU64_END are there to check
65 (DADD): Likewise, but also remove previous comment about
68 2002-02-10 Chris Demetriou <cgd@broadcom.com>
70 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
71 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
72 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
73 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
74 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
75 fields (i.e., add and move commas) so that they more closely
76 match the MIPS ISA documentation opcode partitioning.
78 2002-02-10 Chris Demetriou <cgd@broadcom.com>
80 * mips.igen (ADDI): Print immediate value.
82 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
83 (SLL): Print "nop" specially, and don't run the code
84 that does the shift for the "nop" case.
86 2001-11-17 Fred Fish <fnf@redhat.com>
88 * sim-main.h (float_operation): Move enum declaration outside
89 of _sim_cpu struct declaration.
91 2001-04-12 Jim Blandy <jimb@redhat.com>
93 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
94 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
96 * sim-main.h (COCIDX): Remove definition; this isn't supported by
97 PENDING_FILL, and you can get the intended effect gracefully by
98 calling PENDING_SCHED directly.
100 2001-02-23 Ben Elliston <bje@redhat.com>
102 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
103 already defined elsewhere.
105 2001-02-19 Ben Elliston <bje@redhat.com>
107 * sim-main.h (sim_monitor): Return an int.
108 * interp.c (sim_monitor): Add return values.
109 (signal_exception): Handle error conditions from sim_monitor.
111 2001-02-08 Ben Elliston <bje@redhat.com>
113 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
114 (store_memory): Likewise, pass cia to sim_core_write*.
116 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
118 On advice from Chris G. Demetriou <cgd@sibyte.com>:
119 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
121 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
123 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
124 * Makefile.in: Don't delete *.igen when cleaning directory.
126 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
128 * m16.igen (break): Call SignalException not sim_engine_halt.
130 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
133 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
135 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
137 * mips.igen (MxC1, DMxC1): Fix printf formatting.
139 2000-05-24 Michael Hayes <mhayes@cygnus.com>
141 * mips.igen (do_dmultx): Fix typo.
143 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
145 * configure: Regenerated to track ../common/aclocal.m4 changes.
147 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
149 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
151 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
153 * sim-main.h (GPR_CLEAR): Define macro.
155 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
157 * interp.c (decode_coproc): Output long using %lx and not %s.
159 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
161 * interp.c (sim_open): Sort & extend dummy memory regions for
162 --board=jmr3904 for eCos.
164 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
166 * configure: Regenerated.
168 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
170 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
171 calls, conditional on the simulator being in verbose mode.
173 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
175 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
176 cache don't get ReservedInstruction traps.
178 1999-11-29 Mark Salter <msalter@cygnus.com>
180 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
181 to clear status bits in sdisr register. This is how the hardware works.
183 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
184 being used by cygmon.
186 1999-11-11 Andrew Haley <aph@cygnus.com>
188 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
191 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
193 * mips.igen (MULT): Correct previous mis-applied patch.
195 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
197 * mips.igen (delayslot32): Handle sequence like
198 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
199 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
200 (MULT): Actually pass the third register...
202 1999-09-03 Mark Salter <msalter@cygnus.com>
204 * interp.c (sim_open): Added more memory aliases for additional
205 hardware being touched by cygmon on jmr3904 board.
207 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
209 * configure: Regenerated to track ../common/aclocal.m4 changes.
211 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
213 * interp.c (sim_store_register): Handle case where client - GDB -
214 specifies that a 4 byte register is 8 bytes in size.
215 (sim_fetch_register): Ditto.
217 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
219 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
220 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
221 (idt_monitor_base): Base address for IDT monitor traps.
222 (pmon_monitor_base): Ditto for PMON.
223 (lsipmon_monitor_base): Ditto for LSI PMON.
224 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
225 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
226 (sim_firmware_command): New function.
227 (mips_option_handler): Call it for OPTION_FIRMWARE.
228 (sim_open): Allocate memory for idt_monitor region. If "--board"
229 option was given, add no monitor by default. Add BREAK hooks only if
230 monitors are also there.
232 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
234 * interp.c (sim_monitor): Flush output before reading input.
236 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
238 * tconfig.in (SIM_HANDLES_LMA): Always define.
240 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
242 From Mark Salter <msalter@cygnus.com>:
243 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
244 (sim_open): Add setup for BSP board.
246 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
248 * mips.igen (MULT, MULTU): Add syntax for two operand version.
249 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
250 them as unimplemented.
252 1999-05-08 Felix Lee <flee@cygnus.com>
254 * configure: Regenerated to track ../common/aclocal.m4 changes.
256 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
258 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
260 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
262 * configure.in: Any mips64vr5*-*-* target should have
263 -DTARGET_ENABLE_FR=1.
264 (default_endian): Any mips64vr*el-*-* target should default to
266 * configure: Re-generate.
268 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
270 * mips.igen (ldl): Extend from _16_, not 32.
272 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
274 * interp.c (sim_store_register): Force registers written to by GDB
275 into an un-interpreted state.
277 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
279 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
280 CPU, start periodic background I/O polls.
281 (tx3904sio_poll): New function: periodic I/O poller.
283 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
285 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
287 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
289 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
292 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
294 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
295 (load_word): Call SIM_CORE_SIGNAL hook on error.
296 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
297 starting. For exception dispatching, pass PC instead of NULL_CIA.
298 (decode_coproc): Use COP0_BADVADDR to store faulting address.
299 * sim-main.h (COP0_BADVADDR): Define.
300 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
301 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
302 (_sim_cpu): Add exc_* fields to store register value snapshots.
303 * mips.igen (*): Replace memory-related SignalException* calls
304 with references to SIM_CORE_SIGNAL hook.
306 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
308 * sim-main.c (*): Minor warning cleanups.
310 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
312 * m16.igen (DADDIU5): Correct type-o.
314 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
316 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
319 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
321 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
323 (interp.o): Add dependency on itable.h
324 (oengine.c, gencode): Delete remaining references.
325 (BUILT_SRC_FROM_GEN): Clean up.
327 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
330 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
331 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
333 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
334 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
335 Drop the "64" qualifier to get the HACK generator working.
336 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
337 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
338 qualifier to get the hack generator working.
339 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
341 (DSLLV): Use do_dsllv.
344 (DSRLV): Use do_dsrlv.
345 (BC1): Move *vr4100 to get the HACK generator working.
346 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
347 get the HACK generator working.
348 (MACC) Rename to get the HACK generator working.
349 (DMACC,MACCS,DMACCS): Add the 64.
351 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
353 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
354 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
356 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
358 * mips/interp.c (DEBUG): Cleanups.
360 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
362 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
363 (tx3904sio_tickle): fflush after a stdout character output.
365 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
367 * interp.c (sim_close): Uninstall modules.
369 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
371 * sim-main.h, interp.c (sim_monitor): Change to global
374 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
376 * configure.in (vr4100): Only include vr4100 instructions in
378 * configure: Re-generate.
379 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
381 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
383 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
384 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
387 * configure.in (sim_default_gen, sim_use_gen): Replace with
389 (--enable-sim-igen): Delete config option. Always using IGEN.
390 * configure: Re-generate.
392 * Makefile.in (gencode): Kill, kill, kill.
395 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
397 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
398 bit mips16 igen simulator.
399 * configure: Re-generate.
401 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
402 as part of vr4100 ISA.
403 * vr.igen: Mark all instructions as 64 bit only.
405 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
407 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
410 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
412 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
413 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
414 * configure: Re-generate.
416 * m16.igen (BREAK): Define breakpoint instruction.
417 (JALX32): Mark instruction as mips16 and not r3900.
418 * mips.igen (C.cond.fmt): Fix typo in instruction format.
420 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
422 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
424 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
425 insn as a debug breakpoint.
427 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
429 (PENDING_SCHED): Clean up trace statement.
430 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
431 (PENDING_FILL): Delay write by only one cycle.
432 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
434 * sim-main.c (pending_tick): Clean up trace statements. Add trace
436 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
438 (pending_tick): Move incrementing of index to FOR statement.
439 (pending_tick): Only update PENDING_OUT after a write has occured.
441 * configure.in: Add explicit mips-lsi-* target. Use gencode to
443 * configure: Re-generate.
445 * interp.c (sim_engine_run OLD): Delete explicit call to
446 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
448 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
450 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
451 interrupt level number to match changed SignalExceptionInterrupt
454 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
456 * interp.c: #include "itable.h" if WITH_IGEN.
457 (get_insn_name): New function.
458 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
459 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
461 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
463 * configure: Rebuilt to inhale new common/aclocal.m4.
465 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
467 * dv-tx3904sio.c: Include sim-assert.h.
469 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
471 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
472 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
473 Reorganize target-specific sim-hardware checks.
474 * configure: rebuilt.
475 * interp.c (sim_open): For tx39 target boards, set
476 OPERATING_ENVIRONMENT, add tx3904sio devices.
477 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
478 ROM executables. Install dv-sockser into sim-modules list.
480 * dv-tx3904irc.c: Compiler warning clean-up.
481 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
482 frequent hw-trace messages.
484 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
486 * vr.igen (MulAcc): Identify as a vr4100 specific function.
488 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
490 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
493 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
494 * mips.igen: Define vr4100 model. Include vr.igen.
495 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
497 * mips.igen (check_mf_hilo): Correct check.
499 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
501 * sim-main.h (interrupt_event): Add prototype.
503 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
504 register_ptr, register_value.
505 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
507 * sim-main.h (tracefh): Make extern.
509 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
511 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
512 Reduce unnecessarily high timer event frequency.
513 * dv-tx3904cpu.c: Ditto for interrupt event.
515 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
517 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
519 (interrupt_event): Made non-static.
521 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
522 interchange of configuration values for external vs. internal
525 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
527 * mips.igen (BREAK): Moved code to here for
528 simulator-reserved break instructions.
529 * gencode.c (build_instruction): Ditto.
530 * interp.c (signal_exception): Code moved from here. Non-
531 reserved instructions now use exception vector, rather
533 * sim-main.h: Moved magic constants to here.
535 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
537 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
538 register upon non-zero interrupt event level, clear upon zero
540 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
541 by passing zero event value.
542 (*_io_{read,write}_buffer): Endianness fixes.
543 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
544 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
546 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
547 serial I/O and timer module at base address 0xFFFF0000.
549 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
551 * mips.igen (SWC1) : Correct the handling of ReverseEndian
554 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
556 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
560 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
562 * dv-tx3904tmr.c: New file - implements tx3904 timer.
563 * dv-tx3904{irc,cpu}.c: Mild reformatting.
564 * configure.in: Include tx3904tmr in hw_device list.
565 * configure: Rebuilt.
566 * interp.c (sim_open): Instantiate three timer instances.
567 Fix address typo of tx3904irc instance.
569 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
571 * interp.c (signal_exception): SystemCall exception now uses
572 the exception vector.
574 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
576 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
579 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
581 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
583 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
585 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
587 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
588 sim-main.h. Declare a struct hw_descriptor instead of struct
589 hw_device_descriptor.
591 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
593 * mips.igen (do_store_left, do_load_left): Compute nr of left and
594 right bits and then re-align left hand bytes to correct byte
595 lanes. Fix incorrect computation in do_store_left when loading
596 bytes from second word.
598 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
600 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
601 * interp.c (sim_open): Only create a device tree when HW is
604 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
605 * interp.c (signal_exception): Ditto.
607 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
609 * gencode.c: Mark BEGEZALL as LIKELY.
611 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
613 * sim-main.h (ALU32_END): Sign extend 32 bit results.
614 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
616 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
618 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
619 modules. Recognize TX39 target with "mips*tx39" pattern.
620 * configure: Rebuilt.
621 * sim-main.h (*): Added many macros defining bits in
622 TX39 control registers.
623 (SignalInterrupt): Send actual PC instead of NULL.
624 (SignalNMIReset): New exception type.
625 * interp.c (board): New variable for future use to identify
626 a particular board being simulated.
627 (mips_option_handler,mips_options): Added "--board" option.
628 (interrupt_event): Send actual PC.
629 (sim_open): Make memory layout conditional on board setting.
630 (signal_exception): Initial implementation of hardware interrupt
631 handling. Accept another break instruction variant for simulator
633 (decode_coproc): Implement RFE instruction for TX39.
634 (mips.igen): Decode RFE instruction as such.
635 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
636 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
637 bbegin to implement memory map.
638 * dv-tx3904cpu.c: New file.
639 * dv-tx3904irc.c: New file.
641 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
643 * mips.igen (check_mt_hilo): Create a separate r3900 version.
645 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
647 * tx.igen (madd,maddu): Replace calls to check_op_hilo
648 with calls to check_div_hilo.
650 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
652 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
653 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
654 Add special r3900 version of do_mult_hilo.
655 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
656 with calls to check_mult_hilo.
657 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
658 with calls to check_div_hilo.
660 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
662 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
663 Document a replacement.
665 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
667 * interp.c (sim_monitor): Make mon_printf work.
669 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
671 * sim-main.h (INSN_NAME): New arg `cpu'.
673 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
675 * configure: Regenerated to track ../common/aclocal.m4 changes.
677 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
679 * configure: Regenerated to track ../common/aclocal.m4 changes.
682 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
684 * acconfig.h: New file.
685 * configure.in: Reverted change of Apr 24; use sinclude again.
687 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
689 * configure: Regenerated to track ../common/aclocal.m4 changes.
692 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
694 * configure.in: Don't call sinclude.
696 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
698 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
700 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
702 * mips.igen (ERET): Implement.
704 * interp.c (decode_coproc): Return sign-extended EPC.
706 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
708 * interp.c (signal_exception): Do not ignore Trap.
709 (signal_exception): On TRAP, restart at exception address.
710 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
711 (signal_exception): Update.
712 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
713 so that TRAP instructions are caught.
715 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
717 * sim-main.h (struct hilo_access, struct hilo_history): Define,
718 contains HI/LO access history.
719 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
720 (HIACCESS, LOACCESS): Delete, replace with
721 (HIHISTORY, LOHISTORY): New macros.
722 (CHECKHILO): Delete all, moved to mips.igen
724 * gencode.c (build_instruction): Do not generate checks for
725 correct HI/LO register usage.
727 * interp.c (old_engine_run): Delete checks for correct HI/LO
730 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
731 check_mf_cycles): New functions.
732 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
733 do_divu, domultx, do_mult, do_multu): Use.
735 * tx.igen ("madd", "maddu"): Use.
737 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
739 * mips.igen (DSRAV): Use function do_dsrav.
740 (SRAV): Use new function do_srav.
742 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
743 (B): Sign extend 11 bit immediate.
744 (EXT-B*): Shift 16 bit immediate left by 1.
745 (ADDIU*): Don't sign extend immediate value.
747 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
749 * m16run.c (sim_engine_run): Restore CIA after handling an event.
751 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
754 * mips.igen (delayslot32, nullify_next_insn): New functions.
755 (m16.igen): Always include.
756 (do_*): Add more tracing.
758 * m16.igen (delayslot16): Add NIA argument, could be called by a
759 32 bit MIPS16 instruction.
761 * interp.c (ifetch16): Move function from here.
762 * sim-main.c (ifetch16): To here.
764 * sim-main.c (ifetch16, ifetch32): Update to match current
765 implementations of LH, LW.
766 (signal_exception): Don't print out incorrect hex value of illegal
769 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
771 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
774 * m16.igen: Implement MIPS16 instructions.
776 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
777 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
778 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
779 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
780 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
781 bodies of corresponding code from 32 bit insn to these. Also used
782 by MIPS16 versions of functions.
784 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
785 (IMEM16): Drop NR argument from macro.
787 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
789 * Makefile.in (SIM_OBJS): Add sim-main.o.
791 * sim-main.h (address_translation, load_memory, store_memory,
792 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
794 (pr_addr, pr_uword64): Declare.
795 (sim-main.c): Include when H_REVEALS_MODULE_P.
797 * interp.c (address_translation, load_memory, store_memory,
798 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
800 * sim-main.c: To here. Fix compilation problems.
802 * configure.in: Enable inlining.
803 * configure: Re-config.
805 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
807 * configure: Regenerated to track ../common/aclocal.m4 changes.
809 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
811 * mips.igen: Include tx.igen.
812 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
813 * tx.igen: New file, contains MADD and MADDU.
815 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
816 the hardwired constant `7'.
817 (store_memory): Ditto.
818 (LOADDRMASK): Move definition to sim-main.h.
820 mips.igen (MTC0): Enable for r3900.
823 mips.igen (do_load_byte): Delete.
824 (do_load, do_store, do_load_left, do_load_write, do_store_left,
825 do_store_right): New functions.
826 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
828 configure.in: Let the tx39 use igen again.
831 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
833 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
834 not an address sized quantity. Return zero for cache sizes.
836 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
838 * mips.igen (r3900): r3900 does not support 64 bit integer
841 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
843 * configure.in (mipstx39*-*-*): Use gencode simulator rather
845 * configure : Rebuild.
847 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
849 * configure: Regenerated to track ../common/aclocal.m4 changes.
851 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
853 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
855 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
857 * configure: Regenerated to track ../common/aclocal.m4 changes.
858 * config.in: Regenerated to track ../common/aclocal.m4 changes.
860 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
862 * configure: Regenerated to track ../common/aclocal.m4 changes.
864 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
866 * interp.c (Max, Min): Comment out functions. Not yet used.
868 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
870 * configure: Regenerated to track ../common/aclocal.m4 changes.
872 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
874 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
875 configurable settings for stand-alone simulator.
877 * configure.in: Added X11 search, just in case.
879 * configure: Regenerated.
881 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
883 * interp.c (sim_write, sim_read, load_memory, store_memory):
884 Replace sim_core_*_map with read_map, write_map, exec_map resp.
886 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
888 * sim-main.h (GETFCC): Return an unsigned value.
890 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
892 * mips.igen (DIV): Fix check for -1 / MIN_INT.
893 (DADD): Result destination is RD not RT.
895 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
897 * sim-main.h (HIACCESS, LOACCESS): Always define.
899 * mdmx.igen (Maxi, Mini): Rename Max, Min.
901 * interp.c (sim_info): Delete.
903 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
905 * interp.c (DECLARE_OPTION_HANDLER): Use it.
906 (mips_option_handler): New argument `cpu'.
907 (sim_open): Update call to sim_add_option_table.
909 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
911 * mips.igen (CxC1): Add tracing.
913 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
915 * sim-main.h (Max, Min): Declare.
917 * interp.c (Max, Min): New functions.
919 * mips.igen (BC1): Add tracing.
921 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
923 * interp.c Added memory map for stack in vr4100
925 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
927 * interp.c (load_memory): Add missing "break"'s.
929 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
931 * interp.c (sim_store_register, sim_fetch_register): Pass in
932 length parameter. Return -1.
934 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
936 * interp.c: Added hardware init hook, fixed warnings.
938 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
940 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
942 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
944 * interp.c (ifetch16): New function.
946 * sim-main.h (IMEM32): Rename IMEM.
947 (IMEM16_IMMED): Define.
949 (DELAY_SLOT): Update.
951 * m16run.c (sim_engine_run): New file.
953 * m16.igen: All instructions except LB.
954 (LB): Call do_load_byte.
955 * mips.igen (do_load_byte): New function.
956 (LB): Call do_load_byte.
958 * mips.igen: Move spec for insn bit size and high bit from here.
959 * Makefile.in (tmp-igen, tmp-m16): To here.
961 * m16.dc: New file, decode mips16 instructions.
963 * Makefile.in (SIM_NO_ALL): Define.
964 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
966 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
968 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
969 point unit to 32 bit registers.
970 * configure: Re-generate.
972 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
974 * configure.in (sim_use_gen): Make IGEN the default simulator
975 generator for generic 32 and 64 bit mips targets.
976 * configure: Re-generate.
978 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
980 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
983 * interp.c (sim_fetch_register, sim_store_register): Read/write
984 FGR from correct location.
985 (sim_open): Set size of FGR's according to
986 WITH_TARGET_FLOATING_POINT_BITSIZE.
988 * sim-main.h (FGR): Store floating point registers in a separate
991 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
993 * configure: Regenerated to track ../common/aclocal.m4 changes.
995 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
997 * interp.c (ColdReset): Call PENDING_INVALIDATE.
999 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1001 * interp.c (pending_tick): New function. Deliver pending writes.
1003 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1004 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1005 it can handle mixed sized quantites and single bits.
1007 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1009 * interp.c (oengine.h): Do not include when building with IGEN.
1010 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1011 (sim_info): Ditto for PROCESSOR_64BIT.
1012 (sim_monitor): Replace ut_reg with unsigned_word.
1013 (*): Ditto for t_reg.
1014 (LOADDRMASK): Define.
1015 (sim_open): Remove defunct check that host FP is IEEE compliant,
1016 using software to emulate floating point.
1017 (value_fpr, ...): Always compile, was conditional on HASFPU.
1019 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1021 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1024 * interp.c (SD, CPU): Define.
1025 (mips_option_handler): Set flags in each CPU.
1026 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1027 (sim_close): Do not clear STATE, deleted anyway.
1028 (sim_write, sim_read): Assume CPU zero's vm should be used for
1030 (sim_create_inferior): Set the PC for all processors.
1031 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1033 (mips16_entry): Pass correct nr of args to store_word, load_word.
1034 (ColdReset): Cold reset all cpu's.
1035 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1036 (sim_monitor, load_memory, store_memory, signal_exception): Use
1037 `CPU' instead of STATE_CPU.
1040 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1043 * sim-main.h (signal_exception): Add sim_cpu arg.
1044 (SignalException*): Pass both SD and CPU to signal_exception.
1045 * interp.c (signal_exception): Update.
1047 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1049 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1050 address_translation): Ditto
1051 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1053 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1055 * configure: Regenerated to track ../common/aclocal.m4 changes.
1057 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1059 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1061 * mips.igen (model): Map processor names onto BFD name.
1063 * sim-main.h (CPU_CIA): Delete.
1064 (SET_CIA, GET_CIA): Define
1066 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1068 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1071 * configure.in (default_endian): Configure a big-endian simulator
1073 * configure: Re-generate.
1075 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1077 * configure: Regenerated to track ../common/aclocal.m4 changes.
1079 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1081 * interp.c (sim_monitor): Handle Densan monitor outbyte
1082 and inbyte functions.
1084 1997-12-29 Felix Lee <flee@cygnus.com>
1086 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1088 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1090 * Makefile.in (tmp-igen): Arrange for $zero to always be
1091 reset to zero after every instruction.
1093 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1095 * configure: Regenerated to track ../common/aclocal.m4 changes.
1098 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1100 * mips.igen (MSUB): Fix to work like MADD.
1101 * gencode.c (MSUB): Similarly.
1103 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1105 * configure: Regenerated to track ../common/aclocal.m4 changes.
1107 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1109 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1111 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1113 * sim-main.h (sim-fpu.h): Include.
1115 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1116 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1117 using host independant sim_fpu module.
1119 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1121 * interp.c (signal_exception): Report internal errors with SIGABRT
1124 * sim-main.h (C0_CONFIG): New register.
1125 (signal.h): No longer include.
1127 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1129 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1131 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1133 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1135 * mips.igen: Tag vr5000 instructions.
1136 (ANDI): Was missing mipsIV model, fix assembler syntax.
1137 (do_c_cond_fmt): New function.
1138 (C.cond.fmt): Handle mips I-III which do not support CC field
1140 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1141 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1143 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1144 vr5000 which saves LO in a GPR separatly.
1146 * configure.in (enable-sim-igen): For vr5000, select vr5000
1147 specific instructions.
1148 * configure: Re-generate.
1150 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1152 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1154 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1155 fmt_uninterpreted_64 bit cases to switch. Convert to
1158 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1160 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1161 as specified in IV3.2 spec.
1162 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1164 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1166 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1167 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1168 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1169 PENDING_FILL versions of instructions. Simplify.
1171 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1173 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1175 (MTHI, MFHI): Disable code checking HI-LO.
1177 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1179 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1181 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1183 * gencode.c (build_mips16_operands): Replace IPC with cia.
1185 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1186 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1188 (UndefinedResult): Replace function with macro/function
1190 (sim_engine_run): Don't save PC in IPC.
1192 * sim-main.h (IPC): Delete.
1195 * interp.c (signal_exception, store_word, load_word,
1196 address_translation, load_memory, store_memory, cache_op,
1197 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1198 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1199 current instruction address - cia - argument.
1200 (sim_read, sim_write): Call address_translation directly.
1201 (sim_engine_run): Rename variable vaddr to cia.
1202 (signal_exception): Pass cia to sim_monitor
1204 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1205 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1206 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1208 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1209 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1212 * interp.c (signal_exception): Pass restart address to
1215 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1216 idecode.o): Add dependency.
1218 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1220 (DELAY_SLOT): Update NIA not PC with branch address.
1221 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1223 * mips.igen: Use CIA not PC in branch calculations.
1224 (illegal): Call SignalException.
1225 (BEQ, ADDIU): Fix assembler.
1227 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1229 * m16.igen (JALX): Was missing.
1231 * configure.in (enable-sim-igen): New configuration option.
1232 * configure: Re-generate.
1234 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1236 * interp.c (load_memory, store_memory): Delete parameter RAW.
1237 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1238 bypassing {load,store}_memory.
1240 * sim-main.h (ByteSwapMem): Delete definition.
1242 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1244 * interp.c (sim_do_command, sim_commands): Delete mips specific
1245 commands. Handled by module sim-options.
1247 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1248 (WITH_MODULO_MEMORY): Define.
1250 * interp.c (sim_info): Delete code printing memory size.
1252 * interp.c (mips_size): Nee sim_size, delete function.
1254 (monitor, monitor_base, monitor_size): Delete global variables.
1255 (sim_open, sim_close): Delete code creating monitor and other
1256 memory regions. Use sim-memopts module, via sim_do_commandf, to
1257 manage memory regions.
1258 (load_memory, store_memory): Use sim-core for memory model.
1260 * interp.c (address_translation): Delete all memory map code
1261 except line forcing 32 bit addresses.
1263 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1265 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1268 * interp.c (logfh, logfile): Delete globals.
1269 (sim_open, sim_close): Delete code opening & closing log file.
1270 (mips_option_handler): Delete -l and -n options.
1271 (OPTION mips_options): Ditto.
1273 * interp.c (OPTION mips_options): Rename option trace to dinero.
1274 (mips_option_handler): Update.
1276 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1278 * interp.c (fetch_str): New function.
1279 (sim_monitor): Rewrite using sim_read & sim_write.
1280 (sim_open): Check magic number.
1281 (sim_open): Write monitor vectors into memory using sim_write.
1282 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1283 (sim_read, sim_write): Simplify - transfer data one byte at a
1285 (load_memory, store_memory): Clarify meaning of parameter RAW.
1287 * sim-main.h (isHOST): Defete definition.
1288 (isTARGET): Mark as depreciated.
1289 (address_translation): Delete parameter HOST.
1291 * interp.c (address_translation): Delete parameter HOST.
1293 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1297 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1298 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1300 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1302 * mips.igen: Add model filter field to records.
1304 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1306 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1308 interp.c (sim_engine_run): Do not compile function sim_engine_run
1309 when WITH_IGEN == 1.
1311 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1312 target architecture.
1314 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1315 igen. Replace with configuration variables sim_igen_flags /
1318 * m16.igen: New file. Copy mips16 insns here.
1319 * mips.igen: From here.
1321 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1323 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1325 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1327 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1329 * gencode.c (build_instruction): Follow sim_write's lead in using
1330 BigEndianMem instead of !ByteSwapMem.
1332 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1334 * configure.in (sim_gen): Dependent on target, select type of
1335 generator. Always select old style generator.
1337 configure: Re-generate.
1339 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1341 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1342 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1343 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1344 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1345 SIM_@sim_gen@_*, set by autoconf.
1347 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1349 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1351 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1352 CURRENT_FLOATING_POINT instead.
1354 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1355 (address_translation): Raise exception InstructionFetch when
1356 translation fails and isINSTRUCTION.
1358 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1359 sim_engine_run): Change type of of vaddr and paddr to
1361 (address_translation, prefetch, load_memory, store_memory,
1362 cache_op): Change type of vAddr and pAddr to address_word.
1364 * gencode.c (build_instruction): Change type of vaddr and paddr to
1367 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1369 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1370 macro to obtain result of ALU op.
1372 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1374 * interp.c (sim_info): Call profile_print.
1376 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1378 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1380 * sim-main.h (WITH_PROFILE): Do not define, defined in
1381 common/sim-config.h. Use sim-profile module.
1382 (simPROFILE): Delete defintion.
1384 * interp.c (PROFILE): Delete definition.
1385 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1386 (sim_close): Delete code writing profile histogram.
1387 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1389 (sim_engine_run): Delete code profiling the PC.
1391 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1393 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1395 * interp.c (sim_monitor): Make register pointers of type
1398 * sim-main.h: Make registers of type unsigned_word not
1401 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1403 * interp.c (sync_operation): Rename from SyncOperation, make
1404 global, add SD argument.
1405 (prefetch): Rename from Prefetch, make global, add SD argument.
1406 (decode_coproc): Make global.
1408 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1410 * gencode.c (build_instruction): Generate DecodeCoproc not
1411 decode_coproc calls.
1413 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1414 (SizeFGR): Move to sim-main.h
1415 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1416 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1417 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1419 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1420 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1421 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1422 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1423 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1424 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1426 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1428 (sim-alu.h): Include.
1429 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1430 (sim_cia): Typedef to instruction_address.
1432 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1434 * Makefile.in (interp.o): Rename generated file engine.c to
1439 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1441 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1443 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1445 * gencode.c (build_instruction): For "FPSQRT", output correct
1446 number of arguments to Recip.
1448 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1450 * Makefile.in (interp.o): Depends on sim-main.h
1452 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1454 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1455 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1456 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1457 STATE, DSSTATE): Define
1458 (GPR, FGRIDX, ..): Define.
1460 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1461 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1462 (GPR, FGRIDX, ...): Delete macros.
1464 * interp.c: Update names to match defines from sim-main.h
1466 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1468 * interp.c (sim_monitor): Add SD argument.
1469 (sim_warning): Delete. Replace calls with calls to
1471 (sim_error): Delete. Replace calls with sim_io_error.
1472 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1473 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1474 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1476 (mips_size): Rename from sim_size. Add SD argument.
1478 * interp.c (simulator): Delete global variable.
1479 (callback): Delete global variable.
1480 (mips_option_handler, sim_open, sim_write, sim_read,
1481 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1482 sim_size,sim_monitor): Use sim_io_* not callback->*.
1483 (sim_open): ZALLOC simulator struct.
1484 (PROFILE): Do not define.
1486 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1488 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1489 support.h with corresponding code.
1491 * sim-main.h (word64, uword64), support.h: Move definition to
1493 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1496 * Makefile.in: Update dependencies
1497 * interp.c: Do not include.
1499 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1501 * interp.c (address_translation, load_memory, store_memory,
1502 cache_op): Rename to from AddressTranslation et.al., make global,
1505 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1508 * interp.c (SignalException): Rename to signal_exception, make
1511 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1513 * sim-main.h (SignalException, SignalExceptionInterrupt,
1514 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1515 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1516 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1519 * interp.c, support.h: Use.
1521 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1523 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1524 to value_fpr / store_fpr. Add SD argument.
1525 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1526 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1528 * sim-main.h (ValueFPR, StoreFPR): Define.
1530 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1532 * interp.c (sim_engine_run): Check consistency between configure
1533 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1536 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1537 (mips_fpu): Configure WITH_FLOATING_POINT.
1538 (mips_endian): Configure WITH_TARGET_ENDIAN.
1539 * configure: Update.
1541 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1543 * configure: Regenerated to track ../common/aclocal.m4 changes.
1545 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1547 * configure: Regenerated.
1549 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1551 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1553 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1555 * gencode.c (print_igen_insn_models): Assume certain architectures
1556 include all mips* instructions.
1557 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1560 * Makefile.in (tmp.igen): Add target. Generate igen input from
1563 * gencode.c (FEATURE_IGEN): Define.
1564 (main): Add --igen option. Generate output in igen format.
1565 (process_instructions): Format output according to igen option.
1566 (print_igen_insn_format): New function.
1567 (print_igen_insn_models): New function.
1568 (process_instructions): Only issue warnings and ignore
1569 instructions when no FEATURE_IGEN.
1571 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1573 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1576 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1578 * configure: Regenerated to track ../common/aclocal.m4 changes.
1580 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1582 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1583 SIM_RESERVED_BITS): Delete, moved to common.
1584 (SIM_EXTRA_CFLAGS): Update.
1586 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1588 * configure.in: Configure non-strict memory alignment.
1589 * configure: Regenerated to track ../common/aclocal.m4 changes.
1591 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1593 * configure: Regenerated to track ../common/aclocal.m4 changes.
1595 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1597 * gencode.c (SDBBP,DERET): Added (3900) insns.
1598 (RFE): Turn on for 3900.
1599 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1600 (dsstate): Made global.
1601 (SUBTARGET_R3900): Added.
1602 (CANCELDELAYSLOT): New.
1603 (SignalException): Ignore SystemCall rather than ignore and
1604 terminate. Add DebugBreakPoint handling.
1605 (decode_coproc): New insns RFE, DERET; and new registers Debug
1606 and DEPC protected by SUBTARGET_R3900.
1607 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1609 * Makefile.in,configure.in: Add mips subtarget option.
1610 * configure: Update.
1612 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1614 * gencode.c: Add r3900 (tx39).
1617 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1619 * gencode.c (build_instruction): Don't need to subtract 4 for
1622 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1624 * interp.c: Correct some HASFPU problems.
1626 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1628 * configure: Regenerated to track ../common/aclocal.m4 changes.
1630 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1632 * interp.c (mips_options): Fix samples option short form, should
1635 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1637 * interp.c (sim_info): Enable info code. Was just returning.
1639 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1641 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1644 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1646 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1648 (build_instruction): Ditto for LL.
1650 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1652 * configure: Regenerated to track ../common/aclocal.m4 changes.
1654 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1656 * configure: Regenerated to track ../common/aclocal.m4 changes.
1659 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1661 * interp.c (sim_open): Add call to sim_analyze_program, update
1664 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1666 * interp.c (sim_kill): Delete.
1667 (sim_create_inferior): Add ABFD argument. Set PC from same.
1668 (sim_load): Move code initializing trap handlers from here.
1669 (sim_open): To here.
1670 (sim_load): Delete, use sim-hload.c.
1672 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1674 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1676 * configure: Regenerated to track ../common/aclocal.m4 changes.
1679 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1681 * interp.c (sim_open): Add ABFD argument.
1682 (sim_load): Move call to sim_config from here.
1683 (sim_open): To here. Check return status.
1685 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1687 * gencode.c (build_instruction): Two arg MADD should
1688 not assign result to $0.
1690 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1692 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1693 * sim/mips/configure.in: Regenerate.
1695 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1697 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1698 signed8, unsigned8 et.al. types.
1700 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1701 hosts when selecting subreg.
1703 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1705 * interp.c (sim_engine_run): Reset the ZERO register to zero
1706 regardless of FEATURE_WARN_ZERO.
1707 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1709 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1711 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1712 (SignalException): For BreakPoints ignore any mode bits and just
1714 (SignalException): Always set the CAUSE register.
1716 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1718 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1719 exception has been taken.
1721 * interp.c: Implement the ERET and mt/f sr instructions.
1723 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1725 * interp.c (SignalException): Don't bother restarting an
1728 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1730 * interp.c (SignalException): Really take an interrupt.
1731 (interrupt_event): Only deliver interrupts when enabled.
1733 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1735 * interp.c (sim_info): Only print info when verbose.
1736 (sim_info) Use sim_io_printf for output.
1738 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1740 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1743 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1745 * interp.c (sim_do_command): Check for common commands if a
1746 simulator specific command fails.
1748 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1750 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1751 and simBE when DEBUG is defined.
1753 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1755 * interp.c (interrupt_event): New function. Pass exception event
1756 onto exception handler.
1758 * configure.in: Check for stdlib.h.
1759 * configure: Regenerate.
1761 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1762 variable declaration.
1763 (build_instruction): Initialize memval1.
1764 (build_instruction): Add UNUSED attribute to byte, bigend,
1766 (build_operands): Ditto.
1768 * interp.c: Fix GCC warnings.
1769 (sim_get_quit_code): Delete.
1771 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1772 * Makefile.in: Ditto.
1773 * configure: Re-generate.
1775 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1777 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1779 * interp.c (mips_option_handler): New function parse argumes using
1781 (myname): Replace with STATE_MY_NAME.
1782 (sim_open): Delete check for host endianness - performed by
1784 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1785 (sim_open): Move much of the initialization from here.
1786 (sim_load): To here. After the image has been loaded and
1788 (sim_open): Move ColdReset from here.
1789 (sim_create_inferior): To here.
1790 (sim_open): Make FP check less dependant on host endianness.
1792 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1794 * interp.c (sim_set_callbacks): Delete.
1796 * interp.c (membank, membank_base, membank_size): Replace with
1797 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1798 (sim_open): Remove call to callback->init. gdb/run do this.
1802 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1804 * interp.c (big_endian_p): Delete, replaced by
1805 current_target_byte_order.
1807 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1809 * interp.c (host_read_long, host_read_word, host_swap_word,
1810 host_swap_long): Delete. Using common sim-endian.
1811 (sim_fetch_register, sim_store_register): Use H2T.
1812 (pipeline_ticks): Delete. Handled by sim-events.
1814 (sim_engine_run): Update.
1816 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1818 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1820 (SignalException): To here. Signal using sim_engine_halt.
1821 (sim_stop_reason): Delete, moved to common.
1823 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1825 * interp.c (sim_open): Add callback argument.
1826 (sim_set_callbacks): Delete SIM_DESC argument.
1829 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1831 * Makefile.in (SIM_OBJS): Add common modules.
1833 * interp.c (sim_set_callbacks): Also set SD callback.
1834 (set_endianness, xfer_*, swap_*): Delete.
1835 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1836 Change to functions using sim-endian macros.
1837 (control_c, sim_stop): Delete, use common version.
1838 (simulate): Convert into.
1839 (sim_engine_run): This function.
1840 (sim_resume): Delete.
1842 * interp.c (simulation): New variable - the simulator object.
1843 (sim_kind): Delete global - merged into simulation.
1844 (sim_load): Cleanup. Move PC assignment from here.
1845 (sim_create_inferior): To here.
1847 * sim-main.h: New file.
1848 * interp.c (sim-main.h): Include.
1850 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1852 * configure: Regenerated to track ../common/aclocal.m4 changes.
1854 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1856 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1858 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1860 * gencode.c (build_instruction): DIV instructions: check
1861 for division by zero and integer overflow before using
1862 host's division operation.
1864 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1866 * Makefile.in (SIM_OBJS): Add sim-load.o.
1867 * interp.c: #include bfd.h.
1868 (target_byte_order): Delete.
1869 (sim_kind, myname, big_endian_p): New static locals.
1870 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1871 after argument parsing. Recognize -E arg, set endianness accordingly.
1872 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1873 load file into simulator. Set PC from bfd.
1874 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1875 (set_endianness): Use big_endian_p instead of target_byte_order.
1877 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1879 * interp.c (sim_size): Delete prototype - conflicts with
1880 definition in remote-sim.h. Correct definition.
1882 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1884 * configure: Regenerated to track ../common/aclocal.m4 changes.
1887 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1889 * interp.c (sim_open): New arg `kind'.
1891 * configure: Regenerated to track ../common/aclocal.m4 changes.
1893 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1895 * configure: Regenerated to track ../common/aclocal.m4 changes.
1897 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1899 * interp.c (sim_open): Set optind to 0 before calling getopt.
1901 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1903 * configure: Regenerated to track ../common/aclocal.m4 changes.
1905 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1907 * interp.c : Replace uses of pr_addr with pr_uword64
1908 where the bit length is always 64 independent of SIM_ADDR.
1909 (pr_uword64) : added.
1911 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1913 * configure: Re-generate.
1915 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1917 * configure: Regenerate to track ../common/aclocal.m4 changes.
1919 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1921 * interp.c (sim_open): New SIM_DESC result. Argument is now
1923 (other sim_*): New SIM_DESC argument.
1925 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1927 * interp.c: Fix printing of addresses for non-64-bit targets.
1928 (pr_addr): Add function to print address based on size.
1930 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1932 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1934 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1936 * gencode.c (build_mips16_operands): Correct computation of base
1937 address for extended PC relative instruction.
1939 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1941 * interp.c (mips16_entry): Add support for floating point cases.
1942 (SignalException): Pass floating point cases to mips16_entry.
1943 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1945 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1947 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1948 and then set the state to fmt_uninterpreted.
1949 (COP_SW): Temporarily set the state to fmt_word while calling
1952 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1954 * gencode.c (build_instruction): The high order may be set in the
1955 comparison flags at any ISA level, not just ISA 4.
1957 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1959 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1960 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1961 * configure.in: sinclude ../common/aclocal.m4.
1962 * configure: Regenerated.
1964 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1966 * configure: Rebuild after change to aclocal.m4.
1968 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1970 * configure configure.in Makefile.in: Update to new configure
1971 scheme which is more compatible with WinGDB builds.
1972 * configure.in: Improve comment on how to run autoconf.
1973 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1974 * Makefile.in: Use autoconf substitution to install common
1977 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1979 * gencode.c (build_instruction): Use BigEndianCPU instead of
1982 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1984 * interp.c (sim_monitor): Make output to stdout visible in
1985 wingdb's I/O log window.
1987 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1989 * support.h: Undo previous change to SIGTRAP
1992 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1994 * interp.c (store_word, load_word): New static functions.
1995 (mips16_entry): New static function.
1996 (SignalException): Look for mips16 entry and exit instructions.
1997 (simulate): Use the correct index when setting fpr_state after
1998 doing a pending move.
2000 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2002 * interp.c: Fix byte-swapping code throughout to work on
2003 both little- and big-endian hosts.
2005 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2007 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2008 with gdb/config/i386/xm-windows.h.
2010 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2012 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2013 that messes up arithmetic shifts.
2015 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2017 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2018 SIGTRAP and SIGQUIT for _WIN32.
2020 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2022 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2023 force a 64 bit multiplication.
2024 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2025 destination register is 0, since that is the default mips16 nop
2028 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2030 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2031 (build_endian_shift): Don't check proc64.
2032 (build_instruction): Always set memval to uword64. Cast op2 to
2033 uword64 when shifting it left in memory instructions. Always use
2034 the same code for stores--don't special case proc64.
2036 * gencode.c (build_mips16_operands): Fix base PC value for PC
2038 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2040 * interp.c (simJALDELAYSLOT): Define.
2041 (JALDELAYSLOT): Define.
2042 (INDELAYSLOT, INJALDELAYSLOT): Define.
2043 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2045 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2047 * interp.c (sim_open): add flush_cache as a PMON routine
2048 (sim_monitor): handle flush_cache by ignoring it
2050 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2052 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2054 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2055 (BigEndianMem): Rename to ByteSwapMem and change sense.
2056 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2057 BigEndianMem references to !ByteSwapMem.
2058 (set_endianness): New function, with prototype.
2059 (sim_open): Call set_endianness.
2060 (sim_info): Use simBE instead of BigEndianMem.
2061 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2062 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2063 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2064 ifdefs, keeping the prototype declaration.
2065 (swap_word): Rewrite correctly.
2066 (ColdReset): Delete references to CONFIG. Delete endianness related
2067 code; moved to set_endianness.
2069 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2071 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2072 * interp.c (CHECKHILO): Define away.
2073 (simSIGINT): New macro.
2074 (membank_size): Increase from 1MB to 2MB.
2075 (control_c): New function.
2076 (sim_resume): Rename parameter signal to signal_number. Add local
2077 variable prev. Call signal before and after simulate.
2078 (sim_stop_reason): Add simSIGINT support.
2079 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2081 (sim_warning): Delete call to SignalException. Do call printf_filtered
2083 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2084 a call to sim_warning.
2086 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2088 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2089 16 bit instructions.
2091 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2093 Add support for mips16 (16 bit MIPS implementation):
2094 * gencode.c (inst_type): Add mips16 instruction encoding types.
2095 (GETDATASIZEINSN): Define.
2096 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2097 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2099 (MIPS16_DECODE): New table, for mips16 instructions.
2100 (bitmap_val): New static function.
2101 (struct mips16_op): Define.
2102 (mips16_op_table): New table, for mips16 operands.
2103 (build_mips16_operands): New static function.
2104 (process_instructions): If PC is odd, decode a mips16
2105 instruction. Break out instruction handling into new
2106 build_instruction function.
2107 (build_instruction): New static function, broken out of
2108 process_instructions. Check modifiers rather than flags for SHIFT
2109 bit count and m[ft]{hi,lo} direction.
2110 (usage): Pass program name to fprintf.
2111 (main): Remove unused variable this_option_optind. Change
2112 ``*loptarg++'' to ``loptarg++''.
2113 (my_strtoul): Parenthesize && within ||.
2114 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2115 (simulate): If PC is odd, fetch a 16 bit instruction, and
2116 increment PC by 2 rather than 4.
2117 * configure.in: Add case for mips16*-*-*.
2118 * configure: Rebuild.
2120 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2122 * interp.c: Allow -t to enable tracing in standalone simulator.
2123 Fix garbage output in trace file and error messages.
2125 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2127 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2128 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2129 * configure.in: Simplify using macros in ../common/aclocal.m4.
2130 * configure: Regenerated.
2131 * tconfig.in: New file.
2133 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2135 * interp.c: Fix bugs in 64-bit port.
2136 Use ansi function declarations for msvc compiler.
2137 Initialize and test file pointer in trace code.
2138 Prevent duplicate definition of LAST_EMED_REGNUM.
2140 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2142 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2144 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2146 * interp.c (SignalException): Check for explicit terminating
2148 * gencode.c: Pass instruction value through SignalException()
2149 calls for Trap, Breakpoint and Syscall.
2151 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2153 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2154 only used on those hosts that provide it.
2155 * configure.in: Add sqrt() to list of functions to be checked for.
2156 * config.in: Re-generated.
2157 * configure: Re-generated.
2159 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2161 * gencode.c (process_instructions): Call build_endian_shift when
2162 expanding STORE RIGHT, to fix swr.
2163 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2164 clear the high bits.
2165 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2166 Fix float to int conversions to produce signed values.
2168 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2170 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2171 (process_instructions): Correct handling of nor instruction.
2172 Correct shift count for 32 bit shift instructions. Correct sign
2173 extension for arithmetic shifts to not shift the number of bits in
2174 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2175 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2177 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2178 It's OK to have a mult follow a mult. What's not OK is to have a
2179 mult follow an mfhi.
2180 (Convert): Comment out incorrect rounding code.
2182 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2184 * interp.c (sim_monitor): Improved monitor printf
2185 simulation. Tidied up simulator warnings, and added "--log" option
2186 for directing warning message output.
2187 * gencode.c: Use sim_warning() rather than WARNING macro.
2189 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2191 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2192 getopt1.o, rather than on gencode.c. Link objects together.
2193 Don't link against -liberty.
2194 (gencode.o, getopt.o, getopt1.o): New targets.
2195 * gencode.c: Include <ctype.h> and "ansidecl.h".
2196 (AND): Undefine after including "ansidecl.h".
2197 (ULONG_MAX): Define if not defined.
2198 (OP_*): Don't define macros; now defined in opcode/mips.h.
2199 (main): Call my_strtoul rather than strtoul.
2200 (my_strtoul): New static function.
2202 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2204 * gencode.c (process_instructions): Generate word64 and uword64
2205 instead of `long long' and `unsigned long long' data types.
2206 * interp.c: #include sysdep.h to get signals, and define default
2208 * (Convert): Work around for Visual-C++ compiler bug with type
2210 * support.h: Make things compile under Visual-C++ by using
2211 __int64 instead of `long long'. Change many refs to long long
2212 into word64/uword64 typedefs.
2214 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2216 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2217 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2219 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2220 (AC_PROG_INSTALL): Added.
2221 (AC_PROG_CC): Moved to before configure.host call.
2222 * configure: Rebuilt.
2224 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2226 * configure.in: Define @SIMCONF@ depending on mips target.
2227 * configure: Rebuild.
2228 * Makefile.in (run): Add @SIMCONF@ to control simulator
2230 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2231 * interp.c: Remove some debugging, provide more detailed error
2232 messages, update memory accesses to use LOADDRMASK.
2234 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2236 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2237 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2239 * configure: Rebuild.
2240 * config.in: New file, generated by autoheader.
2241 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2242 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2243 HAVE_ANINT and HAVE_AINT, as appropriate.
2244 * Makefile.in (run): Use @LIBS@ rather than -lm.
2245 (interp.o): Depend upon config.h.
2246 (Makefile): Just rebuild Makefile.
2247 (clean): Remove stamp-h.
2248 (mostlyclean): Make the same as clean, not as distclean.
2249 (config.h, stamp-h): New targets.
2251 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2253 * interp.c (ColdReset): Fix boolean test. Make all simulator
2256 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2258 * interp.c (xfer_direct_word, xfer_direct_long,
2259 swap_direct_word, swap_direct_long, xfer_big_word,
2260 xfer_big_long, xfer_little_word, xfer_little_long,
2261 swap_word,swap_long): Added.
2262 * interp.c (ColdReset): Provide function indirection to
2263 host<->simulated_target transfer routines.
2264 * interp.c (sim_store_register, sim_fetch_register): Updated to
2265 make use of indirected transfer routines.
2267 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2269 * gencode.c (process_instructions): Ensure FP ABS instruction
2271 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2272 system call support.
2274 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2276 * interp.c (sim_do_command): Complain if callback structure not
2279 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2281 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2282 support for Sun hosts.
2283 * Makefile.in (gencode): Ensure the host compiler and libraries
2284 used for cross-hosted build.
2286 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2288 * interp.c, gencode.c: Some more (TODO) tidying.
2290 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2292 * gencode.c, interp.c: Replaced explicit long long references with
2293 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2294 * support.h (SET64LO, SET64HI): Macros added.
2296 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2298 * configure: Regenerate with autoconf 2.7.
2300 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2302 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2303 * support.h: Remove superfluous "1" from #if.
2304 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2306 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2308 * interp.c (StoreFPR): Control UndefinedResult() call on
2309 WARN_RESULT manifest.
2311 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2313 * gencode.c: Tidied instruction decoding, and added FP instruction
2316 * interp.c: Added dineroIII, and BSD profiling support. Also
2317 run-time FP handling.
2319 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2321 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2322 gencode.c, interp.c, support.h: created.
projects / deliverable / binutils-gdb.git / blob