2 Thu Sep 10 11:50:54 1998 Doug Evans <devans@canuck.cygnus.com>
4 * r5900.igen (plzcw): Make `i' signed.
6 Wed Sep 9 11:28:20 1998 Ron Unrau <runrau@cygnus.com>
8 * sim-main.h: track COP0 registers
9 * interp.c (sim_{fetch,store}_register): read/write COP0 registers
11 Fri Sep 4 10:37:57 1998 Frank Ch. Eigler <fche@cygnus.com>
13 * r5900.igen (mtsab): Correct typo in input register.
15 * sim-main.h (TMP_*): New macros for accessing local 128-bit
16 temporary for multimedia instructions.
17 * r5900.igen (*): Convert most instructions to use new TMP
18 macros to store output result during computation.
22 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
24 * dv-tx3904sio.c: Include sim-assert.h.
26 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
28 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
29 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
30 Reorganize target-specific sim-hardware checks.
32 * interp.c (sim_open): For tx39 target boards, set
33 OPERATING_ENVIRONMENT, add tx3904sio devices.
34 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
35 ROM executables. Install dv-sockser into sim-modules list.
37 * dv-tx3904irc.c: Compiler warning clean-up.
38 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
39 frequent hw-trace messages.
42 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
44 * vr.igen (MulAcc): Identify as a vr4100 specific function.
46 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
48 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
51 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
52 * mips.igen: Define vr4100 model. Include vr.igen.
54 * vr5400.igen: Move instructions to vr.igen
55 * Makefile.in (IGEN_INCLUDE): Remove vr5400.igen.
58 * vr4320.igen: Move instructions to vr.igen.
59 * Makefile.in (IGEN_INCLUDE): Remove vr5320.igen.
63 Tue Jul 14 16:10:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
65 * r5900.igen (r59fp_overflow): Replace argument ANS with argument
68 (r59fp_store): Update calls.
69 (DIV.S): Compute 0/0 sign from inputs. Ditto for X/0.
72 start-sanitize-branchbug4011
73 Mon Jun 29 09:31:27 1998 Gavin Koch <gavin@cygnus.com>
75 * interp.c (OPTION_BRANCH_BUG_4011): Add.
76 (mips_option_handler): Handle OPTION_BRANCH_BUG_4011.
77 (mips_options): Define the option.
78 * mips.igen (check_4011_branch_bug): New.
79 (mark_4011_branch_bug): New.
80 (all branch insn): Call mark_branch_bug, and check_branch_bug.
81 * sim-main.h (branchbug4011_option, branchbug4011_last_target,
82 branchbug4011_last_cia, BRANCHBUG4011_OPTION,
83 BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA,
84 check_branch_bug, mark_branch_bug): Define.
86 end-sanitize-branchbug4011
87 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
89 * mips.igen (check_mf_hilo): Correct check.
92 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
94 * sim-main.h (NR_COP0_GPR, COP0_GPR, cop0_gpr, NR_COP0_BP,
95 COP0_BP, cop0_bp, NR_COP0_P, COP0_P, cop0_p): Add 32 COP0 general
96 purpose registers, add 8 COP0 break-point registers, add 64 COP0
97 performance registers.
99 * interp.c (decode_coproc): Accept any MTC0/MFC0, MTBP/MFBP, MTP*
100 MFP* instructions. Just transfer value to/from corresponding
103 * r5900.igen (BC0F, BC0FL, BC0T, BC0TL): Implement, assume COP0
104 status is always true.
105 (CACHE, TLBP, TPGWI, TLBWR): Treat as NOP.
106 (EI, DI): Set/clear Status-EIE bit.
110 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
112 * mips.igen (BC0F, BC0FL, BC0T, BC0TL): Move to sky code to
116 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
119 * sky-vu.c (vu0_read_cop2_register, vu0_write_cop2_register): Call
121 * sky-gdb.c: Include "sim-assert.h".
124 * sim-main.h (interrupt_event): Add prototype.
126 start-sanitize-tx3904
127 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
128 register_ptr, register_value.
129 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
132 * sim-main.h (tracefh): Make extern.
134 start-sanitize-tx3904
135 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
137 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
138 Reduce unnecessarily high timer event frequency.
139 * dv-tx3904cpu.c: Ditto for interrupt event.
143 Tue Jun 16 14:12:09 1998 Frank Ch. Eigler <fche@cygnus.com>
145 * interp.c (decode_coproc): Removed COP2 branches.
146 * r5900.igen: Moved COP2 branch instructions here.
147 * mips.igen: Restricted COPz == COP2 bit pattern to
148 exclude COP2 branches.
151 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
153 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
155 (interrupt_event): Made non-static.
156 start-sanitize-tx3904
158 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
159 interchange of configuration values for external vs. internal
163 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
165 * mips.igen (BREAK): Moved code to here for
166 simulator-reserved break instructions.
167 * gencode.c (build_instruction): Ditto.
168 * interp.c (signal_exception): Code moved from here. Non-
169 reserved instructions now use exception vector, rather
171 * sim-main.h: Moved magic constants to here.
173 start-sanitize-tx3904
174 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
176 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
177 register upon non-zero interrupt event level, clear upon zero
179 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
180 by passing zero event value.
181 (*_io_{read,write}_buffer): Endianness fixes.
182 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
183 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
185 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
186 serial I/O and timer module at base address 0xFFFF0000.
189 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
191 * mips.igen (SWC1) : Correct the handling of ReverseEndian
194 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
196 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
200 start-sanitize-tx3904
201 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
203 * dv-tx3904tmr.c: New file - implements tx3904 timer.
204 * dv-tx3904{irc,cpu}.c: Mild reformatting.
205 * configure.in: Include tx3904tmr in hw_device list.
206 * configure: Rebuilt.
207 * interp.c (sim_open): Instantiate three timer instances.
208 Fix address typo of tx3904irc instance.
212 Thu Jun 4 16:47:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
214 * mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO.
215 Select corresponding check_mt_hilo function.
216 (check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo):
219 * r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark
223 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
225 * interp.c (signal_exception): SystemCall exception now uses
226 the exception vector.
228 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
230 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
234 Mon Jun 1 10:28:25 1998 Jeffrey A Law (law@cygnus.com)
236 * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1.
240 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
242 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
244 start-sanitize-tx3904
245 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
247 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
249 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
250 sim-main.h. Declare a struct hw_descriptor instead of struct
251 hw_device_descriptor.
254 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
256 * mips.igen (do_store_left, do_load_left): Compute nr of left and
257 right bits and then re-align left hand bytes to correct byte
258 lanes. Fix incorrect computation in do_store_left when loading
259 bytes from second word.
261 start-sanitize-tx3904
262 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
264 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
265 * interp.c (sim_open): Only create a device tree when HW is
268 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
269 * interp.c (signal_exception): Ditto.
272 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
274 * gencode.c: Mark BEGEZALL as LIKELY.
276 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
278 * sim-main.h (ALU32_END): Sign extend 32 bit results.
279 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
282 Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
284 * interp.c (sim_fetch_register): Convert internal r5900 regs to
288 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
290 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
291 modules. Recognize TX39 target with "mips*tx39" pattern.
292 * configure: Rebuilt.
293 * sim-main.h (*): Added many macros defining bits in
294 TX39 control registers.
295 (SignalInterrupt): Send actual PC instead of NULL.
296 (SignalNMIReset): New exception type.
297 * interp.c (board): New variable for future use to identify
298 a particular board being simulated.
299 (mips_option_handler,mips_options): Added "--board" option.
300 (interrupt_event): Send actual PC.
301 (sim_open): Make memory layout conditional on board setting.
302 (signal_exception): Initial implementation of hardware interrupt
303 handling. Accept another break instruction variant for simulator
305 (decode_coproc): Implement RFE instruction for TX39.
306 (mips.igen): Decode RFE instruction as such.
307 start-sanitize-tx3904
308 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
309 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
310 bbegin to implement memory map.
311 * dv-tx3904cpu.c: New file.
312 * dv-tx3904irc.c: New file.
315 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
317 * mips.igen (check_mt_hilo): Create a separate r3900 version.
320 Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
322 * r5900.igen: Replace the calls and the definition of the
323 function check_op_hilo_hi1lo1 with the pair
324 check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
327 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
329 * tx.igen (madd,maddu): Replace calls to check_op_hilo
330 with calls to check_div_hilo.
332 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
334 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
335 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
336 Add special r3900 version of do_mult_hilo.
337 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
338 with calls to check_mult_hilo.
339 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
340 with calls to check_div_hilo.
342 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
344 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
345 Document a replacement.
347 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
349 * interp.c (sim_monitor): Make mon_printf work.
351 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
353 * sim-main.h (INSN_NAME): New arg `cpu'.
356 Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com>
358 * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
363 Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
365 * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
366 * r5900.igen (r59fp_overflow): Use.
368 * r5900.igen (r59fp_op3): Rename to
369 (r59fp_mula): This, delete opm argument.
370 (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
371 (r59fp_mula): Overflowing product propogates through to result.
372 (r59fp_mula): ACC to the MAX propogates to result.
373 (r59fp_mula): Underflow during multiply only sets SU.
376 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
378 * configure: Regenerated to track ../common/aclocal.m4 changes.
380 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
382 * configure: Regenerated to track ../common/aclocal.m4 changes.
385 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
387 * acconfig.h: New file.
388 * configure.in: Reverted change of Apr 24; use sinclude again.
390 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
392 * configure: Regenerated to track ../common/aclocal.m4 changes.
395 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
397 * configure.in: Don't call sinclude.
399 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
401 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
403 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
405 * mips.igen (ERET): Implement.
407 * interp.c (decode_coproc): Return sign-extended EPC.
409 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
411 * interp.c (signal_exception): Do not ignore Trap.
412 (signal_exception): On TRAP, restart at exception address.
413 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
414 (signal_exception): Update.
415 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
416 so that TRAP instructions are caught.
418 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
420 * sim-main.h (struct hilo_access, struct hilo_history): Define,
421 contains HI/LO access history.
422 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
423 (HIACCESS, LOACCESS): Delete, replace with
424 (HIHISTORY, LOHISTORY): New macros.
425 (start-sanitize-r5900):
426 (struct sim_5900_cpu): Make hi1access, lo1access of type
428 (HI1ACCESS, LO1ACCESS): Delete, replace with
429 (HI1HISTORY, LO1HISTORY): New macros.
430 (end-sanitize-r5900):
431 (CHECKHILO): Delete all, moved to mips.igen
433 * gencode.c (build_instruction): Do not generate checks for
434 correct HI/LO register usage.
436 * interp.c (old_engine_run): Delete checks for correct HI/LO
439 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
440 check_mf_cycles): New functions.
441 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
442 do_divu, domultx, do_mult, do_multu): Use.
444 * tx.igen ("madd", "maddu"): Use.
445 (start-sanitize-r5900):
447 r5900.igen: Update all HI/LO checks.
448 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
449 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
450 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
451 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
452 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
454 (end-sanitize-r5900):
457 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
459 * interp.c (decode_coproc): Correct CMFC2/QMTC2
462 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
463 instead of a single 128-bit access.
467 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
469 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
470 * interp.c (cop_[ls]q): Fixes corresponding to above.
474 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
476 * interp.c (decode_coproc): Adapt COP2 micro interlock to
477 clarified specs. Reset "M" bit; exit also on "E" bit.
481 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
483 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
484 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
486 * r5900.igen (r59fp_unpack): New function.
487 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
488 RSQRT.S, SQRT.S): Use.
489 (r59fp_zero): New function.
490 (r59fp_overflow): Generate r5900 specific overflow value.
491 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
493 (CVT.S.W, CVT.W.S): Exchange implementations.
495 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
499 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
501 * configure.in (tx19, sim_use_gen): Switch to igen.
502 * configure: Re-build.
506 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
508 * interp.c (decode_coproc): Make COP2 branch code compile after
509 igen signature changes.
512 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
514 * mips.igen (DSRAV): Use function do_dsrav.
515 (SRAV): Use new function do_srav.
517 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
518 (B): Sign extend 11 bit immediate.
519 (EXT-B*): Shift 16 bit immediate left by 1.
520 (ADDIU*): Don't sign extend immediate value.
522 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
524 * m16run.c (sim_engine_run): Restore CIA after handling an event.
527 * mips.igen (mtc0): Valid tx19 instruction.
530 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
533 * mips.igen (delayslot32, nullify_next_insn): New functions.
534 (m16.igen): Always include.
535 (do_*): Add more tracing.
537 * m16.igen (delayslot16): Add NIA argument, could be called by a
538 32 bit MIPS16 instruction.
540 * interp.c (ifetch16): Move function from here.
541 * sim-main.c (ifetch16): To here.
543 * sim-main.c (ifetch16, ifetch32): Update to match current
544 implementations of LH, LW.
545 (signal_exception): Don't print out incorrect hex value of illegal
548 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
550 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
553 * m16.igen: Implement MIPS16 instructions.
555 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
556 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
557 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
558 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
559 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
560 bodies of corresponding code from 32 bit insn to these. Also used
561 by MIPS16 versions of functions.
563 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
564 (IMEM16): Drop NR argument from macro.
567 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
569 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
570 of VU lower instruction.
574 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
576 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
579 * sim-main.h: Removed attempt at allowing 128-bit access.
583 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
585 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
587 * interp.c (decode_coproc): Refer to VU CIA as a "special"
588 register, not as a "misc" register. Aha. Add activity
589 assertions after VCALLMS* instructions.
593 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
595 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
596 to upper code of generated VU instruction.
600 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
602 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
604 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
607 * r5900.igen (SQC2): Thinko.
611 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
613 * interp.c (*): Adapt code to merged VU device & state structs.
614 (decode_coproc): Execute COP2 each macroinstruction without
615 pipelining, by stepping VU to completion state. Adapted to
616 read_vu_*_reg style of register access.
618 * mips.igen ([SL]QC2): Removed these COP2 instructions.
620 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
622 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
625 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
627 * Makefile.in (SIM_OBJS): Add sim-main.o.
629 * sim-main.h (address_translation, load_memory, store_memory,
630 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
632 (pr_addr, pr_uword64): Declare.
633 (sim-main.c): Include when H_REVEALS_MODULE_P.
635 * interp.c (address_translation, load_memory, store_memory,
636 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
638 * sim-main.c: To here. Fix compilation problems.
640 * configure.in: Enable inlining.
641 * configure: Re-config.
643 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
645 * configure: Regenerated to track ../common/aclocal.m4 changes.
647 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
649 * mips.igen: Include tx.igen.
650 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
651 * tx.igen: New file, contains MADD and MADDU.
653 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
654 the hardwired constant `7'.
655 (store_memory): Ditto.
656 (LOADDRMASK): Move definition to sim-main.h.
658 mips.igen (MTC0): Enable for r3900.
661 mips.igen (do_load_byte): Delete.
662 (do_load, do_store, do_load_left, do_load_write, do_store_left,
663 do_store_right): New functions.
664 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
666 configure.in: Let the tx39 use igen again.
669 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
671 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
672 not an address sized quantity. Return zero for cache sizes.
674 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
676 * mips.igen (r3900): r3900 does not support 64 bit integer
680 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
682 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
686 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
688 * interp.c (decode_coproc): Continuing COP2 work.
689 (cop_[ls]q): Make sky-target-only.
691 * sim-main.h (COP_[LS]Q): Make sky-target-only.
693 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
695 * configure.in (mipstx39*-*-*): Use gencode simulator rather
697 * configure : Rebuild.
700 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
702 * interp.c (decode_coproc): Added a missing TARGET_SKY check
703 around COP2 implementation skeleton.
707 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
709 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
711 * interp.c (sim_{load,store}_register): Use new vu[01]_device
712 static to access VU registers.
713 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
714 decoding. Work in progress.
716 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
717 overlapping/redundant bit pattern.
718 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
721 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
724 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
725 access to coprocessor registers.
727 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
729 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
731 * configure: Regenerated to track ../common/aclocal.m4 changes.
733 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
735 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
737 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
739 * configure: Regenerated to track ../common/aclocal.m4 changes.
740 * config.in: Regenerated to track ../common/aclocal.m4 changes.
742 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
744 * configure: Regenerated to track ../common/aclocal.m4 changes.
746 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
748 * interp.c (Max, Min): Comment out functions. Not yet used.
750 start-sanitize-vr4320
751 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
753 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
756 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
758 * configure: Regenerated to track ../common/aclocal.m4 changes.
760 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
762 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
763 configurable settings for stand-alone simulator.
766 * configure.in: Added --with-sim-gpu2 option to specify path of
767 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
768 links/compiles stand-alone simulator with this library.
770 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
772 * configure.in: Added X11 search, just in case.
774 * configure: Regenerated.
776 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
778 * interp.c (sim_write, sim_read, load_memory, store_memory):
779 Replace sim_core_*_map with read_map, write_map, exec_map resp.
781 start-sanitize-vr4320
782 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
784 * vr4320.igen (clz,dclz) : Added.
785 (dmac): Replaced 99, with LO.
788 start-sanitize-cygnus
789 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
791 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
794 start-sanitize-vr4320
795 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
797 * vr4320.igen: New file.
798 * Makefile.in (vr4320.igen) : Added.
799 * configure.in (mips64vr4320-*-*): Added.
800 * configure : Rebuilt.
801 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
802 Add the vr4320 model entry and mark the vr4320 insn as necessary.
805 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
807 * sim-main.h (GETFCC): Return an unsigned value.
810 * r5900.igen: Use an unsigned array index variable `i'.
811 (QFSRV): Ditto for variable bytes.
814 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
816 * mips.igen (DIV): Fix check for -1 / MIN_INT.
817 (DADD): Result destination is RD not RT.
820 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
821 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
825 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
827 * sim-main.h (HIACCESS, LOACCESS): Always define.
829 * mdmx.igen (Maxi, Mini): Rename Max, Min.
831 * interp.c (sim_info): Delete.
833 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
835 * interp.c (DECLARE_OPTION_HANDLER): Use it.
836 (mips_option_handler): New argument `cpu'.
837 (sim_open): Update call to sim_add_option_table.
839 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
841 * mips.igen (CxC1): Add tracing.
844 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
846 * r5900.igen (StoreFP): Delete.
847 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
849 (rsqrt.s, sqrt.s): Implement.
850 (r59cond): New function.
851 (C.COND.S): Call r59cond in assembler line.
852 (cvt.w.s, cvt.s.w): Implement.
854 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
857 * sim-main.h: Define an enum of r5900 FCSR bit fields.
861 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
863 * r5900.igen: Add tracing to all p* instructions.
865 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
867 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
868 to get gdb talking to re-aranged sim_cpu register structure.
871 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
873 * sim-main.h (Max, Min): Declare.
875 * interp.c (Max, Min): New functions.
877 * mips.igen (BC1): Add tracing.
879 start-sanitize-cygnus
880 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
882 * mdmx.igen: Tag all functions as requiring either with mdmx or
887 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
889 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
891 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
893 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
895 * r5900.igen: Rewrite.
897 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
899 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
900 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
903 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
905 * interp.c Added memory map for stack in vr4100
907 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
909 * interp.c (load_memory): Add missing "break"'s.
911 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
913 * interp.c (sim_store_register, sim_fetch_register): Pass in
914 length parameter. Return -1.
916 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
918 * interp.c: Added hardware init hook, fixed warnings.
920 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
922 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
924 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
926 * interp.c (ifetch16): New function.
928 * sim-main.h (IMEM32): Rename IMEM.
929 (IMEM16_IMMED): Define.
931 (DELAY_SLOT): Update.
933 * m16run.c (sim_engine_run): New file.
935 * m16.igen: All instructions except LB.
936 (LB): Call do_load_byte.
937 * mips.igen (do_load_byte): New function.
938 (LB): Call do_load_byte.
940 * mips.igen: Move spec for insn bit size and high bit from here.
941 * Makefile.in (tmp-igen, tmp-m16): To here.
943 * m16.dc: New file, decode mips16 instructions.
945 * Makefile.in (SIM_NO_ALL): Define.
946 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
949 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
953 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
955 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
956 point unit to 32 bit registers.
957 * configure: Re-generate.
959 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
961 * configure.in (sim_use_gen): Make IGEN the default simulator
962 generator for generic 32 and 64 bit mips targets.
963 * configure: Re-generate.
965 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
967 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
970 * interp.c (sim_fetch_register, sim_store_register): Read/write
971 FGR from correct location.
972 (sim_open): Set size of FGR's according to
973 WITH_TARGET_FLOATING_POINT_BITSIZE.
975 * sim-main.h (FGR): Store floating point registers in a separate
978 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
980 * configure: Regenerated to track ../common/aclocal.m4 changes.
982 start-sanitize-cygnus
983 * mdmx.igen: Mark all instructions as 64bit/fp specific.
986 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
988 * interp.c (ColdReset): Call PENDING_INVALIDATE.
990 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
992 * interp.c (pending_tick): New function. Deliver pending writes.
994 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
995 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
996 it can handle mixed sized quantites and single bits.
998 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1000 * interp.c (oengine.h): Do not include when building with IGEN.
1001 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1002 (sim_info): Ditto for PROCESSOR_64BIT.
1003 (sim_monitor): Replace ut_reg with unsigned_word.
1004 (*): Ditto for t_reg.
1005 (LOADDRMASK): Define.
1006 (sim_open): Remove defunct check that host FP is IEEE compliant,
1007 using software to emulate floating point.
1008 (value_fpr, ...): Always compile, was conditional on HASFPU.
1010 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1012 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1015 * interp.c (SD, CPU): Define.
1016 (mips_option_handler): Set flags in each CPU.
1017 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1018 (sim_close): Do not clear STATE, deleted anyway.
1019 (sim_write, sim_read): Assume CPU zero's vm should be used for
1021 (sim_create_inferior): Set the PC for all processors.
1022 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1024 (mips16_entry): Pass correct nr of args to store_word, load_word.
1025 (ColdReset): Cold reset all cpu's.
1026 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1027 (sim_monitor, load_memory, store_memory, signal_exception): Use
1028 `CPU' instead of STATE_CPU.
1031 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1034 * sim-main.h (signal_exception): Add sim_cpu arg.
1035 (SignalException*): Pass both SD and CPU to signal_exception.
1036 * interp.c (signal_exception): Update.
1038 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1040 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1041 address_translation): Ditto
1042 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1044 start-sanitize-cygnus
1045 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
1047 (ByteAlign): Use StoreFPR, pass args in correct order.
1050 start-sanitize-r5900
1051 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1053 * configure.in (sim_igen_filter): For r5900, configure as SMP.
1056 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1058 * configure: Regenerated to track ../common/aclocal.m4 changes.
1060 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1062 start-sanitize-r5900
1063 * configure.in (sim_igen_filter): For r5900, use igen.
1064 * configure: Re-generate.
1067 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1069 * mips.igen (model): Map processor names onto BFD name.
1071 * sim-main.h (CPU_CIA): Delete.
1072 (SET_CIA, GET_CIA): Define
1074 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1076 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1079 * configure.in (default_endian): Configure a big-endian simulator
1081 * configure: Re-generate.
1083 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1085 * configure: Regenerated to track ../common/aclocal.m4 changes.
1087 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1089 * interp.c (sim_monitor): Handle Densan monitor outbyte
1090 and inbyte functions.
1092 1997-12-29 Felix Lee <flee@cygnus.com>
1094 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1096 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1098 * Makefile.in (tmp-igen): Arrange for $zero to always be
1099 reset to zero after every instruction.
1101 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1103 * configure: Regenerated to track ../common/aclocal.m4 changes.
1106 start-sanitize-cygnus
1107 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1109 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
1112 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
1114 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
1115 vr5400 with the vr5000 as the default.
1118 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1120 * mips.igen (MSUB): Fix to work like MADD.
1121 * gencode.c (MSUB): Similarly.
1123 start-sanitize-cygnus
1124 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
1126 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
1130 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1132 * configure: Regenerated to track ../common/aclocal.m4 changes.
1134 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1136 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1138 start-sanitize-cygnus
1139 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
1140 (value_cc, store_cc): Implement.
1142 * sim-main.h: Add 8*3*8 bit accumulator.
1144 * vr5400.igen: Move mdmx instructins from here
1145 * mdmx.igen: To here - new file. Add/fix missing instructions.
1146 * mips.igen: Include mdmx.igen.
1147 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1150 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1152 * sim-main.h (sim-fpu.h): Include.
1154 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1155 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1156 using host independant sim_fpu module.
1158 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1160 * interp.c (signal_exception): Report internal errors with SIGABRT
1163 * sim-main.h (C0_CONFIG): New register.
1164 (signal.h): No longer include.
1166 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1168 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1170 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1172 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1174 * mips.igen: Tag vr5000 instructions.
1175 (ANDI): Was missing mipsIV model, fix assembler syntax.
1176 (do_c_cond_fmt): New function.
1177 (C.cond.fmt): Handle mips I-III which do not support CC field
1179 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1180 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1182 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1183 vr5000 which saves LO in a GPR separatly.
1185 * configure.in (enable-sim-igen): For vr5000, select vr5000
1186 specific instructions.
1187 * configure: Re-generate.
1189 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1191 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1193 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1194 fmt_uninterpreted_64 bit cases to switch. Convert to
1197 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1199 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1200 as specified in IV3.2 spec.
1201 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1203 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1205 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1206 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1207 (start-sanitize-r5900):
1208 (LWXC1, SWXC1): Delete from r5900 instruction set.
1209 (end-sanitize-r5900):
1210 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1211 PENDING_FILL versions of instructions. Simplify.
1213 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1215 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1217 (MTHI, MFHI): Disable code checking HI-LO.
1219 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1221 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1223 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1225 * gencode.c (build_mips16_operands): Replace IPC with cia.
1227 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1228 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1230 (UndefinedResult): Replace function with macro/function
1232 (sim_engine_run): Don't save PC in IPC.
1234 * sim-main.h (IPC): Delete.
1236 start-sanitize-cygnus
1237 * vr5400.igen (vr): Add missing cia argument to value_fpr.
1238 (do_select): Rename function select.
1241 * interp.c (signal_exception, store_word, load_word,
1242 address_translation, load_memory, store_memory, cache_op,
1243 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1244 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1245 current instruction address - cia - argument.
1246 (sim_read, sim_write): Call address_translation directly.
1247 (sim_engine_run): Rename variable vaddr to cia.
1248 (signal_exception): Pass cia to sim_monitor
1250 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1251 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1252 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1254 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1255 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1258 * interp.c (signal_exception): Pass restart address to
1261 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1262 idecode.o): Add dependency.
1264 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1266 (DELAY_SLOT): Update NIA not PC with branch address.
1267 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1269 * mips.igen: Use CIA not PC in branch calculations.
1270 (illegal): Call SignalException.
1271 (BEQ, ADDIU): Fix assembler.
1273 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1275 * m16.igen (JALX): Was missing.
1277 * configure.in (enable-sim-igen): New configuration option.
1278 * configure: Re-generate.
1280 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1282 * interp.c (load_memory, store_memory): Delete parameter RAW.
1283 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1284 bypassing {load,store}_memory.
1286 * sim-main.h (ByteSwapMem): Delete definition.
1288 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1290 * interp.c (sim_do_command, sim_commands): Delete mips specific
1291 commands. Handled by module sim-options.
1293 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1294 (WITH_MODULO_MEMORY): Define.
1296 * interp.c (sim_info): Delete code printing memory size.
1298 * interp.c (mips_size): Nee sim_size, delete function.
1300 (monitor, monitor_base, monitor_size): Delete global variables.
1301 (sim_open, sim_close): Delete code creating monitor and other
1302 memory regions. Use sim-memopts module, via sim_do_commandf, to
1303 manage memory regions.
1304 (load_memory, store_memory): Use sim-core for memory model.
1306 * interp.c (address_translation): Delete all memory map code
1307 except line forcing 32 bit addresses.
1309 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1311 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1314 * interp.c (logfh, logfile): Delete globals.
1315 (sim_open, sim_close): Delete code opening & closing log file.
1316 (mips_option_handler): Delete -l and -n options.
1317 (OPTION mips_options): Ditto.
1319 * interp.c (OPTION mips_options): Rename option trace to dinero.
1320 (mips_option_handler): Update.
1322 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1324 * interp.c (fetch_str): New function.
1325 (sim_monitor): Rewrite using sim_read & sim_write.
1326 (sim_open): Check magic number.
1327 (sim_open): Write monitor vectors into memory using sim_write.
1328 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1329 (sim_read, sim_write): Simplify - transfer data one byte at a
1331 (load_memory, store_memory): Clarify meaning of parameter RAW.
1333 * sim-main.h (isHOST): Defete definition.
1334 (isTARGET): Mark as depreciated.
1335 (address_translation): Delete parameter HOST.
1337 * interp.c (address_translation): Delete parameter HOST.
1340 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
1342 * gencode.c: Add tx49 configury and insns.
1343 * configure.in: Add tx49 configury.
1344 * configure: Update.
1347 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1351 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1352 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1354 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1356 * mips.igen: Add model filter field to records.
1358 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1360 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1362 interp.c (sim_engine_run): Do not compile function sim_engine_run
1363 when WITH_IGEN == 1.
1365 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1366 target architecture.
1368 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1369 igen. Replace with configuration variables sim_igen_flags /
1372 start-sanitize-r5900
1373 * r5900.igen: New file. Copy r5900 insns here.
1375 start-sanitize-cygnus
1376 * vr5400.igen: New file.
1378 * m16.igen: New file. Copy mips16 insns here.
1379 * mips.igen: From here.
1381 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1383 start-sanitize-cygnus
1384 * mips.igen: Tag all mipsIV instructions with vr5400 model.
1386 * configure.in: Add mips64vr5400 target.
1387 * configure: Re-generate.
1390 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1392 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1394 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1396 * gencode.c (build_instruction): Follow sim_write's lead in using
1397 BigEndianMem instead of !ByteSwapMem.
1399 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1401 * configure.in (sim_gen): Dependent on target, select type of
1402 generator. Always select old style generator.
1404 configure: Re-generate.
1406 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1408 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1409 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1410 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1411 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1412 SIM_@sim_gen@_*, set by autoconf.
1414 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1416 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1418 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1419 CURRENT_FLOATING_POINT instead.
1421 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1422 (address_translation): Raise exception InstructionFetch when
1423 translation fails and isINSTRUCTION.
1425 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1426 sim_engine_run): Change type of of vaddr and paddr to
1428 (address_translation, prefetch, load_memory, store_memory,
1429 cache_op): Change type of vAddr and pAddr to address_word.
1431 * gencode.c (build_instruction): Change type of vaddr and paddr to
1434 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1436 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1437 macro to obtain result of ALU op.
1439 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1441 * interp.c (sim_info): Call profile_print.
1443 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1445 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1447 * sim-main.h (WITH_PROFILE): Do not define, defined in
1448 common/sim-config.h. Use sim-profile module.
1449 (simPROFILE): Delete defintion.
1451 * interp.c (PROFILE): Delete definition.
1452 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1453 (sim_close): Delete code writing profile histogram.
1454 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1456 (sim_engine_run): Delete code profiling the PC.
1458 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1460 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1462 * interp.c (sim_monitor): Make register pointers of type
1465 * sim-main.h: Make registers of type unsigned_word not
1468 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1470 start-sanitize-r5900
1471 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1472 ...): Move to sim-main.h
1475 * interp.c (sync_operation): Rename from SyncOperation, make
1476 global, add SD argument.
1477 (prefetch): Rename from Prefetch, make global, add SD argument.
1478 (decode_coproc): Make global.
1480 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1482 * gencode.c (build_instruction): Generate DecodeCoproc not
1483 decode_coproc calls.
1485 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1486 (SizeFGR): Move to sim-main.h
1487 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1488 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1489 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1491 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1492 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1493 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1494 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1495 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1496 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1498 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1500 (sim-alu.h): Include.
1501 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1502 (sim_cia): Typedef to instruction_address.
1504 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1506 * Makefile.in (interp.o): Rename generated file engine.c to
1511 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1513 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1515 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1517 * gencode.c (build_instruction): For "FPSQRT", output correct
1518 number of arguments to Recip.
1520 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1522 * Makefile.in (interp.o): Depends on sim-main.h
1524 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1526 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1527 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1528 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1529 STATE, DSSTATE): Define
1530 (GPR, FGRIDX, ..): Define.
1532 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1533 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1534 (GPR, FGRIDX, ...): Delete macros.
1536 * interp.c: Update names to match defines from sim-main.h
1538 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1540 * interp.c (sim_monitor): Add SD argument.
1541 (sim_warning): Delete. Replace calls with calls to
1543 (sim_error): Delete. Replace calls with sim_io_error.
1544 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1545 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1546 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1548 (mips_size): Rename from sim_size. Add SD argument.
1550 * interp.c (simulator): Delete global variable.
1551 (callback): Delete global variable.
1552 (mips_option_handler, sim_open, sim_write, sim_read,
1553 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1554 sim_size,sim_monitor): Use sim_io_* not callback->*.
1555 (sim_open): ZALLOC simulator struct.
1556 (PROFILE): Do not define.
1558 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1560 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1561 support.h with corresponding code.
1563 * sim-main.h (word64, uword64), support.h: Move definition to
1565 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1568 * Makefile.in: Update dependencies
1569 * interp.c: Do not include.
1571 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1573 * interp.c (address_translation, load_memory, store_memory,
1574 cache_op): Rename to from AddressTranslation et.al., make global,
1577 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1580 * interp.c (SignalException): Rename to signal_exception, make
1583 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1585 * sim-main.h (SignalException, SignalExceptionInterrupt,
1586 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1587 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1588 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1591 * interp.c, support.h: Use.
1593 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1595 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1596 to value_fpr / store_fpr. Add SD argument.
1597 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1598 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1600 * sim-main.h (ValueFPR, StoreFPR): Define.
1602 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1604 * interp.c (sim_engine_run): Check consistency between configure
1605 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1608 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1609 (mips_fpu): Configure WITH_FLOATING_POINT.
1610 (mips_endian): Configure WITH_TARGET_ENDIAN.
1611 * configure: Update.
1613 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1615 * configure: Regenerated to track ../common/aclocal.m4 changes.
1617 start-sanitize-r5900
1618 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1620 * interp.c (MAX_REG): Allow up-to 128 registers.
1621 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1622 (REGISTER_SA): Ditto.
1623 (sim_open): Initialize register_widths for r5900 specific
1625 (sim_fetch_register, sim_store_register): Check for request of
1626 r5900 specific SA register. Check for request for hi 64 bits of
1627 r5900 specific registers.
1630 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1632 * configure: Regenerated.
1634 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1636 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1638 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1640 * gencode.c (print_igen_insn_models): Assume certain architectures
1641 include all mips* instructions.
1642 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1645 * Makefile.in (tmp.igen): Add target. Generate igen input from
1648 * gencode.c (FEATURE_IGEN): Define.
1649 (main): Add --igen option. Generate output in igen format.
1650 (process_instructions): Format output according to igen option.
1651 (print_igen_insn_format): New function.
1652 (print_igen_insn_models): New function.
1653 (process_instructions): Only issue warnings and ignore
1654 instructions when no FEATURE_IGEN.
1656 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1658 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1661 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1663 * configure: Regenerated to track ../common/aclocal.m4 changes.
1665 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1667 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1668 SIM_RESERVED_BITS): Delete, moved to common.
1669 (SIM_EXTRA_CFLAGS): Update.
1671 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1673 * configure.in: Configure non-strict memory alignment.
1674 * configure: Regenerated to track ../common/aclocal.m4 changes.
1676 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1678 * configure: Regenerated to track ../common/aclocal.m4 changes.
1680 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1682 * gencode.c (SDBBP,DERET): Added (3900) insns.
1683 (RFE): Turn on for 3900.
1684 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1685 (dsstate): Made global.
1686 (SUBTARGET_R3900): Added.
1687 (CANCELDELAYSLOT): New.
1688 (SignalException): Ignore SystemCall rather than ignore and
1689 terminate. Add DebugBreakPoint handling.
1690 (decode_coproc): New insns RFE, DERET; and new registers Debug
1691 and DEPC protected by SUBTARGET_R3900.
1692 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1694 * Makefile.in,configure.in: Add mips subtarget option.
1695 * configure: Update.
1697 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1699 * gencode.c: Add r3900 (tx39).
1702 * gencode.c: Fix some configuration problems by improving
1703 the relationship between tx19 and tx39.
1706 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1708 * gencode.c (build_instruction): Don't need to subtract 4 for
1711 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1713 * interp.c: Correct some HASFPU problems.
1715 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1717 * configure: Regenerated to track ../common/aclocal.m4 changes.
1719 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1721 * interp.c (mips_options): Fix samples option short form, should
1724 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1726 * interp.c (sim_info): Enable info code. Was just returning.
1728 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1730 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1733 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1735 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1737 (build_instruction): Ditto for LL.
1740 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1742 * mips/configure.in, mips/gencode: Add tx19/r1900.
1745 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1747 * configure: Regenerated to track ../common/aclocal.m4 changes.
1749 start-sanitize-r5900
1750 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1752 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1753 for overflow due to ABS of MININT, set result to MAXINT.
1754 (build_instruction): For "psrlvw", signextend bit 31.
1757 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1759 * configure: Regenerated to track ../common/aclocal.m4 changes.
1762 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1764 * interp.c (sim_open): Add call to sim_analyze_program, update
1767 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1769 * interp.c (sim_kill): Delete.
1770 (sim_create_inferior): Add ABFD argument. Set PC from same.
1771 (sim_load): Move code initializing trap handlers from here.
1772 (sim_open): To here.
1773 (sim_load): Delete, use sim-hload.c.
1775 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1777 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1779 * configure: Regenerated to track ../common/aclocal.m4 changes.
1782 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1784 * interp.c (sim_open): Add ABFD argument.
1785 (sim_load): Move call to sim_config from here.
1786 (sim_open): To here. Check return status.
1788 start-sanitize-r5900
1789 * gencode.c (build_instruction): Do not define x8000000000000000,
1790 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1793 start-sanitize-r5900
1794 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1796 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1797 "pdivuw" check for overflow due to signed divide by -1.
1800 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1802 * gencode.c (build_instruction): Two arg MADD should
1803 not assign result to $0.
1805 start-sanitize-r5900
1806 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1808 * gencode.c (build_instruction): For "ppac5" use unsigned
1809 arrithmetic so that the sign bit doesn't smear when right shifted.
1810 (build_instruction): For "pdiv" perform sign extension when
1811 storing results in HI and LO.
1812 (build_instructions): For "pdiv" and "pdivbw" check for
1814 (build_instruction): For "pmfhl.slw" update hi part of dest
1815 register as well as low part.
1816 (build_instruction): For "pmfhl" portably handle long long values.
1817 (build_instruction): For "pmfhl.sh" correctly negative values.
1818 Store half words 2 and three in the correct place.
1819 (build_instruction): For "psllvw", sign extend value after shift.
1822 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1824 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1825 * sim/mips/configure.in: Regenerate.
1827 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1829 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1830 signed8, unsigned8 et.al. types.
1832 start-sanitize-r5900
1833 * gencode.c (build_instruction): For PMULTU* do not sign extend
1834 registers. Make generated code easier to debug.
1837 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1838 hosts when selecting subreg.
1840 start-sanitize-r5900
1841 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1843 * gencode.c (type_for_data_len): For 32bit operations concerned
1844 with overflow, perform op using 64bits.
1845 (build_instruction): For PADD, always compute operation using type
1846 returned by type_for_data_len.
1847 (build_instruction): For PSUBU, when overflow, saturate to zero as
1851 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1853 start-sanitize-r5900
1854 * gencode.c (build_instruction): Handle "pext5" according to
1855 version 1.95 of the r5900 ISA.
1857 * gencode.c (build_instruction): Handle "ppac5" according to
1858 version 1.95 of the r5900 ISA.
1861 * interp.c (sim_engine_run): Reset the ZERO register to zero
1862 regardless of FEATURE_WARN_ZERO.
1863 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1865 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1867 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1868 (SignalException): For BreakPoints ignore any mode bits and just
1870 (SignalException): Always set the CAUSE register.
1872 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1874 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1875 exception has been taken.
1877 * interp.c: Implement the ERET and mt/f sr instructions.
1879 start-sanitize-r5900
1880 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
1882 * gencode.c (build_instruction): For paddu, extract unsigned
1885 * gencode.c (build_instruction): Saturate padds instead of padd
1889 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1891 * interp.c (SignalException): Don't bother restarting an
1894 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1896 * interp.c (SignalException): Really take an interrupt.
1897 (interrupt_event): Only deliver interrupts when enabled.
1899 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1901 * interp.c (sim_info): Only print info when verbose.
1902 (sim_info) Use sim_io_printf for output.
1904 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1906 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1909 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1911 * interp.c (sim_do_command): Check for common commands if a
1912 simulator specific command fails.
1914 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1916 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1917 and simBE when DEBUG is defined.
1919 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1921 * interp.c (interrupt_event): New function. Pass exception event
1922 onto exception handler.
1924 * configure.in: Check for stdlib.h.
1925 * configure: Regenerate.
1927 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1928 variable declaration.
1929 (build_instruction): Initialize memval1.
1930 (build_instruction): Add UNUSED attribute to byte, bigend,
1932 (build_operands): Ditto.
1934 * interp.c: Fix GCC warnings.
1935 (sim_get_quit_code): Delete.
1937 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1938 * Makefile.in: Ditto.
1939 * configure: Re-generate.
1941 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1943 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1945 * interp.c (mips_option_handler): New function parse argumes using
1947 (myname): Replace with STATE_MY_NAME.
1948 (sim_open): Delete check for host endianness - performed by
1950 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1951 (sim_open): Move much of the initialization from here.
1952 (sim_load): To here. After the image has been loaded and
1954 (sim_open): Move ColdReset from here.
1955 (sim_create_inferior): To here.
1956 (sim_open): Make FP check less dependant on host endianness.
1958 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1960 * interp.c (sim_set_callbacks): Delete.
1962 * interp.c (membank, membank_base, membank_size): Replace with
1963 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1964 (sim_open): Remove call to callback->init. gdb/run do this.
1968 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1970 * interp.c (big_endian_p): Delete, replaced by
1971 current_target_byte_order.
1973 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1975 * interp.c (host_read_long, host_read_word, host_swap_word,
1976 host_swap_long): Delete. Using common sim-endian.
1977 (sim_fetch_register, sim_store_register): Use H2T.
1978 (pipeline_ticks): Delete. Handled by sim-events.
1980 (sim_engine_run): Update.
1982 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1984 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1986 (SignalException): To here. Signal using sim_engine_halt.
1987 (sim_stop_reason): Delete, moved to common.
1989 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1991 * interp.c (sim_open): Add callback argument.
1992 (sim_set_callbacks): Delete SIM_DESC argument.
1995 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1997 * Makefile.in (SIM_OBJS): Add common modules.
1999 * interp.c (sim_set_callbacks): Also set SD callback.
2000 (set_endianness, xfer_*, swap_*): Delete.
2001 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2002 Change to functions using sim-endian macros.
2003 (control_c, sim_stop): Delete, use common version.
2004 (simulate): Convert into.
2005 (sim_engine_run): This function.
2006 (sim_resume): Delete.
2008 * interp.c (simulation): New variable - the simulator object.
2009 (sim_kind): Delete global - merged into simulation.
2010 (sim_load): Cleanup. Move PC assignment from here.
2011 (sim_create_inferior): To here.
2013 * sim-main.h: New file.
2014 * interp.c (sim-main.h): Include.
2016 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2018 * configure: Regenerated to track ../common/aclocal.m4 changes.
2020 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2022 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2024 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2026 * gencode.c (build_instruction): DIV instructions: check
2027 for division by zero and integer overflow before using
2028 host's division operation.
2030 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2032 * Makefile.in (SIM_OBJS): Add sim-load.o.
2033 * interp.c: #include bfd.h.
2034 (target_byte_order): Delete.
2035 (sim_kind, myname, big_endian_p): New static locals.
2036 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2037 after argument parsing. Recognize -E arg, set endianness accordingly.
2038 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2039 load file into simulator. Set PC from bfd.
2040 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2041 (set_endianness): Use big_endian_p instead of target_byte_order.
2043 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2045 * interp.c (sim_size): Delete prototype - conflicts with
2046 definition in remote-sim.h. Correct definition.
2048 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2050 * configure: Regenerated to track ../common/aclocal.m4 changes.
2053 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2055 * interp.c (sim_open): New arg `kind'.
2057 * configure: Regenerated to track ../common/aclocal.m4 changes.
2059 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2061 * configure: Regenerated to track ../common/aclocal.m4 changes.
2063 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2065 * interp.c (sim_open): Set optind to 0 before calling getopt.
2067 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2069 * configure: Regenerated to track ../common/aclocal.m4 changes.
2071 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2073 * interp.c : Replace uses of pr_addr with pr_uword64
2074 where the bit length is always 64 independent of SIM_ADDR.
2075 (pr_uword64) : added.
2077 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2079 * configure: Re-generate.
2081 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2083 * configure: Regenerate to track ../common/aclocal.m4 changes.
2085 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2087 * interp.c (sim_open): New SIM_DESC result. Argument is now
2089 (other sim_*): New SIM_DESC argument.
2091 start-sanitize-r5900
2092 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
2094 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
2095 Change values to avoid overloading DOUBLEWORD which is tested
2097 * gencode.c: reinstate "offending code".
2100 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2102 * interp.c: Fix printing of addresses for non-64-bit targets.
2103 (pr_addr): Add function to print address based on size.
2104 start-sanitize-r5900
2105 * gencode.c: #ifdef out offending code until a permanent fix
2106 can be added. Code is causing build errors for non-5900 mips targets.
2109 start-sanitize-r5900
2110 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
2112 * gencode.c (process_instructions): Correct test for ISA dependent
2113 architecture bits in isa field of MIPS_DECODE.
2116 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2118 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2120 start-sanitize-r5900
2121 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
2123 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
2127 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2129 * gencode.c (build_mips16_operands): Correct computation of base
2130 address for extended PC relative instruction.
2132 start-sanitize-r5900
2133 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
2135 * Makefile.in, configure, configure.in, gencode.c,
2136 interp.c, support.h: add r5900.
2139 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2141 * interp.c (mips16_entry): Add support for floating point cases.
2142 (SignalException): Pass floating point cases to mips16_entry.
2143 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2145 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2147 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2148 and then set the state to fmt_uninterpreted.
2149 (COP_SW): Temporarily set the state to fmt_word while calling
2152 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2154 * gencode.c (build_instruction): The high order may be set in the
2155 comparison flags at any ISA level, not just ISA 4.
2157 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2159 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2160 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2161 * configure.in: sinclude ../common/aclocal.m4.
2162 * configure: Regenerated.
2164 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2166 * configure: Rebuild after change to aclocal.m4.
2168 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2170 * configure configure.in Makefile.in: Update to new configure
2171 scheme which is more compatible with WinGDB builds.
2172 * configure.in: Improve comment on how to run autoconf.
2173 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2174 * Makefile.in: Use autoconf substitution to install common
2177 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2179 * gencode.c (build_instruction): Use BigEndianCPU instead of
2182 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2184 * interp.c (sim_monitor): Make output to stdout visible in
2185 wingdb's I/O log window.
2187 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2189 * support.h: Undo previous change to SIGTRAP
2192 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2194 * interp.c (store_word, load_word): New static functions.
2195 (mips16_entry): New static function.
2196 (SignalException): Look for mips16 entry and exit instructions.
2197 (simulate): Use the correct index when setting fpr_state after
2198 doing a pending move.
2200 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2202 * interp.c: Fix byte-swapping code throughout to work on
2203 both little- and big-endian hosts.
2205 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2207 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2208 with gdb/config/i386/xm-windows.h.
2210 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2212 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2213 that messes up arithmetic shifts.
2215 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2217 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2218 SIGTRAP and SIGQUIT for _WIN32.
2220 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2222 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2223 force a 64 bit multiplication.
2224 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2225 destination register is 0, since that is the default mips16 nop
2228 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2230 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2231 (build_endian_shift): Don't check proc64.
2232 (build_instruction): Always set memval to uword64. Cast op2 to
2233 uword64 when shifting it left in memory instructions. Always use
2234 the same code for stores--don't special case proc64.
2236 * gencode.c (build_mips16_operands): Fix base PC value for PC
2238 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2240 * interp.c (simJALDELAYSLOT): Define.
2241 (JALDELAYSLOT): Define.
2242 (INDELAYSLOT, INJALDELAYSLOT): Define.
2243 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2245 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2247 * interp.c (sim_open): add flush_cache as a PMON routine
2248 (sim_monitor): handle flush_cache by ignoring it
2250 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2252 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2254 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2255 (BigEndianMem): Rename to ByteSwapMem and change sense.
2256 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2257 BigEndianMem references to !ByteSwapMem.
2258 (set_endianness): New function, with prototype.
2259 (sim_open): Call set_endianness.
2260 (sim_info): Use simBE instead of BigEndianMem.
2261 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2262 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2263 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2264 ifdefs, keeping the prototype declaration.
2265 (swap_word): Rewrite correctly.
2266 (ColdReset): Delete references to CONFIG. Delete endianness related
2267 code; moved to set_endianness.
2269 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2271 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2272 * interp.c (CHECKHILO): Define away.
2273 (simSIGINT): New macro.
2274 (membank_size): Increase from 1MB to 2MB.
2275 (control_c): New function.
2276 (sim_resume): Rename parameter signal to signal_number. Add local
2277 variable prev. Call signal before and after simulate.
2278 (sim_stop_reason): Add simSIGINT support.
2279 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2281 (sim_warning): Delete call to SignalException. Do call printf_filtered
2283 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2284 a call to sim_warning.
2286 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2288 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2289 16 bit instructions.
2291 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2293 Add support for mips16 (16 bit MIPS implementation):
2294 * gencode.c (inst_type): Add mips16 instruction encoding types.
2295 (GETDATASIZEINSN): Define.
2296 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2297 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2299 (MIPS16_DECODE): New table, for mips16 instructions.
2300 (bitmap_val): New static function.
2301 (struct mips16_op): Define.
2302 (mips16_op_table): New table, for mips16 operands.
2303 (build_mips16_operands): New static function.
2304 (process_instructions): If PC is odd, decode a mips16
2305 instruction. Break out instruction handling into new
2306 build_instruction function.
2307 (build_instruction): New static function, broken out of
2308 process_instructions. Check modifiers rather than flags for SHIFT
2309 bit count and m[ft]{hi,lo} direction.
2310 (usage): Pass program name to fprintf.
2311 (main): Remove unused variable this_option_optind. Change
2312 ``*loptarg++'' to ``loptarg++''.
2313 (my_strtoul): Parenthesize && within ||.
2314 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2315 (simulate): If PC is odd, fetch a 16 bit instruction, and
2316 increment PC by 2 rather than 4.
2317 * configure.in: Add case for mips16*-*-*.
2318 * configure: Rebuild.
2320 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2322 * interp.c: Allow -t to enable tracing in standalone simulator.
2323 Fix garbage output in trace file and error messages.
2325 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2327 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2328 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2329 * configure.in: Simplify using macros in ../common/aclocal.m4.
2330 * configure: Regenerated.
2331 * tconfig.in: New file.
2333 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2335 * interp.c: Fix bugs in 64-bit port.
2336 Use ansi function declarations for msvc compiler.
2337 Initialize and test file pointer in trace code.
2338 Prevent duplicate definition of LAST_EMED_REGNUM.
2340 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2342 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2344 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2346 * interp.c (SignalException): Check for explicit terminating
2348 * gencode.c: Pass instruction value through SignalException()
2349 calls for Trap, Breakpoint and Syscall.
2351 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2353 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2354 only used on those hosts that provide it.
2355 * configure.in: Add sqrt() to list of functions to be checked for.
2356 * config.in: Re-generated.
2357 * configure: Re-generated.
2359 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2361 * gencode.c (process_instructions): Call build_endian_shift when
2362 expanding STORE RIGHT, to fix swr.
2363 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2364 clear the high bits.
2365 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2366 Fix float to int conversions to produce signed values.
2368 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2370 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2371 (process_instructions): Correct handling of nor instruction.
2372 Correct shift count for 32 bit shift instructions. Correct sign
2373 extension for arithmetic shifts to not shift the number of bits in
2374 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2375 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2377 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2378 It's OK to have a mult follow a mult. What's not OK is to have a
2379 mult follow an mfhi.
2380 (Convert): Comment out incorrect rounding code.
2382 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2384 * interp.c (sim_monitor): Improved monitor printf
2385 simulation. Tidied up simulator warnings, and added "--log" option
2386 for directing warning message output.
2387 * gencode.c: Use sim_warning() rather than WARNING macro.
2389 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2391 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2392 getopt1.o, rather than on gencode.c. Link objects together.
2393 Don't link against -liberty.
2394 (gencode.o, getopt.o, getopt1.o): New targets.
2395 * gencode.c: Include <ctype.h> and "ansidecl.h".
2396 (AND): Undefine after including "ansidecl.h".
2397 (ULONG_MAX): Define if not defined.
2398 (OP_*): Don't define macros; now defined in opcode/mips.h.
2399 (main): Call my_strtoul rather than strtoul.
2400 (my_strtoul): New static function.
2402 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2404 * gencode.c (process_instructions): Generate word64 and uword64
2405 instead of `long long' and `unsigned long long' data types.
2406 * interp.c: #include sysdep.h to get signals, and define default
2408 * (Convert): Work around for Visual-C++ compiler bug with type
2410 * support.h: Make things compile under Visual-C++ by using
2411 __int64 instead of `long long'. Change many refs to long long
2412 into word64/uword64 typedefs.
2414 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2416 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2417 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2419 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2420 (AC_PROG_INSTALL): Added.
2421 (AC_PROG_CC): Moved to before configure.host call.
2422 * configure: Rebuilt.
2424 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2426 * configure.in: Define @SIMCONF@ depending on mips target.
2427 * configure: Rebuild.
2428 * Makefile.in (run): Add @SIMCONF@ to control simulator
2430 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2431 * interp.c: Remove some debugging, provide more detailed error
2432 messages, update memory accesses to use LOADDRMASK.
2434 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2436 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2437 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2439 * configure: Rebuild.
2440 * config.in: New file, generated by autoheader.
2441 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2442 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2443 HAVE_ANINT and HAVE_AINT, as appropriate.
2444 * Makefile.in (run): Use @LIBS@ rather than -lm.
2445 (interp.o): Depend upon config.h.
2446 (Makefile): Just rebuild Makefile.
2447 (clean): Remove stamp-h.
2448 (mostlyclean): Make the same as clean, not as distclean.
2449 (config.h, stamp-h): New targets.
2451 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2453 * interp.c (ColdReset): Fix boolean test. Make all simulator
2456 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2458 * interp.c (xfer_direct_word, xfer_direct_long,
2459 swap_direct_word, swap_direct_long, xfer_big_word,
2460 xfer_big_long, xfer_little_word, xfer_little_long,
2461 swap_word,swap_long): Added.
2462 * interp.c (ColdReset): Provide function indirection to
2463 host<->simulated_target transfer routines.
2464 * interp.c (sim_store_register, sim_fetch_register): Updated to
2465 make use of indirected transfer routines.
2467 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2469 * gencode.c (process_instructions): Ensure FP ABS instruction
2471 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2472 system call support.
2474 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2476 * interp.c (sim_do_command): Complain if callback structure not
2479 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2481 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2482 support for Sun hosts.
2483 * Makefile.in (gencode): Ensure the host compiler and libraries
2484 used for cross-hosted build.
2486 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2488 * interp.c, gencode.c: Some more (TODO) tidying.
2490 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2492 * gencode.c, interp.c: Replaced explicit long long references with
2493 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2494 * support.h (SET64LO, SET64HI): Macros added.
2496 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2498 * configure: Regenerate with autoconf 2.7.
2500 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2502 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2503 * support.h: Remove superfluous "1" from #if.
2504 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2506 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2508 * interp.c (StoreFPR): Control UndefinedResult() call on
2509 WARN_RESULT manifest.
2511 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2513 * gencode.c: Tidied instruction decoding, and added FP instruction
2516 * interp.c: Added dineroIII, and BSD profiling support. Also
2517 run-time FP handling.
2519 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2521 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2522 gencode.c, interp.c, support.h: created.