sim/mips/ChangeLog

   1 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
   2
   3         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
   4         immediate or code as a hex value with the "%#lx" format.
   5         (ANDI): Likewise, and fix printed instruction name.
   6
   7 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
   8
   9         * sim-main.h (UndefinedResult, Unpredictable): New macros
  10         which currently do nothing.
  11
  12 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  13
  14         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
  15         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
  16         (status_CU3): New definitions.
  17
  18         * sim-main.h (ExceptionCause): Add new values for MIPS32
  19         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
  20         for DebugBreakPoint and NMIReset to note their status in
  21         MIPS32 and MIPS64.
  22         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
  23         (SignalExceptionCacheErr): New exception macros.
  24
  25 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  26
  27         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
  28         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
  29         is always enabled.
  30         (SignalExceptionCoProcessorUnusable): Take as argument the
  31         unusable coprocessor number.
  32
  33 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  34
  35         * mips.igen: Fix formatting of all SignalException calls.
  36
  37 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  38
  39         * sim-main.h (SIGNEXTEND): Remove.
  40
  41 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
  42
  43         * mips.igen: Remove gencode comment from top of file, fix
  44         spelling in another comment.
  45
  46 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
  47
  48         * mips.igen (check_fmt, check_fmt_p): New functions to check
  49         whether specific floating point formats are usable.
  50         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
  51         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
  52         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
  53         Use the new functions.
  54         (do_c_cond_fmt): Remove format checks...
  55         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
  56
  57 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
  58
  59         * mips.igen: Fix formatting of check_fpu calls.
  60
  61 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
  62
  63         * mips.igen (FLOOR.L.fmt): Store correct destination register.
  64
  65 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
  66
  67         * mips.igen: Remove whitespace at end of lines.
  68
  69 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
  70
  71         * mips.igen (loadstore_ea): New function to do effective
  72         address calculations.
  73         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
  74         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
  75         CACHE): Use loadstore_ea to do effective address computations.
  76
  77 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
  78
  79         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
  80         * mips.igen (LL, CxC1, MxC1): Likewise.
  81
  82 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
  83
  84         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
  85         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
  86         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
  87         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
  88         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
  89         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
  90         Don't split opcode fields by hand, use the opcode field values
  91         provided by igen.
  92
  93 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
  94
  95         * mips.igen (do_divu): Fix spacing.
  96
  97         * mips.igen (do_dsllv): Move to be right before DSLLV,
  98         to match the rest of the do_<shift> functions.
  99
 100 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 101
 102         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 103         DSRL32, do_dsrlv): Trace inputs and results.
 104
 105 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 106
 107         * mips.igen (CACHE): Provide instruction-printing string.
 108
 109         * interp.c (signal_exception): Comment tokens after #endif.
 110
 111 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 112
 113         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 114         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 115         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 116         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 117         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 118         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 119         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 120         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 121
 122 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 123
 124         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 125         instruction-printing string.
 126         (LWU): Use '64' as the filter flag.
 127
 128 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 129
 130         * mips.igen (SDXC1): Fix instruction-printing string.
 131
 132 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 133
 134         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 135         filter flags "32,f".
 136
 137 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 138
 139         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 140         as the filter flag.
 141
 142 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 143
 144         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 145         add a comma) so that it more closely match the MIPS ISA
 146         documentation opcode partitioning.
 147         (PREF): Put useful names on opcode fields, and include
 148         instruction-printing string.
 149
 150 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 151
 152         * mips.igen (check_u64): New function which in the future will
 153         check whether 64-bit instructions are usable and signal an
 154         exception if not.  Currently a no-op.
 155         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 156         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 157         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 158         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 159
 160         * mips.igen (check_fpu): New function which in the future will
 161         check whether FPU instructions are usable and signal an exception
 162         if not.  Currently a no-op.
 163         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 164         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 165         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 166         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 167         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 168         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 169         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 170         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 171
 172 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 173
 174         * mips.igen (do_load_left, do_load_right): Move to be immediately
 175         following do_load.
 176         (do_store_left, do_store_right): Move to be immediately following
 177         do_store.
 178
 179 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 180
 181         * mips.igen (mipsV): New model name.  Also, add it to
 182         all instructions and functions where it is appropriate.
 183
 184 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 185
 186         * mips.igen: For all functions and instructions, list model
 187         names that support that instruction one per line.
 188
 189 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 190
 191         * mips.igen: Add some additional comments about supported
 192         models, and about which instructions go where.
 193         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 194         order as is used in the rest of the file.
 195
 196 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 197
 198         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 199         indicating that ALU32_END or ALU64_END are there to check
 200         for overflow.
 201         (DADD): Likewise, but also remove previous comment about
 202         overflow checking.
 203
 204 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 205
 206         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 207         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 208         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 209         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 210         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 211         fields (i.e., add and move commas) so that they more closely
 212         match the MIPS ISA documentation opcode partitioning.
 213
 214 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 215
 216         * mips.igen (ADDI): Print immediate value.
 217         (BREAK): Print code.
 218         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 219         (SLL): Print "nop" specially, and don't run the code
 220         that does the shift for the "nop" case.
 221
 222 2001-11-17  Fred Fish  <fnf@redhat.com>
 223
 224         * sim-main.h (float_operation): Move enum declaration outside
 225         of _sim_cpu struct declaration.
 226
 227 2001-04-12  Jim Blandy  <jimb@redhat.com>
 228
 229         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 230         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 231         set of the FCSR.
 232         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 233         PENDING_FILL, and you can get the intended effect gracefully by
 234         calling PENDING_SCHED directly.
 235
 236 2001-02-23  Ben Elliston  <bje@redhat.com>
 237
 238         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 239         already defined elsewhere.
 240
 241 2001-02-19  Ben Elliston  <bje@redhat.com>
 242
 243         * sim-main.h (sim_monitor): Return an int.
 244         * interp.c (sim_monitor): Add return values.
 245         (signal_exception): Handle error conditions from sim_monitor.
 246
 247 2001-02-08  Ben Elliston  <bje@redhat.com>
 248
 249         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 250         (store_memory): Likewise, pass cia to sim_core_write*.
 251
 252 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 253
 254         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 255         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 256
 257 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 258
 259         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 260         * Makefile.in: Don't delete *.igen when cleaning directory.
 261
 262 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 263
 264         * m16.igen (break): Call SignalException not sim_engine_halt.
 265
 266 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 267
 268         From Jason Eckhardt:
 269         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 270
 271 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 272
 273         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 274
 275 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 276
 277         * mips.igen (do_dmultx): Fix typo.
 278
 279 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 280
 281         * configure: Regenerated to track ../common/aclocal.m4 changes.
 282
 283 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 284
 285         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 286
 287 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 288
 289         * sim-main.h (GPR_CLEAR): Define macro.
 290
 291 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 292
 293         * interp.c (decode_coproc): Output long using %lx and not %s.
 294
 295 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 296
 297         * interp.c (sim_open): Sort & extend dummy memory regions for
 298         --board=jmr3904 for eCos.
 299
 300 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 301
 302         * configure: Regenerated.
 303
 304 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 305
 306         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 307         calls, conditional on the simulator being in verbose mode.
 308
 309 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 310
 311         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 312         cache don't get ReservedInstruction traps.
 313
 314 1999-11-29  Mark Salter  <msalter@cygnus.com>
 315
 316         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 317         to clear status bits in sdisr register. This is how the hardware works.
 318
 319         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 320         being used by cygmon.
 321
 322 1999-11-11  Andrew Haley  <aph@cygnus.com>
 323
 324         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 325         instructions.
 326
 327 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 328
 329         * mips.igen (MULT): Correct previous mis-applied patch.
 330
 331 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 332
 333         * mips.igen (delayslot32): Handle sequence like
 334         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 335         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 336         (MULT): Actually pass the third register...
 337
 338 1999-09-03  Mark Salter  <msalter@cygnus.com>
 339
 340         * interp.c (sim_open): Added more memory aliases for additional
 341         hardware being touched by cygmon on jmr3904 board.
 342
 343 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 344
 345         * configure: Regenerated to track ../common/aclocal.m4 changes.
 346
 347 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 348
 349         * interp.c (sim_store_register): Handle case where client - GDB -
 350         specifies that a 4 byte register is 8 bytes in size.
 351         (sim_fetch_register): Ditto.
 352
 353 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 354
 355         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 356         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 357         (idt_monitor_base): Base address for IDT monitor traps.
 358         (pmon_monitor_base): Ditto for PMON.
 359         (lsipmon_monitor_base): Ditto for LSI PMON.
 360         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 361         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 362         (sim_firmware_command): New function.
 363         (mips_option_handler): Call it for OPTION_FIRMWARE.
 364         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 365         option was given, add no monitor by default.  Add BREAK hooks only if
 366         monitors are also there.
 367
 368 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 369
 370         * interp.c (sim_monitor): Flush output before reading input.
 371
 372 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 373
 374         * tconfig.in (SIM_HANDLES_LMA): Always define.
 375
 376 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 377
 378         From Mark Salter <msalter@cygnus.com>:
 379         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 380         (sim_open): Add setup for BSP board.
 381
 382 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 383
 384         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 385         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 386         them as unimplemented.
 387
 388 1999-05-08  Felix Lee  <flee@cygnus.com>
 389
 390         * configure: Regenerated to track ../common/aclocal.m4 changes.
 391
 392 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 393
 394         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 395
 396 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 397
 398         * configure.in: Any mips64vr5*-*-* target should have
 399         -DTARGET_ENABLE_FR=1.
 400         (default_endian): Any mips64vr*el-*-* target should default to
 401         LITTLE_ENDIAN.
 402         * configure: Re-generate.
 403
 404 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 405
 406         * mips.igen (ldl): Extend from _16_, not 32.
 407
 408 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 409
 410         * interp.c (sim_store_register): Force registers written to by GDB
 411         into an un-interpreted state.
 412
 413 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 414
 415         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 416         CPU, start periodic background I/O polls.
 417         (tx3904sio_poll): New function: periodic I/O poller.
 418
 419 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 420
 421         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 422
 423 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 424
 425         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 426         case statement.
 427
 428 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 429
 430         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 431         (load_word): Call SIM_CORE_SIGNAL hook on error.
 432         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 433         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 434         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 435         * sim-main.h (COP0_BADVADDR): Define.
 436         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 437         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 438         (_sim_cpu): Add exc_* fields to store register value snapshots.
 439         * mips.igen (*): Replace memory-related SignalException* calls
 440         with references to SIM_CORE_SIGNAL hook.
 441
 442         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 443         fix.
 444         * sim-main.c (*): Minor warning cleanups.
 445
 446 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 447
 448         * m16.igen (DADDIU5): Correct type-o.
 449
 450 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 451
 452         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 453         variables.
 454
 455 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 456
 457         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 458         to include path.
 459         (interp.o): Add dependency on itable.h
 460         (oengine.c, gencode): Delete remaining references.
 461         (BUILT_SRC_FROM_GEN): Clean up.
 462
 463 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 464
 465         * vr4run.c: New.
 466         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 467         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 468         tmp-run-hack) : New.
 469         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 470         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 471         Drop the "64" qualifier to get the HACK generator working.
 472         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 473         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 474         qualifier to get the hack generator working.
 475         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 476         (DSLL): Use do_dsll.
 477         (DSLLV): Use do_dsllv.
 478         (DSRA): Use do_dsra.
 479         (DSRL): Use do_dsrl.
 480         (DSRLV): Use do_dsrlv.
 481         (BC1): Move *vr4100 to get the HACK generator working.
 482         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 483         get the HACK generator working.
 484         (MACC) Rename to get the HACK generator working.
 485         (DMACC,MACCS,DMACCS): Add the 64.
 486
 487 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 488
 489         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 490         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 491
 492 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 493
 494     * mips/interp.c (DEBUG): Cleanups.
 495
 496 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 497
 498         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 499         (tx3904sio_tickle): fflush after a stdout character output.
 500
 501 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 502
 503         * interp.c (sim_close): Uninstall modules.
 504
 505 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 506
 507         * sim-main.h, interp.c (sim_monitor): Change to global
 508         function.
 509
 510 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 511
 512         * configure.in (vr4100): Only include vr4100 instructions in
 513         simulator.
 514         * configure: Re-generate.
 515         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 516
 517 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 518
 519         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 520         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 521         true alternative.
 522
 523         * configure.in (sim_default_gen, sim_use_gen): Replace with
 524         sim_gen.
 525         (--enable-sim-igen): Delete config option. Always using IGEN.
 526         * configure: Re-generate.
 527
 528         * Makefile.in (gencode): Kill, kill, kill.
 529         * gencode.c: Ditto.
 530
 531 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 532
 533         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 534         bit mips16 igen simulator.
 535         * configure: Re-generate.
 536
 537         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 538         as part of vr4100 ISA.
 539         * vr.igen: Mark all instructions as 64 bit only.
 540
 541 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 542
 543         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 544         Pacify GCC.
 545
 546 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 547
 548         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 549         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 550         * configure: Re-generate.
 551
 552         * m16.igen (BREAK): Define breakpoint instruction.
 553         (JALX32): Mark instruction as mips16 and not r3900.
 554         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 555
 556         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 557
 558 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 559
 560         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 561         insn as a debug breakpoint.
 562
 563         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 564         pending.slot_size.
 565         (PENDING_SCHED): Clean up trace statement.
 566         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 567         (PENDING_FILL): Delay write by only one cycle.
 568         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 569
 570         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 571         of pending writes.
 572         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 573         32 & 64.
 574         (pending_tick): Move incrementing of index to FOR statement.
 575         (pending_tick): Only update PENDING_OUT after a write has occured.
 576
 577         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 578         build simulator.
 579         * configure: Re-generate.
 580
 581         * interp.c (sim_engine_run OLD): Delete explicit call to
 582         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 583
 584 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 585
 586         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 587         interrupt level number to match changed SignalExceptionInterrupt
 588         macro.
 589
 590 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 591
 592         * interp.c: #include "itable.h" if WITH_IGEN.
 593         (get_insn_name): New function.
 594         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 595         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 596
 597 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 598
 599         * configure: Rebuilt to inhale new common/aclocal.m4.
 600
 601 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 602
 603         * dv-tx3904sio.c: Include sim-assert.h.
 604
 605 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 606
 607         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 608         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 609         Reorganize target-specific sim-hardware checks.
 610         * configure: rebuilt.
 611         * interp.c (sim_open): For tx39 target boards, set
 612         OPERATING_ENVIRONMENT, add tx3904sio devices.
 613         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 614         ROM executables.  Install dv-sockser into sim-modules list.
 615
 616         * dv-tx3904irc.c: Compiler warning clean-up.
 617         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 618         frequent hw-trace messages.
 619
 620 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 621
 622         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 623
 624 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 625
 626         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 627
 628         * vr.igen: New file.
 629         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 630         * mips.igen: Define vr4100 model. Include vr.igen.
 631 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 632
 633         * mips.igen (check_mf_hilo): Correct check.
 634
 635 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 636
 637         * sim-main.h (interrupt_event): Add prototype.
 638
 639         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 640         register_ptr, register_value.
 641         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 642
 643         * sim-main.h (tracefh): Make extern.
 644
 645 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 646
 647         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 648         Reduce unnecessarily high timer event frequency.
 649         * dv-tx3904cpu.c: Ditto for interrupt event.
 650
 651 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 652
 653         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 654         to allay warnings.
 655         (interrupt_event): Made non-static.
 656
 657         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 658         interchange of configuration values for external vs. internal
 659         clock dividers.
 660
 661 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 662
 663         * mips.igen (BREAK): Moved code to here for
 664         simulator-reserved break instructions.
 665         * gencode.c (build_instruction): Ditto.
 666         * interp.c (signal_exception): Code moved from here.  Non-
 667         reserved instructions now use exception vector, rather
 668         than halting sim.
 669         * sim-main.h: Moved magic constants to here.
 670
 671 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 672
 673         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 674         register upon non-zero interrupt event level, clear upon zero
 675         event value.
 676         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 677         by passing zero event value.
 678         (*_io_{read,write}_buffer): Endianness fixes.
 679         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 680         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 681
 682         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 683         serial I/O and timer module at base address 0xFFFF0000.
 684
 685 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 686
 687         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 688         and BigEndianCPU.
 689
 690 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 691
 692         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 693         parts.
 694         * configure: Update.
 695
 696 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 697
 698         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 699         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 700         * configure.in: Include tx3904tmr in hw_device list.
 701         * configure: Rebuilt.
 702         * interp.c (sim_open): Instantiate three timer instances.
 703         Fix address typo of tx3904irc instance.
 704
 705 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 706
 707         * interp.c (signal_exception): SystemCall exception now uses
 708         the exception vector.
 709
 710 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 711
 712         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 713         to allay warnings.
 714
 715 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 716
 717         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 718
 719 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 720
 721         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 722
 723         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 724         sim-main.h. Declare a struct hw_descriptor instead of struct
 725         hw_device_descriptor.
 726
 727 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 728
 729         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 730         right bits and then re-align left hand bytes to correct byte
 731         lanes.  Fix incorrect computation in do_store_left when loading
 732         bytes from second word.
 733
 734 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 735
 736         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 737         * interp.c (sim_open): Only create a device tree when HW is
 738         enabled.
 739
 740         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 741         * interp.c (signal_exception): Ditto.
 742
 743 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 744
 745         * gencode.c: Mark BEGEZALL as LIKELY.
 746
 747 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 748
 749         * sim-main.h (ALU32_END): Sign extend 32 bit results.
 750         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
 751
 752 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
 753
 754         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 755         modules.  Recognize TX39 target with "mips*tx39" pattern.
 756         * configure: Rebuilt.
 757         * sim-main.h (*): Added many macros defining bits in
 758         TX39 control registers.
 759         (SignalInterrupt): Send actual PC instead of NULL.
 760         (SignalNMIReset): New exception type.
 761         * interp.c (board): New variable for future use to identify
 762         a particular board being simulated.
 763         (mips_option_handler,mips_options): Added "--board" option.
 764         (interrupt_event): Send actual PC.
 765         (sim_open): Make memory layout conditional on board setting.
 766         (signal_exception): Initial implementation of hardware interrupt
 767         handling.  Accept another break instruction variant for simulator
 768         exit.
 769         (decode_coproc): Implement RFE instruction for TX39.
 770         (mips.igen): Decode RFE instruction as such.
 771         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
 772         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
 773         bbegin to implement memory map.
 774         * dv-tx3904cpu.c: New file.
 775         * dv-tx3904irc.c: New file.
 776
 777 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
 778
 779         * mips.igen (check_mt_hilo): Create a separate r3900 version.
 780
 781 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
 782
 783         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
 784         with calls to check_div_hilo.
 785
 786 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
 787
 788         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
 789         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
 790         Add special r3900 version of do_mult_hilo.
 791         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
 792         with calls to check_mult_hilo.
 793         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
 794         with calls to check_div_hilo.
 795
 796 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 797
 798         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
 799         Document a replacement.
 800
 801 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
 802
 803         * interp.c (sim_monitor): Make mon_printf work.
 804
 805 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
 806
 807         * sim-main.h (INSN_NAME): New arg `cpu'.
 808
 809 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
 810
 811         * configure: Regenerated to track ../common/aclocal.m4 changes.
 812
 813 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
 814
 815         * configure: Regenerated to track ../common/aclocal.m4 changes.
 816         * config.in: Ditto.
 817
 818 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
 819
 820         * acconfig.h: New file.
 821         * configure.in: Reverted change of Apr 24; use sinclude again.
 822
 823 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
 824
 825         * configure: Regenerated to track ../common/aclocal.m4 changes.
 826         * config.in: Ditto.
 827
 828 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
 829
 830         * configure.in: Don't call sinclude.
 831
 832 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
 833
 834         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
 835
 836 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 837
 838         * mips.igen (ERET): Implement.
 839
 840         * interp.c (decode_coproc): Return sign-extended EPC.
 841
 842         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
 843
 844         * interp.c (signal_exception): Do not ignore Trap.
 845         (signal_exception): On TRAP, restart at exception address.
 846         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
 847         (signal_exception): Update.
 848         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
 849         so that TRAP instructions are caught.
 850
 851 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 852
 853         * sim-main.h (struct hilo_access, struct hilo_history): Define,
 854         contains HI/LO access history.
 855         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
 856         (HIACCESS, LOACCESS): Delete, replace with
 857         (HIHISTORY, LOHISTORY): New macros.
 858         (CHECKHILO): Delete all, moved to mips.igen
 859
 860         * gencode.c (build_instruction): Do not generate checks for
 861         correct HI/LO register usage.
 862
 863         * interp.c (old_engine_run): Delete checks for correct HI/LO
 864         register usage.
 865
 866         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
 867         check_mf_cycles): New functions.
 868         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
 869         do_divu, domultx, do_mult, do_multu): Use.
 870
 871         * tx.igen ("madd", "maddu"): Use.
 872
 873 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 874
 875         * mips.igen (DSRAV): Use function do_dsrav.
 876         (SRAV): Use new function do_srav.
 877
 878         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
 879         (B): Sign extend 11 bit immediate.
 880         (EXT-B*): Shift 16 bit immediate left by 1.
 881         (ADDIU*): Don't sign extend immediate value.
 882
 883 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 884
 885         * m16run.c (sim_engine_run): Restore CIA after handling an event.
 886
 887         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
 888         functions.
 889
 890         * mips.igen (delayslot32, nullify_next_insn): New functions.
 891         (m16.igen): Always include.
 892         (do_*): Add more tracing.
 893
 894         * m16.igen (delayslot16): Add NIA argument, could be called by a
 895         32 bit MIPS16 instruction.
 896
 897         * interp.c (ifetch16): Move function from here.
 898         * sim-main.c (ifetch16): To here.
 899
 900         * sim-main.c (ifetch16, ifetch32): Update to match current
 901         implementations of LH, LW.
 902         (signal_exception): Don't print out incorrect hex value of illegal
 903         instruction.
 904
 905 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 906
 907         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
 908         instruction.
 909
 910         * m16.igen: Implement MIPS16 instructions.
 911
 912         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
 913         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
 914         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
 915         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
 916         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
 917         bodies of corresponding code from 32 bit insn to these.  Also used
 918         by MIPS16 versions of functions.
 919
 920         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
 921         (IMEM16): Drop NR argument from macro.
 922
 923 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 924
 925         * Makefile.in (SIM_OBJS): Add sim-main.o.
 926
 927         * sim-main.h (address_translation, load_memory, store_memory,
 928         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
 929         as INLINE_SIM_MAIN.
 930         (pr_addr, pr_uword64): Declare.
 931         (sim-main.c): Include when H_REVEALS_MODULE_P.
 932
 933         * interp.c (address_translation, load_memory, store_memory,
 934         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
 935         from here.
 936         * sim-main.c: To here. Fix compilation problems.
 937
 938         * configure.in: Enable inlining.
 939         * configure: Re-config.
 940
 941 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 942
 943         * configure: Regenerated to track ../common/aclocal.m4 changes.
 944
 945 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 946
 947         * mips.igen: Include tx.igen.
 948         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
 949         * tx.igen: New file, contains MADD and MADDU.
 950
 951         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
 952         the hardwired constant `7'.
 953         (store_memory): Ditto.
 954         (LOADDRMASK): Move definition to sim-main.h.
 955
 956         mips.igen (MTC0): Enable for r3900.
 957         (ADDU): Add trace.
 958
 959         mips.igen (do_load_byte): Delete.
 960         (do_load, do_store, do_load_left, do_load_write, do_store_left,
 961         do_store_right): New functions.
 962         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
 963
 964         configure.in: Let the tx39 use igen again.
 965         configure: Update.
 966
 967 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 968
 969         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
 970         not an address sized quantity.  Return zero for cache sizes.
 971
 972 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 973
 974         * mips.igen (r3900): r3900 does not support 64 bit integer
 975         operations.
 976
 977 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
 978
 979         * configure.in (mipstx39*-*-*): Use gencode simulator rather
 980         than igen one.
 981         * configure : Rebuild.
 982
 983 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 984
 985         * configure: Regenerated to track ../common/aclocal.m4 changes.
 986
 987 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 988
 989         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
 990
 991 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
 992
 993         * configure: Regenerated to track ../common/aclocal.m4 changes.
 994         * config.in: Regenerated to track ../common/aclocal.m4 changes.
 995
 996 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 997
 998         * configure: Regenerated to track ../common/aclocal.m4 changes.
 999
1000 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1001
1002         * interp.c (Max, Min): Comment out functions. Not yet used.
1003
1004 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1005
1006         * configure: Regenerated to track ../common/aclocal.m4 changes.
1007
1008 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1009
1010         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1011         configurable settings for stand-alone simulator.
1012
1013         * configure.in: Added X11 search, just in case.
1014
1015         * configure: Regenerated.
1016
1017 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1018
1019         * interp.c (sim_write, sim_read, load_memory, store_memory):
1020         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1021
1022 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1023
1024         * sim-main.h (GETFCC): Return an unsigned value.
1025
1026 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1027
1028         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1029         (DADD): Result destination is RD not RT.
1030
1031 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1032
1033         * sim-main.h (HIACCESS, LOACCESS): Always define.
1034
1035         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1036
1037         * interp.c (sim_info): Delete.
1038
1039 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1040
1041         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1042         (mips_option_handler): New argument `cpu'.
1043         (sim_open): Update call to sim_add_option_table.
1044
1045 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1046
1047         * mips.igen (CxC1): Add tracing.
1048
1049 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1050
1051         * sim-main.h (Max, Min): Declare.
1052
1053         * interp.c (Max, Min): New functions.
1054
1055         * mips.igen (BC1): Add tracing.
1056
1057 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1058
1059         * interp.c Added memory map for stack in vr4100
1060
1061 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1062
1063         * interp.c (load_memory): Add missing "break"'s.
1064
1065 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1066
1067         * interp.c (sim_store_register, sim_fetch_register): Pass in
1068         length parameter.  Return -1.
1069
1070 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1071
1072         * interp.c: Added hardware init hook, fixed warnings.
1073
1074 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1075
1076         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1077
1078 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1079
1080         * interp.c (ifetch16): New function.
1081
1082         * sim-main.h (IMEM32): Rename IMEM.
1083         (IMEM16_IMMED): Define.
1084         (IMEM16): Define.
1085         (DELAY_SLOT): Update.
1086
1087         * m16run.c (sim_engine_run): New file.
1088
1089         * m16.igen: All instructions except LB.
1090         (LB): Call do_load_byte.
1091         * mips.igen (do_load_byte): New function.
1092         (LB): Call do_load_byte.
1093
1094         * mips.igen: Move spec for insn bit size and high bit from here.
1095         * Makefile.in (tmp-igen, tmp-m16): To here.
1096
1097         * m16.dc: New file, decode mips16 instructions.
1098
1099         * Makefile.in (SIM_NO_ALL): Define.
1100         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1101
1102 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1103
1104         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1105         point unit to 32 bit registers.
1106         * configure: Re-generate.
1107
1108 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1109
1110         * configure.in (sim_use_gen): Make IGEN the default simulator
1111         generator for generic 32 and 64 bit mips targets.
1112         * configure: Re-generate.
1113
1114 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1115
1116         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1117         bitsize.
1118
1119         * interp.c (sim_fetch_register, sim_store_register): Read/write
1120         FGR from correct location.
1121         (sim_open): Set size of FGR's according to
1122         WITH_TARGET_FLOATING_POINT_BITSIZE.
1123
1124         * sim-main.h (FGR): Store floating point registers in a separate
1125         array.
1126
1127 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1128
1129         * configure: Regenerated to track ../common/aclocal.m4 changes.
1130
1131 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1132
1133         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1134
1135         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1136
1137         * interp.c (pending_tick): New function.  Deliver pending writes.
1138
1139         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1140         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1141         it can handle mixed sized quantites and single bits.
1142
1143 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1144
1145         * interp.c (oengine.h): Do not include when building with IGEN.
1146         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1147         (sim_info): Ditto for PROCESSOR_64BIT.
1148         (sim_monitor): Replace ut_reg with unsigned_word.
1149         (*): Ditto for t_reg.
1150         (LOADDRMASK): Define.
1151         (sim_open): Remove defunct check that host FP is IEEE compliant,
1152         using software to emulate floating point.
1153         (value_fpr, ...): Always compile, was conditional on HASFPU.
1154
1155 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1156
1157         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1158         size.
1159
1160         * interp.c (SD, CPU): Define.
1161         (mips_option_handler): Set flags in each CPU.
1162         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1163         (sim_close): Do not clear STATE, deleted anyway.
1164         (sim_write, sim_read): Assume CPU zero's vm should be used for
1165         data transfers.
1166         (sim_create_inferior): Set the PC for all processors.
1167         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1168         argument.
1169         (mips16_entry): Pass correct nr of args to store_word, load_word.
1170         (ColdReset): Cold reset all cpu's.
1171         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1172         (sim_monitor, load_memory, store_memory, signal_exception): Use
1173         `CPU' instead of STATE_CPU.
1174
1175
1176         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1177         SD or CPU_.
1178
1179         * sim-main.h (signal_exception): Add sim_cpu arg.
1180         (SignalException*): Pass both SD and CPU to signal_exception.
1181         * interp.c (signal_exception): Update.
1182
1183         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1184         Ditto
1185         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1186         address_translation): Ditto
1187         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1188
1189 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1190
1191         * configure: Regenerated to track ../common/aclocal.m4 changes.
1192
1193 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1194
1195         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1196
1197         * mips.igen (model): Map processor names onto BFD name.
1198
1199         * sim-main.h (CPU_CIA): Delete.
1200         (SET_CIA, GET_CIA): Define
1201
1202 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1203
1204         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1205         regiser.
1206
1207         * configure.in (default_endian): Configure a big-endian simulator
1208         by default.
1209         * configure: Re-generate.
1210
1211 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1212
1213         * configure: Regenerated to track ../common/aclocal.m4 changes.
1214
1215 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1216
1217         * interp.c (sim_monitor): Handle Densan monitor outbyte
1218         and inbyte functions.
1219
1220 1997-12-29  Felix Lee  <flee@cygnus.com>
1221
1222         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1223
1224 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1225
1226         * Makefile.in (tmp-igen): Arrange for $zero to always be
1227         reset to zero after every instruction.
1228
1229 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1230
1231         * configure: Regenerated to track ../common/aclocal.m4 changes.
1232         * config.in: Ditto.
1233
1234 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1235
1236         * mips.igen (MSUB): Fix to work like MADD.
1237         * gencode.c (MSUB): Similarly.
1238
1239 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1240
1241         * configure: Regenerated to track ../common/aclocal.m4 changes.
1242
1243 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1244
1245         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1246
1247 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1248
1249         * sim-main.h (sim-fpu.h): Include.
1250
1251         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1252         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1253         using host independant sim_fpu module.
1254
1255 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1256
1257         * interp.c (signal_exception): Report internal errors with SIGABRT
1258         not SIGQUIT.
1259
1260         * sim-main.h (C0_CONFIG): New register.
1261         (signal.h): No longer include.
1262
1263         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1264
1265 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1266
1267         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1268
1269 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1270
1271         * mips.igen: Tag vr5000 instructions.
1272         (ANDI): Was missing mipsIV model, fix assembler syntax.
1273         (do_c_cond_fmt): New function.
1274         (C.cond.fmt): Handle mips I-III which do not support CC field
1275         separatly.
1276         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1277         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1278         in IV3.2 spec.
1279         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1280         vr5000 which saves LO in a GPR separatly.
1281
1282         * configure.in (enable-sim-igen): For vr5000, select vr5000
1283         specific instructions.
1284         * configure: Re-generate.
1285
1286 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1287
1288         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1289
1290         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1291         fmt_uninterpreted_64 bit cases to switch.  Convert to
1292         fmt_formatted,
1293
1294         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1295
1296         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1297         as specified in IV3.2 spec.
1298         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1299
1300 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1301
1302         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1303         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1304         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1305         PENDING_FILL versions of instructions.  Simplify.
1306         (X): New function.
1307         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1308         instructions.
1309         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1310         a signed value.
1311         (MTHI, MFHI): Disable code checking HI-LO.
1312
1313         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1314         global.
1315         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1316
1317 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1318
1319         * gencode.c (build_mips16_operands): Replace IPC with cia.
1320
1321         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1322         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1323         IPC to `cia'.
1324         (UndefinedResult): Replace function with macro/function
1325         combination.
1326         (sim_engine_run): Don't save PC in IPC.
1327
1328         * sim-main.h (IPC): Delete.
1329
1330
1331         * interp.c (signal_exception, store_word, load_word,
1332         address_translation, load_memory, store_memory, cache_op,
1333         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1334         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1335         current instruction address - cia - argument.
1336         (sim_read, sim_write): Call address_translation directly.
1337         (sim_engine_run): Rename variable vaddr to cia.
1338         (signal_exception): Pass cia to sim_monitor
1339
1340         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1341         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1342         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1343
1344         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1345         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1346         SIM_ASSERT.
1347
1348         * interp.c (signal_exception): Pass restart address to
1349         sim_engine_restart.
1350
1351         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1352         idecode.o): Add dependency.
1353
1354         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1355         Delete definitions
1356         (DELAY_SLOT): Update NIA not PC with branch address.
1357         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1358
1359         * mips.igen: Use CIA not PC in branch calculations.
1360         (illegal): Call SignalException.
1361         (BEQ, ADDIU): Fix assembler.
1362
1363 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1364
1365         * m16.igen (JALX): Was missing.
1366
1367         * configure.in (enable-sim-igen): New configuration option.
1368         * configure: Re-generate.
1369
1370         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1371
1372         * interp.c (load_memory, store_memory): Delete parameter RAW.
1373         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1374         bypassing {load,store}_memory.
1375
1376         * sim-main.h (ByteSwapMem): Delete definition.
1377
1378         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1379
1380         * interp.c (sim_do_command, sim_commands): Delete mips specific
1381         commands.  Handled by module sim-options.
1382
1383         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1384         (WITH_MODULO_MEMORY): Define.
1385
1386         * interp.c (sim_info): Delete code printing memory size.
1387
1388         * interp.c (mips_size): Nee sim_size, delete function.
1389         (power2): Delete.
1390         (monitor, monitor_base, monitor_size): Delete global variables.
1391         (sim_open, sim_close): Delete code creating monitor and other
1392         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1393         manage memory regions.
1394         (load_memory, store_memory): Use sim-core for memory model.
1395
1396         * interp.c (address_translation): Delete all memory map code
1397         except line forcing 32 bit addresses.
1398
1399 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1400
1401         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1402         trace options.
1403
1404         * interp.c (logfh, logfile): Delete globals.
1405         (sim_open, sim_close): Delete code opening & closing log file.
1406         (mips_option_handler): Delete -l and -n options.
1407         (OPTION mips_options): Ditto.
1408
1409         * interp.c (OPTION mips_options): Rename option trace to dinero.
1410         (mips_option_handler): Update.
1411
1412 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1413
1414         * interp.c (fetch_str): New function.
1415         (sim_monitor): Rewrite using sim_read & sim_write.
1416         (sim_open): Check magic number.
1417         (sim_open): Write monitor vectors into memory using sim_write.
1418         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1419         (sim_read, sim_write): Simplify - transfer data one byte at a
1420         time.
1421         (load_memory, store_memory): Clarify meaning of parameter RAW.
1422
1423         * sim-main.h (isHOST): Defete definition.
1424         (isTARGET): Mark as depreciated.
1425         (address_translation): Delete parameter HOST.
1426
1427         * interp.c (address_translation): Delete parameter HOST.
1428
1429 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1430
1431         * mips.igen:
1432
1433         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1434         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1435
1436 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1437
1438         * mips.igen: Add model filter field to records.
1439
1440 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1441
1442         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1443
1444         interp.c (sim_engine_run): Do not compile function sim_engine_run
1445         when WITH_IGEN == 1.
1446
1447         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1448         target architecture.
1449
1450         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1451         igen. Replace with configuration variables sim_igen_flags /
1452         sim_m16_flags.
1453
1454         * m16.igen: New file.  Copy mips16 insns here.
1455         * mips.igen: From here.
1456
1457 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1458
1459         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1460         to top.
1461         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1462
1463 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1464
1465         * gencode.c (build_instruction): Follow sim_write's lead in using
1466         BigEndianMem instead of !ByteSwapMem.
1467
1468 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1469
1470         * configure.in (sim_gen): Dependent on target, select type of
1471         generator.  Always select old style generator.
1472
1473         configure: Re-generate.
1474
1475         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1476         targets.
1477         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1478         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1479         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1480         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1481         SIM_@sim_gen@_*, set by autoconf.
1482
1483 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1484
1485         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1486
1487         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1488         CURRENT_FLOATING_POINT instead.
1489
1490         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1491         (address_translation): Raise exception InstructionFetch when
1492         translation fails and isINSTRUCTION.
1493
1494         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1495         sim_engine_run): Change type of of vaddr and paddr to
1496         address_word.
1497         (address_translation, prefetch, load_memory, store_memory,
1498         cache_op): Change type of vAddr and pAddr to address_word.
1499
1500         * gencode.c (build_instruction): Change type of vaddr and paddr to
1501         address_word.
1502
1503 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1504
1505         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1506         macro to obtain result of ALU op.
1507
1508 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1509
1510         * interp.c (sim_info): Call profile_print.
1511
1512 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1513
1514         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1515
1516         * sim-main.h (WITH_PROFILE): Do not define, defined in
1517         common/sim-config.h.  Use sim-profile module.
1518         (simPROFILE): Delete defintion.
1519
1520         * interp.c (PROFILE): Delete definition.
1521         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1522         (sim_close): Delete code writing profile histogram.
1523         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1524         Delete.
1525         (sim_engine_run): Delete code profiling the PC.
1526
1527 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1528
1529         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1530
1531         * interp.c (sim_monitor): Make register pointers of type
1532         unsigned_word*.
1533
1534         * sim-main.h: Make registers of type unsigned_word not
1535         signed_word.
1536
1537 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1538
1539         * interp.c (sync_operation): Rename from SyncOperation, make
1540         global, add SD argument.
1541         (prefetch): Rename from Prefetch, make global, add SD argument.
1542         (decode_coproc): Make global.
1543
1544         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1545
1546         * gencode.c (build_instruction): Generate DecodeCoproc not
1547         decode_coproc calls.
1548
1549         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1550         (SizeFGR): Move to sim-main.h
1551         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1552         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1553         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1554         sim-main.h.
1555         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1556         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1557         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1558         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1559         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1560         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1561
1562         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1563         exception.
1564         (sim-alu.h): Include.
1565         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1566         (sim_cia): Typedef to instruction_address.
1567
1568 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1569
1570         * Makefile.in (interp.o): Rename generated file engine.c to
1571         oengine.c.
1572
1573         * interp.c: Update.
1574
1575 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1576
1577         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1578
1579 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1580
1581         * gencode.c (build_instruction): For "FPSQRT", output correct
1582         number of arguments to Recip.
1583
1584 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1585
1586         * Makefile.in (interp.o): Depends on sim-main.h
1587
1588         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1589
1590         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1591         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1592         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1593         STATE, DSSTATE): Define
1594         (GPR, FGRIDX, ..): Define.
1595
1596         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1597         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1598         (GPR, FGRIDX, ...): Delete macros.
1599
1600         * interp.c: Update names to match defines from sim-main.h
1601
1602 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1603
1604         * interp.c (sim_monitor): Add SD argument.
1605         (sim_warning): Delete.  Replace calls with calls to
1606         sim_io_eprintf.
1607         (sim_error): Delete. Replace calls with sim_io_error.
1608         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1609         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1610         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1611         argument.
1612         (mips_size): Rename from sim_size. Add SD argument.
1613
1614         * interp.c (simulator): Delete global variable.
1615         (callback): Delete global variable.
1616         (mips_option_handler, sim_open, sim_write, sim_read,
1617         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1618         sim_size,sim_monitor): Use sim_io_* not callback->*.
1619         (sim_open): ZALLOC simulator struct.
1620         (PROFILE): Do not define.
1621
1622 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1623
1624         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1625         support.h with corresponding code.
1626
1627         * sim-main.h (word64, uword64), support.h: Move definition to
1628         sim-main.h.
1629         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1630
1631         * support.h: Delete
1632         * Makefile.in: Update dependencies
1633         * interp.c: Do not include.
1634
1635 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1636
1637         * interp.c (address_translation, load_memory, store_memory,
1638         cache_op): Rename to from AddressTranslation et.al., make global,
1639         add SD argument
1640
1641         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1642         CacheOp): Define.
1643
1644         * interp.c (SignalException): Rename to signal_exception, make
1645         global.
1646
1647         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1648
1649         * sim-main.h (SignalException, SignalExceptionInterrupt,
1650         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1651         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1652         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1653         Define.
1654
1655         * interp.c, support.h: Use.
1656
1657 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1658
1659         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1660         to value_fpr / store_fpr. Add SD argument.
1661         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1662         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1663
1664         * sim-main.h (ValueFPR, StoreFPR): Define.
1665
1666 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1667
1668         * interp.c (sim_engine_run): Check consistency between configure
1669         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1670         and HASFPU.
1671
1672         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1673         (mips_fpu): Configure WITH_FLOATING_POINT.
1674         (mips_endian): Configure WITH_TARGET_ENDIAN.
1675         * configure: Update.
1676
1677 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1678
1679         * configure: Regenerated to track ../common/aclocal.m4 changes.
1680
1681 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1682
1683         * configure: Regenerated.
1684
1685 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1686
1687         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1688
1689 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1690
1691         * gencode.c (print_igen_insn_models): Assume certain architectures
1692         include all mips* instructions.
1693         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1694         instruction.
1695
1696         * Makefile.in (tmp.igen): Add target. Generate igen input from
1697         gencode file.
1698
1699         * gencode.c (FEATURE_IGEN): Define.
1700         (main): Add --igen option.  Generate output in igen format.
1701         (process_instructions): Format output according to igen option.
1702         (print_igen_insn_format): New function.
1703         (print_igen_insn_models): New function.
1704         (process_instructions): Only issue warnings and ignore
1705         instructions when no FEATURE_IGEN.
1706
1707 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1708
1709         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1710         MIPS targets.
1711
1712 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1713
1714         * configure: Regenerated to track ../common/aclocal.m4 changes.
1715
1716 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1717
1718         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1719         SIM_RESERVED_BITS): Delete, moved to common.
1720         (SIM_EXTRA_CFLAGS): Update.
1721
1722 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1723
1724         * configure.in: Configure non-strict memory alignment.
1725         * configure: Regenerated to track ../common/aclocal.m4 changes.
1726
1727 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1728
1729         * configure: Regenerated to track ../common/aclocal.m4 changes.
1730
1731 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1732
1733         * gencode.c (SDBBP,DERET): Added (3900) insns.
1734         (RFE): Turn on for 3900.
1735         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1736         (dsstate): Made global.
1737         (SUBTARGET_R3900): Added.
1738         (CANCELDELAYSLOT): New.
1739         (SignalException): Ignore SystemCall rather than ignore and
1740         terminate.  Add DebugBreakPoint handling.
1741         (decode_coproc): New insns RFE, DERET; and new registers Debug
1742         and DEPC protected by SUBTARGET_R3900.
1743         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1744         bits explicitly.
1745         * Makefile.in,configure.in: Add mips subtarget option.
1746         * configure: Update.
1747
1748 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
1749
1750         * gencode.c: Add r3900 (tx39).
1751
1752
1753 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
1754
1755         * gencode.c (build_instruction): Don't need to subtract 4 for
1756         JALR, just 2.
1757
1758 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
1759
1760         * interp.c: Correct some HASFPU problems.
1761
1762 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1763
1764         * configure: Regenerated to track ../common/aclocal.m4 changes.
1765
1766 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1767
1768         * interp.c (mips_options): Fix samples option short form, should
1769         be `x'.
1770
1771 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1772
1773         * interp.c (sim_info): Enable info code.  Was just returning.
1774
1775 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1776
1777         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1778         MFC0.
1779
1780 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1781
1782         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1783         constants.
1784         (build_instruction): Ditto for LL.
1785
1786 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
1787
1788         * configure: Regenerated to track ../common/aclocal.m4 changes.
1789
1790 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1791
1792         * configure: Regenerated to track ../common/aclocal.m4 changes.
1793         * config.in: Ditto.
1794
1795 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1796
1797         * interp.c (sim_open): Add call to sim_analyze_program, update
1798         call to sim_config.
1799
1800 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1801
1802         * interp.c (sim_kill): Delete.
1803         (sim_create_inferior): Add ABFD argument. Set PC from same.
1804         (sim_load): Move code initializing trap handlers from here.
1805         (sim_open): To here.
1806         (sim_load): Delete, use sim-hload.c.
1807
1808         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1809
1810 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1811
1812         * configure: Regenerated to track ../common/aclocal.m4 changes.
1813         * config.in: Ditto.
1814
1815 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1816
1817         * interp.c (sim_open): Add ABFD argument.
1818         (sim_load): Move call to sim_config from here.
1819         (sim_open): To here.  Check return status.
1820
1821 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
1822
1823         * gencode.c (build_instruction): Two arg MADD should
1824         not assign result to $0.
1825
1826 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
1827
1828         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1829         * sim/mips/configure.in: Regenerate.
1830
1831 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
1832
1833         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1834         signed8, unsigned8 et.al. types.
1835
1836         * interp.c (SUB_REG_FETCH): Handle both little and big endian
1837         hosts when selecting subreg.
1838
1839 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
1840
1841         * interp.c (sim_engine_run): Reset the ZERO register to zero
1842         regardless of FEATURE_WARN_ZERO.
1843         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1844
1845 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1846
1847         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1848         (SignalException): For BreakPoints ignore any mode bits and just
1849         save the PC.
1850         (SignalException): Always set the CAUSE register.
1851
1852 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1853
1854         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1855         exception has been taken.
1856
1857         * interp.c: Implement the ERET and mt/f sr instructions.
1858
1859 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1860
1861         * interp.c (SignalException): Don't bother restarting an
1862         interrupt.
1863
1864 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1865
1866         * interp.c (SignalException): Really take an interrupt.
1867         (interrupt_event): Only deliver interrupts when enabled.
1868
1869 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1870
1871         * interp.c (sim_info): Only print info when verbose.
1872         (sim_info) Use sim_io_printf for output.
1873
1874 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1875
1876         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1877         mips architectures.
1878
1879 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1880
1881         * interp.c (sim_do_command): Check for common commands if a
1882         simulator specific command fails.
1883
1884 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
1885
1886         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1887         and simBE when DEBUG is defined.
1888
1889 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1890
1891         * interp.c (interrupt_event): New function.  Pass exception event
1892         onto exception handler.
1893
1894         * configure.in: Check for stdlib.h.
1895         * configure: Regenerate.
1896
1897         * gencode.c (build_instruction): Add UNUSED attribute to tempS
1898         variable declaration.
1899         (build_instruction): Initialize memval1.
1900         (build_instruction): Add UNUSED attribute to byte, bigend,
1901         reverse.
1902         (build_operands): Ditto.
1903
1904         * interp.c: Fix GCC warnings.
1905         (sim_get_quit_code): Delete.
1906
1907         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1908         * Makefile.in: Ditto.
1909         * configure: Re-generate.
1910
1911         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1912
1913 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1914
1915         * interp.c (mips_option_handler): New function parse argumes using
1916         sim-options.
1917         (myname): Replace with STATE_MY_NAME.
1918         (sim_open): Delete check for host endianness - performed by
1919         sim_config.
1920         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1921         (sim_open): Move much of the initialization from here.
1922         (sim_load): To here.  After the image has been loaded and
1923         endianness set.
1924         (sim_open): Move ColdReset from here.
1925         (sim_create_inferior): To here.
1926         (sim_open): Make FP check less dependant on host endianness.
1927
1928         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1929         run.
1930         * interp.c (sim_set_callbacks): Delete.
1931
1932         * interp.c (membank, membank_base, membank_size): Replace with
1933         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1934         (sim_open): Remove call to callback->init. gdb/run do this.
1935
1936         * interp.c: Update
1937
1938         * sim-main.h (SIM_HAVE_FLATMEM): Define.
1939
1940         * interp.c (big_endian_p): Delete, replaced by
1941         current_target_byte_order.
1942
1943 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1944
1945         * interp.c (host_read_long, host_read_word, host_swap_word,
1946         host_swap_long): Delete. Using common sim-endian.
1947         (sim_fetch_register, sim_store_register): Use H2T.
1948         (pipeline_ticks): Delete.  Handled by sim-events.
1949         (sim_info): Update.
1950         (sim_engine_run): Update.
1951
1952 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1953
1954         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1955         reason from here.
1956         (SignalException): To here. Signal using sim_engine_halt.
1957         (sim_stop_reason): Delete, moved to common.
1958
1959 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
1960
1961         * interp.c (sim_open): Add callback argument.
1962         (sim_set_callbacks): Delete SIM_DESC argument.
1963         (sim_size): Ditto.
1964
1965 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1966
1967         * Makefile.in (SIM_OBJS): Add common modules.
1968
1969         * interp.c (sim_set_callbacks): Also set SD callback.
1970         (set_endianness, xfer_*, swap_*): Delete.
1971         (host_read_word, host_read_long, host_swap_word, host_swap_long):
1972         Change to functions using sim-endian macros.
1973         (control_c, sim_stop): Delete, use common version.
1974         (simulate): Convert into.
1975         (sim_engine_run): This function.
1976         (sim_resume): Delete.
1977
1978         * interp.c (simulation): New variable - the simulator object.
1979         (sim_kind): Delete global - merged into simulation.
1980         (sim_load): Cleanup.  Move PC assignment from here.
1981         (sim_create_inferior): To here.
1982
1983         * sim-main.h: New file.
1984         * interp.c (sim-main.h): Include.
1985
1986 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
1987
1988         * configure: Regenerated to track ../common/aclocal.m4 changes.
1989
1990 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
1991
1992         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1993
1994 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
1995
1996         * gencode.c (build_instruction): DIV instructions: check
1997         for division by zero and integer overflow before using
1998         host's division operation.
1999
2000 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2001
2002         * Makefile.in (SIM_OBJS): Add sim-load.o.
2003         * interp.c: #include bfd.h.
2004         (target_byte_order): Delete.
2005         (sim_kind, myname, big_endian_p): New static locals.
2006         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2007         after argument parsing.  Recognize -E arg, set endianness accordingly.
2008         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2009         load file into simulator.  Set PC from bfd.
2010         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2011         (set_endianness): Use big_endian_p instead of target_byte_order.
2012
2013 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2014
2015         * interp.c (sim_size): Delete prototype - conflicts with
2016         definition in remote-sim.h.  Correct definition.
2017
2018 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2019
2020         * configure: Regenerated to track ../common/aclocal.m4 changes.
2021         * config.in: Ditto.
2022
2023 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2024
2025         * interp.c (sim_open): New arg `kind'.
2026
2027         * configure: Regenerated to track ../common/aclocal.m4 changes.
2028
2029 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2030
2031         * configure: Regenerated to track ../common/aclocal.m4 changes.
2032
2033 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2034
2035         * interp.c (sim_open): Set optind to 0 before calling getopt.
2036
2037 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2038
2039         * configure: Regenerated to track ../common/aclocal.m4 changes.
2040
2041 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2042
2043         * interp.c : Replace uses of pr_addr with pr_uword64
2044         where the bit length is always 64 independent of SIM_ADDR.
2045         (pr_uword64) : added.
2046
2047 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2048
2049         * configure: Re-generate.
2050
2051 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2052
2053         * configure: Regenerate to track ../common/aclocal.m4 changes.
2054
2055 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2056
2057         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2058         in argv form.
2059         (other sim_*): New SIM_DESC argument.
2060
2061 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2062
2063         * interp.c: Fix printing of addresses for non-64-bit targets.
2064         (pr_addr): Add function to print address based on size.
2065
2066 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2067
2068         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2069
2070 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2071
2072         * gencode.c (build_mips16_operands): Correct computation of base
2073         address for extended PC relative instruction.
2074
2075 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2076
2077         * interp.c (mips16_entry): Add support for floating point cases.
2078         (SignalException): Pass floating point cases to mips16_entry.
2079         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2080         registers.
2081         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2082         or fmt_word.
2083         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2084         and then set the state to fmt_uninterpreted.
2085         (COP_SW): Temporarily set the state to fmt_word while calling
2086         ValueFPR.
2087
2088 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2089
2090         * gencode.c (build_instruction): The high order may be set in the
2091         comparison flags at any ISA level, not just ISA 4.
2092
2093 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2094
2095         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2096         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2097         * configure.in: sinclude ../common/aclocal.m4.
2098         * configure: Regenerated.
2099
2100 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2101
2102         * configure: Rebuild after change to aclocal.m4.
2103
2104 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2105
2106         * configure configure.in Makefile.in:  Update to new configure
2107         scheme which is more compatible with WinGDB builds.
2108         * configure.in:  Improve comment on how to run autoconf.
2109         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2110         * Makefile.in:  Use autoconf substitution to install common
2111         makefile fragment.
2112
2113 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2114
2115         * gencode.c (build_instruction): Use BigEndianCPU instead of
2116         ByteSwapMem.
2117
2118 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2119
2120         * interp.c (sim_monitor): Make output to stdout visible in
2121         wingdb's I/O log window.
2122
2123 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2124
2125         * support.h: Undo previous change to SIGTRAP
2126         and SIGQUIT values.
2127
2128 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2129
2130         * interp.c (store_word, load_word): New static functions.
2131         (mips16_entry): New static function.
2132         (SignalException): Look for mips16 entry and exit instructions.
2133         (simulate): Use the correct index when setting fpr_state after
2134         doing a pending move.
2135
2136 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2137
2138         * interp.c: Fix byte-swapping code throughout to work on
2139         both little- and big-endian hosts.
2140
2141 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2142
2143         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2144         with gdb/config/i386/xm-windows.h.
2145
2146 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2147
2148         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2149         that messes up arithmetic shifts.
2150
2151 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2152
2153         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2154         SIGTRAP and SIGQUIT for _WIN32.
2155
2156 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2157
2158         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2159         force a 64 bit multiplication.
2160         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2161         destination register is 0, since that is the default mips16 nop
2162         instruction.
2163
2164 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2165
2166         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2167         (build_endian_shift): Don't check proc64.
2168         (build_instruction): Always set memval to uword64.  Cast op2 to
2169         uword64 when shifting it left in memory instructions.  Always use
2170         the same code for stores--don't special case proc64.
2171
2172         * gencode.c (build_mips16_operands): Fix base PC value for PC
2173         relative operands.
2174         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2175         jal instruction.
2176         * interp.c (simJALDELAYSLOT): Define.
2177         (JALDELAYSLOT): Define.
2178         (INDELAYSLOT, INJALDELAYSLOT): Define.
2179         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2180
2181 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2182
2183         * interp.c (sim_open): add flush_cache as a PMON routine
2184         (sim_monitor): handle flush_cache by ignoring it
2185
2186 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2187
2188         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2189         BigEndianMem.
2190         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2191         (BigEndianMem): Rename to ByteSwapMem and change sense.
2192         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2193         BigEndianMem references to !ByteSwapMem.
2194         (set_endianness): New function, with prototype.
2195         (sim_open): Call set_endianness.
2196         (sim_info): Use simBE instead of BigEndianMem.
2197         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2198         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2199         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2200         ifdefs, keeping the prototype declaration.
2201         (swap_word): Rewrite correctly.
2202         (ColdReset): Delete references to CONFIG.  Delete endianness related
2203         code; moved to set_endianness.
2204
2205 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2206
2207         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2208         * interp.c (CHECKHILO): Define away.
2209         (simSIGINT): New macro.
2210         (membank_size): Increase from 1MB to 2MB.
2211         (control_c): New function.
2212         (sim_resume): Rename parameter signal to signal_number.  Add local
2213         variable prev.  Call signal before and after simulate.
2214         (sim_stop_reason): Add simSIGINT support.
2215         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2216         functions always.
2217         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2218         if logfh is NULL.
2219         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2220         a call to sim_warning.
2221
2222 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2223
2224         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2225         16 bit instructions.
2226
2227 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2228
2229         Add support for mips16 (16 bit MIPS implementation):
2230         * gencode.c (inst_type): Add mips16 instruction encoding types.
2231         (GETDATASIZEINSN): Define.
2232         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2233         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2234         mtlo.
2235         (MIPS16_DECODE): New table, for mips16 instructions.
2236         (bitmap_val): New static function.
2237         (struct mips16_op): Define.
2238         (mips16_op_table): New table, for mips16 operands.
2239         (build_mips16_operands): New static function.
2240         (process_instructions): If PC is odd, decode a mips16
2241         instruction.  Break out instruction handling into new
2242         build_instruction function.
2243         (build_instruction): New static function, broken out of
2244         process_instructions.  Check modifiers rather than flags for SHIFT
2245         bit count and m[ft]{hi,lo} direction.
2246         (usage): Pass program name to fprintf.
2247         (main): Remove unused variable this_option_optind.  Change
2248         ``*loptarg++'' to ``loptarg++''.
2249         (my_strtoul): Parenthesize && within ||.
2250         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2251         (simulate): If PC is odd, fetch a 16 bit instruction, and
2252         increment PC by 2 rather than 4.
2253         * configure.in: Add case for mips16*-*-*.
2254         * configure: Rebuild.
2255
2256 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2257
2258         * interp.c: Allow -t to enable tracing in standalone simulator.
2259         Fix garbage output in trace file and error messages.
2260
2261 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2262
2263         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2264         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2265         * configure.in: Simplify using macros in ../common/aclocal.m4.
2266         * configure: Regenerated.
2267         * tconfig.in: New file.
2268
2269 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2270
2271         * interp.c: Fix bugs in 64-bit port.
2272         Use ansi function declarations for msvc compiler.
2273         Initialize and test file pointer in trace code.
2274         Prevent duplicate definition of LAST_EMED_REGNUM.
2275
2276 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2277
2278         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2279
2280 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2281
2282         * interp.c (SignalException): Check for explicit terminating
2283         breakpoint value.
2284         * gencode.c: Pass instruction value through SignalException()
2285         calls for Trap, Breakpoint and Syscall.
2286
2287 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2288
2289         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2290         only used on those hosts that provide it.
2291         * configure.in: Add sqrt() to list of functions to be checked for.
2292         * config.in: Re-generated.
2293         * configure: Re-generated.
2294
2295 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2296
2297         * gencode.c (process_instructions): Call build_endian_shift when
2298         expanding STORE RIGHT, to fix swr.
2299         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2300         clear the high bits.
2301         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2302         Fix float to int conversions to produce signed values.
2303
2304 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2305
2306         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2307         (process_instructions): Correct handling of nor instruction.
2308         Correct shift count for 32 bit shift instructions. Correct sign
2309         extension for arithmetic shifts to not shift the number of bits in
2310         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2311         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2312         Fix madd.
2313         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2314         It's OK to have a mult follow a mult.  What's not OK is to have a
2315         mult follow an mfhi.
2316         (Convert): Comment out incorrect rounding code.
2317
2318 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2319
2320         * interp.c (sim_monitor): Improved monitor printf
2321         simulation. Tidied up simulator warnings, and added "--log" option
2322         for directing warning message output.
2323         * gencode.c: Use sim_warning() rather than WARNING macro.
2324
2325 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2326
2327         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2328         getopt1.o, rather than on gencode.c.  Link objects together.
2329         Don't link against -liberty.
2330         (gencode.o, getopt.o, getopt1.o): New targets.
2331         * gencode.c: Include <ctype.h> and "ansidecl.h".
2332         (AND): Undefine after including "ansidecl.h".
2333         (ULONG_MAX): Define if not defined.
2334         (OP_*): Don't define macros; now defined in opcode/mips.h.
2335         (main): Call my_strtoul rather than strtoul.
2336         (my_strtoul): New static function.
2337
2338 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2339
2340         * gencode.c (process_instructions):  Generate word64 and uword64
2341         instead of `long long' and `unsigned long long' data types.
2342         * interp.c:  #include sysdep.h to get signals, and define default
2343         for SIGBUS.
2344         * (Convert):  Work around for Visual-C++ compiler bug with type
2345         conversion.
2346         * support.h:  Make things compile under Visual-C++ by using
2347         __int64 instead of `long long'.  Change many refs to long long
2348         into word64/uword64 typedefs.
2349
2350 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2351
2352         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2353         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2354         (docdir): Removed.
2355         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2356         (AC_PROG_INSTALL): Added.
2357         (AC_PROG_CC): Moved to before configure.host call.
2358         * configure: Rebuilt.
2359
2360 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2361
2362         * configure.in: Define @SIMCONF@ depending on mips target.
2363         * configure: Rebuild.
2364         * Makefile.in (run): Add @SIMCONF@ to control simulator
2365         construction.
2366         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2367         * interp.c: Remove some debugging, provide more detailed error
2368         messages, update memory accesses to use LOADDRMASK.
2369
2370 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2371
2372         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2373         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2374         stamp-h.
2375         * configure: Rebuild.
2376         * config.in: New file, generated by autoheader.
2377         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2378         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2379         HAVE_ANINT and HAVE_AINT, as appropriate.
2380         * Makefile.in (run): Use @LIBS@ rather than -lm.
2381         (interp.o): Depend upon config.h.
2382         (Makefile): Just rebuild Makefile.
2383         (clean): Remove stamp-h.
2384         (mostlyclean): Make the same as clean, not as distclean.
2385         (config.h, stamp-h): New targets.
2386
2387 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2388
2389         * interp.c (ColdReset): Fix boolean test. Make all simulator
2390         globals static.
2391
2392 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2393
2394         * interp.c (xfer_direct_word, xfer_direct_long,
2395         swap_direct_word, swap_direct_long, xfer_big_word,
2396         xfer_big_long, xfer_little_word, xfer_little_long,
2397         swap_word,swap_long): Added.
2398         * interp.c (ColdReset): Provide function indirection to
2399         host<->simulated_target transfer routines.
2400         * interp.c (sim_store_register, sim_fetch_register): Updated to
2401         make use of indirected transfer routines.
2402
2403 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2404
2405         * gencode.c (process_instructions): Ensure FP ABS instruction
2406         recognised.
2407         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2408         system call support.
2409
2410 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2411
2412         * interp.c (sim_do_command): Complain if callback structure not
2413         initialised.
2414
2415 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2416
2417         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2418         support for Sun hosts.
2419         * Makefile.in (gencode): Ensure the host compiler and libraries
2420         used for cross-hosted build.
2421
2422 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2423
2424         * interp.c, gencode.c: Some more (TODO) tidying.
2425
2426 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2427
2428         * gencode.c, interp.c: Replaced explicit long long references with
2429         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2430         * support.h (SET64LO, SET64HI): Macros added.
2431
2432 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2433
2434         * configure: Regenerate with autoconf 2.7.
2435
2436 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2437
2438         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2439         * support.h: Remove superfluous "1" from #if.
2440         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2441
2442 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2443
2444         * interp.c (StoreFPR): Control UndefinedResult() call on
2445         WARN_RESULT manifest.
2446
2447 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2448
2449         * gencode.c: Tidied instruction decoding, and added FP instruction
2450         support.
2451
2452         * interp.c: Added dineroIII, and BSD profiling support. Also
2453         run-time FP handling.
2454
2455 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2456
2457         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2458         gencode.c, interp.c, support.h: created.