sim/mips/ChangeLog

   1 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
   2
   3         * mips.igen (MOVN, MOVZ): Trace result.
   4         (TNEI): Print "tnei" as the opcode name in traces.
   5         (CEIL.W): Add disassembly string for traces.
   6         (RSQRT.fmt): Make location of disassembly string consistent
   7         with other instructions.
   8
   9 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
  10
  11         * mips.igen (X): Delete unused function.
  12
  13 2002-06-08  Andrew Cagney  <cagney@redhat.com>
  14
  15         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
  16
  17 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  18             Ed Satterthwaite  <ehs@broadcom.com>
  19
  20         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
  21         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
  22         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
  23         (fp_nmsub): New prototypes.
  24         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
  25         (NegMultiplySub): New defines.
  26         * mips.igen (RSQRT.fmt): Use RSquareRoot().
  27         (MADD.D, MADD.S): Replace with...
  28         (MADD.fmt): New instruction.
  29         (MSUB.D, MSUB.S): Replace with...
  30         (MSUB.fmt): New instruction.
  31         (NMADD.D, NMADD.S): Replace with...
  32         (NMADD.fmt): New instruction.
  33         (NMSUB.D, MSUB.S): Replace with...
  34         (NMSUB.fmt): New instruction.
  35
  36 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  37             Ed Satterthwaite  <ehs@broadcom.com>
  38
  39         * cp1.c: Fix more comment spelling and formatting.
  40         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
  41         (denorm_mode): New function.
  42         (fpu_unary, fpu_binary): Round results after operation, collect
  43         status from rounding operations, and update the FCSR.
  44         (convert): Collect status from integer conversions and rounding
  45         operations, and update the FCSR.  Adjust NaN values that result
  46         from conversions.  Convert to use sim_io_eprintf rather than
  47         fprintf, and remove some debugging code.
  48         * cp1.h (fenr_FS): New define.
  49
  50 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  51
  52         * cp1.c (convert): Remove unusable debugging code, and move MIPS
  53         rounding mode to sim FP rounding mode flag conversion code into...
  54         (rounding_mode): New function.
  55
  56 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  57
  58         * cp1.c: Clean up formatting of a few comments.
  59         (value_fpr): Reformat switch statement.
  60
  61 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
  62             Ed Satterthwaite  <ehs@broadcom.com>
  63
  64         * cp1.h: New file.
  65         * sim-main.h: Include cp1.h.
  66         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
  67         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
  68         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
  69         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
  70         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
  71         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
  72         * cp1.c: Don't include sim-fpu.h; already included by
  73         sim-main.h.  Clean up formatting of some comments.
  74         (NaN, Equal, Less): Remove.
  75         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
  76         (fp_cmp): New functions.
  77         * mips.igen (do_c_cond_fmt): Remove.
  78         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
  79         Compare.  Add result tracing.
  80         (CxC1): Remove, replace with...
  81         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
  82         (DMxC1): Remove, replace with...
  83         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
  84         (MxC1): Remove, replace with...
  85         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
  86
  87 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
  88
  89         * sim-main.h (FGRIDX): Remove, replace all uses with...
  90         (FGR_BASE): New macro.
  91         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
  92         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
  93         (NR_FGR, FGR): Likewise.
  94         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
  95         * mips.igen: Likewise.
  96
  97 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
  98
  99         * cp1.c: Add an FSF Copyright notice to this file.
 100
 101 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 102             Ed Satterthwaite  <ehs@broadcom.com>
 103
 104         * cp1.c (Infinity): Remove.
 105         * sim-main.h (Infinity): Likewise.
 106
 107         * cp1.c (fp_unary, fp_binary): New functions.
 108         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 109         (fp_sqrt): New functions, implemented in terms of the above.
 110         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 111         (Recip, SquareRoot): Remove (replaced by functions above).
 112         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 113         (fp_recip, fp_sqrt): New prototypes.
 114         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 115         (Recip, SquareRoot): Replace prototypes with #defines which
 116         invoke the functions above.
 117
 118 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 119
 120         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 121         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 122         file, remove PARAMS from prototypes.
 123         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 124         simulator state arguments.
 125         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 126         pass simulator state arguments.
 127         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 128         (store_fpr, convert): Remove 'sd' argument.
 129         (value_fpr): Likewise.  Convert to use 'SD' instead.
 130
 131 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 132
 133         * cp1.c (Min, Max): Remove #if 0'd functions.
 134         * sim-main.h (Min, Max): Remove.
 135
 136 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 137
 138         * cp1.c: fix formatting of switch case and default labels.
 139         * interp.c: Likewise.
 140         * sim-main.c: Likewise.
 141
 142 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 143
 144         * cp1.c: Clean up comments which describe FP formats.
 145          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 146
 147 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 148             Ed Satterthwaite  <ehs@broadcom.com>
 149
 150         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 151         Broadcom SiByte SB-1 processor configurations.
 152         * configure: Regenerate.
 153         * sb1.igen: New file.
 154         * mips.igen: Include sb1.igen.
 155         (sb1): New model.
 156         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 157         * mdmx.igen: Add "sb1" model to all appropriate functions and
 158         instructions.
 159         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 160         (ob_func, ob_acc): Reference the above.
 161         (qh_acc): Adjust to keep the same size as ob_acc.
 162         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 163         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 164
 165 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 166
 167         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 168
 169 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 170             Ed Satterthwaite  <ehs@broadcom.com>
 171
 172         * mips.igen (mdmx): New (pseudo-)model.
 173         * mdmx.c, mdmx.igen: New files.
 174         * Makefile.in (SIM_OBJS): Add mdmx.o.
 175         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 176         New typedefs.
 177         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 178         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 179         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 180         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 181         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 182         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 183         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 184         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 185         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 186         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 187         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 188         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 189         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 190         (qh_fmtsel): New macros.
 191         (_sim_cpu): New member "acc".
 192         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 193         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 194
 195 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 196
 197         * interp.c: Use 'deprecated' rather than 'depreciated.'
 198         * sim-main.h: Likewise.
 199
 200 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 201
 202         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 203         which wouldn't compile anyway.
 204         * sim-main.h (unpredictable_action): New function prototype.
 205         (Unpredictable): Define to call igen function unpredictable().
 206         (NotWordValue): New macro to call igen function not_word_value().
 207         (UndefinedResult): Remove.
 208         * interp.c (undefined_result): Remove.
 209         (unpredictable_action): New function.
 210         * mips.igen (not_word_value, unpredictable): New functions.
 211         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 212         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 213         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 214         NotWordValue() to check for unpredictable inputs, then
 215         Unpredictable() to handle them.
 216
 217 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 218
 219         * mips.igen: Fix formatting of calls to Unpredictable().
 220
 221 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 222
 223         * interp.c (sim_open): Revert previous change.
 224
 225 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 226
 227         * interp.c (sim_open): Disable chunk of code that wrote code in
 228         vector table entries.
 229
 230 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 231
 232         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 233         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 234         unused definitions.
 235
 236 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 237
 238         * cp1.c: Fix many formatting issues.
 239
 240 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 241
 242         * cp1.c (fpu_format_name): New function to replace...
 243         (DOFMT): This.  Delete, and update all callers.
 244         (fpu_rounding_mode_name): New function to replace...
 245         (RMMODE): This.  Delete, and update all callers.
 246
 247 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 248
 249         * interp.c: Move FPU support routines from here to...
 250         * cp1.c: Here.  New file.
 251         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 252         (cp1.o): New target.
 253
 254 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 255
 256         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 257         * mips.igen (mips32, mips64): New models, add to all instructions
 258         and functions as appropriate.
 259         (loadstore_ea, check_u64): New variant for model mips64.
 260         (check_fmt_p): New variant for models mipsV and mips64, remove
 261         mipsV model marking fro other variant.
 262         (SLL) Rename to...
 263         (SLLa) this.
 264         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 265         for mips32 and mips64.
 266         (DCLO, DCLZ): New instructions for mips64.
 267
 268 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 269
 270         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 271         immediate or code as a hex value with the "%#lx" format.
 272         (ANDI): Likewise, and fix printed instruction name.
 273
 274 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 275
 276         * sim-main.h (UndefinedResult, Unpredictable): New macros
 277         which currently do nothing.
 278
 279 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 280
 281         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 282         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 283         (status_CU3): New definitions.
 284
 285         * sim-main.h (ExceptionCause): Add new values for MIPS32
 286         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 287         for DebugBreakPoint and NMIReset to note their status in
 288         MIPS32 and MIPS64.
 289         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 290         (SignalExceptionCacheErr): New exception macros.
 291
 292 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 293
 294         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 295         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 296         is always enabled.
 297         (SignalExceptionCoProcessorUnusable): Take as argument the
 298         unusable coprocessor number.
 299
 300 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 301
 302         * mips.igen: Fix formatting of all SignalException calls.
 303
 304 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 305
 306         * sim-main.h (SIGNEXTEND): Remove.
 307
 308 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 309
 310         * mips.igen: Remove gencode comment from top of file, fix
 311         spelling in another comment.
 312
 313 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 314
 315         * mips.igen (check_fmt, check_fmt_p): New functions to check
 316         whether specific floating point formats are usable.
 317         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 318         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 319         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 320         Use the new functions.
 321         (do_c_cond_fmt): Remove format checks...
 322         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 323
 324 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 325
 326         * mips.igen: Fix formatting of check_fpu calls.
 327
 328 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 329
 330         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 331
 332 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 333
 334         * mips.igen: Remove whitespace at end of lines.
 335
 336 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 337
 338         * mips.igen (loadstore_ea): New function to do effective
 339         address calculations.
 340         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 341         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 342         CACHE): Use loadstore_ea to do effective address computations.
 343
 344 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 345
 346         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 347         * mips.igen (LL, CxC1, MxC1): Likewise.
 348
 349 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 350
 351         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 352         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 353         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 354         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 355         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 356         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 357         Don't split opcode fields by hand, use the opcode field values
 358         provided by igen.
 359
 360 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 361
 362         * mips.igen (do_divu): Fix spacing.
 363
 364         * mips.igen (do_dsllv): Move to be right before DSLLV,
 365         to match the rest of the do_<shift> functions.
 366
 367 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 368
 369         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 370         DSRL32, do_dsrlv): Trace inputs and results.
 371
 372 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 373
 374         * mips.igen (CACHE): Provide instruction-printing string.
 375
 376         * interp.c (signal_exception): Comment tokens after #endif.
 377
 378 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 379
 380         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 381         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 382         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 383         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 384         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 385         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 386         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 387         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 388
 389 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 390
 391         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 392         instruction-printing string.
 393         (LWU): Use '64' as the filter flag.
 394
 395 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 396
 397         * mips.igen (SDXC1): Fix instruction-printing string.
 398
 399 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 400
 401         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 402         filter flags "32,f".
 403
 404 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 405
 406         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 407         as the filter flag.
 408
 409 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 410
 411         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 412         add a comma) so that it more closely match the MIPS ISA
 413         documentation opcode partitioning.
 414         (PREF): Put useful names on opcode fields, and include
 415         instruction-printing string.
 416
 417 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 418
 419         * mips.igen (check_u64): New function which in the future will
 420         check whether 64-bit instructions are usable and signal an
 421         exception if not.  Currently a no-op.
 422         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 423         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 424         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 425         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 426
 427         * mips.igen (check_fpu): New function which in the future will
 428         check whether FPU instructions are usable and signal an exception
 429         if not.  Currently a no-op.
 430         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 431         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 432         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 433         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 434         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 435         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 436         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 437         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 438
 439 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 440
 441         * mips.igen (do_load_left, do_load_right): Move to be immediately
 442         following do_load.
 443         (do_store_left, do_store_right): Move to be immediately following
 444         do_store.
 445
 446 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 447
 448         * mips.igen (mipsV): New model name.  Also, add it to
 449         all instructions and functions where it is appropriate.
 450
 451 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 452
 453         * mips.igen: For all functions and instructions, list model
 454         names that support that instruction one per line.
 455
 456 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 457
 458         * mips.igen: Add some additional comments about supported
 459         models, and about which instructions go where.
 460         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 461         order as is used in the rest of the file.
 462
 463 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 464
 465         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 466         indicating that ALU32_END or ALU64_END are there to check
 467         for overflow.
 468         (DADD): Likewise, but also remove previous comment about
 469         overflow checking.
 470
 471 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 472
 473         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 474         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 475         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 476         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 477         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 478         fields (i.e., add and move commas) so that they more closely
 479         match the MIPS ISA documentation opcode partitioning.
 480
 481 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 482
 483         * mips.igen (ADDI): Print immediate value.
 484         (BREAK): Print code.
 485         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 486         (SLL): Print "nop" specially, and don't run the code
 487         that does the shift for the "nop" case.
 488
 489 2001-11-17  Fred Fish  <fnf@redhat.com>
 490
 491         * sim-main.h (float_operation): Move enum declaration outside
 492         of _sim_cpu struct declaration.
 493
 494 2001-04-12  Jim Blandy  <jimb@redhat.com>
 495
 496         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 497         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 498         set of the FCSR.
 499         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 500         PENDING_FILL, and you can get the intended effect gracefully by
 501         calling PENDING_SCHED directly.
 502
 503 2001-02-23  Ben Elliston  <bje@redhat.com>
 504
 505         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 506         already defined elsewhere.
 507
 508 2001-02-19  Ben Elliston  <bje@redhat.com>
 509
 510         * sim-main.h (sim_monitor): Return an int.
 511         * interp.c (sim_monitor): Add return values.
 512         (signal_exception): Handle error conditions from sim_monitor.
 513
 514 2001-02-08  Ben Elliston  <bje@redhat.com>
 515
 516         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 517         (store_memory): Likewise, pass cia to sim_core_write*.
 518
 519 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 520
 521         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 522         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 523
 524 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 525
 526         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 527         * Makefile.in: Don't delete *.igen when cleaning directory.
 528
 529 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 530
 531         * m16.igen (break): Call SignalException not sim_engine_halt.
 532
 533 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 534
 535         From Jason Eckhardt:
 536         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 537
 538 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 539
 540         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 541
 542 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 543
 544         * mips.igen (do_dmultx): Fix typo.
 545
 546 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 547
 548         * configure: Regenerated to track ../common/aclocal.m4 changes.
 549
 550 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 551
 552         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 553
 554 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 555
 556         * sim-main.h (GPR_CLEAR): Define macro.
 557
 558 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 559
 560         * interp.c (decode_coproc): Output long using %lx and not %s.
 561
 562 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 563
 564         * interp.c (sim_open): Sort & extend dummy memory regions for
 565         --board=jmr3904 for eCos.
 566
 567 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 568
 569         * configure: Regenerated.
 570
 571 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 572
 573         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 574         calls, conditional on the simulator being in verbose mode.
 575
 576 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 577
 578         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 579         cache don't get ReservedInstruction traps.
 580
 581 1999-11-29  Mark Salter  <msalter@cygnus.com>
 582
 583         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 584         to clear status bits in sdisr register. This is how the hardware works.
 585
 586         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 587         being used by cygmon.
 588
 589 1999-11-11  Andrew Haley  <aph@cygnus.com>
 590
 591         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 592         instructions.
 593
 594 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 595
 596         * mips.igen (MULT): Correct previous mis-applied patch.
 597
 598 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 599
 600         * mips.igen (delayslot32): Handle sequence like
 601         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 602         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 603         (MULT): Actually pass the third register...
 604
 605 1999-09-03  Mark Salter  <msalter@cygnus.com>
 606
 607         * interp.c (sim_open): Added more memory aliases for additional
 608         hardware being touched by cygmon on jmr3904 board.
 609
 610 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 611
 612         * configure: Regenerated to track ../common/aclocal.m4 changes.
 613
 614 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 615
 616         * interp.c (sim_store_register): Handle case where client - GDB -
 617         specifies that a 4 byte register is 8 bytes in size.
 618         (sim_fetch_register): Ditto.
 619
 620 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 621
 622         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 623         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 624         (idt_monitor_base): Base address for IDT monitor traps.
 625         (pmon_monitor_base): Ditto for PMON.
 626         (lsipmon_monitor_base): Ditto for LSI PMON.
 627         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 628         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 629         (sim_firmware_command): New function.
 630         (mips_option_handler): Call it for OPTION_FIRMWARE.
 631         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 632         option was given, add no monitor by default.  Add BREAK hooks only if
 633         monitors are also there.
 634
 635 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 636
 637         * interp.c (sim_monitor): Flush output before reading input.
 638
 639 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 640
 641         * tconfig.in (SIM_HANDLES_LMA): Always define.
 642
 643 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 644
 645         From Mark Salter <msalter@cygnus.com>:
 646         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 647         (sim_open): Add setup for BSP board.
 648
 649 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 650
 651         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 652         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 653         them as unimplemented.
 654
 655 1999-05-08  Felix Lee  <flee@cygnus.com>
 656
 657         * configure: Regenerated to track ../common/aclocal.m4 changes.
 658
 659 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 660
 661         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 662
 663 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 664
 665         * configure.in: Any mips64vr5*-*-* target should have
 666         -DTARGET_ENABLE_FR=1.
 667         (default_endian): Any mips64vr*el-*-* target should default to
 668         LITTLE_ENDIAN.
 669         * configure: Re-generate.
 670
 671 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 672
 673         * mips.igen (ldl): Extend from _16_, not 32.
 674
 675 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 676
 677         * interp.c (sim_store_register): Force registers written to by GDB
 678         into an un-interpreted state.
 679
 680 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 681
 682         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 683         CPU, start periodic background I/O polls.
 684         (tx3904sio_poll): New function: periodic I/O poller.
 685
 686 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 687
 688         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 689
 690 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 691
 692         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 693         case statement.
 694
 695 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 696
 697         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 698         (load_word): Call SIM_CORE_SIGNAL hook on error.
 699         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 700         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 701         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 702         * sim-main.h (COP0_BADVADDR): Define.
 703         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 704         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 705         (_sim_cpu): Add exc_* fields to store register value snapshots.
 706         * mips.igen (*): Replace memory-related SignalException* calls
 707         with references to SIM_CORE_SIGNAL hook.
 708
 709         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 710         fix.
 711         * sim-main.c (*): Minor warning cleanups.
 712
 713 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 714
 715         * m16.igen (DADDIU5): Correct type-o.
 716
 717 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 718
 719         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 720         variables.
 721
 722 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 723
 724         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 725         to include path.
 726         (interp.o): Add dependency on itable.h
 727         (oengine.c, gencode): Delete remaining references.
 728         (BUILT_SRC_FROM_GEN): Clean up.
 729
 730 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 731
 732         * vr4run.c: New.
 733         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 734         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 735         tmp-run-hack) : New.
 736         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 737         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 738         Drop the "64" qualifier to get the HACK generator working.
 739         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 740         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 741         qualifier to get the hack generator working.
 742         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 743         (DSLL): Use do_dsll.
 744         (DSLLV): Use do_dsllv.
 745         (DSRA): Use do_dsra.
 746         (DSRL): Use do_dsrl.
 747         (DSRLV): Use do_dsrlv.
 748         (BC1): Move *vr4100 to get the HACK generator working.
 749         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 750         get the HACK generator working.
 751         (MACC) Rename to get the HACK generator working.
 752         (DMACC,MACCS,DMACCS): Add the 64.
 753
 754 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 755
 756         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 757         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 758
 759 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 760
 761     * mips/interp.c (DEBUG): Cleanups.
 762
 763 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 764
 765         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 766         (tx3904sio_tickle): fflush after a stdout character output.
 767
 768 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 769
 770         * interp.c (sim_close): Uninstall modules.
 771
 772 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 773
 774         * sim-main.h, interp.c (sim_monitor): Change to global
 775         function.
 776
 777 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 778
 779         * configure.in (vr4100): Only include vr4100 instructions in
 780         simulator.
 781         * configure: Re-generate.
 782         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 783
 784 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 785
 786         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 787         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 788         true alternative.
 789
 790         * configure.in (sim_default_gen, sim_use_gen): Replace with
 791         sim_gen.
 792         (--enable-sim-igen): Delete config option. Always using IGEN.
 793         * configure: Re-generate.
 794
 795         * Makefile.in (gencode): Kill, kill, kill.
 796         * gencode.c: Ditto.
 797
 798 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 799
 800         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 801         bit mips16 igen simulator.
 802         * configure: Re-generate.
 803
 804         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 805         as part of vr4100 ISA.
 806         * vr.igen: Mark all instructions as 64 bit only.
 807
 808 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 809
 810         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 811         Pacify GCC.
 812
 813 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 814
 815         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 816         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 817         * configure: Re-generate.
 818
 819         * m16.igen (BREAK): Define breakpoint instruction.
 820         (JALX32): Mark instruction as mips16 and not r3900.
 821         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 822
 823         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 824
 825 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 826
 827         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 828         insn as a debug breakpoint.
 829
 830         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 831         pending.slot_size.
 832         (PENDING_SCHED): Clean up trace statement.
 833         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 834         (PENDING_FILL): Delay write by only one cycle.
 835         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 836
 837         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 838         of pending writes.
 839         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 840         32 & 64.
 841         (pending_tick): Move incrementing of index to FOR statement.
 842         (pending_tick): Only update PENDING_OUT after a write has occured.
 843
 844         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 845         build simulator.
 846         * configure: Re-generate.
 847
 848         * interp.c (sim_engine_run OLD): Delete explicit call to
 849         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 850
 851 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 852
 853         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 854         interrupt level number to match changed SignalExceptionInterrupt
 855         macro.
 856
 857 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 858
 859         * interp.c: #include "itable.h" if WITH_IGEN.
 860         (get_insn_name): New function.
 861         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 862         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 863
 864 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 865
 866         * configure: Rebuilt to inhale new common/aclocal.m4.
 867
 868 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 869
 870         * dv-tx3904sio.c: Include sim-assert.h.
 871
 872 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 873
 874         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 875         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 876         Reorganize target-specific sim-hardware checks.
 877         * configure: rebuilt.
 878         * interp.c (sim_open): For tx39 target boards, set
 879         OPERATING_ENVIRONMENT, add tx3904sio devices.
 880         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 881         ROM executables.  Install dv-sockser into sim-modules list.
 882
 883         * dv-tx3904irc.c: Compiler warning clean-up.
 884         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 885         frequent hw-trace messages.
 886
 887 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 888
 889         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 890
 891 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 892
 893         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 894
 895         * vr.igen: New file.
 896         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 897         * mips.igen: Define vr4100 model. Include vr.igen.
 898 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 899
 900         * mips.igen (check_mf_hilo): Correct check.
 901
 902 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 903
 904         * sim-main.h (interrupt_event): Add prototype.
 905
 906         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 907         register_ptr, register_value.
 908         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 909
 910         * sim-main.h (tracefh): Make extern.
 911
 912 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 913
 914         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 915         Reduce unnecessarily high timer event frequency.
 916         * dv-tx3904cpu.c: Ditto for interrupt event.
 917
 918 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 919
 920         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 921         to allay warnings.
 922         (interrupt_event): Made non-static.
 923
 924         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 925         interchange of configuration values for external vs. internal
 926         clock dividers.
 927
 928 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 929
 930         * mips.igen (BREAK): Moved code to here for
 931         simulator-reserved break instructions.
 932         * gencode.c (build_instruction): Ditto.
 933         * interp.c (signal_exception): Code moved from here.  Non-
 934         reserved instructions now use exception vector, rather
 935         than halting sim.
 936         * sim-main.h: Moved magic constants to here.
 937
 938 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 939
 940         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 941         register upon non-zero interrupt event level, clear upon zero
 942         event value.
 943         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 944         by passing zero event value.
 945         (*_io_{read,write}_buffer): Endianness fixes.
 946         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 947         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 948
 949         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 950         serial I/O and timer module at base address 0xFFFF0000.
 951
 952 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 953
 954         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 955         and BigEndianCPU.
 956
 957 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 958
 959         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 960         parts.
 961         * configure: Update.
 962
 963 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 964
 965         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 966         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 967         * configure.in: Include tx3904tmr in hw_device list.
 968         * configure: Rebuilt.
 969         * interp.c (sim_open): Instantiate three timer instances.
 970         Fix address typo of tx3904irc instance.
 971
 972 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 973
 974         * interp.c (signal_exception): SystemCall exception now uses
 975         the exception vector.
 976
 977 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 978
 979         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 980         to allay warnings.
 981
 982 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 983
 984         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 985
 986 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 987
 988         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 989
 990         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 991         sim-main.h. Declare a struct hw_descriptor instead of struct
 992         hw_device_descriptor.
 993
 994 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 995
 996         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 997         right bits and then re-align left hand bytes to correct byte
 998         lanes.  Fix incorrect computation in do_store_left when loading
 999         bytes from second word.
1000
1001 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1002
1003         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1004         * interp.c (sim_open): Only create a device tree when HW is
1005         enabled.
1006
1007         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1008         * interp.c (signal_exception): Ditto.
1009
1010 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1011
1012         * gencode.c: Mark BEGEZALL as LIKELY.
1013
1014 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1015
1016         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1017         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1018
1019 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1020
1021         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1022         modules.  Recognize TX39 target with "mips*tx39" pattern.
1023         * configure: Rebuilt.
1024         * sim-main.h (*): Added many macros defining bits in
1025         TX39 control registers.
1026         (SignalInterrupt): Send actual PC instead of NULL.
1027         (SignalNMIReset): New exception type.
1028         * interp.c (board): New variable for future use to identify
1029         a particular board being simulated.
1030         (mips_option_handler,mips_options): Added "--board" option.
1031         (interrupt_event): Send actual PC.
1032         (sim_open): Make memory layout conditional on board setting.
1033         (signal_exception): Initial implementation of hardware interrupt
1034         handling.  Accept another break instruction variant for simulator
1035         exit.
1036         (decode_coproc): Implement RFE instruction for TX39.
1037         (mips.igen): Decode RFE instruction as such.
1038         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1039         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1040         bbegin to implement memory map.
1041         * dv-tx3904cpu.c: New file.
1042         * dv-tx3904irc.c: New file.
1043
1044 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1045
1046         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1047
1048 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1049
1050         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1051         with calls to check_div_hilo.
1052
1053 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1054
1055         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1056         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1057         Add special r3900 version of do_mult_hilo.
1058         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1059         with calls to check_mult_hilo.
1060         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1061         with calls to check_div_hilo.
1062
1063 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1064
1065         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1066         Document a replacement.
1067
1068 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1069
1070         * interp.c (sim_monitor): Make mon_printf work.
1071
1072 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1073
1074         * sim-main.h (INSN_NAME): New arg `cpu'.
1075
1076 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1077
1078         * configure: Regenerated to track ../common/aclocal.m4 changes.
1079
1080 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1081
1082         * configure: Regenerated to track ../common/aclocal.m4 changes.
1083         * config.in: Ditto.
1084
1085 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1086
1087         * acconfig.h: New file.
1088         * configure.in: Reverted change of Apr 24; use sinclude again.
1089
1090 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1091
1092         * configure: Regenerated to track ../common/aclocal.m4 changes.
1093         * config.in: Ditto.
1094
1095 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1096
1097         * configure.in: Don't call sinclude.
1098
1099 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1100
1101         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1102
1103 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1104
1105         * mips.igen (ERET): Implement.
1106
1107         * interp.c (decode_coproc): Return sign-extended EPC.
1108
1109         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1110
1111         * interp.c (signal_exception): Do not ignore Trap.
1112         (signal_exception): On TRAP, restart at exception address.
1113         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1114         (signal_exception): Update.
1115         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1116         so that TRAP instructions are caught.
1117
1118 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1119
1120         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1121         contains HI/LO access history.
1122         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1123         (HIACCESS, LOACCESS): Delete, replace with
1124         (HIHISTORY, LOHISTORY): New macros.
1125         (CHECKHILO): Delete all, moved to mips.igen
1126
1127         * gencode.c (build_instruction): Do not generate checks for
1128         correct HI/LO register usage.
1129
1130         * interp.c (old_engine_run): Delete checks for correct HI/LO
1131         register usage.
1132
1133         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1134         check_mf_cycles): New functions.
1135         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1136         do_divu, domultx, do_mult, do_multu): Use.
1137
1138         * tx.igen ("madd", "maddu"): Use.
1139
1140 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1141
1142         * mips.igen (DSRAV): Use function do_dsrav.
1143         (SRAV): Use new function do_srav.
1144
1145         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1146         (B): Sign extend 11 bit immediate.
1147         (EXT-B*): Shift 16 bit immediate left by 1.
1148         (ADDIU*): Don't sign extend immediate value.
1149
1150 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1151
1152         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1153
1154         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1155         functions.
1156
1157         * mips.igen (delayslot32, nullify_next_insn): New functions.
1158         (m16.igen): Always include.
1159         (do_*): Add more tracing.
1160
1161         * m16.igen (delayslot16): Add NIA argument, could be called by a
1162         32 bit MIPS16 instruction.
1163
1164         * interp.c (ifetch16): Move function from here.
1165         * sim-main.c (ifetch16): To here.
1166
1167         * sim-main.c (ifetch16, ifetch32): Update to match current
1168         implementations of LH, LW.
1169         (signal_exception): Don't print out incorrect hex value of illegal
1170         instruction.
1171
1172 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1173
1174         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1175         instruction.
1176
1177         * m16.igen: Implement MIPS16 instructions.
1178
1179         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1180         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1181         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1182         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1183         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1184         bodies of corresponding code from 32 bit insn to these.  Also used
1185         by MIPS16 versions of functions.
1186
1187         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1188         (IMEM16): Drop NR argument from macro.
1189
1190 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1191
1192         * Makefile.in (SIM_OBJS): Add sim-main.o.
1193
1194         * sim-main.h (address_translation, load_memory, store_memory,
1195         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1196         as INLINE_SIM_MAIN.
1197         (pr_addr, pr_uword64): Declare.
1198         (sim-main.c): Include when H_REVEALS_MODULE_P.
1199
1200         * interp.c (address_translation, load_memory, store_memory,
1201         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1202         from here.
1203         * sim-main.c: To here. Fix compilation problems.
1204
1205         * configure.in: Enable inlining.
1206         * configure: Re-config.
1207
1208 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1209
1210         * configure: Regenerated to track ../common/aclocal.m4 changes.
1211
1212 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1213
1214         * mips.igen: Include tx.igen.
1215         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1216         * tx.igen: New file, contains MADD and MADDU.
1217
1218         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1219         the hardwired constant `7'.
1220         (store_memory): Ditto.
1221         (LOADDRMASK): Move definition to sim-main.h.
1222
1223         mips.igen (MTC0): Enable for r3900.
1224         (ADDU): Add trace.
1225
1226         mips.igen (do_load_byte): Delete.
1227         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1228         do_store_right): New functions.
1229         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1230
1231         configure.in: Let the tx39 use igen again.
1232         configure: Update.
1233
1234 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1235
1236         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1237         not an address sized quantity.  Return zero for cache sizes.
1238
1239 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1240
1241         * mips.igen (r3900): r3900 does not support 64 bit integer
1242         operations.
1243
1244 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1245
1246         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1247         than igen one.
1248         * configure : Rebuild.
1249
1250 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1251
1252         * configure: Regenerated to track ../common/aclocal.m4 changes.
1253
1254 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1255
1256         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1257
1258 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1259
1260         * configure: Regenerated to track ../common/aclocal.m4 changes.
1261         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1262
1263 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1264
1265         * configure: Regenerated to track ../common/aclocal.m4 changes.
1266
1267 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1268
1269         * interp.c (Max, Min): Comment out functions. Not yet used.
1270
1271 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1272
1273         * configure: Regenerated to track ../common/aclocal.m4 changes.
1274
1275 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1276
1277         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1278         configurable settings for stand-alone simulator.
1279
1280         * configure.in: Added X11 search, just in case.
1281
1282         * configure: Regenerated.
1283
1284 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1285
1286         * interp.c (sim_write, sim_read, load_memory, store_memory):
1287         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1288
1289 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1290
1291         * sim-main.h (GETFCC): Return an unsigned value.
1292
1293 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1294
1295         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1296         (DADD): Result destination is RD not RT.
1297
1298 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1299
1300         * sim-main.h (HIACCESS, LOACCESS): Always define.
1301
1302         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1303
1304         * interp.c (sim_info): Delete.
1305
1306 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1307
1308         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1309         (mips_option_handler): New argument `cpu'.
1310         (sim_open): Update call to sim_add_option_table.
1311
1312 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1313
1314         * mips.igen (CxC1): Add tracing.
1315
1316 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1317
1318         * sim-main.h (Max, Min): Declare.
1319
1320         * interp.c (Max, Min): New functions.
1321
1322         * mips.igen (BC1): Add tracing.
1323
1324 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1325
1326         * interp.c Added memory map for stack in vr4100
1327
1328 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1329
1330         * interp.c (load_memory): Add missing "break"'s.
1331
1332 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1333
1334         * interp.c (sim_store_register, sim_fetch_register): Pass in
1335         length parameter.  Return -1.
1336
1337 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1338
1339         * interp.c: Added hardware init hook, fixed warnings.
1340
1341 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1342
1343         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1344
1345 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1346
1347         * interp.c (ifetch16): New function.
1348
1349         * sim-main.h (IMEM32): Rename IMEM.
1350         (IMEM16_IMMED): Define.
1351         (IMEM16): Define.
1352         (DELAY_SLOT): Update.
1353
1354         * m16run.c (sim_engine_run): New file.
1355
1356         * m16.igen: All instructions except LB.
1357         (LB): Call do_load_byte.
1358         * mips.igen (do_load_byte): New function.
1359         (LB): Call do_load_byte.
1360
1361         * mips.igen: Move spec for insn bit size and high bit from here.
1362         * Makefile.in (tmp-igen, tmp-m16): To here.
1363
1364         * m16.dc: New file, decode mips16 instructions.
1365
1366         * Makefile.in (SIM_NO_ALL): Define.
1367         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1368
1369 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1370
1371         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1372         point unit to 32 bit registers.
1373         * configure: Re-generate.
1374
1375 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1376
1377         * configure.in (sim_use_gen): Make IGEN the default simulator
1378         generator for generic 32 and 64 bit mips targets.
1379         * configure: Re-generate.
1380
1381 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1382
1383         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1384         bitsize.
1385
1386         * interp.c (sim_fetch_register, sim_store_register): Read/write
1387         FGR from correct location.
1388         (sim_open): Set size of FGR's according to
1389         WITH_TARGET_FLOATING_POINT_BITSIZE.
1390
1391         * sim-main.h (FGR): Store floating point registers in a separate
1392         array.
1393
1394 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1395
1396         * configure: Regenerated to track ../common/aclocal.m4 changes.
1397
1398 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1399
1400         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1401
1402         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1403
1404         * interp.c (pending_tick): New function.  Deliver pending writes.
1405
1406         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1407         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1408         it can handle mixed sized quantites and single bits.
1409
1410 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1411
1412         * interp.c (oengine.h): Do not include when building with IGEN.
1413         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1414         (sim_info): Ditto for PROCESSOR_64BIT.
1415         (sim_monitor): Replace ut_reg with unsigned_word.
1416         (*): Ditto for t_reg.
1417         (LOADDRMASK): Define.
1418         (sim_open): Remove defunct check that host FP is IEEE compliant,
1419         using software to emulate floating point.
1420         (value_fpr, ...): Always compile, was conditional on HASFPU.
1421
1422 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1423
1424         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1425         size.
1426
1427         * interp.c (SD, CPU): Define.
1428         (mips_option_handler): Set flags in each CPU.
1429         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1430         (sim_close): Do not clear STATE, deleted anyway.
1431         (sim_write, sim_read): Assume CPU zero's vm should be used for
1432         data transfers.
1433         (sim_create_inferior): Set the PC for all processors.
1434         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1435         argument.
1436         (mips16_entry): Pass correct nr of args to store_word, load_word.
1437         (ColdReset): Cold reset all cpu's.
1438         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1439         (sim_monitor, load_memory, store_memory, signal_exception): Use
1440         `CPU' instead of STATE_CPU.
1441
1442
1443         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1444         SD or CPU_.
1445
1446         * sim-main.h (signal_exception): Add sim_cpu arg.
1447         (SignalException*): Pass both SD and CPU to signal_exception.
1448         * interp.c (signal_exception): Update.
1449
1450         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1451         Ditto
1452         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1453         address_translation): Ditto
1454         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1455
1456 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1457
1458         * configure: Regenerated to track ../common/aclocal.m4 changes.
1459
1460 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1461
1462         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1463
1464         * mips.igen (model): Map processor names onto BFD name.
1465
1466         * sim-main.h (CPU_CIA): Delete.
1467         (SET_CIA, GET_CIA): Define
1468
1469 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1470
1471         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1472         regiser.
1473
1474         * configure.in (default_endian): Configure a big-endian simulator
1475         by default.
1476         * configure: Re-generate.
1477
1478 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1479
1480         * configure: Regenerated to track ../common/aclocal.m4 changes.
1481
1482 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1483
1484         * interp.c (sim_monitor): Handle Densan monitor outbyte
1485         and inbyte functions.
1486
1487 1997-12-29  Felix Lee  <flee@cygnus.com>
1488
1489         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1490
1491 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1492
1493         * Makefile.in (tmp-igen): Arrange for $zero to always be
1494         reset to zero after every instruction.
1495
1496 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1497
1498         * configure: Regenerated to track ../common/aclocal.m4 changes.
1499         * config.in: Ditto.
1500
1501 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1502
1503         * mips.igen (MSUB): Fix to work like MADD.
1504         * gencode.c (MSUB): Similarly.
1505
1506 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1507
1508         * configure: Regenerated to track ../common/aclocal.m4 changes.
1509
1510 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1511
1512         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1513
1514 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1515
1516         * sim-main.h (sim-fpu.h): Include.
1517
1518         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1519         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1520         using host independant sim_fpu module.
1521
1522 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1523
1524         * interp.c (signal_exception): Report internal errors with SIGABRT
1525         not SIGQUIT.
1526
1527         * sim-main.h (C0_CONFIG): New register.
1528         (signal.h): No longer include.
1529
1530         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1531
1532 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1533
1534         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1535
1536 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1537
1538         * mips.igen: Tag vr5000 instructions.
1539         (ANDI): Was missing mipsIV model, fix assembler syntax.
1540         (do_c_cond_fmt): New function.
1541         (C.cond.fmt): Handle mips I-III which do not support CC field
1542         separatly.
1543         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1544         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1545         in IV3.2 spec.
1546         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1547         vr5000 which saves LO in a GPR separatly.
1548
1549         * configure.in (enable-sim-igen): For vr5000, select vr5000
1550         specific instructions.
1551         * configure: Re-generate.
1552
1553 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1554
1555         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1556
1557         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1558         fmt_uninterpreted_64 bit cases to switch.  Convert to
1559         fmt_formatted,
1560
1561         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1562
1563         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1564         as specified in IV3.2 spec.
1565         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1566
1567 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1568
1569         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1570         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1571         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1572         PENDING_FILL versions of instructions.  Simplify.
1573         (X): New function.
1574         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1575         instructions.
1576         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1577         a signed value.
1578         (MTHI, MFHI): Disable code checking HI-LO.
1579
1580         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1581         global.
1582         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1583
1584 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1585
1586         * gencode.c (build_mips16_operands): Replace IPC with cia.
1587
1588         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1589         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1590         IPC to `cia'.
1591         (UndefinedResult): Replace function with macro/function
1592         combination.
1593         (sim_engine_run): Don't save PC in IPC.
1594
1595         * sim-main.h (IPC): Delete.
1596
1597
1598         * interp.c (signal_exception, store_word, load_word,
1599         address_translation, load_memory, store_memory, cache_op,
1600         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1601         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1602         current instruction address - cia - argument.
1603         (sim_read, sim_write): Call address_translation directly.
1604         (sim_engine_run): Rename variable vaddr to cia.
1605         (signal_exception): Pass cia to sim_monitor
1606
1607         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1608         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1609         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1610
1611         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1612         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1613         SIM_ASSERT.
1614
1615         * interp.c (signal_exception): Pass restart address to
1616         sim_engine_restart.
1617
1618         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1619         idecode.o): Add dependency.
1620
1621         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1622         Delete definitions
1623         (DELAY_SLOT): Update NIA not PC with branch address.
1624         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1625
1626         * mips.igen: Use CIA not PC in branch calculations.
1627         (illegal): Call SignalException.
1628         (BEQ, ADDIU): Fix assembler.
1629
1630 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1631
1632         * m16.igen (JALX): Was missing.
1633
1634         * configure.in (enable-sim-igen): New configuration option.
1635         * configure: Re-generate.
1636
1637         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1638
1639         * interp.c (load_memory, store_memory): Delete parameter RAW.
1640         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1641         bypassing {load,store}_memory.
1642
1643         * sim-main.h (ByteSwapMem): Delete definition.
1644
1645         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1646
1647         * interp.c (sim_do_command, sim_commands): Delete mips specific
1648         commands.  Handled by module sim-options.
1649
1650         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1651         (WITH_MODULO_MEMORY): Define.
1652
1653         * interp.c (sim_info): Delete code printing memory size.
1654
1655         * interp.c (mips_size): Nee sim_size, delete function.
1656         (power2): Delete.
1657         (monitor, monitor_base, monitor_size): Delete global variables.
1658         (sim_open, sim_close): Delete code creating monitor and other
1659         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1660         manage memory regions.
1661         (load_memory, store_memory): Use sim-core for memory model.
1662
1663         * interp.c (address_translation): Delete all memory map code
1664         except line forcing 32 bit addresses.
1665
1666 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1667
1668         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1669         trace options.
1670
1671         * interp.c (logfh, logfile): Delete globals.
1672         (sim_open, sim_close): Delete code opening & closing log file.
1673         (mips_option_handler): Delete -l and -n options.
1674         (OPTION mips_options): Ditto.
1675
1676         * interp.c (OPTION mips_options): Rename option trace to dinero.
1677         (mips_option_handler): Update.
1678
1679 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1680
1681         * interp.c (fetch_str): New function.
1682         (sim_monitor): Rewrite using sim_read & sim_write.
1683         (sim_open): Check magic number.
1684         (sim_open): Write monitor vectors into memory using sim_write.
1685         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1686         (sim_read, sim_write): Simplify - transfer data one byte at a
1687         time.
1688         (load_memory, store_memory): Clarify meaning of parameter RAW.
1689
1690         * sim-main.h (isHOST): Defete definition.
1691         (isTARGET): Mark as depreciated.
1692         (address_translation): Delete parameter HOST.
1693
1694         * interp.c (address_translation): Delete parameter HOST.
1695
1696 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1697
1698         * mips.igen:
1699
1700         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1701         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1702
1703 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1704
1705         * mips.igen: Add model filter field to records.
1706
1707 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1708
1709         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1710
1711         interp.c (sim_engine_run): Do not compile function sim_engine_run
1712         when WITH_IGEN == 1.
1713
1714         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1715         target architecture.
1716
1717         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1718         igen. Replace with configuration variables sim_igen_flags /
1719         sim_m16_flags.
1720
1721         * m16.igen: New file.  Copy mips16 insns here.
1722         * mips.igen: From here.
1723
1724 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1725
1726         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1727         to top.
1728         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1729
1730 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1731
1732         * gencode.c (build_instruction): Follow sim_write's lead in using
1733         BigEndianMem instead of !ByteSwapMem.
1734
1735 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1736
1737         * configure.in (sim_gen): Dependent on target, select type of
1738         generator.  Always select old style generator.
1739
1740         configure: Re-generate.
1741
1742         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1743         targets.
1744         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1745         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1746         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1747         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1748         SIM_@sim_gen@_*, set by autoconf.
1749
1750 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1751
1752         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1753
1754         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1755         CURRENT_FLOATING_POINT instead.
1756
1757         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1758         (address_translation): Raise exception InstructionFetch when
1759         translation fails and isINSTRUCTION.
1760
1761         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1762         sim_engine_run): Change type of of vaddr and paddr to
1763         address_word.
1764         (address_translation, prefetch, load_memory, store_memory,
1765         cache_op): Change type of vAddr and pAddr to address_word.
1766
1767         * gencode.c (build_instruction): Change type of vaddr and paddr to
1768         address_word.
1769
1770 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1771
1772         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1773         macro to obtain result of ALU op.
1774
1775 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1776
1777         * interp.c (sim_info): Call profile_print.
1778
1779 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1780
1781         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1782
1783         * sim-main.h (WITH_PROFILE): Do not define, defined in
1784         common/sim-config.h.  Use sim-profile module.
1785         (simPROFILE): Delete defintion.
1786
1787         * interp.c (PROFILE): Delete definition.
1788         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1789         (sim_close): Delete code writing profile histogram.
1790         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1791         Delete.
1792         (sim_engine_run): Delete code profiling the PC.
1793
1794 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1795
1796         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1797
1798         * interp.c (sim_monitor): Make register pointers of type
1799         unsigned_word*.
1800
1801         * sim-main.h: Make registers of type unsigned_word not
1802         signed_word.
1803
1804 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1805
1806         * interp.c (sync_operation): Rename from SyncOperation, make
1807         global, add SD argument.
1808         (prefetch): Rename from Prefetch, make global, add SD argument.
1809         (decode_coproc): Make global.
1810
1811         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1812
1813         * gencode.c (build_instruction): Generate DecodeCoproc not
1814         decode_coproc calls.
1815
1816         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1817         (SizeFGR): Move to sim-main.h
1818         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1819         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1820         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1821         sim-main.h.
1822         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1823         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1824         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1825         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1826         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1827         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1828
1829         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1830         exception.
1831         (sim-alu.h): Include.
1832         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1833         (sim_cia): Typedef to instruction_address.
1834
1835 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1836
1837         * Makefile.in (interp.o): Rename generated file engine.c to
1838         oengine.c.
1839
1840         * interp.c: Update.
1841
1842 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1843
1844         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1845
1846 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1847
1848         * gencode.c (build_instruction): For "FPSQRT", output correct
1849         number of arguments to Recip.
1850
1851 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1852
1853         * Makefile.in (interp.o): Depends on sim-main.h
1854
1855         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1856
1857         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1858         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1859         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1860         STATE, DSSTATE): Define
1861         (GPR, FGRIDX, ..): Define.
1862
1863         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1864         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1865         (GPR, FGRIDX, ...): Delete macros.
1866
1867         * interp.c: Update names to match defines from sim-main.h
1868
1869 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1870
1871         * interp.c (sim_monitor): Add SD argument.
1872         (sim_warning): Delete.  Replace calls with calls to
1873         sim_io_eprintf.
1874         (sim_error): Delete. Replace calls with sim_io_error.
1875         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1876         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1877         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1878         argument.
1879         (mips_size): Rename from sim_size. Add SD argument.
1880
1881         * interp.c (simulator): Delete global variable.
1882         (callback): Delete global variable.
1883         (mips_option_handler, sim_open, sim_write, sim_read,
1884         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1885         sim_size,sim_monitor): Use sim_io_* not callback->*.
1886         (sim_open): ZALLOC simulator struct.
1887         (PROFILE): Do not define.
1888
1889 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1890
1891         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1892         support.h with corresponding code.
1893
1894         * sim-main.h (word64, uword64), support.h: Move definition to
1895         sim-main.h.
1896         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1897
1898         * support.h: Delete
1899         * Makefile.in: Update dependencies
1900         * interp.c: Do not include.
1901
1902 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1903
1904         * interp.c (address_translation, load_memory, store_memory,
1905         cache_op): Rename to from AddressTranslation et.al., make global,
1906         add SD argument
1907
1908         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1909         CacheOp): Define.
1910
1911         * interp.c (SignalException): Rename to signal_exception, make
1912         global.
1913
1914         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1915
1916         * sim-main.h (SignalException, SignalExceptionInterrupt,
1917         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1918         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1919         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1920         Define.
1921
1922         * interp.c, support.h: Use.
1923
1924 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1925
1926         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1927         to value_fpr / store_fpr. Add SD argument.
1928         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1929         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1930
1931         * sim-main.h (ValueFPR, StoreFPR): Define.
1932
1933 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1934
1935         * interp.c (sim_engine_run): Check consistency between configure
1936         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1937         and HASFPU.
1938
1939         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1940         (mips_fpu): Configure WITH_FLOATING_POINT.
1941         (mips_endian): Configure WITH_TARGET_ENDIAN.
1942         * configure: Update.
1943
1944 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1945
1946         * configure: Regenerated to track ../common/aclocal.m4 changes.
1947
1948 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1949
1950         * configure: Regenerated.
1951
1952 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1953
1954         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1955
1956 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1957
1958         * gencode.c (print_igen_insn_models): Assume certain architectures
1959         include all mips* instructions.
1960         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1961         instruction.
1962
1963         * Makefile.in (tmp.igen): Add target. Generate igen input from
1964         gencode file.
1965
1966         * gencode.c (FEATURE_IGEN): Define.
1967         (main): Add --igen option.  Generate output in igen format.
1968         (process_instructions): Format output according to igen option.
1969         (print_igen_insn_format): New function.
1970         (print_igen_insn_models): New function.
1971         (process_instructions): Only issue warnings and ignore
1972         instructions when no FEATURE_IGEN.
1973
1974 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1975
1976         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1977         MIPS targets.
1978
1979 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1980
1981         * configure: Regenerated to track ../common/aclocal.m4 changes.
1982
1983 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1984
1985         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1986         SIM_RESERVED_BITS): Delete, moved to common.
1987         (SIM_EXTRA_CFLAGS): Update.
1988
1989 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1990
1991         * configure.in: Configure non-strict memory alignment.
1992         * configure: Regenerated to track ../common/aclocal.m4 changes.
1993
1994 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1995
1996         * configure: Regenerated to track ../common/aclocal.m4 changes.
1997
1998 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1999
2000         * gencode.c (SDBBP,DERET): Added (3900) insns.
2001         (RFE): Turn on for 3900.
2002         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2003         (dsstate): Made global.
2004         (SUBTARGET_R3900): Added.
2005         (CANCELDELAYSLOT): New.
2006         (SignalException): Ignore SystemCall rather than ignore and
2007         terminate.  Add DebugBreakPoint handling.
2008         (decode_coproc): New insns RFE, DERET; and new registers Debug
2009         and DEPC protected by SUBTARGET_R3900.
2010         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2011         bits explicitly.
2012         * Makefile.in,configure.in: Add mips subtarget option.
2013         * configure: Update.
2014
2015 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2016
2017         * gencode.c: Add r3900 (tx39).
2018
2019
2020 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2021
2022         * gencode.c (build_instruction): Don't need to subtract 4 for
2023         JALR, just 2.
2024
2025 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2026
2027         * interp.c: Correct some HASFPU problems.
2028
2029 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2030
2031         * configure: Regenerated to track ../common/aclocal.m4 changes.
2032
2033 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2034
2035         * interp.c (mips_options): Fix samples option short form, should
2036         be `x'.
2037
2038 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2039
2040         * interp.c (sim_info): Enable info code.  Was just returning.
2041
2042 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2043
2044         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2045         MFC0.
2046
2047 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2048
2049         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2050         constants.
2051         (build_instruction): Ditto for LL.
2052
2053 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2054
2055         * configure: Regenerated to track ../common/aclocal.m4 changes.
2056
2057 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2058
2059         * configure: Regenerated to track ../common/aclocal.m4 changes.
2060         * config.in: Ditto.
2061
2062 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2063
2064         * interp.c (sim_open): Add call to sim_analyze_program, update
2065         call to sim_config.
2066
2067 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2068
2069         * interp.c (sim_kill): Delete.
2070         (sim_create_inferior): Add ABFD argument. Set PC from same.
2071         (sim_load): Move code initializing trap handlers from here.
2072         (sim_open): To here.
2073         (sim_load): Delete, use sim-hload.c.
2074
2075         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2076
2077 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2078
2079         * configure: Regenerated to track ../common/aclocal.m4 changes.
2080         * config.in: Ditto.
2081
2082 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2083
2084         * interp.c (sim_open): Add ABFD argument.
2085         (sim_load): Move call to sim_config from here.
2086         (sim_open): To here.  Check return status.
2087
2088 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2089
2090         * gencode.c (build_instruction): Two arg MADD should
2091         not assign result to $0.
2092
2093 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2094
2095         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2096         * sim/mips/configure.in: Regenerate.
2097
2098 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2099
2100         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2101         signed8, unsigned8 et.al. types.
2102
2103         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2104         hosts when selecting subreg.
2105
2106 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2107
2108         * interp.c (sim_engine_run): Reset the ZERO register to zero
2109         regardless of FEATURE_WARN_ZERO.
2110         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2111
2112 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2113
2114         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2115         (SignalException): For BreakPoints ignore any mode bits and just
2116         save the PC.
2117         (SignalException): Always set the CAUSE register.
2118
2119 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2120
2121         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2122         exception has been taken.
2123
2124         * interp.c: Implement the ERET and mt/f sr instructions.
2125
2126 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2127
2128         * interp.c (SignalException): Don't bother restarting an
2129         interrupt.
2130
2131 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2132
2133         * interp.c (SignalException): Really take an interrupt.
2134         (interrupt_event): Only deliver interrupts when enabled.
2135
2136 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2137
2138         * interp.c (sim_info): Only print info when verbose.
2139         (sim_info) Use sim_io_printf for output.
2140
2141 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2142
2143         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2144         mips architectures.
2145
2146 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2147
2148         * interp.c (sim_do_command): Check for common commands if a
2149         simulator specific command fails.
2150
2151 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2152
2153         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2154         and simBE when DEBUG is defined.
2155
2156 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2157
2158         * interp.c (interrupt_event): New function.  Pass exception event
2159         onto exception handler.
2160
2161         * configure.in: Check for stdlib.h.
2162         * configure: Regenerate.
2163
2164         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2165         variable declaration.
2166         (build_instruction): Initialize memval1.
2167         (build_instruction): Add UNUSED attribute to byte, bigend,
2168         reverse.
2169         (build_operands): Ditto.
2170
2171         * interp.c: Fix GCC warnings.
2172         (sim_get_quit_code): Delete.
2173
2174         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2175         * Makefile.in: Ditto.
2176         * configure: Re-generate.
2177
2178         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2179
2180 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2181
2182         * interp.c (mips_option_handler): New function parse argumes using
2183         sim-options.
2184         (myname): Replace with STATE_MY_NAME.
2185         (sim_open): Delete check for host endianness - performed by
2186         sim_config.
2187         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2188         (sim_open): Move much of the initialization from here.
2189         (sim_load): To here.  After the image has been loaded and
2190         endianness set.
2191         (sim_open): Move ColdReset from here.
2192         (sim_create_inferior): To here.
2193         (sim_open): Make FP check less dependant on host endianness.
2194
2195         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2196         run.
2197         * interp.c (sim_set_callbacks): Delete.
2198
2199         * interp.c (membank, membank_base, membank_size): Replace with
2200         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2201         (sim_open): Remove call to callback->init. gdb/run do this.
2202
2203         * interp.c: Update
2204
2205         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2206
2207         * interp.c (big_endian_p): Delete, replaced by
2208         current_target_byte_order.
2209
2210 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2211
2212         * interp.c (host_read_long, host_read_word, host_swap_word,
2213         host_swap_long): Delete. Using common sim-endian.
2214         (sim_fetch_register, sim_store_register): Use H2T.
2215         (pipeline_ticks): Delete.  Handled by sim-events.
2216         (sim_info): Update.
2217         (sim_engine_run): Update.
2218
2219 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2220
2221         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2222         reason from here.
2223         (SignalException): To here. Signal using sim_engine_halt.
2224         (sim_stop_reason): Delete, moved to common.
2225
2226 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2227
2228         * interp.c (sim_open): Add callback argument.
2229         (sim_set_callbacks): Delete SIM_DESC argument.
2230         (sim_size): Ditto.
2231
2232 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2233
2234         * Makefile.in (SIM_OBJS): Add common modules.
2235
2236         * interp.c (sim_set_callbacks): Also set SD callback.
2237         (set_endianness, xfer_*, swap_*): Delete.
2238         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2239         Change to functions using sim-endian macros.
2240         (control_c, sim_stop): Delete, use common version.
2241         (simulate): Convert into.
2242         (sim_engine_run): This function.
2243         (sim_resume): Delete.
2244
2245         * interp.c (simulation): New variable - the simulator object.
2246         (sim_kind): Delete global - merged into simulation.
2247         (sim_load): Cleanup.  Move PC assignment from here.
2248         (sim_create_inferior): To here.
2249
2250         * sim-main.h: New file.
2251         * interp.c (sim-main.h): Include.
2252
2253 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2254
2255         * configure: Regenerated to track ../common/aclocal.m4 changes.
2256
2257 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2258
2259         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2260
2261 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2262
2263         * gencode.c (build_instruction): DIV instructions: check
2264         for division by zero and integer overflow before using
2265         host's division operation.
2266
2267 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2268
2269         * Makefile.in (SIM_OBJS): Add sim-load.o.
2270         * interp.c: #include bfd.h.
2271         (target_byte_order): Delete.
2272         (sim_kind, myname, big_endian_p): New static locals.
2273         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2274         after argument parsing.  Recognize -E arg, set endianness accordingly.
2275         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2276         load file into simulator.  Set PC from bfd.
2277         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2278         (set_endianness): Use big_endian_p instead of target_byte_order.
2279
2280 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2281
2282         * interp.c (sim_size): Delete prototype - conflicts with
2283         definition in remote-sim.h.  Correct definition.
2284
2285 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2286
2287         * configure: Regenerated to track ../common/aclocal.m4 changes.
2288         * config.in: Ditto.
2289
2290 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2291
2292         * interp.c (sim_open): New arg `kind'.
2293
2294         * configure: Regenerated to track ../common/aclocal.m4 changes.
2295
2296 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2297
2298         * configure: Regenerated to track ../common/aclocal.m4 changes.
2299
2300 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2301
2302         * interp.c (sim_open): Set optind to 0 before calling getopt.
2303
2304 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2305
2306         * configure: Regenerated to track ../common/aclocal.m4 changes.
2307
2308 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2309
2310         * interp.c : Replace uses of pr_addr with pr_uword64
2311         where the bit length is always 64 independent of SIM_ADDR.
2312         (pr_uword64) : added.
2313
2314 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2315
2316         * configure: Re-generate.
2317
2318 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2319
2320         * configure: Regenerate to track ../common/aclocal.m4 changes.
2321
2322 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2323
2324         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2325         in argv form.
2326         (other sim_*): New SIM_DESC argument.
2327
2328 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2329
2330         * interp.c: Fix printing of addresses for non-64-bit targets.
2331         (pr_addr): Add function to print address based on size.
2332
2333 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2334
2335         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2336
2337 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2338
2339         * gencode.c (build_mips16_operands): Correct computation of base
2340         address for extended PC relative instruction.
2341
2342 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2343
2344         * interp.c (mips16_entry): Add support for floating point cases.
2345         (SignalException): Pass floating point cases to mips16_entry.
2346         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2347         registers.
2348         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2349         or fmt_word.
2350         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2351         and then set the state to fmt_uninterpreted.
2352         (COP_SW): Temporarily set the state to fmt_word while calling
2353         ValueFPR.
2354
2355 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2356
2357         * gencode.c (build_instruction): The high order may be set in the
2358         comparison flags at any ISA level, not just ISA 4.
2359
2360 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2361
2362         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2363         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2364         * configure.in: sinclude ../common/aclocal.m4.
2365         * configure: Regenerated.
2366
2367 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2368
2369         * configure: Rebuild after change to aclocal.m4.
2370
2371 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2372
2373         * configure configure.in Makefile.in:  Update to new configure
2374         scheme which is more compatible with WinGDB builds.
2375         * configure.in:  Improve comment on how to run autoconf.
2376         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2377         * Makefile.in:  Use autoconf substitution to install common
2378         makefile fragment.
2379
2380 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2381
2382         * gencode.c (build_instruction): Use BigEndianCPU instead of
2383         ByteSwapMem.
2384
2385 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2386
2387         * interp.c (sim_monitor): Make output to stdout visible in
2388         wingdb's I/O log window.
2389
2390 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2391
2392         * support.h: Undo previous change to SIGTRAP
2393         and SIGQUIT values.
2394
2395 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2396
2397         * interp.c (store_word, load_word): New static functions.
2398         (mips16_entry): New static function.
2399         (SignalException): Look for mips16 entry and exit instructions.
2400         (simulate): Use the correct index when setting fpr_state after
2401         doing a pending move.
2402
2403 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2404
2405         * interp.c: Fix byte-swapping code throughout to work on
2406         both little- and big-endian hosts.
2407
2408 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2409
2410         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2411         with gdb/config/i386/xm-windows.h.
2412
2413 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2414
2415         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2416         that messes up arithmetic shifts.
2417
2418 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2419
2420         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2421         SIGTRAP and SIGQUIT for _WIN32.
2422
2423 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2424
2425         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2426         force a 64 bit multiplication.
2427         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2428         destination register is 0, since that is the default mips16 nop
2429         instruction.
2430
2431 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2432
2433         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2434         (build_endian_shift): Don't check proc64.
2435         (build_instruction): Always set memval to uword64.  Cast op2 to
2436         uword64 when shifting it left in memory instructions.  Always use
2437         the same code for stores--don't special case proc64.
2438
2439         * gencode.c (build_mips16_operands): Fix base PC value for PC
2440         relative operands.
2441         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2442         jal instruction.
2443         * interp.c (simJALDELAYSLOT): Define.
2444         (JALDELAYSLOT): Define.
2445         (INDELAYSLOT, INJALDELAYSLOT): Define.
2446         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2447
2448 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2449
2450         * interp.c (sim_open): add flush_cache as a PMON routine
2451         (sim_monitor): handle flush_cache by ignoring it
2452
2453 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2454
2455         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2456         BigEndianMem.
2457         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2458         (BigEndianMem): Rename to ByteSwapMem and change sense.
2459         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2460         BigEndianMem references to !ByteSwapMem.
2461         (set_endianness): New function, with prototype.
2462         (sim_open): Call set_endianness.
2463         (sim_info): Use simBE instead of BigEndianMem.
2464         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2465         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2466         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2467         ifdefs, keeping the prototype declaration.
2468         (swap_word): Rewrite correctly.
2469         (ColdReset): Delete references to CONFIG.  Delete endianness related
2470         code; moved to set_endianness.
2471
2472 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2473
2474         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2475         * interp.c (CHECKHILO): Define away.
2476         (simSIGINT): New macro.
2477         (membank_size): Increase from 1MB to 2MB.
2478         (control_c): New function.
2479         (sim_resume): Rename parameter signal to signal_number.  Add local
2480         variable prev.  Call signal before and after simulate.
2481         (sim_stop_reason): Add simSIGINT support.
2482         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2483         functions always.
2484         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2485         if logfh is NULL.
2486         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2487         a call to sim_warning.
2488
2489 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2490
2491         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2492         16 bit instructions.
2493
2494 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2495
2496         Add support for mips16 (16 bit MIPS implementation):
2497         * gencode.c (inst_type): Add mips16 instruction encoding types.
2498         (GETDATASIZEINSN): Define.
2499         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2500         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2501         mtlo.
2502         (MIPS16_DECODE): New table, for mips16 instructions.
2503         (bitmap_val): New static function.
2504         (struct mips16_op): Define.
2505         (mips16_op_table): New table, for mips16 operands.
2506         (build_mips16_operands): New static function.
2507         (process_instructions): If PC is odd, decode a mips16
2508         instruction.  Break out instruction handling into new
2509         build_instruction function.
2510         (build_instruction): New static function, broken out of
2511         process_instructions.  Check modifiers rather than flags for SHIFT
2512         bit count and m[ft]{hi,lo} direction.
2513         (usage): Pass program name to fprintf.
2514         (main): Remove unused variable this_option_optind.  Change
2515         ``*loptarg++'' to ``loptarg++''.
2516         (my_strtoul): Parenthesize && within ||.
2517         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2518         (simulate): If PC is odd, fetch a 16 bit instruction, and
2519         increment PC by 2 rather than 4.
2520         * configure.in: Add case for mips16*-*-*.
2521         * configure: Rebuild.
2522
2523 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2524
2525         * interp.c: Allow -t to enable tracing in standalone simulator.
2526         Fix garbage output in trace file and error messages.
2527
2528 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2529
2530         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2531         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2532         * configure.in: Simplify using macros in ../common/aclocal.m4.
2533         * configure: Regenerated.
2534         * tconfig.in: New file.
2535
2536 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2537
2538         * interp.c: Fix bugs in 64-bit port.
2539         Use ansi function declarations for msvc compiler.
2540         Initialize and test file pointer in trace code.
2541         Prevent duplicate definition of LAST_EMED_REGNUM.
2542
2543 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2544
2545         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2546
2547 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2548
2549         * interp.c (SignalException): Check for explicit terminating
2550         breakpoint value.
2551         * gencode.c: Pass instruction value through SignalException()
2552         calls for Trap, Breakpoint and Syscall.
2553
2554 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2555
2556         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2557         only used on those hosts that provide it.
2558         * configure.in: Add sqrt() to list of functions to be checked for.
2559         * config.in: Re-generated.
2560         * configure: Re-generated.
2561
2562 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2563
2564         * gencode.c (process_instructions): Call build_endian_shift when
2565         expanding STORE RIGHT, to fix swr.
2566         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2567         clear the high bits.
2568         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2569         Fix float to int conversions to produce signed values.
2570
2571 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2572
2573         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2574         (process_instructions): Correct handling of nor instruction.
2575         Correct shift count for 32 bit shift instructions. Correct sign
2576         extension for arithmetic shifts to not shift the number of bits in
2577         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2578         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2579         Fix madd.
2580         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2581         It's OK to have a mult follow a mult.  What's not OK is to have a
2582         mult follow an mfhi.
2583         (Convert): Comment out incorrect rounding code.
2584
2585 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2586
2587         * interp.c (sim_monitor): Improved monitor printf
2588         simulation. Tidied up simulator warnings, and added "--log" option
2589         for directing warning message output.
2590         * gencode.c: Use sim_warning() rather than WARNING macro.
2591
2592 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2593
2594         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2595         getopt1.o, rather than on gencode.c.  Link objects together.
2596         Don't link against -liberty.
2597         (gencode.o, getopt.o, getopt1.o): New targets.
2598         * gencode.c: Include <ctype.h> and "ansidecl.h".
2599         (AND): Undefine after including "ansidecl.h".
2600         (ULONG_MAX): Define if not defined.
2601         (OP_*): Don't define macros; now defined in opcode/mips.h.
2602         (main): Call my_strtoul rather than strtoul.
2603         (my_strtoul): New static function.
2604
2605 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2606
2607         * gencode.c (process_instructions):  Generate word64 and uword64
2608         instead of `long long' and `unsigned long long' data types.
2609         * interp.c:  #include sysdep.h to get signals, and define default
2610         for SIGBUS.
2611         * (Convert):  Work around for Visual-C++ compiler bug with type
2612         conversion.
2613         * support.h:  Make things compile under Visual-C++ by using
2614         __int64 instead of `long long'.  Change many refs to long long
2615         into word64/uword64 typedefs.
2616
2617 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2618
2619         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2620         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2621         (docdir): Removed.
2622         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2623         (AC_PROG_INSTALL): Added.
2624         (AC_PROG_CC): Moved to before configure.host call.
2625         * configure: Rebuilt.
2626
2627 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2628
2629         * configure.in: Define @SIMCONF@ depending on mips target.
2630         * configure: Rebuild.
2631         * Makefile.in (run): Add @SIMCONF@ to control simulator
2632         construction.
2633         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2634         * interp.c: Remove some debugging, provide more detailed error
2635         messages, update memory accesses to use LOADDRMASK.
2636
2637 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2638
2639         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2640         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2641         stamp-h.
2642         * configure: Rebuild.
2643         * config.in: New file, generated by autoheader.
2644         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2645         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2646         HAVE_ANINT and HAVE_AINT, as appropriate.
2647         * Makefile.in (run): Use @LIBS@ rather than -lm.
2648         (interp.o): Depend upon config.h.
2649         (Makefile): Just rebuild Makefile.
2650         (clean): Remove stamp-h.
2651         (mostlyclean): Make the same as clean, not as distclean.
2652         (config.h, stamp-h): New targets.
2653
2654 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2655
2656         * interp.c (ColdReset): Fix boolean test. Make all simulator
2657         globals static.
2658
2659 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2660
2661         * interp.c (xfer_direct_word, xfer_direct_long,
2662         swap_direct_word, swap_direct_long, xfer_big_word,
2663         xfer_big_long, xfer_little_word, xfer_little_long,
2664         swap_word,swap_long): Added.
2665         * interp.c (ColdReset): Provide function indirection to
2666         host<->simulated_target transfer routines.
2667         * interp.c (sim_store_register, sim_fetch_register): Updated to
2668         make use of indirected transfer routines.
2669
2670 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2671
2672         * gencode.c (process_instructions): Ensure FP ABS instruction
2673         recognised.
2674         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2675         system call support.
2676
2677 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2678
2679         * interp.c (sim_do_command): Complain if callback structure not
2680         initialised.
2681
2682 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2683
2684         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2685         support for Sun hosts.
2686         * Makefile.in (gencode): Ensure the host compiler and libraries
2687         used for cross-hosted build.
2688
2689 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2690
2691         * interp.c, gencode.c: Some more (TODO) tidying.
2692
2693 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2694
2695         * gencode.c, interp.c: Replaced explicit long long references with
2696         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2697         * support.h (SET64LO, SET64HI): Macros added.
2698
2699 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2700
2701         * configure: Regenerate with autoconf 2.7.
2702
2703 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2704
2705         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2706         * support.h: Remove superfluous "1" from #if.
2707         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2708
2709 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2710
2711         * interp.c (StoreFPR): Control UndefinedResult() call on
2712         WARN_RESULT manifest.
2713
2714 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2715
2716         * gencode.c: Tidied instruction decoding, and added FP instruction
2717         support.
2718
2719         * interp.c: Added dineroIII, and BSD profiling support. Also
2720         run-time FP handling.
2721
2722 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2723
2724         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2725         gencode.c, interp.c, support.h: created.