1 2002-02-03 Chris Demetriou <cgd@broadcom.com>
3 * mips.igen: Fix formatting of check_fpu calls.
5 2002-03-03 Chris Demetriou <cgd@broadcom.com>
7 * mips.igen (FLOOR.L.fmt): Store correct destination register.
9 2002-03-03 Chris Demetriou <cgd@broadcom.com>
11 * mips.igen: Remove whitespace at end of lines.
13 2002-03-02 Chris Demetriou <cgd@broadcom.com>
15 * mips.igen (loadstore_ea): New function to do effective
17 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
18 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
19 CACHE): Use loadstore_ea to do effective address computations.
21 2002-03-02 Chris Demetriou <cgd@broadcom.com>
23 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
24 * mips.igen (LL, CxC1, MxC1): Likewise.
26 2002-03-02 Chris Demetriou <cgd@broadcom.com>
28 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
29 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
30 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
31 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
32 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
33 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
34 Don't split opcode fields by hand, use the opcode field values
37 2002-03-01 Chris Demetriou <cgd@broadcom.com>
39 * mips.igen (do_divu): Fix spacing.
41 * mips.igen (do_dsllv): Move to be right before DSLLV,
42 to match the rest of the do_<shift> functions.
44 2002-03-01 Chris Demetriou <cgd@broadcom.com>
46 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
47 DSRL32, do_dsrlv): Trace inputs and results.
49 2002-03-01 Chris Demetriou <cgd@broadcom.com>
51 * mips.igen (CACHE): Provide instruction-printing string.
53 * interp.c (signal_exception): Comment tokens after #endif.
55 2002-02-28 Chris Demetriou <cgd@broadcom.com>
57 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
58 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
59 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
60 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
61 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
62 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
63 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
64 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
66 2002-02-28 Chris Demetriou <cgd@broadcom.com>
68 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
69 instruction-printing string.
70 (LWU): Use '64' as the filter flag.
72 2002-02-28 Chris Demetriou <cgd@broadcom.com>
74 * mips.igen (SDXC1): Fix instruction-printing string.
76 2002-02-28 Chris Demetriou <cgd@broadcom.com>
78 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
81 2002-02-27 Chris Demetriou <cgd@broadcom.com>
83 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
86 2002-02-27 Chris Demetriou <cgd@broadcom.com>
88 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
89 add a comma) so that it more closely match the MIPS ISA
90 documentation opcode partitioning.
91 (PREF): Put useful names on opcode fields, and include
92 instruction-printing string.
94 2002-02-27 Chris Demetriou <cgd@broadcom.com>
96 * mips.igen (check_u64): New function which in the future will
97 check whether 64-bit instructions are usable and signal an
98 exception if not. Currently a no-op.
99 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
100 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
101 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
102 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
104 * mips.igen (check_fpu): New function which in the future will
105 check whether FPU instructions are usable and signal an exception
106 if not. Currently a no-op.
107 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
108 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
109 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
110 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
111 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
112 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
113 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
114 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
116 2002-02-27 Chris Demetriou <cgd@broadcom.com>
118 * mips.igen (do_load_left, do_load_right): Move to be immediately
120 (do_store_left, do_store_right): Move to be immediately following
123 2002-02-27 Chris Demetriou <cgd@broadcom.com>
125 * mips.igen (mipsV): New model name. Also, add it to
126 all instructions and functions where it is appropriate.
128 2002-02-18 Chris Demetriou <cgd@broadcom.com>
130 * mips.igen: For all functions and instructions, list model
131 names that support that instruction one per line.
133 2002-02-11 Chris Demetriou <cgd@broadcom.com>
135 * mips.igen: Add some additional comments about supported
136 models, and about which instructions go where.
137 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
138 order as is used in the rest of the file.
140 2002-02-11 Chris Demetriou <cgd@broadcom.com>
142 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
143 indicating that ALU32_END or ALU64_END are there to check
145 (DADD): Likewise, but also remove previous comment about
148 2002-02-10 Chris Demetriou <cgd@broadcom.com>
150 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
151 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
152 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
153 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
154 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
155 fields (i.e., add and move commas) so that they more closely
156 match the MIPS ISA documentation opcode partitioning.
158 2002-02-10 Chris Demetriou <cgd@broadcom.com>
160 * mips.igen (ADDI): Print immediate value.
162 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
163 (SLL): Print "nop" specially, and don't run the code
164 that does the shift for the "nop" case.
166 2001-11-17 Fred Fish <fnf@redhat.com>
168 * sim-main.h (float_operation): Move enum declaration outside
169 of _sim_cpu struct declaration.
171 2001-04-12 Jim Blandy <jimb@redhat.com>
173 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
174 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
176 * sim-main.h (COCIDX): Remove definition; this isn't supported by
177 PENDING_FILL, and you can get the intended effect gracefully by
178 calling PENDING_SCHED directly.
180 2001-02-23 Ben Elliston <bje@redhat.com>
182 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
183 already defined elsewhere.
185 2001-02-19 Ben Elliston <bje@redhat.com>
187 * sim-main.h (sim_monitor): Return an int.
188 * interp.c (sim_monitor): Add return values.
189 (signal_exception): Handle error conditions from sim_monitor.
191 2001-02-08 Ben Elliston <bje@redhat.com>
193 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
194 (store_memory): Likewise, pass cia to sim_core_write*.
196 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
198 On advice from Chris G. Demetriou <cgd@sibyte.com>:
199 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
201 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
203 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
204 * Makefile.in: Don't delete *.igen when cleaning directory.
206 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
208 * m16.igen (break): Call SignalException not sim_engine_halt.
210 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
213 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
215 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
217 * mips.igen (MxC1, DMxC1): Fix printf formatting.
219 2000-05-24 Michael Hayes <mhayes@cygnus.com>
221 * mips.igen (do_dmultx): Fix typo.
223 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
225 * configure: Regenerated to track ../common/aclocal.m4 changes.
227 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
229 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
231 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
233 * sim-main.h (GPR_CLEAR): Define macro.
235 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
237 * interp.c (decode_coproc): Output long using %lx and not %s.
239 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
241 * interp.c (sim_open): Sort & extend dummy memory regions for
242 --board=jmr3904 for eCos.
244 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
246 * configure: Regenerated.
248 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
250 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
251 calls, conditional on the simulator being in verbose mode.
253 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
255 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
256 cache don't get ReservedInstruction traps.
258 1999-11-29 Mark Salter <msalter@cygnus.com>
260 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
261 to clear status bits in sdisr register. This is how the hardware works.
263 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
264 being used by cygmon.
266 1999-11-11 Andrew Haley <aph@cygnus.com>
268 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
271 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
273 * mips.igen (MULT): Correct previous mis-applied patch.
275 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
277 * mips.igen (delayslot32): Handle sequence like
278 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
279 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
280 (MULT): Actually pass the third register...
282 1999-09-03 Mark Salter <msalter@cygnus.com>
284 * interp.c (sim_open): Added more memory aliases for additional
285 hardware being touched by cygmon on jmr3904 board.
287 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
289 * configure: Regenerated to track ../common/aclocal.m4 changes.
291 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
293 * interp.c (sim_store_register): Handle case where client - GDB -
294 specifies that a 4 byte register is 8 bytes in size.
295 (sim_fetch_register): Ditto.
297 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
299 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
300 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
301 (idt_monitor_base): Base address for IDT monitor traps.
302 (pmon_monitor_base): Ditto for PMON.
303 (lsipmon_monitor_base): Ditto for LSI PMON.
304 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
305 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
306 (sim_firmware_command): New function.
307 (mips_option_handler): Call it for OPTION_FIRMWARE.
308 (sim_open): Allocate memory for idt_monitor region. If "--board"
309 option was given, add no monitor by default. Add BREAK hooks only if
310 monitors are also there.
312 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
314 * interp.c (sim_monitor): Flush output before reading input.
316 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
318 * tconfig.in (SIM_HANDLES_LMA): Always define.
320 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
322 From Mark Salter <msalter@cygnus.com>:
323 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
324 (sim_open): Add setup for BSP board.
326 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
328 * mips.igen (MULT, MULTU): Add syntax for two operand version.
329 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
330 them as unimplemented.
332 1999-05-08 Felix Lee <flee@cygnus.com>
334 * configure: Regenerated to track ../common/aclocal.m4 changes.
336 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
338 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
340 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
342 * configure.in: Any mips64vr5*-*-* target should have
343 -DTARGET_ENABLE_FR=1.
344 (default_endian): Any mips64vr*el-*-* target should default to
346 * configure: Re-generate.
348 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
350 * mips.igen (ldl): Extend from _16_, not 32.
352 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
354 * interp.c (sim_store_register): Force registers written to by GDB
355 into an un-interpreted state.
357 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
359 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
360 CPU, start periodic background I/O polls.
361 (tx3904sio_poll): New function: periodic I/O poller.
363 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
365 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
367 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
369 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
372 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
374 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
375 (load_word): Call SIM_CORE_SIGNAL hook on error.
376 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
377 starting. For exception dispatching, pass PC instead of NULL_CIA.
378 (decode_coproc): Use COP0_BADVADDR to store faulting address.
379 * sim-main.h (COP0_BADVADDR): Define.
380 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
381 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
382 (_sim_cpu): Add exc_* fields to store register value snapshots.
383 * mips.igen (*): Replace memory-related SignalException* calls
384 with references to SIM_CORE_SIGNAL hook.
386 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
388 * sim-main.c (*): Minor warning cleanups.
390 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
392 * m16.igen (DADDIU5): Correct type-o.
394 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
396 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
399 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
401 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
403 (interp.o): Add dependency on itable.h
404 (oengine.c, gencode): Delete remaining references.
405 (BUILT_SRC_FROM_GEN): Clean up.
407 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
410 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
411 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
413 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
414 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
415 Drop the "64" qualifier to get the HACK generator working.
416 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
417 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
418 qualifier to get the hack generator working.
419 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
421 (DSLLV): Use do_dsllv.
424 (DSRLV): Use do_dsrlv.
425 (BC1): Move *vr4100 to get the HACK generator working.
426 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
427 get the HACK generator working.
428 (MACC) Rename to get the HACK generator working.
429 (DMACC,MACCS,DMACCS): Add the 64.
431 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
433 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
434 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
436 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
438 * mips/interp.c (DEBUG): Cleanups.
440 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
442 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
443 (tx3904sio_tickle): fflush after a stdout character output.
445 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
447 * interp.c (sim_close): Uninstall modules.
449 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
451 * sim-main.h, interp.c (sim_monitor): Change to global
454 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
456 * configure.in (vr4100): Only include vr4100 instructions in
458 * configure: Re-generate.
459 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
461 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
463 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
464 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
467 * configure.in (sim_default_gen, sim_use_gen): Replace with
469 (--enable-sim-igen): Delete config option. Always using IGEN.
470 * configure: Re-generate.
472 * Makefile.in (gencode): Kill, kill, kill.
475 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
477 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
478 bit mips16 igen simulator.
479 * configure: Re-generate.
481 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
482 as part of vr4100 ISA.
483 * vr.igen: Mark all instructions as 64 bit only.
485 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
487 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
490 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
492 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
493 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
494 * configure: Re-generate.
496 * m16.igen (BREAK): Define breakpoint instruction.
497 (JALX32): Mark instruction as mips16 and not r3900.
498 * mips.igen (C.cond.fmt): Fix typo in instruction format.
500 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
502 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
504 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
505 insn as a debug breakpoint.
507 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
509 (PENDING_SCHED): Clean up trace statement.
510 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
511 (PENDING_FILL): Delay write by only one cycle.
512 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
514 * sim-main.c (pending_tick): Clean up trace statements. Add trace
516 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
518 (pending_tick): Move incrementing of index to FOR statement.
519 (pending_tick): Only update PENDING_OUT after a write has occured.
521 * configure.in: Add explicit mips-lsi-* target. Use gencode to
523 * configure: Re-generate.
525 * interp.c (sim_engine_run OLD): Delete explicit call to
526 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
528 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
530 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
531 interrupt level number to match changed SignalExceptionInterrupt
534 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
536 * interp.c: #include "itable.h" if WITH_IGEN.
537 (get_insn_name): New function.
538 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
539 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
541 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
543 * configure: Rebuilt to inhale new common/aclocal.m4.
545 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
547 * dv-tx3904sio.c: Include sim-assert.h.
549 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
551 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
552 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
553 Reorganize target-specific sim-hardware checks.
554 * configure: rebuilt.
555 * interp.c (sim_open): For tx39 target boards, set
556 OPERATING_ENVIRONMENT, add tx3904sio devices.
557 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
558 ROM executables. Install dv-sockser into sim-modules list.
560 * dv-tx3904irc.c: Compiler warning clean-up.
561 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
562 frequent hw-trace messages.
564 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
566 * vr.igen (MulAcc): Identify as a vr4100 specific function.
568 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
570 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
573 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
574 * mips.igen: Define vr4100 model. Include vr.igen.
575 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
577 * mips.igen (check_mf_hilo): Correct check.
579 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
581 * sim-main.h (interrupt_event): Add prototype.
583 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
584 register_ptr, register_value.
585 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
587 * sim-main.h (tracefh): Make extern.
589 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
591 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
592 Reduce unnecessarily high timer event frequency.
593 * dv-tx3904cpu.c: Ditto for interrupt event.
595 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
597 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
599 (interrupt_event): Made non-static.
601 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
602 interchange of configuration values for external vs. internal
605 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
607 * mips.igen (BREAK): Moved code to here for
608 simulator-reserved break instructions.
609 * gencode.c (build_instruction): Ditto.
610 * interp.c (signal_exception): Code moved from here. Non-
611 reserved instructions now use exception vector, rather
613 * sim-main.h: Moved magic constants to here.
615 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
617 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
618 register upon non-zero interrupt event level, clear upon zero
620 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
621 by passing zero event value.
622 (*_io_{read,write}_buffer): Endianness fixes.
623 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
624 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
626 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
627 serial I/O and timer module at base address 0xFFFF0000.
629 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
631 * mips.igen (SWC1) : Correct the handling of ReverseEndian
634 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
636 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
640 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
642 * dv-tx3904tmr.c: New file - implements tx3904 timer.
643 * dv-tx3904{irc,cpu}.c: Mild reformatting.
644 * configure.in: Include tx3904tmr in hw_device list.
645 * configure: Rebuilt.
646 * interp.c (sim_open): Instantiate three timer instances.
647 Fix address typo of tx3904irc instance.
649 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
651 * interp.c (signal_exception): SystemCall exception now uses
652 the exception vector.
654 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
656 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
659 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
661 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
663 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
665 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
667 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
668 sim-main.h. Declare a struct hw_descriptor instead of struct
669 hw_device_descriptor.
671 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
673 * mips.igen (do_store_left, do_load_left): Compute nr of left and
674 right bits and then re-align left hand bytes to correct byte
675 lanes. Fix incorrect computation in do_store_left when loading
676 bytes from second word.
678 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
680 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
681 * interp.c (sim_open): Only create a device tree when HW is
684 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
685 * interp.c (signal_exception): Ditto.
687 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
689 * gencode.c: Mark BEGEZALL as LIKELY.
691 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
693 * sim-main.h (ALU32_END): Sign extend 32 bit results.
694 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
696 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
698 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
699 modules. Recognize TX39 target with "mips*tx39" pattern.
700 * configure: Rebuilt.
701 * sim-main.h (*): Added many macros defining bits in
702 TX39 control registers.
703 (SignalInterrupt): Send actual PC instead of NULL.
704 (SignalNMIReset): New exception type.
705 * interp.c (board): New variable for future use to identify
706 a particular board being simulated.
707 (mips_option_handler,mips_options): Added "--board" option.
708 (interrupt_event): Send actual PC.
709 (sim_open): Make memory layout conditional on board setting.
710 (signal_exception): Initial implementation of hardware interrupt
711 handling. Accept another break instruction variant for simulator
713 (decode_coproc): Implement RFE instruction for TX39.
714 (mips.igen): Decode RFE instruction as such.
715 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
716 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
717 bbegin to implement memory map.
718 * dv-tx3904cpu.c: New file.
719 * dv-tx3904irc.c: New file.
721 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
723 * mips.igen (check_mt_hilo): Create a separate r3900 version.
725 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
727 * tx.igen (madd,maddu): Replace calls to check_op_hilo
728 with calls to check_div_hilo.
730 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
732 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
733 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
734 Add special r3900 version of do_mult_hilo.
735 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
736 with calls to check_mult_hilo.
737 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
738 with calls to check_div_hilo.
740 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
742 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
743 Document a replacement.
745 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
747 * interp.c (sim_monitor): Make mon_printf work.
749 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
751 * sim-main.h (INSN_NAME): New arg `cpu'.
753 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
755 * configure: Regenerated to track ../common/aclocal.m4 changes.
757 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
759 * configure: Regenerated to track ../common/aclocal.m4 changes.
762 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
764 * acconfig.h: New file.
765 * configure.in: Reverted change of Apr 24; use sinclude again.
767 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
769 * configure: Regenerated to track ../common/aclocal.m4 changes.
772 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
774 * configure.in: Don't call sinclude.
776 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
778 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
780 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
782 * mips.igen (ERET): Implement.
784 * interp.c (decode_coproc): Return sign-extended EPC.
786 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
788 * interp.c (signal_exception): Do not ignore Trap.
789 (signal_exception): On TRAP, restart at exception address.
790 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
791 (signal_exception): Update.
792 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
793 so that TRAP instructions are caught.
795 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
797 * sim-main.h (struct hilo_access, struct hilo_history): Define,
798 contains HI/LO access history.
799 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
800 (HIACCESS, LOACCESS): Delete, replace with
801 (HIHISTORY, LOHISTORY): New macros.
802 (CHECKHILO): Delete all, moved to mips.igen
804 * gencode.c (build_instruction): Do not generate checks for
805 correct HI/LO register usage.
807 * interp.c (old_engine_run): Delete checks for correct HI/LO
810 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
811 check_mf_cycles): New functions.
812 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
813 do_divu, domultx, do_mult, do_multu): Use.
815 * tx.igen ("madd", "maddu"): Use.
817 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
819 * mips.igen (DSRAV): Use function do_dsrav.
820 (SRAV): Use new function do_srav.
822 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
823 (B): Sign extend 11 bit immediate.
824 (EXT-B*): Shift 16 bit immediate left by 1.
825 (ADDIU*): Don't sign extend immediate value.
827 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
829 * m16run.c (sim_engine_run): Restore CIA after handling an event.
831 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
834 * mips.igen (delayslot32, nullify_next_insn): New functions.
835 (m16.igen): Always include.
836 (do_*): Add more tracing.
838 * m16.igen (delayslot16): Add NIA argument, could be called by a
839 32 bit MIPS16 instruction.
841 * interp.c (ifetch16): Move function from here.
842 * sim-main.c (ifetch16): To here.
844 * sim-main.c (ifetch16, ifetch32): Update to match current
845 implementations of LH, LW.
846 (signal_exception): Don't print out incorrect hex value of illegal
849 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
851 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
854 * m16.igen: Implement MIPS16 instructions.
856 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
857 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
858 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
859 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
860 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
861 bodies of corresponding code from 32 bit insn to these. Also used
862 by MIPS16 versions of functions.
864 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
865 (IMEM16): Drop NR argument from macro.
867 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
869 * Makefile.in (SIM_OBJS): Add sim-main.o.
871 * sim-main.h (address_translation, load_memory, store_memory,
872 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
874 (pr_addr, pr_uword64): Declare.
875 (sim-main.c): Include when H_REVEALS_MODULE_P.
877 * interp.c (address_translation, load_memory, store_memory,
878 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
880 * sim-main.c: To here. Fix compilation problems.
882 * configure.in: Enable inlining.
883 * configure: Re-config.
885 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
887 * configure: Regenerated to track ../common/aclocal.m4 changes.
889 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
891 * mips.igen: Include tx.igen.
892 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
893 * tx.igen: New file, contains MADD and MADDU.
895 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
896 the hardwired constant `7'.
897 (store_memory): Ditto.
898 (LOADDRMASK): Move definition to sim-main.h.
900 mips.igen (MTC0): Enable for r3900.
903 mips.igen (do_load_byte): Delete.
904 (do_load, do_store, do_load_left, do_load_write, do_store_left,
905 do_store_right): New functions.
906 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
908 configure.in: Let the tx39 use igen again.
911 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
913 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
914 not an address sized quantity. Return zero for cache sizes.
916 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
918 * mips.igen (r3900): r3900 does not support 64 bit integer
921 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
923 * configure.in (mipstx39*-*-*): Use gencode simulator rather
925 * configure : Rebuild.
927 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
929 * configure: Regenerated to track ../common/aclocal.m4 changes.
931 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
933 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
935 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
937 * configure: Regenerated to track ../common/aclocal.m4 changes.
938 * config.in: Regenerated to track ../common/aclocal.m4 changes.
940 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
942 * configure: Regenerated to track ../common/aclocal.m4 changes.
944 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
946 * interp.c (Max, Min): Comment out functions. Not yet used.
948 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
950 * configure: Regenerated to track ../common/aclocal.m4 changes.
952 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
954 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
955 configurable settings for stand-alone simulator.
957 * configure.in: Added X11 search, just in case.
959 * configure: Regenerated.
961 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
963 * interp.c (sim_write, sim_read, load_memory, store_memory):
964 Replace sim_core_*_map with read_map, write_map, exec_map resp.
966 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
968 * sim-main.h (GETFCC): Return an unsigned value.
970 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
972 * mips.igen (DIV): Fix check for -1 / MIN_INT.
973 (DADD): Result destination is RD not RT.
975 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
977 * sim-main.h (HIACCESS, LOACCESS): Always define.
979 * mdmx.igen (Maxi, Mini): Rename Max, Min.
981 * interp.c (sim_info): Delete.
983 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
985 * interp.c (DECLARE_OPTION_HANDLER): Use it.
986 (mips_option_handler): New argument `cpu'.
987 (sim_open): Update call to sim_add_option_table.
989 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
991 * mips.igen (CxC1): Add tracing.
993 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
995 * sim-main.h (Max, Min): Declare.
997 * interp.c (Max, Min): New functions.
999 * mips.igen (BC1): Add tracing.
1001 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1003 * interp.c Added memory map for stack in vr4100
1005 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1007 * interp.c (load_memory): Add missing "break"'s.
1009 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1011 * interp.c (sim_store_register, sim_fetch_register): Pass in
1012 length parameter. Return -1.
1014 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1016 * interp.c: Added hardware init hook, fixed warnings.
1018 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1020 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1022 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1024 * interp.c (ifetch16): New function.
1026 * sim-main.h (IMEM32): Rename IMEM.
1027 (IMEM16_IMMED): Define.
1029 (DELAY_SLOT): Update.
1031 * m16run.c (sim_engine_run): New file.
1033 * m16.igen: All instructions except LB.
1034 (LB): Call do_load_byte.
1035 * mips.igen (do_load_byte): New function.
1036 (LB): Call do_load_byte.
1038 * mips.igen: Move spec for insn bit size and high bit from here.
1039 * Makefile.in (tmp-igen, tmp-m16): To here.
1041 * m16.dc: New file, decode mips16 instructions.
1043 * Makefile.in (SIM_NO_ALL): Define.
1044 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1046 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1048 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1049 point unit to 32 bit registers.
1050 * configure: Re-generate.
1052 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1054 * configure.in (sim_use_gen): Make IGEN the default simulator
1055 generator for generic 32 and 64 bit mips targets.
1056 * configure: Re-generate.
1058 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1060 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1063 * interp.c (sim_fetch_register, sim_store_register): Read/write
1064 FGR from correct location.
1065 (sim_open): Set size of FGR's according to
1066 WITH_TARGET_FLOATING_POINT_BITSIZE.
1068 * sim-main.h (FGR): Store floating point registers in a separate
1071 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1073 * configure: Regenerated to track ../common/aclocal.m4 changes.
1075 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1077 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1079 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1081 * interp.c (pending_tick): New function. Deliver pending writes.
1083 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1084 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1085 it can handle mixed sized quantites and single bits.
1087 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1089 * interp.c (oengine.h): Do not include when building with IGEN.
1090 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1091 (sim_info): Ditto for PROCESSOR_64BIT.
1092 (sim_monitor): Replace ut_reg with unsigned_word.
1093 (*): Ditto for t_reg.
1094 (LOADDRMASK): Define.
1095 (sim_open): Remove defunct check that host FP is IEEE compliant,
1096 using software to emulate floating point.
1097 (value_fpr, ...): Always compile, was conditional on HASFPU.
1099 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1101 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1104 * interp.c (SD, CPU): Define.
1105 (mips_option_handler): Set flags in each CPU.
1106 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1107 (sim_close): Do not clear STATE, deleted anyway.
1108 (sim_write, sim_read): Assume CPU zero's vm should be used for
1110 (sim_create_inferior): Set the PC for all processors.
1111 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1113 (mips16_entry): Pass correct nr of args to store_word, load_word.
1114 (ColdReset): Cold reset all cpu's.
1115 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1116 (sim_monitor, load_memory, store_memory, signal_exception): Use
1117 `CPU' instead of STATE_CPU.
1120 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1123 * sim-main.h (signal_exception): Add sim_cpu arg.
1124 (SignalException*): Pass both SD and CPU to signal_exception.
1125 * interp.c (signal_exception): Update.
1127 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1129 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1130 address_translation): Ditto
1131 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1133 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1135 * configure: Regenerated to track ../common/aclocal.m4 changes.
1137 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1139 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1141 * mips.igen (model): Map processor names onto BFD name.
1143 * sim-main.h (CPU_CIA): Delete.
1144 (SET_CIA, GET_CIA): Define
1146 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1148 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1151 * configure.in (default_endian): Configure a big-endian simulator
1153 * configure: Re-generate.
1155 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1157 * configure: Regenerated to track ../common/aclocal.m4 changes.
1159 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1161 * interp.c (sim_monitor): Handle Densan monitor outbyte
1162 and inbyte functions.
1164 1997-12-29 Felix Lee <flee@cygnus.com>
1166 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1168 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1170 * Makefile.in (tmp-igen): Arrange for $zero to always be
1171 reset to zero after every instruction.
1173 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1175 * configure: Regenerated to track ../common/aclocal.m4 changes.
1178 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1180 * mips.igen (MSUB): Fix to work like MADD.
1181 * gencode.c (MSUB): Similarly.
1183 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1185 * configure: Regenerated to track ../common/aclocal.m4 changes.
1187 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1189 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1191 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1193 * sim-main.h (sim-fpu.h): Include.
1195 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1196 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1197 using host independant sim_fpu module.
1199 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1201 * interp.c (signal_exception): Report internal errors with SIGABRT
1204 * sim-main.h (C0_CONFIG): New register.
1205 (signal.h): No longer include.
1207 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1209 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1211 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1213 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1215 * mips.igen: Tag vr5000 instructions.
1216 (ANDI): Was missing mipsIV model, fix assembler syntax.
1217 (do_c_cond_fmt): New function.
1218 (C.cond.fmt): Handle mips I-III which do not support CC field
1220 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1221 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1223 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1224 vr5000 which saves LO in a GPR separatly.
1226 * configure.in (enable-sim-igen): For vr5000, select vr5000
1227 specific instructions.
1228 * configure: Re-generate.
1230 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1232 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1234 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1235 fmt_uninterpreted_64 bit cases to switch. Convert to
1238 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1240 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1241 as specified in IV3.2 spec.
1242 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1244 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1246 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1247 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1248 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1249 PENDING_FILL versions of instructions. Simplify.
1251 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1253 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1255 (MTHI, MFHI): Disable code checking HI-LO.
1257 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1259 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1261 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1263 * gencode.c (build_mips16_operands): Replace IPC with cia.
1265 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1266 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1268 (UndefinedResult): Replace function with macro/function
1270 (sim_engine_run): Don't save PC in IPC.
1272 * sim-main.h (IPC): Delete.
1275 * interp.c (signal_exception, store_word, load_word,
1276 address_translation, load_memory, store_memory, cache_op,
1277 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1278 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1279 current instruction address - cia - argument.
1280 (sim_read, sim_write): Call address_translation directly.
1281 (sim_engine_run): Rename variable vaddr to cia.
1282 (signal_exception): Pass cia to sim_monitor
1284 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1285 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1286 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1288 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1289 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1292 * interp.c (signal_exception): Pass restart address to
1295 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1296 idecode.o): Add dependency.
1298 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1300 (DELAY_SLOT): Update NIA not PC with branch address.
1301 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1303 * mips.igen: Use CIA not PC in branch calculations.
1304 (illegal): Call SignalException.
1305 (BEQ, ADDIU): Fix assembler.
1307 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1309 * m16.igen (JALX): Was missing.
1311 * configure.in (enable-sim-igen): New configuration option.
1312 * configure: Re-generate.
1314 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1316 * interp.c (load_memory, store_memory): Delete parameter RAW.
1317 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1318 bypassing {load,store}_memory.
1320 * sim-main.h (ByteSwapMem): Delete definition.
1322 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1324 * interp.c (sim_do_command, sim_commands): Delete mips specific
1325 commands. Handled by module sim-options.
1327 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1328 (WITH_MODULO_MEMORY): Define.
1330 * interp.c (sim_info): Delete code printing memory size.
1332 * interp.c (mips_size): Nee sim_size, delete function.
1334 (monitor, monitor_base, monitor_size): Delete global variables.
1335 (sim_open, sim_close): Delete code creating monitor and other
1336 memory regions. Use sim-memopts module, via sim_do_commandf, to
1337 manage memory regions.
1338 (load_memory, store_memory): Use sim-core for memory model.
1340 * interp.c (address_translation): Delete all memory map code
1341 except line forcing 32 bit addresses.
1343 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1345 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1348 * interp.c (logfh, logfile): Delete globals.
1349 (sim_open, sim_close): Delete code opening & closing log file.
1350 (mips_option_handler): Delete -l and -n options.
1351 (OPTION mips_options): Ditto.
1353 * interp.c (OPTION mips_options): Rename option trace to dinero.
1354 (mips_option_handler): Update.
1356 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1358 * interp.c (fetch_str): New function.
1359 (sim_monitor): Rewrite using sim_read & sim_write.
1360 (sim_open): Check magic number.
1361 (sim_open): Write monitor vectors into memory using sim_write.
1362 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1363 (sim_read, sim_write): Simplify - transfer data one byte at a
1365 (load_memory, store_memory): Clarify meaning of parameter RAW.
1367 * sim-main.h (isHOST): Defete definition.
1368 (isTARGET): Mark as depreciated.
1369 (address_translation): Delete parameter HOST.
1371 * interp.c (address_translation): Delete parameter HOST.
1373 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1377 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1378 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1380 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1382 * mips.igen: Add model filter field to records.
1384 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1386 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1388 interp.c (sim_engine_run): Do not compile function sim_engine_run
1389 when WITH_IGEN == 1.
1391 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1392 target architecture.
1394 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1395 igen. Replace with configuration variables sim_igen_flags /
1398 * m16.igen: New file. Copy mips16 insns here.
1399 * mips.igen: From here.
1401 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1403 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1405 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1407 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1409 * gencode.c (build_instruction): Follow sim_write's lead in using
1410 BigEndianMem instead of !ByteSwapMem.
1412 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1414 * configure.in (sim_gen): Dependent on target, select type of
1415 generator. Always select old style generator.
1417 configure: Re-generate.
1419 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1421 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1422 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1423 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1424 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1425 SIM_@sim_gen@_*, set by autoconf.
1427 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1429 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1431 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1432 CURRENT_FLOATING_POINT instead.
1434 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1435 (address_translation): Raise exception InstructionFetch when
1436 translation fails and isINSTRUCTION.
1438 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1439 sim_engine_run): Change type of of vaddr and paddr to
1441 (address_translation, prefetch, load_memory, store_memory,
1442 cache_op): Change type of vAddr and pAddr to address_word.
1444 * gencode.c (build_instruction): Change type of vaddr and paddr to
1447 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1449 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1450 macro to obtain result of ALU op.
1452 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1454 * interp.c (sim_info): Call profile_print.
1456 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1458 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1460 * sim-main.h (WITH_PROFILE): Do not define, defined in
1461 common/sim-config.h. Use sim-profile module.
1462 (simPROFILE): Delete defintion.
1464 * interp.c (PROFILE): Delete definition.
1465 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1466 (sim_close): Delete code writing profile histogram.
1467 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1469 (sim_engine_run): Delete code profiling the PC.
1471 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1473 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1475 * interp.c (sim_monitor): Make register pointers of type
1478 * sim-main.h: Make registers of type unsigned_word not
1481 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1483 * interp.c (sync_operation): Rename from SyncOperation, make
1484 global, add SD argument.
1485 (prefetch): Rename from Prefetch, make global, add SD argument.
1486 (decode_coproc): Make global.
1488 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1490 * gencode.c (build_instruction): Generate DecodeCoproc not
1491 decode_coproc calls.
1493 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1494 (SizeFGR): Move to sim-main.h
1495 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1496 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1497 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1499 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1500 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1501 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1502 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1503 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1504 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1506 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1508 (sim-alu.h): Include.
1509 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1510 (sim_cia): Typedef to instruction_address.
1512 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1514 * Makefile.in (interp.o): Rename generated file engine.c to
1519 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1521 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1523 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1525 * gencode.c (build_instruction): For "FPSQRT", output correct
1526 number of arguments to Recip.
1528 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1530 * Makefile.in (interp.o): Depends on sim-main.h
1532 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1534 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1535 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1536 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1537 STATE, DSSTATE): Define
1538 (GPR, FGRIDX, ..): Define.
1540 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1541 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1542 (GPR, FGRIDX, ...): Delete macros.
1544 * interp.c: Update names to match defines from sim-main.h
1546 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1548 * interp.c (sim_monitor): Add SD argument.
1549 (sim_warning): Delete. Replace calls with calls to
1551 (sim_error): Delete. Replace calls with sim_io_error.
1552 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1553 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1554 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1556 (mips_size): Rename from sim_size. Add SD argument.
1558 * interp.c (simulator): Delete global variable.
1559 (callback): Delete global variable.
1560 (mips_option_handler, sim_open, sim_write, sim_read,
1561 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1562 sim_size,sim_monitor): Use sim_io_* not callback->*.
1563 (sim_open): ZALLOC simulator struct.
1564 (PROFILE): Do not define.
1566 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1568 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1569 support.h with corresponding code.
1571 * sim-main.h (word64, uword64), support.h: Move definition to
1573 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1576 * Makefile.in: Update dependencies
1577 * interp.c: Do not include.
1579 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1581 * interp.c (address_translation, load_memory, store_memory,
1582 cache_op): Rename to from AddressTranslation et.al., make global,
1585 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1588 * interp.c (SignalException): Rename to signal_exception, make
1591 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1593 * sim-main.h (SignalException, SignalExceptionInterrupt,
1594 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1595 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1596 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1599 * interp.c, support.h: Use.
1601 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1603 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1604 to value_fpr / store_fpr. Add SD argument.
1605 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1606 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1608 * sim-main.h (ValueFPR, StoreFPR): Define.
1610 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1612 * interp.c (sim_engine_run): Check consistency between configure
1613 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1616 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1617 (mips_fpu): Configure WITH_FLOATING_POINT.
1618 (mips_endian): Configure WITH_TARGET_ENDIAN.
1619 * configure: Update.
1621 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1623 * configure: Regenerated to track ../common/aclocal.m4 changes.
1625 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1627 * configure: Regenerated.
1629 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1631 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1633 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1635 * gencode.c (print_igen_insn_models): Assume certain architectures
1636 include all mips* instructions.
1637 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1640 * Makefile.in (tmp.igen): Add target. Generate igen input from
1643 * gencode.c (FEATURE_IGEN): Define.
1644 (main): Add --igen option. Generate output in igen format.
1645 (process_instructions): Format output according to igen option.
1646 (print_igen_insn_format): New function.
1647 (print_igen_insn_models): New function.
1648 (process_instructions): Only issue warnings and ignore
1649 instructions when no FEATURE_IGEN.
1651 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1653 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1656 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1658 * configure: Regenerated to track ../common/aclocal.m4 changes.
1660 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1662 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1663 SIM_RESERVED_BITS): Delete, moved to common.
1664 (SIM_EXTRA_CFLAGS): Update.
1666 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1668 * configure.in: Configure non-strict memory alignment.
1669 * configure: Regenerated to track ../common/aclocal.m4 changes.
1671 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1673 * configure: Regenerated to track ../common/aclocal.m4 changes.
1675 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1677 * gencode.c (SDBBP,DERET): Added (3900) insns.
1678 (RFE): Turn on for 3900.
1679 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1680 (dsstate): Made global.
1681 (SUBTARGET_R3900): Added.
1682 (CANCELDELAYSLOT): New.
1683 (SignalException): Ignore SystemCall rather than ignore and
1684 terminate. Add DebugBreakPoint handling.
1685 (decode_coproc): New insns RFE, DERET; and new registers Debug
1686 and DEPC protected by SUBTARGET_R3900.
1687 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1689 * Makefile.in,configure.in: Add mips subtarget option.
1690 * configure: Update.
1692 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1694 * gencode.c: Add r3900 (tx39).
1697 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1699 * gencode.c (build_instruction): Don't need to subtract 4 for
1702 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1704 * interp.c: Correct some HASFPU problems.
1706 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1708 * configure: Regenerated to track ../common/aclocal.m4 changes.
1710 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1712 * interp.c (mips_options): Fix samples option short form, should
1715 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1717 * interp.c (sim_info): Enable info code. Was just returning.
1719 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1721 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1724 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1726 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1728 (build_instruction): Ditto for LL.
1730 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1732 * configure: Regenerated to track ../common/aclocal.m4 changes.
1734 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1736 * configure: Regenerated to track ../common/aclocal.m4 changes.
1739 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1741 * interp.c (sim_open): Add call to sim_analyze_program, update
1744 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1746 * interp.c (sim_kill): Delete.
1747 (sim_create_inferior): Add ABFD argument. Set PC from same.
1748 (sim_load): Move code initializing trap handlers from here.
1749 (sim_open): To here.
1750 (sim_load): Delete, use sim-hload.c.
1752 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1754 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1756 * configure: Regenerated to track ../common/aclocal.m4 changes.
1759 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1761 * interp.c (sim_open): Add ABFD argument.
1762 (sim_load): Move call to sim_config from here.
1763 (sim_open): To here. Check return status.
1765 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1767 * gencode.c (build_instruction): Two arg MADD should
1768 not assign result to $0.
1770 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1772 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1773 * sim/mips/configure.in: Regenerate.
1775 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1777 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1778 signed8, unsigned8 et.al. types.
1780 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1781 hosts when selecting subreg.
1783 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1785 * interp.c (sim_engine_run): Reset the ZERO register to zero
1786 regardless of FEATURE_WARN_ZERO.
1787 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1789 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1791 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1792 (SignalException): For BreakPoints ignore any mode bits and just
1794 (SignalException): Always set the CAUSE register.
1796 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1798 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1799 exception has been taken.
1801 * interp.c: Implement the ERET and mt/f sr instructions.
1803 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1805 * interp.c (SignalException): Don't bother restarting an
1808 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1810 * interp.c (SignalException): Really take an interrupt.
1811 (interrupt_event): Only deliver interrupts when enabled.
1813 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1815 * interp.c (sim_info): Only print info when verbose.
1816 (sim_info) Use sim_io_printf for output.
1818 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1820 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1823 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1825 * interp.c (sim_do_command): Check for common commands if a
1826 simulator specific command fails.
1828 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1830 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1831 and simBE when DEBUG is defined.
1833 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1835 * interp.c (interrupt_event): New function. Pass exception event
1836 onto exception handler.
1838 * configure.in: Check for stdlib.h.
1839 * configure: Regenerate.
1841 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1842 variable declaration.
1843 (build_instruction): Initialize memval1.
1844 (build_instruction): Add UNUSED attribute to byte, bigend,
1846 (build_operands): Ditto.
1848 * interp.c: Fix GCC warnings.
1849 (sim_get_quit_code): Delete.
1851 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1852 * Makefile.in: Ditto.
1853 * configure: Re-generate.
1855 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1857 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1859 * interp.c (mips_option_handler): New function parse argumes using
1861 (myname): Replace with STATE_MY_NAME.
1862 (sim_open): Delete check for host endianness - performed by
1864 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1865 (sim_open): Move much of the initialization from here.
1866 (sim_load): To here. After the image has been loaded and
1868 (sim_open): Move ColdReset from here.
1869 (sim_create_inferior): To here.
1870 (sim_open): Make FP check less dependant on host endianness.
1872 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1874 * interp.c (sim_set_callbacks): Delete.
1876 * interp.c (membank, membank_base, membank_size): Replace with
1877 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1878 (sim_open): Remove call to callback->init. gdb/run do this.
1882 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1884 * interp.c (big_endian_p): Delete, replaced by
1885 current_target_byte_order.
1887 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1889 * interp.c (host_read_long, host_read_word, host_swap_word,
1890 host_swap_long): Delete. Using common sim-endian.
1891 (sim_fetch_register, sim_store_register): Use H2T.
1892 (pipeline_ticks): Delete. Handled by sim-events.
1894 (sim_engine_run): Update.
1896 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1898 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1900 (SignalException): To here. Signal using sim_engine_halt.
1901 (sim_stop_reason): Delete, moved to common.
1903 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1905 * interp.c (sim_open): Add callback argument.
1906 (sim_set_callbacks): Delete SIM_DESC argument.
1909 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1911 * Makefile.in (SIM_OBJS): Add common modules.
1913 * interp.c (sim_set_callbacks): Also set SD callback.
1914 (set_endianness, xfer_*, swap_*): Delete.
1915 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1916 Change to functions using sim-endian macros.
1917 (control_c, sim_stop): Delete, use common version.
1918 (simulate): Convert into.
1919 (sim_engine_run): This function.
1920 (sim_resume): Delete.
1922 * interp.c (simulation): New variable - the simulator object.
1923 (sim_kind): Delete global - merged into simulation.
1924 (sim_load): Cleanup. Move PC assignment from here.
1925 (sim_create_inferior): To here.
1927 * sim-main.h: New file.
1928 * interp.c (sim-main.h): Include.
1930 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1932 * configure: Regenerated to track ../common/aclocal.m4 changes.
1934 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1936 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1938 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1940 * gencode.c (build_instruction): DIV instructions: check
1941 for division by zero and integer overflow before using
1942 host's division operation.
1944 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1946 * Makefile.in (SIM_OBJS): Add sim-load.o.
1947 * interp.c: #include bfd.h.
1948 (target_byte_order): Delete.
1949 (sim_kind, myname, big_endian_p): New static locals.
1950 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1951 after argument parsing. Recognize -E arg, set endianness accordingly.
1952 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1953 load file into simulator. Set PC from bfd.
1954 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1955 (set_endianness): Use big_endian_p instead of target_byte_order.
1957 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1959 * interp.c (sim_size): Delete prototype - conflicts with
1960 definition in remote-sim.h. Correct definition.
1962 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1964 * configure: Regenerated to track ../common/aclocal.m4 changes.
1967 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1969 * interp.c (sim_open): New arg `kind'.
1971 * configure: Regenerated to track ../common/aclocal.m4 changes.
1973 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1975 * configure: Regenerated to track ../common/aclocal.m4 changes.
1977 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1979 * interp.c (sim_open): Set optind to 0 before calling getopt.
1981 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1983 * configure: Regenerated to track ../common/aclocal.m4 changes.
1985 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1987 * interp.c : Replace uses of pr_addr with pr_uword64
1988 where the bit length is always 64 independent of SIM_ADDR.
1989 (pr_uword64) : added.
1991 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1993 * configure: Re-generate.
1995 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1997 * configure: Regenerate to track ../common/aclocal.m4 changes.
1999 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2001 * interp.c (sim_open): New SIM_DESC result. Argument is now
2003 (other sim_*): New SIM_DESC argument.
2005 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2007 * interp.c: Fix printing of addresses for non-64-bit targets.
2008 (pr_addr): Add function to print address based on size.
2010 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2012 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2014 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2016 * gencode.c (build_mips16_operands): Correct computation of base
2017 address for extended PC relative instruction.
2019 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2021 * interp.c (mips16_entry): Add support for floating point cases.
2022 (SignalException): Pass floating point cases to mips16_entry.
2023 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2025 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2027 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2028 and then set the state to fmt_uninterpreted.
2029 (COP_SW): Temporarily set the state to fmt_word while calling
2032 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2034 * gencode.c (build_instruction): The high order may be set in the
2035 comparison flags at any ISA level, not just ISA 4.
2037 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2039 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2040 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2041 * configure.in: sinclude ../common/aclocal.m4.
2042 * configure: Regenerated.
2044 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2046 * configure: Rebuild after change to aclocal.m4.
2048 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2050 * configure configure.in Makefile.in: Update to new configure
2051 scheme which is more compatible with WinGDB builds.
2052 * configure.in: Improve comment on how to run autoconf.
2053 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2054 * Makefile.in: Use autoconf substitution to install common
2057 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2059 * gencode.c (build_instruction): Use BigEndianCPU instead of
2062 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2064 * interp.c (sim_monitor): Make output to stdout visible in
2065 wingdb's I/O log window.
2067 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2069 * support.h: Undo previous change to SIGTRAP
2072 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2074 * interp.c (store_word, load_word): New static functions.
2075 (mips16_entry): New static function.
2076 (SignalException): Look for mips16 entry and exit instructions.
2077 (simulate): Use the correct index when setting fpr_state after
2078 doing a pending move.
2080 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2082 * interp.c: Fix byte-swapping code throughout to work on
2083 both little- and big-endian hosts.
2085 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2087 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2088 with gdb/config/i386/xm-windows.h.
2090 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2092 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2093 that messes up arithmetic shifts.
2095 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2097 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2098 SIGTRAP and SIGQUIT for _WIN32.
2100 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2102 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2103 force a 64 bit multiplication.
2104 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2105 destination register is 0, since that is the default mips16 nop
2108 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2110 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2111 (build_endian_shift): Don't check proc64.
2112 (build_instruction): Always set memval to uword64. Cast op2 to
2113 uword64 when shifting it left in memory instructions. Always use
2114 the same code for stores--don't special case proc64.
2116 * gencode.c (build_mips16_operands): Fix base PC value for PC
2118 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2120 * interp.c (simJALDELAYSLOT): Define.
2121 (JALDELAYSLOT): Define.
2122 (INDELAYSLOT, INJALDELAYSLOT): Define.
2123 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2125 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2127 * interp.c (sim_open): add flush_cache as a PMON routine
2128 (sim_monitor): handle flush_cache by ignoring it
2130 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2132 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2134 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2135 (BigEndianMem): Rename to ByteSwapMem and change sense.
2136 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2137 BigEndianMem references to !ByteSwapMem.
2138 (set_endianness): New function, with prototype.
2139 (sim_open): Call set_endianness.
2140 (sim_info): Use simBE instead of BigEndianMem.
2141 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2142 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2143 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2144 ifdefs, keeping the prototype declaration.
2145 (swap_word): Rewrite correctly.
2146 (ColdReset): Delete references to CONFIG. Delete endianness related
2147 code; moved to set_endianness.
2149 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2151 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2152 * interp.c (CHECKHILO): Define away.
2153 (simSIGINT): New macro.
2154 (membank_size): Increase from 1MB to 2MB.
2155 (control_c): New function.
2156 (sim_resume): Rename parameter signal to signal_number. Add local
2157 variable prev. Call signal before and after simulate.
2158 (sim_stop_reason): Add simSIGINT support.
2159 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2161 (sim_warning): Delete call to SignalException. Do call printf_filtered
2163 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2164 a call to sim_warning.
2166 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2168 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2169 16 bit instructions.
2171 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2173 Add support for mips16 (16 bit MIPS implementation):
2174 * gencode.c (inst_type): Add mips16 instruction encoding types.
2175 (GETDATASIZEINSN): Define.
2176 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2177 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2179 (MIPS16_DECODE): New table, for mips16 instructions.
2180 (bitmap_val): New static function.
2181 (struct mips16_op): Define.
2182 (mips16_op_table): New table, for mips16 operands.
2183 (build_mips16_operands): New static function.
2184 (process_instructions): If PC is odd, decode a mips16
2185 instruction. Break out instruction handling into new
2186 build_instruction function.
2187 (build_instruction): New static function, broken out of
2188 process_instructions. Check modifiers rather than flags for SHIFT
2189 bit count and m[ft]{hi,lo} direction.
2190 (usage): Pass program name to fprintf.
2191 (main): Remove unused variable this_option_optind. Change
2192 ``*loptarg++'' to ``loptarg++''.
2193 (my_strtoul): Parenthesize && within ||.
2194 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2195 (simulate): If PC is odd, fetch a 16 bit instruction, and
2196 increment PC by 2 rather than 4.
2197 * configure.in: Add case for mips16*-*-*.
2198 * configure: Rebuild.
2200 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2202 * interp.c: Allow -t to enable tracing in standalone simulator.
2203 Fix garbage output in trace file and error messages.
2205 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2207 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2208 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2209 * configure.in: Simplify using macros in ../common/aclocal.m4.
2210 * configure: Regenerated.
2211 * tconfig.in: New file.
2213 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2215 * interp.c: Fix bugs in 64-bit port.
2216 Use ansi function declarations for msvc compiler.
2217 Initialize and test file pointer in trace code.
2218 Prevent duplicate definition of LAST_EMED_REGNUM.
2220 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2222 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2224 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2226 * interp.c (SignalException): Check for explicit terminating
2228 * gencode.c: Pass instruction value through SignalException()
2229 calls for Trap, Breakpoint and Syscall.
2231 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2233 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2234 only used on those hosts that provide it.
2235 * configure.in: Add sqrt() to list of functions to be checked for.
2236 * config.in: Re-generated.
2237 * configure: Re-generated.
2239 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2241 * gencode.c (process_instructions): Call build_endian_shift when
2242 expanding STORE RIGHT, to fix swr.
2243 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2244 clear the high bits.
2245 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2246 Fix float to int conversions to produce signed values.
2248 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2250 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2251 (process_instructions): Correct handling of nor instruction.
2252 Correct shift count for 32 bit shift instructions. Correct sign
2253 extension for arithmetic shifts to not shift the number of bits in
2254 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2255 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2257 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2258 It's OK to have a mult follow a mult. What's not OK is to have a
2259 mult follow an mfhi.
2260 (Convert): Comment out incorrect rounding code.
2262 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2264 * interp.c (sim_monitor): Improved monitor printf
2265 simulation. Tidied up simulator warnings, and added "--log" option
2266 for directing warning message output.
2267 * gencode.c: Use sim_warning() rather than WARNING macro.
2269 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2271 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2272 getopt1.o, rather than on gencode.c. Link objects together.
2273 Don't link against -liberty.
2274 (gencode.o, getopt.o, getopt1.o): New targets.
2275 * gencode.c: Include <ctype.h> and "ansidecl.h".
2276 (AND): Undefine after including "ansidecl.h".
2277 (ULONG_MAX): Define if not defined.
2278 (OP_*): Don't define macros; now defined in opcode/mips.h.
2279 (main): Call my_strtoul rather than strtoul.
2280 (my_strtoul): New static function.
2282 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2284 * gencode.c (process_instructions): Generate word64 and uword64
2285 instead of `long long' and `unsigned long long' data types.
2286 * interp.c: #include sysdep.h to get signals, and define default
2288 * (Convert): Work around for Visual-C++ compiler bug with type
2290 * support.h: Make things compile under Visual-C++ by using
2291 __int64 instead of `long long'. Change many refs to long long
2292 into word64/uword64 typedefs.
2294 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2296 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2297 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2299 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2300 (AC_PROG_INSTALL): Added.
2301 (AC_PROG_CC): Moved to before configure.host call.
2302 * configure: Rebuilt.
2304 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2306 * configure.in: Define @SIMCONF@ depending on mips target.
2307 * configure: Rebuild.
2308 * Makefile.in (run): Add @SIMCONF@ to control simulator
2310 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2311 * interp.c: Remove some debugging, provide more detailed error
2312 messages, update memory accesses to use LOADDRMASK.
2314 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2316 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2317 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2319 * configure: Rebuild.
2320 * config.in: New file, generated by autoheader.
2321 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2322 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2323 HAVE_ANINT and HAVE_AINT, as appropriate.
2324 * Makefile.in (run): Use @LIBS@ rather than -lm.
2325 (interp.o): Depend upon config.h.
2326 (Makefile): Just rebuild Makefile.
2327 (clean): Remove stamp-h.
2328 (mostlyclean): Make the same as clean, not as distclean.
2329 (config.h, stamp-h): New targets.
2331 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2333 * interp.c (ColdReset): Fix boolean test. Make all simulator
2336 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2338 * interp.c (xfer_direct_word, xfer_direct_long,
2339 swap_direct_word, swap_direct_long, xfer_big_word,
2340 xfer_big_long, xfer_little_word, xfer_little_long,
2341 swap_word,swap_long): Added.
2342 * interp.c (ColdReset): Provide function indirection to
2343 host<->simulated_target transfer routines.
2344 * interp.c (sim_store_register, sim_fetch_register): Updated to
2345 make use of indirected transfer routines.
2347 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2349 * gencode.c (process_instructions): Ensure FP ABS instruction
2351 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2352 system call support.
2354 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2356 * interp.c (sim_do_command): Complain if callback structure not
2359 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2361 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2362 support for Sun hosts.
2363 * Makefile.in (gencode): Ensure the host compiler and libraries
2364 used for cross-hosted build.
2366 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2368 * interp.c, gencode.c: Some more (TODO) tidying.
2370 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2372 * gencode.c, interp.c: Replaced explicit long long references with
2373 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2374 * support.h (SET64LO, SET64HI): Macros added.
2376 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2378 * configure: Regenerate with autoconf 2.7.
2380 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2382 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2383 * support.h: Remove superfluous "1" from #if.
2384 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2386 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2388 * interp.c (StoreFPR): Control UndefinedResult() call on
2389 WARN_RESULT manifest.
2391 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2393 * gencode.c: Tidied instruction decoding, and added FP instruction
2396 * interp.c: Added dineroIII, and BSD profiling support. Also
2397 run-time FP handling.
2399 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2401 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2402 gencode.c, interp.c, support.h: created.