sim/mips/ChangeLog

   1 2002-06-18  Andrew Cagney  <cagney@redhat.com>
   2
   3         * interp.c (sim_firmware_command): Initialize `address'.
   4
   5 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
   6
   7         * configure: Regenerated to track ../common/aclocal.m4 changes.
   8
   9 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
  10             Ed Satterthwaite  <ehs@broadcom.com>
  11
  12         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
  13         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
  14         * mips.igen: Include mips3d.igen.
  15         (mips3d): New model name for MIPS-3D ASE instructions.
  16         (CVT.W.fmt): Don't use this instruction for word (source) format
  17         instructions.
  18         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
  19         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
  20         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
  21         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
  22         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
  23         (RSquareRoot1, RSquareRoot2): New macros.
  24         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
  25         (fp_rsqrt2): New functions.
  26         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
  27         * configure: Regenerate.
  28
  29 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
  30             Ed Satterthwaite  <ehs@broadcom.com>
  31
  32         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
  33         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
  34         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
  35         (convert): Note that this function is not used for paired-single
  36         format conversions.
  37         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
  38         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
  39         (check_fmt_p): Enable paired-single support.
  40         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
  41         (PUU.PS): New instructions.
  42         (CVT.S.fmt): Don't use this instruction for paired-single format
  43         destinations.
  44         * sim-main.h (FP_formats): New value 'fmt_ps.'
  45         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
  46         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
  47
  48 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
  49
  50         * mips.igen: Fix formatting of function calls in
  51         many FP operations.
  52
  53 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
  54
  55         * mips.igen (MOVN, MOVZ): Trace result.
  56         (TNEI): Print "tnei" as the opcode name in traces.
  57         (CEIL.W): Add disassembly string for traces.
  58         (RSQRT.fmt): Make location of disassembly string consistent
  59         with other instructions.
  60
  61 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
  62
  63         * mips.igen (X): Delete unused function.
  64
  65 2002-06-08  Andrew Cagney  <cagney@redhat.com>
  66
  67         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
  68
  69 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  70             Ed Satterthwaite  <ehs@broadcom.com>
  71
  72         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
  73         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
  74         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
  75         (fp_nmsub): New prototypes.
  76         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
  77         (NegMultiplySub): New defines.
  78         * mips.igen (RSQRT.fmt): Use RSquareRoot().
  79         (MADD.D, MADD.S): Replace with...
  80         (MADD.fmt): New instruction.
  81         (MSUB.D, MSUB.S): Replace with...
  82         (MSUB.fmt): New instruction.
  83         (NMADD.D, NMADD.S): Replace with...
  84         (NMADD.fmt): New instruction.
  85         (NMSUB.D, MSUB.S): Replace with...
  86         (NMSUB.fmt): New instruction.
  87
  88 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  89             Ed Satterthwaite  <ehs@broadcom.com>
  90
  91         * cp1.c: Fix more comment spelling and formatting.
  92         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
  93         (denorm_mode): New function.
  94         (fpu_unary, fpu_binary): Round results after operation, collect
  95         status from rounding operations, and update the FCSR.
  96         (convert): Collect status from integer conversions and rounding
  97         operations, and update the FCSR.  Adjust NaN values that result
  98         from conversions.  Convert to use sim_io_eprintf rather than
  99         fprintf, and remove some debugging code.
 100         * cp1.h (fenr_FS): New define.
 101
 102 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 103
 104         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 105         rounding mode to sim FP rounding mode flag conversion code into...
 106         (rounding_mode): New function.
 107
 108 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 109
 110         * cp1.c: Clean up formatting of a few comments.
 111         (value_fpr): Reformat switch statement.
 112
 113 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 114             Ed Satterthwaite  <ehs@broadcom.com>
 115
 116         * cp1.h: New file.
 117         * sim-main.h: Include cp1.h.
 118         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 119         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 120         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 121         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 122         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 123         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 124         * cp1.c: Don't include sim-fpu.h; already included by
 125         sim-main.h.  Clean up formatting of some comments.
 126         (NaN, Equal, Less): Remove.
 127         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 128         (fp_cmp): New functions.
 129         * mips.igen (do_c_cond_fmt): Remove.
 130         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 131         Compare.  Add result tracing.
 132         (CxC1): Remove, replace with...
 133         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 134         (DMxC1): Remove, replace with...
 135         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 136         (MxC1): Remove, replace with...
 137         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 138
 139 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 140
 141         * sim-main.h (FGRIDX): Remove, replace all uses with...
 142         (FGR_BASE): New macro.
 143         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 144         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 145         (NR_FGR, FGR): Likewise.
 146         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 147         * mips.igen: Likewise.
 148
 149 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 150
 151         * cp1.c: Add an FSF Copyright notice to this file.
 152
 153 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 154             Ed Satterthwaite  <ehs@broadcom.com>
 155
 156         * cp1.c (Infinity): Remove.
 157         * sim-main.h (Infinity): Likewise.
 158
 159         * cp1.c (fp_unary, fp_binary): New functions.
 160         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 161         (fp_sqrt): New functions, implemented in terms of the above.
 162         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 163         (Recip, SquareRoot): Remove (replaced by functions above).
 164         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 165         (fp_recip, fp_sqrt): New prototypes.
 166         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 167         (Recip, SquareRoot): Replace prototypes with #defines which
 168         invoke the functions above.
 169
 170 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 171
 172         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 173         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 174         file, remove PARAMS from prototypes.
 175         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 176         simulator state arguments.
 177         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 178         pass simulator state arguments.
 179         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 180         (store_fpr, convert): Remove 'sd' argument.
 181         (value_fpr): Likewise.  Convert to use 'SD' instead.
 182
 183 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 184
 185         * cp1.c (Min, Max): Remove #if 0'd functions.
 186         * sim-main.h (Min, Max): Remove.
 187
 188 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 189
 190         * cp1.c: fix formatting of switch case and default labels.
 191         * interp.c: Likewise.
 192         * sim-main.c: Likewise.
 193
 194 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 195
 196         * cp1.c: Clean up comments which describe FP formats.
 197          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 198
 199 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 200             Ed Satterthwaite  <ehs@broadcom.com>
 201
 202         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 203         Broadcom SiByte SB-1 processor configurations.
 204         * configure: Regenerate.
 205         * sb1.igen: New file.
 206         * mips.igen: Include sb1.igen.
 207         (sb1): New model.
 208         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 209         * mdmx.igen: Add "sb1" model to all appropriate functions and
 210         instructions.
 211         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 212         (ob_func, ob_acc): Reference the above.
 213         (qh_acc): Adjust to keep the same size as ob_acc.
 214         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 215         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 216
 217 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 218
 219         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 220
 221 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 222             Ed Satterthwaite  <ehs@broadcom.com>
 223
 224         * mips.igen (mdmx): New (pseudo-)model.
 225         * mdmx.c, mdmx.igen: New files.
 226         * Makefile.in (SIM_OBJS): Add mdmx.o.
 227         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 228         New typedefs.
 229         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 230         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 231         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 232         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 233         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 234         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 235         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 236         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 237         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 238         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 239         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 240         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 241         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 242         (qh_fmtsel): New macros.
 243         (_sim_cpu): New member "acc".
 244         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 245         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 246
 247 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 248
 249         * interp.c: Use 'deprecated' rather than 'depreciated.'
 250         * sim-main.h: Likewise.
 251
 252 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 253
 254         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 255         which wouldn't compile anyway.
 256         * sim-main.h (unpredictable_action): New function prototype.
 257         (Unpredictable): Define to call igen function unpredictable().
 258         (NotWordValue): New macro to call igen function not_word_value().
 259         (UndefinedResult): Remove.
 260         * interp.c (undefined_result): Remove.
 261         (unpredictable_action): New function.
 262         * mips.igen (not_word_value, unpredictable): New functions.
 263         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 264         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 265         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 266         NotWordValue() to check for unpredictable inputs, then
 267         Unpredictable() to handle them.
 268
 269 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 270
 271         * mips.igen: Fix formatting of calls to Unpredictable().
 272
 273 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 274
 275         * interp.c (sim_open): Revert previous change.
 276
 277 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 278
 279         * interp.c (sim_open): Disable chunk of code that wrote code in
 280         vector table entries.
 281
 282 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 283
 284         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 285         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 286         unused definitions.
 287
 288 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 289
 290         * cp1.c: Fix many formatting issues.
 291
 292 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 293
 294         * cp1.c (fpu_format_name): New function to replace...
 295         (DOFMT): This.  Delete, and update all callers.
 296         (fpu_rounding_mode_name): New function to replace...
 297         (RMMODE): This.  Delete, and update all callers.
 298
 299 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 300
 301         * interp.c: Move FPU support routines from here to...
 302         * cp1.c: Here.  New file.
 303         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 304         (cp1.o): New target.
 305
 306 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 307
 308         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 309         * mips.igen (mips32, mips64): New models, add to all instructions
 310         and functions as appropriate.
 311         (loadstore_ea, check_u64): New variant for model mips64.
 312         (check_fmt_p): New variant for models mipsV and mips64, remove
 313         mipsV model marking fro other variant.
 314         (SLL) Rename to...
 315         (SLLa) this.
 316         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 317         for mips32 and mips64.
 318         (DCLO, DCLZ): New instructions for mips64.
 319
 320 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 321
 322         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 323         immediate or code as a hex value with the "%#lx" format.
 324         (ANDI): Likewise, and fix printed instruction name.
 325
 326 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 327
 328         * sim-main.h (UndefinedResult, Unpredictable): New macros
 329         which currently do nothing.
 330
 331 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 332
 333         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 334         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 335         (status_CU3): New definitions.
 336
 337         * sim-main.h (ExceptionCause): Add new values for MIPS32
 338         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 339         for DebugBreakPoint and NMIReset to note their status in
 340         MIPS32 and MIPS64.
 341         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 342         (SignalExceptionCacheErr): New exception macros.
 343
 344 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 345
 346         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 347         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 348         is always enabled.
 349         (SignalExceptionCoProcessorUnusable): Take as argument the
 350         unusable coprocessor number.
 351
 352 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 353
 354         * mips.igen: Fix formatting of all SignalException calls.
 355
 356 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 357
 358         * sim-main.h (SIGNEXTEND): Remove.
 359
 360 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 361
 362         * mips.igen: Remove gencode comment from top of file, fix
 363         spelling in another comment.
 364
 365 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 366
 367         * mips.igen (check_fmt, check_fmt_p): New functions to check
 368         whether specific floating point formats are usable.
 369         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 370         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 371         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 372         Use the new functions.
 373         (do_c_cond_fmt): Remove format checks...
 374         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 375
 376 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 377
 378         * mips.igen: Fix formatting of check_fpu calls.
 379
 380 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 381
 382         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 383
 384 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 385
 386         * mips.igen: Remove whitespace at end of lines.
 387
 388 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 389
 390         * mips.igen (loadstore_ea): New function to do effective
 391         address calculations.
 392         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 393         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 394         CACHE): Use loadstore_ea to do effective address computations.
 395
 396 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 397
 398         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 399         * mips.igen (LL, CxC1, MxC1): Likewise.
 400
 401 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 402
 403         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 404         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 405         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 406         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 407         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 408         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 409         Don't split opcode fields by hand, use the opcode field values
 410         provided by igen.
 411
 412 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 413
 414         * mips.igen (do_divu): Fix spacing.
 415
 416         * mips.igen (do_dsllv): Move to be right before DSLLV,
 417         to match the rest of the do_<shift> functions.
 418
 419 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 420
 421         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 422         DSRL32, do_dsrlv): Trace inputs and results.
 423
 424 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 425
 426         * mips.igen (CACHE): Provide instruction-printing string.
 427
 428         * interp.c (signal_exception): Comment tokens after #endif.
 429
 430 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 431
 432         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 433         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 434         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 435         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 436         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 437         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 438         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 439         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 440
 441 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 442
 443         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 444         instruction-printing string.
 445         (LWU): Use '64' as the filter flag.
 446
 447 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 448
 449         * mips.igen (SDXC1): Fix instruction-printing string.
 450
 451 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 452
 453         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 454         filter flags "32,f".
 455
 456 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 457
 458         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 459         as the filter flag.
 460
 461 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 462
 463         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 464         add a comma) so that it more closely match the MIPS ISA
 465         documentation opcode partitioning.
 466         (PREF): Put useful names on opcode fields, and include
 467         instruction-printing string.
 468
 469 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 470
 471         * mips.igen (check_u64): New function which in the future will
 472         check whether 64-bit instructions are usable and signal an
 473         exception if not.  Currently a no-op.
 474         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 475         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 476         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 477         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 478
 479         * mips.igen (check_fpu): New function which in the future will
 480         check whether FPU instructions are usable and signal an exception
 481         if not.  Currently a no-op.
 482         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 483         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 484         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 485         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 486         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 487         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 488         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 489         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 490
 491 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 492
 493         * mips.igen (do_load_left, do_load_right): Move to be immediately
 494         following do_load.
 495         (do_store_left, do_store_right): Move to be immediately following
 496         do_store.
 497
 498 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 499
 500         * mips.igen (mipsV): New model name.  Also, add it to
 501         all instructions and functions where it is appropriate.
 502
 503 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 504
 505         * mips.igen: For all functions and instructions, list model
 506         names that support that instruction one per line.
 507
 508 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 509
 510         * mips.igen: Add some additional comments about supported
 511         models, and about which instructions go where.
 512         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 513         order as is used in the rest of the file.
 514
 515 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 516
 517         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 518         indicating that ALU32_END or ALU64_END are there to check
 519         for overflow.
 520         (DADD): Likewise, but also remove previous comment about
 521         overflow checking.
 522
 523 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 524
 525         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 526         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 527         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 528         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 529         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 530         fields (i.e., add and move commas) so that they more closely
 531         match the MIPS ISA documentation opcode partitioning.
 532
 533 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 534
 535         * mips.igen (ADDI): Print immediate value.
 536         (BREAK): Print code.
 537         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 538         (SLL): Print "nop" specially, and don't run the code
 539         that does the shift for the "nop" case.
 540
 541 2001-11-17  Fred Fish  <fnf@redhat.com>
 542
 543         * sim-main.h (float_operation): Move enum declaration outside
 544         of _sim_cpu struct declaration.
 545
 546 2001-04-12  Jim Blandy  <jimb@redhat.com>
 547
 548         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 549         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 550         set of the FCSR.
 551         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 552         PENDING_FILL, and you can get the intended effect gracefully by
 553         calling PENDING_SCHED directly.
 554
 555 2001-02-23  Ben Elliston  <bje@redhat.com>
 556
 557         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 558         already defined elsewhere.
 559
 560 2001-02-19  Ben Elliston  <bje@redhat.com>
 561
 562         * sim-main.h (sim_monitor): Return an int.
 563         * interp.c (sim_monitor): Add return values.
 564         (signal_exception): Handle error conditions from sim_monitor.
 565
 566 2001-02-08  Ben Elliston  <bje@redhat.com>
 567
 568         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 569         (store_memory): Likewise, pass cia to sim_core_write*.
 570
 571 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 572
 573         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 574         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 575
 576 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 577
 578         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 579         * Makefile.in: Don't delete *.igen when cleaning directory.
 580
 581 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 582
 583         * m16.igen (break): Call SignalException not sim_engine_halt.
 584
 585 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 586
 587         From Jason Eckhardt:
 588         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 589
 590 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 591
 592         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 593
 594 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 595
 596         * mips.igen (do_dmultx): Fix typo.
 597
 598 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 599
 600         * configure: Regenerated to track ../common/aclocal.m4 changes.
 601
 602 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 603
 604         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 605
 606 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 607
 608         * sim-main.h (GPR_CLEAR): Define macro.
 609
 610 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 611
 612         * interp.c (decode_coproc): Output long using %lx and not %s.
 613
 614 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 615
 616         * interp.c (sim_open): Sort & extend dummy memory regions for
 617         --board=jmr3904 for eCos.
 618
 619 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 620
 621         * configure: Regenerated.
 622
 623 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 624
 625         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 626         calls, conditional on the simulator being in verbose mode.
 627
 628 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 629
 630         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 631         cache don't get ReservedInstruction traps.
 632
 633 1999-11-29  Mark Salter  <msalter@cygnus.com>
 634
 635         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 636         to clear status bits in sdisr register. This is how the hardware works.
 637
 638         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 639         being used by cygmon.
 640
 641 1999-11-11  Andrew Haley  <aph@cygnus.com>
 642
 643         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 644         instructions.
 645
 646 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 647
 648         * mips.igen (MULT): Correct previous mis-applied patch.
 649
 650 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 651
 652         * mips.igen (delayslot32): Handle sequence like
 653         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 654         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 655         (MULT): Actually pass the third register...
 656
 657 1999-09-03  Mark Salter  <msalter@cygnus.com>
 658
 659         * interp.c (sim_open): Added more memory aliases for additional
 660         hardware being touched by cygmon on jmr3904 board.
 661
 662 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 663
 664         * configure: Regenerated to track ../common/aclocal.m4 changes.
 665
 666 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 667
 668         * interp.c (sim_store_register): Handle case where client - GDB -
 669         specifies that a 4 byte register is 8 bytes in size.
 670         (sim_fetch_register): Ditto.
 671
 672 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 673
 674         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 675         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 676         (idt_monitor_base): Base address for IDT monitor traps.
 677         (pmon_monitor_base): Ditto for PMON.
 678         (lsipmon_monitor_base): Ditto for LSI PMON.
 679         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 680         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 681         (sim_firmware_command): New function.
 682         (mips_option_handler): Call it for OPTION_FIRMWARE.
 683         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 684         option was given, add no monitor by default.  Add BREAK hooks only if
 685         monitors are also there.
 686
 687 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 688
 689         * interp.c (sim_monitor): Flush output before reading input.
 690
 691 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 692
 693         * tconfig.in (SIM_HANDLES_LMA): Always define.
 694
 695 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 696
 697         From Mark Salter <msalter@cygnus.com>:
 698         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 699         (sim_open): Add setup for BSP board.
 700
 701 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 702
 703         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 704         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 705         them as unimplemented.
 706
 707 1999-05-08  Felix Lee  <flee@cygnus.com>
 708
 709         * configure: Regenerated to track ../common/aclocal.m4 changes.
 710
 711 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 712
 713         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 714
 715 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 716
 717         * configure.in: Any mips64vr5*-*-* target should have
 718         -DTARGET_ENABLE_FR=1.
 719         (default_endian): Any mips64vr*el-*-* target should default to
 720         LITTLE_ENDIAN.
 721         * configure: Re-generate.
 722
 723 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 724
 725         * mips.igen (ldl): Extend from _16_, not 32.
 726
 727 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 728
 729         * interp.c (sim_store_register): Force registers written to by GDB
 730         into an un-interpreted state.
 731
 732 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 733
 734         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 735         CPU, start periodic background I/O polls.
 736         (tx3904sio_poll): New function: periodic I/O poller.
 737
 738 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 739
 740         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 741
 742 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 743
 744         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 745         case statement.
 746
 747 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 748
 749         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 750         (load_word): Call SIM_CORE_SIGNAL hook on error.
 751         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 752         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 753         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 754         * sim-main.h (COP0_BADVADDR): Define.
 755         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 756         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 757         (_sim_cpu): Add exc_* fields to store register value snapshots.
 758         * mips.igen (*): Replace memory-related SignalException* calls
 759         with references to SIM_CORE_SIGNAL hook.
 760
 761         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 762         fix.
 763         * sim-main.c (*): Minor warning cleanups.
 764
 765 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 766
 767         * m16.igen (DADDIU5): Correct type-o.
 768
 769 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 770
 771         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 772         variables.
 773
 774 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 775
 776         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 777         to include path.
 778         (interp.o): Add dependency on itable.h
 779         (oengine.c, gencode): Delete remaining references.
 780         (BUILT_SRC_FROM_GEN): Clean up.
 781
 782 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 783
 784         * vr4run.c: New.
 785         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 786         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 787         tmp-run-hack) : New.
 788         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 789         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 790         Drop the "64" qualifier to get the HACK generator working.
 791         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 792         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 793         qualifier to get the hack generator working.
 794         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 795         (DSLL): Use do_dsll.
 796         (DSLLV): Use do_dsllv.
 797         (DSRA): Use do_dsra.
 798         (DSRL): Use do_dsrl.
 799         (DSRLV): Use do_dsrlv.
 800         (BC1): Move *vr4100 to get the HACK generator working.
 801         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 802         get the HACK generator working.
 803         (MACC) Rename to get the HACK generator working.
 804         (DMACC,MACCS,DMACCS): Add the 64.
 805
 806 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 807
 808         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 809         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 810
 811 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 812
 813     * mips/interp.c (DEBUG): Cleanups.
 814
 815 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 816
 817         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 818         (tx3904sio_tickle): fflush after a stdout character output.
 819
 820 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 821
 822         * interp.c (sim_close): Uninstall modules.
 823
 824 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 825
 826         * sim-main.h, interp.c (sim_monitor): Change to global
 827         function.
 828
 829 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 830
 831         * configure.in (vr4100): Only include vr4100 instructions in
 832         simulator.
 833         * configure: Re-generate.
 834         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 835
 836 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 837
 838         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 839         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 840         true alternative.
 841
 842         * configure.in (sim_default_gen, sim_use_gen): Replace with
 843         sim_gen.
 844         (--enable-sim-igen): Delete config option. Always using IGEN.
 845         * configure: Re-generate.
 846
 847         * Makefile.in (gencode): Kill, kill, kill.
 848         * gencode.c: Ditto.
 849
 850 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 851
 852         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 853         bit mips16 igen simulator.
 854         * configure: Re-generate.
 855
 856         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 857         as part of vr4100 ISA.
 858         * vr.igen: Mark all instructions as 64 bit only.
 859
 860 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 861
 862         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 863         Pacify GCC.
 864
 865 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 866
 867         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 868         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 869         * configure: Re-generate.
 870
 871         * m16.igen (BREAK): Define breakpoint instruction.
 872         (JALX32): Mark instruction as mips16 and not r3900.
 873         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 874
 875         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 876
 877 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 878
 879         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 880         insn as a debug breakpoint.
 881
 882         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 883         pending.slot_size.
 884         (PENDING_SCHED): Clean up trace statement.
 885         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 886         (PENDING_FILL): Delay write by only one cycle.
 887         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 888
 889         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 890         of pending writes.
 891         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 892         32 & 64.
 893         (pending_tick): Move incrementing of index to FOR statement.
 894         (pending_tick): Only update PENDING_OUT after a write has occured.
 895
 896         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 897         build simulator.
 898         * configure: Re-generate.
 899
 900         * interp.c (sim_engine_run OLD): Delete explicit call to
 901         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 902
 903 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 904
 905         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 906         interrupt level number to match changed SignalExceptionInterrupt
 907         macro.
 908
 909 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 910
 911         * interp.c: #include "itable.h" if WITH_IGEN.
 912         (get_insn_name): New function.
 913         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 914         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 915
 916 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 917
 918         * configure: Rebuilt to inhale new common/aclocal.m4.
 919
 920 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 921
 922         * dv-tx3904sio.c: Include sim-assert.h.
 923
 924 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 925
 926         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 927         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 928         Reorganize target-specific sim-hardware checks.
 929         * configure: rebuilt.
 930         * interp.c (sim_open): For tx39 target boards, set
 931         OPERATING_ENVIRONMENT, add tx3904sio devices.
 932         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 933         ROM executables.  Install dv-sockser into sim-modules list.
 934
 935         * dv-tx3904irc.c: Compiler warning clean-up.
 936         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 937         frequent hw-trace messages.
 938
 939 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 940
 941         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 942
 943 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 944
 945         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 946
 947         * vr.igen: New file.
 948         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 949         * mips.igen: Define vr4100 model. Include vr.igen.
 950 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 951
 952         * mips.igen (check_mf_hilo): Correct check.
 953
 954 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 955
 956         * sim-main.h (interrupt_event): Add prototype.
 957
 958         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 959         register_ptr, register_value.
 960         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 961
 962         * sim-main.h (tracefh): Make extern.
 963
 964 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 965
 966         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 967         Reduce unnecessarily high timer event frequency.
 968         * dv-tx3904cpu.c: Ditto for interrupt event.
 969
 970 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 971
 972         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 973         to allay warnings.
 974         (interrupt_event): Made non-static.
 975
 976         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 977         interchange of configuration values for external vs. internal
 978         clock dividers.
 979
 980 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 981
 982         * mips.igen (BREAK): Moved code to here for
 983         simulator-reserved break instructions.
 984         * gencode.c (build_instruction): Ditto.
 985         * interp.c (signal_exception): Code moved from here.  Non-
 986         reserved instructions now use exception vector, rather
 987         than halting sim.
 988         * sim-main.h: Moved magic constants to here.
 989
 990 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 991
 992         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 993         register upon non-zero interrupt event level, clear upon zero
 994         event value.
 995         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 996         by passing zero event value.
 997         (*_io_{read,write}_buffer): Endianness fixes.
 998         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 999         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1000
1001         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1002         serial I/O and timer module at base address 0xFFFF0000.
1003
1004 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1005
1006         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1007         and BigEndianCPU.
1008
1009 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1010
1011         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1012         parts.
1013         * configure: Update.
1014
1015 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1016
1017         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1018         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1019         * configure.in: Include tx3904tmr in hw_device list.
1020         * configure: Rebuilt.
1021         * interp.c (sim_open): Instantiate three timer instances.
1022         Fix address typo of tx3904irc instance.
1023
1024 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1025
1026         * interp.c (signal_exception): SystemCall exception now uses
1027         the exception vector.
1028
1029 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1030
1031         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1032         to allay warnings.
1033
1034 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1035
1036         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1037
1038 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1039
1040         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1041
1042         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1043         sim-main.h. Declare a struct hw_descriptor instead of struct
1044         hw_device_descriptor.
1045
1046 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1047
1048         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1049         right bits and then re-align left hand bytes to correct byte
1050         lanes.  Fix incorrect computation in do_store_left when loading
1051         bytes from second word.
1052
1053 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1054
1055         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1056         * interp.c (sim_open): Only create a device tree when HW is
1057         enabled.
1058
1059         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1060         * interp.c (signal_exception): Ditto.
1061
1062 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1063
1064         * gencode.c: Mark BEGEZALL as LIKELY.
1065
1066 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1067
1068         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1069         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1070
1071 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1072
1073         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1074         modules.  Recognize TX39 target with "mips*tx39" pattern.
1075         * configure: Rebuilt.
1076         * sim-main.h (*): Added many macros defining bits in
1077         TX39 control registers.
1078         (SignalInterrupt): Send actual PC instead of NULL.
1079         (SignalNMIReset): New exception type.
1080         * interp.c (board): New variable for future use to identify
1081         a particular board being simulated.
1082         (mips_option_handler,mips_options): Added "--board" option.
1083         (interrupt_event): Send actual PC.
1084         (sim_open): Make memory layout conditional on board setting.
1085         (signal_exception): Initial implementation of hardware interrupt
1086         handling.  Accept another break instruction variant for simulator
1087         exit.
1088         (decode_coproc): Implement RFE instruction for TX39.
1089         (mips.igen): Decode RFE instruction as such.
1090         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1091         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1092         bbegin to implement memory map.
1093         * dv-tx3904cpu.c: New file.
1094         * dv-tx3904irc.c: New file.
1095
1096 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1097
1098         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1099
1100 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1101
1102         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1103         with calls to check_div_hilo.
1104
1105 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1106
1107         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1108         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1109         Add special r3900 version of do_mult_hilo.
1110         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1111         with calls to check_mult_hilo.
1112         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1113         with calls to check_div_hilo.
1114
1115 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1116
1117         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1118         Document a replacement.
1119
1120 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1121
1122         * interp.c (sim_monitor): Make mon_printf work.
1123
1124 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1125
1126         * sim-main.h (INSN_NAME): New arg `cpu'.
1127
1128 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1129
1130         * configure: Regenerated to track ../common/aclocal.m4 changes.
1131
1132 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1133
1134         * configure: Regenerated to track ../common/aclocal.m4 changes.
1135         * config.in: Ditto.
1136
1137 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1138
1139         * acconfig.h: New file.
1140         * configure.in: Reverted change of Apr 24; use sinclude again.
1141
1142 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1143
1144         * configure: Regenerated to track ../common/aclocal.m4 changes.
1145         * config.in: Ditto.
1146
1147 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1148
1149         * configure.in: Don't call sinclude.
1150
1151 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1152
1153         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1154
1155 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1156
1157         * mips.igen (ERET): Implement.
1158
1159         * interp.c (decode_coproc): Return sign-extended EPC.
1160
1161         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1162
1163         * interp.c (signal_exception): Do not ignore Trap.
1164         (signal_exception): On TRAP, restart at exception address.
1165         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1166         (signal_exception): Update.
1167         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1168         so that TRAP instructions are caught.
1169
1170 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1171
1172         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1173         contains HI/LO access history.
1174         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1175         (HIACCESS, LOACCESS): Delete, replace with
1176         (HIHISTORY, LOHISTORY): New macros.
1177         (CHECKHILO): Delete all, moved to mips.igen
1178
1179         * gencode.c (build_instruction): Do not generate checks for
1180         correct HI/LO register usage.
1181
1182         * interp.c (old_engine_run): Delete checks for correct HI/LO
1183         register usage.
1184
1185         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1186         check_mf_cycles): New functions.
1187         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1188         do_divu, domultx, do_mult, do_multu): Use.
1189
1190         * tx.igen ("madd", "maddu"): Use.
1191
1192 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1193
1194         * mips.igen (DSRAV): Use function do_dsrav.
1195         (SRAV): Use new function do_srav.
1196
1197         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1198         (B): Sign extend 11 bit immediate.
1199         (EXT-B*): Shift 16 bit immediate left by 1.
1200         (ADDIU*): Don't sign extend immediate value.
1201
1202 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1203
1204         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1205
1206         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1207         functions.
1208
1209         * mips.igen (delayslot32, nullify_next_insn): New functions.
1210         (m16.igen): Always include.
1211         (do_*): Add more tracing.
1212
1213         * m16.igen (delayslot16): Add NIA argument, could be called by a
1214         32 bit MIPS16 instruction.
1215
1216         * interp.c (ifetch16): Move function from here.
1217         * sim-main.c (ifetch16): To here.
1218
1219         * sim-main.c (ifetch16, ifetch32): Update to match current
1220         implementations of LH, LW.
1221         (signal_exception): Don't print out incorrect hex value of illegal
1222         instruction.
1223
1224 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1225
1226         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1227         instruction.
1228
1229         * m16.igen: Implement MIPS16 instructions.
1230
1231         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1232         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1233         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1234         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1235         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1236         bodies of corresponding code from 32 bit insn to these.  Also used
1237         by MIPS16 versions of functions.
1238
1239         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1240         (IMEM16): Drop NR argument from macro.
1241
1242 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1243
1244         * Makefile.in (SIM_OBJS): Add sim-main.o.
1245
1246         * sim-main.h (address_translation, load_memory, store_memory,
1247         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1248         as INLINE_SIM_MAIN.
1249         (pr_addr, pr_uword64): Declare.
1250         (sim-main.c): Include when H_REVEALS_MODULE_P.
1251
1252         * interp.c (address_translation, load_memory, store_memory,
1253         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1254         from here.
1255         * sim-main.c: To here. Fix compilation problems.
1256
1257         * configure.in: Enable inlining.
1258         * configure: Re-config.
1259
1260 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1261
1262         * configure: Regenerated to track ../common/aclocal.m4 changes.
1263
1264 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1265
1266         * mips.igen: Include tx.igen.
1267         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1268         * tx.igen: New file, contains MADD and MADDU.
1269
1270         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1271         the hardwired constant `7'.
1272         (store_memory): Ditto.
1273         (LOADDRMASK): Move definition to sim-main.h.
1274
1275         mips.igen (MTC0): Enable for r3900.
1276         (ADDU): Add trace.
1277
1278         mips.igen (do_load_byte): Delete.
1279         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1280         do_store_right): New functions.
1281         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1282
1283         configure.in: Let the tx39 use igen again.
1284         configure: Update.
1285
1286 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1287
1288         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1289         not an address sized quantity.  Return zero for cache sizes.
1290
1291 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1292
1293         * mips.igen (r3900): r3900 does not support 64 bit integer
1294         operations.
1295
1296 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1297
1298         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1299         than igen one.
1300         * configure : Rebuild.
1301
1302 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1303
1304         * configure: Regenerated to track ../common/aclocal.m4 changes.
1305
1306 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1307
1308         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1309
1310 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1311
1312         * configure: Regenerated to track ../common/aclocal.m4 changes.
1313         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1314
1315 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1316
1317         * configure: Regenerated to track ../common/aclocal.m4 changes.
1318
1319 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1320
1321         * interp.c (Max, Min): Comment out functions. Not yet used.
1322
1323 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1324
1325         * configure: Regenerated to track ../common/aclocal.m4 changes.
1326
1327 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1328
1329         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1330         configurable settings for stand-alone simulator.
1331
1332         * configure.in: Added X11 search, just in case.
1333
1334         * configure: Regenerated.
1335
1336 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1337
1338         * interp.c (sim_write, sim_read, load_memory, store_memory):
1339         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1340
1341 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1342
1343         * sim-main.h (GETFCC): Return an unsigned value.
1344
1345 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1346
1347         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1348         (DADD): Result destination is RD not RT.
1349
1350 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1351
1352         * sim-main.h (HIACCESS, LOACCESS): Always define.
1353
1354         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1355
1356         * interp.c (sim_info): Delete.
1357
1358 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1359
1360         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1361         (mips_option_handler): New argument `cpu'.
1362         (sim_open): Update call to sim_add_option_table.
1363
1364 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1365
1366         * mips.igen (CxC1): Add tracing.
1367
1368 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1369
1370         * sim-main.h (Max, Min): Declare.
1371
1372         * interp.c (Max, Min): New functions.
1373
1374         * mips.igen (BC1): Add tracing.
1375
1376 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1377
1378         * interp.c Added memory map for stack in vr4100
1379
1380 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1381
1382         * interp.c (load_memory): Add missing "break"'s.
1383
1384 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1385
1386         * interp.c (sim_store_register, sim_fetch_register): Pass in
1387         length parameter.  Return -1.
1388
1389 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1390
1391         * interp.c: Added hardware init hook, fixed warnings.
1392
1393 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1394
1395         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1396
1397 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1398
1399         * interp.c (ifetch16): New function.
1400
1401         * sim-main.h (IMEM32): Rename IMEM.
1402         (IMEM16_IMMED): Define.
1403         (IMEM16): Define.
1404         (DELAY_SLOT): Update.
1405
1406         * m16run.c (sim_engine_run): New file.
1407
1408         * m16.igen: All instructions except LB.
1409         (LB): Call do_load_byte.
1410         * mips.igen (do_load_byte): New function.
1411         (LB): Call do_load_byte.
1412
1413         * mips.igen: Move spec for insn bit size and high bit from here.
1414         * Makefile.in (tmp-igen, tmp-m16): To here.
1415
1416         * m16.dc: New file, decode mips16 instructions.
1417
1418         * Makefile.in (SIM_NO_ALL): Define.
1419         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1420
1421 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1422
1423         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1424         point unit to 32 bit registers.
1425         * configure: Re-generate.
1426
1427 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1428
1429         * configure.in (sim_use_gen): Make IGEN the default simulator
1430         generator for generic 32 and 64 bit mips targets.
1431         * configure: Re-generate.
1432
1433 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1434
1435         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1436         bitsize.
1437
1438         * interp.c (sim_fetch_register, sim_store_register): Read/write
1439         FGR from correct location.
1440         (sim_open): Set size of FGR's according to
1441         WITH_TARGET_FLOATING_POINT_BITSIZE.
1442
1443         * sim-main.h (FGR): Store floating point registers in a separate
1444         array.
1445
1446 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1447
1448         * configure: Regenerated to track ../common/aclocal.m4 changes.
1449
1450 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1451
1452         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1453
1454         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1455
1456         * interp.c (pending_tick): New function.  Deliver pending writes.
1457
1458         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1459         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1460         it can handle mixed sized quantites and single bits.
1461
1462 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1463
1464         * interp.c (oengine.h): Do not include when building with IGEN.
1465         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1466         (sim_info): Ditto for PROCESSOR_64BIT.
1467         (sim_monitor): Replace ut_reg with unsigned_word.
1468         (*): Ditto for t_reg.
1469         (LOADDRMASK): Define.
1470         (sim_open): Remove defunct check that host FP is IEEE compliant,
1471         using software to emulate floating point.
1472         (value_fpr, ...): Always compile, was conditional on HASFPU.
1473
1474 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1475
1476         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1477         size.
1478
1479         * interp.c (SD, CPU): Define.
1480         (mips_option_handler): Set flags in each CPU.
1481         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1482         (sim_close): Do not clear STATE, deleted anyway.
1483         (sim_write, sim_read): Assume CPU zero's vm should be used for
1484         data transfers.
1485         (sim_create_inferior): Set the PC for all processors.
1486         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1487         argument.
1488         (mips16_entry): Pass correct nr of args to store_word, load_word.
1489         (ColdReset): Cold reset all cpu's.
1490         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1491         (sim_monitor, load_memory, store_memory, signal_exception): Use
1492         `CPU' instead of STATE_CPU.
1493
1494
1495         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1496         SD or CPU_.
1497
1498         * sim-main.h (signal_exception): Add sim_cpu arg.
1499         (SignalException*): Pass both SD and CPU to signal_exception.
1500         * interp.c (signal_exception): Update.
1501
1502         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1503         Ditto
1504         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1505         address_translation): Ditto
1506         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1507
1508 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1509
1510         * configure: Regenerated to track ../common/aclocal.m4 changes.
1511
1512 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1513
1514         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1515
1516         * mips.igen (model): Map processor names onto BFD name.
1517
1518         * sim-main.h (CPU_CIA): Delete.
1519         (SET_CIA, GET_CIA): Define
1520
1521 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1522
1523         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1524         regiser.
1525
1526         * configure.in (default_endian): Configure a big-endian simulator
1527         by default.
1528         * configure: Re-generate.
1529
1530 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1531
1532         * configure: Regenerated to track ../common/aclocal.m4 changes.
1533
1534 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1535
1536         * interp.c (sim_monitor): Handle Densan monitor outbyte
1537         and inbyte functions.
1538
1539 1997-12-29  Felix Lee  <flee@cygnus.com>
1540
1541         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1542
1543 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1544
1545         * Makefile.in (tmp-igen): Arrange for $zero to always be
1546         reset to zero after every instruction.
1547
1548 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1549
1550         * configure: Regenerated to track ../common/aclocal.m4 changes.
1551         * config.in: Ditto.
1552
1553 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1554
1555         * mips.igen (MSUB): Fix to work like MADD.
1556         * gencode.c (MSUB): Similarly.
1557
1558 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1559
1560         * configure: Regenerated to track ../common/aclocal.m4 changes.
1561
1562 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1563
1564         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1565
1566 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1567
1568         * sim-main.h (sim-fpu.h): Include.
1569
1570         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1571         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1572         using host independant sim_fpu module.
1573
1574 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1575
1576         * interp.c (signal_exception): Report internal errors with SIGABRT
1577         not SIGQUIT.
1578
1579         * sim-main.h (C0_CONFIG): New register.
1580         (signal.h): No longer include.
1581
1582         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1583
1584 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1585
1586         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1587
1588 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1589
1590         * mips.igen: Tag vr5000 instructions.
1591         (ANDI): Was missing mipsIV model, fix assembler syntax.
1592         (do_c_cond_fmt): New function.
1593         (C.cond.fmt): Handle mips I-III which do not support CC field
1594         separatly.
1595         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1596         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1597         in IV3.2 spec.
1598         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1599         vr5000 which saves LO in a GPR separatly.
1600
1601         * configure.in (enable-sim-igen): For vr5000, select vr5000
1602         specific instructions.
1603         * configure: Re-generate.
1604
1605 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1606
1607         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1608
1609         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1610         fmt_uninterpreted_64 bit cases to switch.  Convert to
1611         fmt_formatted,
1612
1613         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1614
1615         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1616         as specified in IV3.2 spec.
1617         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1618
1619 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1620
1621         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1622         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1623         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1624         PENDING_FILL versions of instructions.  Simplify.
1625         (X): New function.
1626         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1627         instructions.
1628         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1629         a signed value.
1630         (MTHI, MFHI): Disable code checking HI-LO.
1631
1632         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1633         global.
1634         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1635
1636 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1637
1638         * gencode.c (build_mips16_operands): Replace IPC with cia.
1639
1640         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1641         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1642         IPC to `cia'.
1643         (UndefinedResult): Replace function with macro/function
1644         combination.
1645         (sim_engine_run): Don't save PC in IPC.
1646
1647         * sim-main.h (IPC): Delete.
1648
1649
1650         * interp.c (signal_exception, store_word, load_word,
1651         address_translation, load_memory, store_memory, cache_op,
1652         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1653         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1654         current instruction address - cia - argument.
1655         (sim_read, sim_write): Call address_translation directly.
1656         (sim_engine_run): Rename variable vaddr to cia.
1657         (signal_exception): Pass cia to sim_monitor
1658
1659         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1660         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1661         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1662
1663         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1664         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1665         SIM_ASSERT.
1666
1667         * interp.c (signal_exception): Pass restart address to
1668         sim_engine_restart.
1669
1670         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1671         idecode.o): Add dependency.
1672
1673         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1674         Delete definitions
1675         (DELAY_SLOT): Update NIA not PC with branch address.
1676         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1677
1678         * mips.igen: Use CIA not PC in branch calculations.
1679         (illegal): Call SignalException.
1680         (BEQ, ADDIU): Fix assembler.
1681
1682 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1683
1684         * m16.igen (JALX): Was missing.
1685
1686         * configure.in (enable-sim-igen): New configuration option.
1687         * configure: Re-generate.
1688
1689         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1690
1691         * interp.c (load_memory, store_memory): Delete parameter RAW.
1692         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1693         bypassing {load,store}_memory.
1694
1695         * sim-main.h (ByteSwapMem): Delete definition.
1696
1697         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1698
1699         * interp.c (sim_do_command, sim_commands): Delete mips specific
1700         commands.  Handled by module sim-options.
1701
1702         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1703         (WITH_MODULO_MEMORY): Define.
1704
1705         * interp.c (sim_info): Delete code printing memory size.
1706
1707         * interp.c (mips_size): Nee sim_size, delete function.
1708         (power2): Delete.
1709         (monitor, monitor_base, monitor_size): Delete global variables.
1710         (sim_open, sim_close): Delete code creating monitor and other
1711         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1712         manage memory regions.
1713         (load_memory, store_memory): Use sim-core for memory model.
1714
1715         * interp.c (address_translation): Delete all memory map code
1716         except line forcing 32 bit addresses.
1717
1718 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1719
1720         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1721         trace options.
1722
1723         * interp.c (logfh, logfile): Delete globals.
1724         (sim_open, sim_close): Delete code opening & closing log file.
1725         (mips_option_handler): Delete -l and -n options.
1726         (OPTION mips_options): Ditto.
1727
1728         * interp.c (OPTION mips_options): Rename option trace to dinero.
1729         (mips_option_handler): Update.
1730
1731 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1732
1733         * interp.c (fetch_str): New function.
1734         (sim_monitor): Rewrite using sim_read & sim_write.
1735         (sim_open): Check magic number.
1736         (sim_open): Write monitor vectors into memory using sim_write.
1737         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1738         (sim_read, sim_write): Simplify - transfer data one byte at a
1739         time.
1740         (load_memory, store_memory): Clarify meaning of parameter RAW.
1741
1742         * sim-main.h (isHOST): Defete definition.
1743         (isTARGET): Mark as depreciated.
1744         (address_translation): Delete parameter HOST.
1745
1746         * interp.c (address_translation): Delete parameter HOST.
1747
1748 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1749
1750         * mips.igen:
1751
1752         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1753         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1754
1755 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1756
1757         * mips.igen: Add model filter field to records.
1758
1759 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1760
1761         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1762
1763         interp.c (sim_engine_run): Do not compile function sim_engine_run
1764         when WITH_IGEN == 1.
1765
1766         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1767         target architecture.
1768
1769         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1770         igen. Replace with configuration variables sim_igen_flags /
1771         sim_m16_flags.
1772
1773         * m16.igen: New file.  Copy mips16 insns here.
1774         * mips.igen: From here.
1775
1776 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1777
1778         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1779         to top.
1780         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1781
1782 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1783
1784         * gencode.c (build_instruction): Follow sim_write's lead in using
1785         BigEndianMem instead of !ByteSwapMem.
1786
1787 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1788
1789         * configure.in (sim_gen): Dependent on target, select type of
1790         generator.  Always select old style generator.
1791
1792         configure: Re-generate.
1793
1794         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1795         targets.
1796         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1797         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1798         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1799         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1800         SIM_@sim_gen@_*, set by autoconf.
1801
1802 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1803
1804         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1805
1806         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1807         CURRENT_FLOATING_POINT instead.
1808
1809         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1810         (address_translation): Raise exception InstructionFetch when
1811         translation fails and isINSTRUCTION.
1812
1813         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1814         sim_engine_run): Change type of of vaddr and paddr to
1815         address_word.
1816         (address_translation, prefetch, load_memory, store_memory,
1817         cache_op): Change type of vAddr and pAddr to address_word.
1818
1819         * gencode.c (build_instruction): Change type of vaddr and paddr to
1820         address_word.
1821
1822 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1823
1824         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1825         macro to obtain result of ALU op.
1826
1827 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1828
1829         * interp.c (sim_info): Call profile_print.
1830
1831 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1832
1833         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1834
1835         * sim-main.h (WITH_PROFILE): Do not define, defined in
1836         common/sim-config.h.  Use sim-profile module.
1837         (simPROFILE): Delete defintion.
1838
1839         * interp.c (PROFILE): Delete definition.
1840         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1841         (sim_close): Delete code writing profile histogram.
1842         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1843         Delete.
1844         (sim_engine_run): Delete code profiling the PC.
1845
1846 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1847
1848         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1849
1850         * interp.c (sim_monitor): Make register pointers of type
1851         unsigned_word*.
1852
1853         * sim-main.h: Make registers of type unsigned_word not
1854         signed_word.
1855
1856 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1857
1858         * interp.c (sync_operation): Rename from SyncOperation, make
1859         global, add SD argument.
1860         (prefetch): Rename from Prefetch, make global, add SD argument.
1861         (decode_coproc): Make global.
1862
1863         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1864
1865         * gencode.c (build_instruction): Generate DecodeCoproc not
1866         decode_coproc calls.
1867
1868         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1869         (SizeFGR): Move to sim-main.h
1870         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1871         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1872         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1873         sim-main.h.
1874         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1875         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1876         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1877         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1878         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1879         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1880
1881         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1882         exception.
1883         (sim-alu.h): Include.
1884         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1885         (sim_cia): Typedef to instruction_address.
1886
1887 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1888
1889         * Makefile.in (interp.o): Rename generated file engine.c to
1890         oengine.c.
1891
1892         * interp.c: Update.
1893
1894 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1895
1896         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1897
1898 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1899
1900         * gencode.c (build_instruction): For "FPSQRT", output correct
1901         number of arguments to Recip.
1902
1903 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1904
1905         * Makefile.in (interp.o): Depends on sim-main.h
1906
1907         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1908
1909         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1910         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1911         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1912         STATE, DSSTATE): Define
1913         (GPR, FGRIDX, ..): Define.
1914
1915         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1916         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1917         (GPR, FGRIDX, ...): Delete macros.
1918
1919         * interp.c: Update names to match defines from sim-main.h
1920
1921 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1922
1923         * interp.c (sim_monitor): Add SD argument.
1924         (sim_warning): Delete.  Replace calls with calls to
1925         sim_io_eprintf.
1926         (sim_error): Delete. Replace calls with sim_io_error.
1927         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1928         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1929         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1930         argument.
1931         (mips_size): Rename from sim_size. Add SD argument.
1932
1933         * interp.c (simulator): Delete global variable.
1934         (callback): Delete global variable.
1935         (mips_option_handler, sim_open, sim_write, sim_read,
1936         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1937         sim_size,sim_monitor): Use sim_io_* not callback->*.
1938         (sim_open): ZALLOC simulator struct.
1939         (PROFILE): Do not define.
1940
1941 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1942
1943         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1944         support.h with corresponding code.
1945
1946         * sim-main.h (word64, uword64), support.h: Move definition to
1947         sim-main.h.
1948         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1949
1950         * support.h: Delete
1951         * Makefile.in: Update dependencies
1952         * interp.c: Do not include.
1953
1954 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1955
1956         * interp.c (address_translation, load_memory, store_memory,
1957         cache_op): Rename to from AddressTranslation et.al., make global,
1958         add SD argument
1959
1960         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1961         CacheOp): Define.
1962
1963         * interp.c (SignalException): Rename to signal_exception, make
1964         global.
1965
1966         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1967
1968         * sim-main.h (SignalException, SignalExceptionInterrupt,
1969         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1970         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1971         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1972         Define.
1973
1974         * interp.c, support.h: Use.
1975
1976 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1977
1978         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1979         to value_fpr / store_fpr. Add SD argument.
1980         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1981         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1982
1983         * sim-main.h (ValueFPR, StoreFPR): Define.
1984
1985 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1986
1987         * interp.c (sim_engine_run): Check consistency between configure
1988         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1989         and HASFPU.
1990
1991         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1992         (mips_fpu): Configure WITH_FLOATING_POINT.
1993         (mips_endian): Configure WITH_TARGET_ENDIAN.
1994         * configure: Update.
1995
1996 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1997
1998         * configure: Regenerated to track ../common/aclocal.m4 changes.
1999
2000 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2001
2002         * configure: Regenerated.
2003
2004 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2005
2006         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2007
2008 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2009
2010         * gencode.c (print_igen_insn_models): Assume certain architectures
2011         include all mips* instructions.
2012         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2013         instruction.
2014
2015         * Makefile.in (tmp.igen): Add target. Generate igen input from
2016         gencode file.
2017
2018         * gencode.c (FEATURE_IGEN): Define.
2019         (main): Add --igen option.  Generate output in igen format.
2020         (process_instructions): Format output according to igen option.
2021         (print_igen_insn_format): New function.
2022         (print_igen_insn_models): New function.
2023         (process_instructions): Only issue warnings and ignore
2024         instructions when no FEATURE_IGEN.
2025
2026 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2027
2028         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2029         MIPS targets.
2030
2031 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2032
2033         * configure: Regenerated to track ../common/aclocal.m4 changes.
2034
2035 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2036
2037         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2038         SIM_RESERVED_BITS): Delete, moved to common.
2039         (SIM_EXTRA_CFLAGS): Update.
2040
2041 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2042
2043         * configure.in: Configure non-strict memory alignment.
2044         * configure: Regenerated to track ../common/aclocal.m4 changes.
2045
2046 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2047
2048         * configure: Regenerated to track ../common/aclocal.m4 changes.
2049
2050 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2051
2052         * gencode.c (SDBBP,DERET): Added (3900) insns.
2053         (RFE): Turn on for 3900.
2054         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2055         (dsstate): Made global.
2056         (SUBTARGET_R3900): Added.
2057         (CANCELDELAYSLOT): New.
2058         (SignalException): Ignore SystemCall rather than ignore and
2059         terminate.  Add DebugBreakPoint handling.
2060         (decode_coproc): New insns RFE, DERET; and new registers Debug
2061         and DEPC protected by SUBTARGET_R3900.
2062         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2063         bits explicitly.
2064         * Makefile.in,configure.in: Add mips subtarget option.
2065         * configure: Update.
2066
2067 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2068
2069         * gencode.c: Add r3900 (tx39).
2070
2071
2072 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2073
2074         * gencode.c (build_instruction): Don't need to subtract 4 for
2075         JALR, just 2.
2076
2077 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2078
2079         * interp.c: Correct some HASFPU problems.
2080
2081 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2082
2083         * configure: Regenerated to track ../common/aclocal.m4 changes.
2084
2085 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2086
2087         * interp.c (mips_options): Fix samples option short form, should
2088         be `x'.
2089
2090 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2091
2092         * interp.c (sim_info): Enable info code.  Was just returning.
2093
2094 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2095
2096         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2097         MFC0.
2098
2099 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2100
2101         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2102         constants.
2103         (build_instruction): Ditto for LL.
2104
2105 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2106
2107         * configure: Regenerated to track ../common/aclocal.m4 changes.
2108
2109 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2110
2111         * configure: Regenerated to track ../common/aclocal.m4 changes.
2112         * config.in: Ditto.
2113
2114 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2115
2116         * interp.c (sim_open): Add call to sim_analyze_program, update
2117         call to sim_config.
2118
2119 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2120
2121         * interp.c (sim_kill): Delete.
2122         (sim_create_inferior): Add ABFD argument. Set PC from same.
2123         (sim_load): Move code initializing trap handlers from here.
2124         (sim_open): To here.
2125         (sim_load): Delete, use sim-hload.c.
2126
2127         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2128
2129 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2130
2131         * configure: Regenerated to track ../common/aclocal.m4 changes.
2132         * config.in: Ditto.
2133
2134 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2135
2136         * interp.c (sim_open): Add ABFD argument.
2137         (sim_load): Move call to sim_config from here.
2138         (sim_open): To here.  Check return status.
2139
2140 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2141
2142         * gencode.c (build_instruction): Two arg MADD should
2143         not assign result to $0.
2144
2145 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2146
2147         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2148         * sim/mips/configure.in: Regenerate.
2149
2150 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2151
2152         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2153         signed8, unsigned8 et.al. types.
2154
2155         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2156         hosts when selecting subreg.
2157
2158 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2159
2160         * interp.c (sim_engine_run): Reset the ZERO register to zero
2161         regardless of FEATURE_WARN_ZERO.
2162         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2163
2164 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2165
2166         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2167         (SignalException): For BreakPoints ignore any mode bits and just
2168         save the PC.
2169         (SignalException): Always set the CAUSE register.
2170
2171 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2172
2173         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2174         exception has been taken.
2175
2176         * interp.c: Implement the ERET and mt/f sr instructions.
2177
2178 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2179
2180         * interp.c (SignalException): Don't bother restarting an
2181         interrupt.
2182
2183 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2184
2185         * interp.c (SignalException): Really take an interrupt.
2186         (interrupt_event): Only deliver interrupts when enabled.
2187
2188 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2189
2190         * interp.c (sim_info): Only print info when verbose.
2191         (sim_info) Use sim_io_printf for output.
2192
2193 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2194
2195         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2196         mips architectures.
2197
2198 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2199
2200         * interp.c (sim_do_command): Check for common commands if a
2201         simulator specific command fails.
2202
2203 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2204
2205         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2206         and simBE when DEBUG is defined.
2207
2208 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2209
2210         * interp.c (interrupt_event): New function.  Pass exception event
2211         onto exception handler.
2212
2213         * configure.in: Check for stdlib.h.
2214         * configure: Regenerate.
2215
2216         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2217         variable declaration.
2218         (build_instruction): Initialize memval1.
2219         (build_instruction): Add UNUSED attribute to byte, bigend,
2220         reverse.
2221         (build_operands): Ditto.
2222
2223         * interp.c: Fix GCC warnings.
2224         (sim_get_quit_code): Delete.
2225
2226         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2227         * Makefile.in: Ditto.
2228         * configure: Re-generate.
2229
2230         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2231
2232 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2233
2234         * interp.c (mips_option_handler): New function parse argumes using
2235         sim-options.
2236         (myname): Replace with STATE_MY_NAME.
2237         (sim_open): Delete check for host endianness - performed by
2238         sim_config.
2239         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2240         (sim_open): Move much of the initialization from here.
2241         (sim_load): To here.  After the image has been loaded and
2242         endianness set.
2243         (sim_open): Move ColdReset from here.
2244         (sim_create_inferior): To here.
2245         (sim_open): Make FP check less dependant on host endianness.
2246
2247         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2248         run.
2249         * interp.c (sim_set_callbacks): Delete.
2250
2251         * interp.c (membank, membank_base, membank_size): Replace with
2252         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2253         (sim_open): Remove call to callback->init. gdb/run do this.
2254
2255         * interp.c: Update
2256
2257         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2258
2259         * interp.c (big_endian_p): Delete, replaced by
2260         current_target_byte_order.
2261
2262 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2263
2264         * interp.c (host_read_long, host_read_word, host_swap_word,
2265         host_swap_long): Delete. Using common sim-endian.
2266         (sim_fetch_register, sim_store_register): Use H2T.
2267         (pipeline_ticks): Delete.  Handled by sim-events.
2268         (sim_info): Update.
2269         (sim_engine_run): Update.
2270
2271 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2272
2273         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2274         reason from here.
2275         (SignalException): To here. Signal using sim_engine_halt.
2276         (sim_stop_reason): Delete, moved to common.
2277
2278 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2279
2280         * interp.c (sim_open): Add callback argument.
2281         (sim_set_callbacks): Delete SIM_DESC argument.
2282         (sim_size): Ditto.
2283
2284 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2285
2286         * Makefile.in (SIM_OBJS): Add common modules.
2287
2288         * interp.c (sim_set_callbacks): Also set SD callback.
2289         (set_endianness, xfer_*, swap_*): Delete.
2290         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2291         Change to functions using sim-endian macros.
2292         (control_c, sim_stop): Delete, use common version.
2293         (simulate): Convert into.
2294         (sim_engine_run): This function.
2295         (sim_resume): Delete.
2296
2297         * interp.c (simulation): New variable - the simulator object.
2298         (sim_kind): Delete global - merged into simulation.
2299         (sim_load): Cleanup.  Move PC assignment from here.
2300         (sim_create_inferior): To here.
2301
2302         * sim-main.h: New file.
2303         * interp.c (sim-main.h): Include.
2304
2305 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2306
2307         * configure: Regenerated to track ../common/aclocal.m4 changes.
2308
2309 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2310
2311         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2312
2313 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2314
2315         * gencode.c (build_instruction): DIV instructions: check
2316         for division by zero and integer overflow before using
2317         host's division operation.
2318
2319 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2320
2321         * Makefile.in (SIM_OBJS): Add sim-load.o.
2322         * interp.c: #include bfd.h.
2323         (target_byte_order): Delete.
2324         (sim_kind, myname, big_endian_p): New static locals.
2325         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2326         after argument parsing.  Recognize -E arg, set endianness accordingly.
2327         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2328         load file into simulator.  Set PC from bfd.
2329         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2330         (set_endianness): Use big_endian_p instead of target_byte_order.
2331
2332 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2333
2334         * interp.c (sim_size): Delete prototype - conflicts with
2335         definition in remote-sim.h.  Correct definition.
2336
2337 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2338
2339         * configure: Regenerated to track ../common/aclocal.m4 changes.
2340         * config.in: Ditto.
2341
2342 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2343
2344         * interp.c (sim_open): New arg `kind'.
2345
2346         * configure: Regenerated to track ../common/aclocal.m4 changes.
2347
2348 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2349
2350         * configure: Regenerated to track ../common/aclocal.m4 changes.
2351
2352 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2353
2354         * interp.c (sim_open): Set optind to 0 before calling getopt.
2355
2356 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2357
2358         * configure: Regenerated to track ../common/aclocal.m4 changes.
2359
2360 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2361
2362         * interp.c : Replace uses of pr_addr with pr_uword64
2363         where the bit length is always 64 independent of SIM_ADDR.
2364         (pr_uword64) : added.
2365
2366 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2367
2368         * configure: Re-generate.
2369
2370 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2371
2372         * configure: Regenerate to track ../common/aclocal.m4 changes.
2373
2374 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2375
2376         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2377         in argv form.
2378         (other sim_*): New SIM_DESC argument.
2379
2380 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2381
2382         * interp.c: Fix printing of addresses for non-64-bit targets.
2383         (pr_addr): Add function to print address based on size.
2384
2385 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2386
2387         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2388
2389 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2390
2391         * gencode.c (build_mips16_operands): Correct computation of base
2392         address for extended PC relative instruction.
2393
2394 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2395
2396         * interp.c (mips16_entry): Add support for floating point cases.
2397         (SignalException): Pass floating point cases to mips16_entry.
2398         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2399         registers.
2400         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2401         or fmt_word.
2402         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2403         and then set the state to fmt_uninterpreted.
2404         (COP_SW): Temporarily set the state to fmt_word while calling
2405         ValueFPR.
2406
2407 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2408
2409         * gencode.c (build_instruction): The high order may be set in the
2410         comparison flags at any ISA level, not just ISA 4.
2411
2412 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2413
2414         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2415         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2416         * configure.in: sinclude ../common/aclocal.m4.
2417         * configure: Regenerated.
2418
2419 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2420
2421         * configure: Rebuild after change to aclocal.m4.
2422
2423 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2424
2425         * configure configure.in Makefile.in:  Update to new configure
2426         scheme which is more compatible with WinGDB builds.
2427         * configure.in:  Improve comment on how to run autoconf.
2428         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2429         * Makefile.in:  Use autoconf substitution to install common
2430         makefile fragment.
2431
2432 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2433
2434         * gencode.c (build_instruction): Use BigEndianCPU instead of
2435         ByteSwapMem.
2436
2437 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2438
2439         * interp.c (sim_monitor): Make output to stdout visible in
2440         wingdb's I/O log window.
2441
2442 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2443
2444         * support.h: Undo previous change to SIGTRAP
2445         and SIGQUIT values.
2446
2447 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2448
2449         * interp.c (store_word, load_word): New static functions.
2450         (mips16_entry): New static function.
2451         (SignalException): Look for mips16 entry and exit instructions.
2452         (simulate): Use the correct index when setting fpr_state after
2453         doing a pending move.
2454
2455 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2456
2457         * interp.c: Fix byte-swapping code throughout to work on
2458         both little- and big-endian hosts.
2459
2460 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2461
2462         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2463         with gdb/config/i386/xm-windows.h.
2464
2465 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2466
2467         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2468         that messes up arithmetic shifts.
2469
2470 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2471
2472         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2473         SIGTRAP and SIGQUIT for _WIN32.
2474
2475 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2476
2477         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2478         force a 64 bit multiplication.
2479         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2480         destination register is 0, since that is the default mips16 nop
2481         instruction.
2482
2483 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2484
2485         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2486         (build_endian_shift): Don't check proc64.
2487         (build_instruction): Always set memval to uword64.  Cast op2 to
2488         uword64 when shifting it left in memory instructions.  Always use
2489         the same code for stores--don't special case proc64.
2490
2491         * gencode.c (build_mips16_operands): Fix base PC value for PC
2492         relative operands.
2493         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2494         jal instruction.
2495         * interp.c (simJALDELAYSLOT): Define.
2496         (JALDELAYSLOT): Define.
2497         (INDELAYSLOT, INJALDELAYSLOT): Define.
2498         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2499
2500 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2501
2502         * interp.c (sim_open): add flush_cache as a PMON routine
2503         (sim_monitor): handle flush_cache by ignoring it
2504
2505 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2506
2507         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2508         BigEndianMem.
2509         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2510         (BigEndianMem): Rename to ByteSwapMem and change sense.
2511         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2512         BigEndianMem references to !ByteSwapMem.
2513         (set_endianness): New function, with prototype.
2514         (sim_open): Call set_endianness.
2515         (sim_info): Use simBE instead of BigEndianMem.
2516         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2517         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2518         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2519         ifdefs, keeping the prototype declaration.
2520         (swap_word): Rewrite correctly.
2521         (ColdReset): Delete references to CONFIG.  Delete endianness related
2522         code; moved to set_endianness.
2523
2524 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2525
2526         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2527         * interp.c (CHECKHILO): Define away.
2528         (simSIGINT): New macro.
2529         (membank_size): Increase from 1MB to 2MB.
2530         (control_c): New function.
2531         (sim_resume): Rename parameter signal to signal_number.  Add local
2532         variable prev.  Call signal before and after simulate.
2533         (sim_stop_reason): Add simSIGINT support.
2534         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2535         functions always.
2536         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2537         if logfh is NULL.
2538         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2539         a call to sim_warning.
2540
2541 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2542
2543         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2544         16 bit instructions.
2545
2546 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2547
2548         Add support for mips16 (16 bit MIPS implementation):
2549         * gencode.c (inst_type): Add mips16 instruction encoding types.
2550         (GETDATASIZEINSN): Define.
2551         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2552         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2553         mtlo.
2554         (MIPS16_DECODE): New table, for mips16 instructions.
2555         (bitmap_val): New static function.
2556         (struct mips16_op): Define.
2557         (mips16_op_table): New table, for mips16 operands.
2558         (build_mips16_operands): New static function.
2559         (process_instructions): If PC is odd, decode a mips16
2560         instruction.  Break out instruction handling into new
2561         build_instruction function.
2562         (build_instruction): New static function, broken out of
2563         process_instructions.  Check modifiers rather than flags for SHIFT
2564         bit count and m[ft]{hi,lo} direction.
2565         (usage): Pass program name to fprintf.
2566         (main): Remove unused variable this_option_optind.  Change
2567         ``*loptarg++'' to ``loptarg++''.
2568         (my_strtoul): Parenthesize && within ||.
2569         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2570         (simulate): If PC is odd, fetch a 16 bit instruction, and
2571         increment PC by 2 rather than 4.
2572         * configure.in: Add case for mips16*-*-*.
2573         * configure: Rebuild.
2574
2575 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2576
2577         * interp.c: Allow -t to enable tracing in standalone simulator.
2578         Fix garbage output in trace file and error messages.
2579
2580 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2581
2582         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2583         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2584         * configure.in: Simplify using macros in ../common/aclocal.m4.
2585         * configure: Regenerated.
2586         * tconfig.in: New file.
2587
2588 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2589
2590         * interp.c: Fix bugs in 64-bit port.
2591         Use ansi function declarations for msvc compiler.
2592         Initialize and test file pointer in trace code.
2593         Prevent duplicate definition of LAST_EMED_REGNUM.
2594
2595 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2596
2597         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2598
2599 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2600
2601         * interp.c (SignalException): Check for explicit terminating
2602         breakpoint value.
2603         * gencode.c: Pass instruction value through SignalException()
2604         calls for Trap, Breakpoint and Syscall.
2605
2606 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2607
2608         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2609         only used on those hosts that provide it.
2610         * configure.in: Add sqrt() to list of functions to be checked for.
2611         * config.in: Re-generated.
2612         * configure: Re-generated.
2613
2614 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2615
2616         * gencode.c (process_instructions): Call build_endian_shift when
2617         expanding STORE RIGHT, to fix swr.
2618         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2619         clear the high bits.
2620         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2621         Fix float to int conversions to produce signed values.
2622
2623 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2624
2625         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2626         (process_instructions): Correct handling of nor instruction.
2627         Correct shift count for 32 bit shift instructions. Correct sign
2628         extension for arithmetic shifts to not shift the number of bits in
2629         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2630         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2631         Fix madd.
2632         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2633         It's OK to have a mult follow a mult.  What's not OK is to have a
2634         mult follow an mfhi.
2635         (Convert): Comment out incorrect rounding code.
2636
2637 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2638
2639         * interp.c (sim_monitor): Improved monitor printf
2640         simulation. Tidied up simulator warnings, and added "--log" option
2641         for directing warning message output.
2642         * gencode.c: Use sim_warning() rather than WARNING macro.
2643
2644 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2645
2646         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2647         getopt1.o, rather than on gencode.c.  Link objects together.
2648         Don't link against -liberty.
2649         (gencode.o, getopt.o, getopt1.o): New targets.
2650         * gencode.c: Include <ctype.h> and "ansidecl.h".
2651         (AND): Undefine after including "ansidecl.h".
2652         (ULONG_MAX): Define if not defined.
2653         (OP_*): Don't define macros; now defined in opcode/mips.h.
2654         (main): Call my_strtoul rather than strtoul.
2655         (my_strtoul): New static function.
2656
2657 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2658
2659         * gencode.c (process_instructions):  Generate word64 and uword64
2660         instead of `long long' and `unsigned long long' data types.
2661         * interp.c:  #include sysdep.h to get signals, and define default
2662         for SIGBUS.
2663         * (Convert):  Work around for Visual-C++ compiler bug with type
2664         conversion.
2665         * support.h:  Make things compile under Visual-C++ by using
2666         __int64 instead of `long long'.  Change many refs to long long
2667         into word64/uword64 typedefs.
2668
2669 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2670
2671         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2672         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2673         (docdir): Removed.
2674         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2675         (AC_PROG_INSTALL): Added.
2676         (AC_PROG_CC): Moved to before configure.host call.
2677         * configure: Rebuilt.
2678
2679 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2680
2681         * configure.in: Define @SIMCONF@ depending on mips target.
2682         * configure: Rebuild.
2683         * Makefile.in (run): Add @SIMCONF@ to control simulator
2684         construction.
2685         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2686         * interp.c: Remove some debugging, provide more detailed error
2687         messages, update memory accesses to use LOADDRMASK.
2688
2689 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2690
2691         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2692         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2693         stamp-h.
2694         * configure: Rebuild.
2695         * config.in: New file, generated by autoheader.
2696         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2697         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2698         HAVE_ANINT and HAVE_AINT, as appropriate.
2699         * Makefile.in (run): Use @LIBS@ rather than -lm.
2700         (interp.o): Depend upon config.h.
2701         (Makefile): Just rebuild Makefile.
2702         (clean): Remove stamp-h.
2703         (mostlyclean): Make the same as clean, not as distclean.
2704         (config.h, stamp-h): New targets.
2705
2706 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2707
2708         * interp.c (ColdReset): Fix boolean test. Make all simulator
2709         globals static.
2710
2711 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2712
2713         * interp.c (xfer_direct_word, xfer_direct_long,
2714         swap_direct_word, swap_direct_long, xfer_big_word,
2715         xfer_big_long, xfer_little_word, xfer_little_long,
2716         swap_word,swap_long): Added.
2717         * interp.c (ColdReset): Provide function indirection to
2718         host<->simulated_target transfer routines.
2719         * interp.c (sim_store_register, sim_fetch_register): Updated to
2720         make use of indirected transfer routines.
2721
2722 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2723
2724         * gencode.c (process_instructions): Ensure FP ABS instruction
2725         recognised.
2726         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2727         system call support.
2728
2729 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2730
2731         * interp.c (sim_do_command): Complain if callback structure not
2732         initialised.
2733
2734 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2735
2736         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2737         support for Sun hosts.
2738         * Makefile.in (gencode): Ensure the host compiler and libraries
2739         used for cross-hosted build.
2740
2741 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2742
2743         * interp.c, gencode.c: Some more (TODO) tidying.
2744
2745 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2746
2747         * gencode.c, interp.c: Replaced explicit long long references with
2748         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2749         * support.h (SET64LO, SET64HI): Macros added.
2750
2751 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2752
2753         * configure: Regenerate with autoconf 2.7.
2754
2755 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2756
2757         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2758         * support.h: Remove superfluous "1" from #if.
2759         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2760
2761 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2762
2763         * interp.c (StoreFPR): Control UndefinedResult() call on
2764         WARN_RESULT manifest.
2765
2766 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2767
2768         * gencode.c: Tidied instruction decoding, and added FP instruction
2769         support.
2770
2771         * interp.c: Added dineroIII, and BSD profiling support. Also
2772         run-time FP handling.
2773
2774 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2775
2776         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2777         gencode.c, interp.c, support.h: created.