sim/mips/ChangeLog

   1 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
   2
   3         * interp.c (sim_open): Disable chunk of code that wrote code in
   4         vector table entries.
   5
   6 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
   7
   8         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
   9         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
  10         unused definitions.
  11
  12 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
  13
  14         * cp1.c: Fix many formatting issues.
  15
  16 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
  17
  18         * cp1.c (fpu_format_name): New function to replace...
  19         (DOFMT): This.  Delete, and update all callers.
  20         (fpu_rounding_mode_name): New function to replace...
  21         (RMMODE): This.  Delete, and update all callers.
  22
  23 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
  24
  25         * interp.c: Move FPU support routines from here to...
  26         * cp1.c: Here.  New file.
  27         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
  28         (cp1.o): New target.
  29
  30 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
  31
  32         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
  33         * mips.igen (mips32, mips64): New models, add to all instructions
  34         and functions as appropriate.
  35         (loadstore_ea, check_u64): New variant for model mips64.
  36         (check_fmt_p): New variant for models mipsV and mips64, remove
  37         mipsV model marking fro other variant.
  38         (SLL) Rename to...
  39         (SLLa) this.
  40         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
  41         for mips32 and mips64.
  42         (DCLO, DCLZ): New instructions for mips64.
  43
  44 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
  45
  46         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
  47         immediate or code as a hex value with the "%#lx" format.
  48         (ANDI): Likewise, and fix printed instruction name.
  49
  50 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  51
  52         * sim-main.h (UndefinedResult, Unpredictable): New macros
  53         which currently do nothing.
  54
  55 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  56
  57         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
  58         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
  59         (status_CU3): New definitions.
  60
  61         * sim-main.h (ExceptionCause): Add new values for MIPS32
  62         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
  63         for DebugBreakPoint and NMIReset to note their status in
  64         MIPS32 and MIPS64.
  65         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
  66         (SignalExceptionCacheErr): New exception macros.
  67
  68 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  69
  70         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
  71         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
  72         is always enabled.
  73         (SignalExceptionCoProcessorUnusable): Take as argument the
  74         unusable coprocessor number.
  75
  76 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  77
  78         * mips.igen: Fix formatting of all SignalException calls.
  79
  80 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  81
  82         * sim-main.h (SIGNEXTEND): Remove.
  83
  84 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
  85
  86         * mips.igen: Remove gencode comment from top of file, fix
  87         spelling in another comment.
  88
  89 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
  90
  91         * mips.igen (check_fmt, check_fmt_p): New functions to check
  92         whether specific floating point formats are usable.
  93         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
  94         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
  95         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
  96         Use the new functions.
  97         (do_c_cond_fmt): Remove format checks...
  98         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
  99
 100 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 101
 102         * mips.igen: Fix formatting of check_fpu calls.
 103
 104 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 105
 106         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 107
 108 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 109
 110         * mips.igen: Remove whitespace at end of lines.
 111
 112 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 113
 114         * mips.igen (loadstore_ea): New function to do effective
 115         address calculations.
 116         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 117         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 118         CACHE): Use loadstore_ea to do effective address computations.
 119
 120 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 121
 122         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 123         * mips.igen (LL, CxC1, MxC1): Likewise.
 124
 125 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 126
 127         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 128         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 129         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 130         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 131         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 132         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 133         Don't split opcode fields by hand, use the opcode field values
 134         provided by igen.
 135
 136 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 137
 138         * mips.igen (do_divu): Fix spacing.
 139
 140         * mips.igen (do_dsllv): Move to be right before DSLLV,
 141         to match the rest of the do_<shift> functions.
 142
 143 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 144
 145         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 146         DSRL32, do_dsrlv): Trace inputs and results.
 147
 148 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 149
 150         * mips.igen (CACHE): Provide instruction-printing string.
 151
 152         * interp.c (signal_exception): Comment tokens after #endif.
 153
 154 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 155
 156         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 157         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 158         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 159         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 160         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 161         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 162         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 163         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 164
 165 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 166
 167         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 168         instruction-printing string.
 169         (LWU): Use '64' as the filter flag.
 170
 171 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 172
 173         * mips.igen (SDXC1): Fix instruction-printing string.
 174
 175 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 176
 177         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 178         filter flags "32,f".
 179
 180 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 181
 182         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 183         as the filter flag.
 184
 185 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 186
 187         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 188         add a comma) so that it more closely match the MIPS ISA
 189         documentation opcode partitioning.
 190         (PREF): Put useful names on opcode fields, and include
 191         instruction-printing string.
 192
 193 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 194
 195         * mips.igen (check_u64): New function which in the future will
 196         check whether 64-bit instructions are usable and signal an
 197         exception if not.  Currently a no-op.
 198         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 199         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 200         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 201         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 202
 203         * mips.igen (check_fpu): New function which in the future will
 204         check whether FPU instructions are usable and signal an exception
 205         if not.  Currently a no-op.
 206         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 207         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 208         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 209         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 210         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 211         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 212         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 213         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 214
 215 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 216
 217         * mips.igen (do_load_left, do_load_right): Move to be immediately
 218         following do_load.
 219         (do_store_left, do_store_right): Move to be immediately following
 220         do_store.
 221
 222 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 223
 224         * mips.igen (mipsV): New model name.  Also, add it to
 225         all instructions and functions where it is appropriate.
 226
 227 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 228
 229         * mips.igen: For all functions and instructions, list model
 230         names that support that instruction one per line.
 231
 232 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 233
 234         * mips.igen: Add some additional comments about supported
 235         models, and about which instructions go where.
 236         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 237         order as is used in the rest of the file.
 238
 239 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 240
 241         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 242         indicating that ALU32_END or ALU64_END are there to check
 243         for overflow.
 244         (DADD): Likewise, but also remove previous comment about
 245         overflow checking.
 246
 247 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 248
 249         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 250         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 251         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 252         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 253         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 254         fields (i.e., add and move commas) so that they more closely
 255         match the MIPS ISA documentation opcode partitioning.
 256
 257 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 258
 259         * mips.igen (ADDI): Print immediate value.
 260         (BREAK): Print code.
 261         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 262         (SLL): Print "nop" specially, and don't run the code
 263         that does the shift for the "nop" case.
 264
 265 2001-11-17  Fred Fish  <fnf@redhat.com>
 266
 267         * sim-main.h (float_operation): Move enum declaration outside
 268         of _sim_cpu struct declaration.
 269
 270 2001-04-12  Jim Blandy  <jimb@redhat.com>
 271
 272         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 273         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 274         set of the FCSR.
 275         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 276         PENDING_FILL, and you can get the intended effect gracefully by
 277         calling PENDING_SCHED directly.
 278
 279 2001-02-23  Ben Elliston  <bje@redhat.com>
 280
 281         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 282         already defined elsewhere.
 283
 284 2001-02-19  Ben Elliston  <bje@redhat.com>
 285
 286         * sim-main.h (sim_monitor): Return an int.
 287         * interp.c (sim_monitor): Add return values.
 288         (signal_exception): Handle error conditions from sim_monitor.
 289
 290 2001-02-08  Ben Elliston  <bje@redhat.com>
 291
 292         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 293         (store_memory): Likewise, pass cia to sim_core_write*.
 294
 295 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 296
 297         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 298         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 299
 300 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 301
 302         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 303         * Makefile.in: Don't delete *.igen when cleaning directory.
 304
 305 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 306
 307         * m16.igen (break): Call SignalException not sim_engine_halt.
 308
 309 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 310
 311         From Jason Eckhardt:
 312         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 313
 314 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 315
 316         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 317
 318 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 319
 320         * mips.igen (do_dmultx): Fix typo.
 321
 322 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 323
 324         * configure: Regenerated to track ../common/aclocal.m4 changes.
 325
 326 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 327
 328         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 329
 330 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 331
 332         * sim-main.h (GPR_CLEAR): Define macro.
 333
 334 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 335
 336         * interp.c (decode_coproc): Output long using %lx and not %s.
 337
 338 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 339
 340         * interp.c (sim_open): Sort & extend dummy memory regions for
 341         --board=jmr3904 for eCos.
 342
 343 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 344
 345         * configure: Regenerated.
 346
 347 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 348
 349         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 350         calls, conditional on the simulator being in verbose mode.
 351
 352 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 353
 354         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 355         cache don't get ReservedInstruction traps.
 356
 357 1999-11-29  Mark Salter  <msalter@cygnus.com>
 358
 359         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 360         to clear status bits in sdisr register. This is how the hardware works.
 361
 362         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 363         being used by cygmon.
 364
 365 1999-11-11  Andrew Haley  <aph@cygnus.com>
 366
 367         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 368         instructions.
 369
 370 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 371
 372         * mips.igen (MULT): Correct previous mis-applied patch.
 373
 374 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 375
 376         * mips.igen (delayslot32): Handle sequence like
 377         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 378         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 379         (MULT): Actually pass the third register...
 380
 381 1999-09-03  Mark Salter  <msalter@cygnus.com>
 382
 383         * interp.c (sim_open): Added more memory aliases for additional
 384         hardware being touched by cygmon on jmr3904 board.
 385
 386 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 387
 388         * configure: Regenerated to track ../common/aclocal.m4 changes.
 389
 390 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 391
 392         * interp.c (sim_store_register): Handle case where client - GDB -
 393         specifies that a 4 byte register is 8 bytes in size.
 394         (sim_fetch_register): Ditto.
 395
 396 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 397
 398         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 399         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 400         (idt_monitor_base): Base address for IDT monitor traps.
 401         (pmon_monitor_base): Ditto for PMON.
 402         (lsipmon_monitor_base): Ditto for LSI PMON.
 403         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 404         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 405         (sim_firmware_command): New function.
 406         (mips_option_handler): Call it for OPTION_FIRMWARE.
 407         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 408         option was given, add no monitor by default.  Add BREAK hooks only if
 409         monitors are also there.
 410
 411 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 412
 413         * interp.c (sim_monitor): Flush output before reading input.
 414
 415 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 416
 417         * tconfig.in (SIM_HANDLES_LMA): Always define.
 418
 419 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 420
 421         From Mark Salter <msalter@cygnus.com>:
 422         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 423         (sim_open): Add setup for BSP board.
 424
 425 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 426
 427         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 428         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 429         them as unimplemented.
 430
 431 1999-05-08  Felix Lee  <flee@cygnus.com>
 432
 433         * configure: Regenerated to track ../common/aclocal.m4 changes.
 434
 435 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 436
 437         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 438
 439 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 440
 441         * configure.in: Any mips64vr5*-*-* target should have
 442         -DTARGET_ENABLE_FR=1.
 443         (default_endian): Any mips64vr*el-*-* target should default to
 444         LITTLE_ENDIAN.
 445         * configure: Re-generate.
 446
 447 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 448
 449         * mips.igen (ldl): Extend from _16_, not 32.
 450
 451 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 452
 453         * interp.c (sim_store_register): Force registers written to by GDB
 454         into an un-interpreted state.
 455
 456 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 457
 458         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 459         CPU, start periodic background I/O polls.
 460         (tx3904sio_poll): New function: periodic I/O poller.
 461
 462 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 463
 464         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 465
 466 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 467
 468         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 469         case statement.
 470
 471 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 472
 473         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 474         (load_word): Call SIM_CORE_SIGNAL hook on error.
 475         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 476         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 477         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 478         * sim-main.h (COP0_BADVADDR): Define.
 479         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 480         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 481         (_sim_cpu): Add exc_* fields to store register value snapshots.
 482         * mips.igen (*): Replace memory-related SignalException* calls
 483         with references to SIM_CORE_SIGNAL hook.
 484
 485         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 486         fix.
 487         * sim-main.c (*): Minor warning cleanups.
 488
 489 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 490
 491         * m16.igen (DADDIU5): Correct type-o.
 492
 493 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 494
 495         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 496         variables.
 497
 498 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 499
 500         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 501         to include path.
 502         (interp.o): Add dependency on itable.h
 503         (oengine.c, gencode): Delete remaining references.
 504         (BUILT_SRC_FROM_GEN): Clean up.
 505
 506 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 507
 508         * vr4run.c: New.
 509         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 510         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 511         tmp-run-hack) : New.
 512         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 513         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 514         Drop the "64" qualifier to get the HACK generator working.
 515         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 516         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 517         qualifier to get the hack generator working.
 518         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 519         (DSLL): Use do_dsll.
 520         (DSLLV): Use do_dsllv.
 521         (DSRA): Use do_dsra.
 522         (DSRL): Use do_dsrl.
 523         (DSRLV): Use do_dsrlv.
 524         (BC1): Move *vr4100 to get the HACK generator working.
 525         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 526         get the HACK generator working.
 527         (MACC) Rename to get the HACK generator working.
 528         (DMACC,MACCS,DMACCS): Add the 64.
 529
 530 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 531
 532         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 533         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 534
 535 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 536
 537     * mips/interp.c (DEBUG): Cleanups.
 538
 539 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 540
 541         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 542         (tx3904sio_tickle): fflush after a stdout character output.
 543
 544 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 545
 546         * interp.c (sim_close): Uninstall modules.
 547
 548 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 549
 550         * sim-main.h, interp.c (sim_monitor): Change to global
 551         function.
 552
 553 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 554
 555         * configure.in (vr4100): Only include vr4100 instructions in
 556         simulator.
 557         * configure: Re-generate.
 558         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 559
 560 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 561
 562         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 563         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 564         true alternative.
 565
 566         * configure.in (sim_default_gen, sim_use_gen): Replace with
 567         sim_gen.
 568         (--enable-sim-igen): Delete config option. Always using IGEN.
 569         * configure: Re-generate.
 570
 571         * Makefile.in (gencode): Kill, kill, kill.
 572         * gencode.c: Ditto.
 573
 574 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 575
 576         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 577         bit mips16 igen simulator.
 578         * configure: Re-generate.
 579
 580         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 581         as part of vr4100 ISA.
 582         * vr.igen: Mark all instructions as 64 bit only.
 583
 584 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 585
 586         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 587         Pacify GCC.
 588
 589 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 590
 591         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 592         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 593         * configure: Re-generate.
 594
 595         * m16.igen (BREAK): Define breakpoint instruction.
 596         (JALX32): Mark instruction as mips16 and not r3900.
 597         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 598
 599         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 600
 601 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 602
 603         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 604         insn as a debug breakpoint.
 605
 606         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 607         pending.slot_size.
 608         (PENDING_SCHED): Clean up trace statement.
 609         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 610         (PENDING_FILL): Delay write by only one cycle.
 611         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 612
 613         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 614         of pending writes.
 615         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 616         32 & 64.
 617         (pending_tick): Move incrementing of index to FOR statement.
 618         (pending_tick): Only update PENDING_OUT after a write has occured.
 619
 620         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 621         build simulator.
 622         * configure: Re-generate.
 623
 624         * interp.c (sim_engine_run OLD): Delete explicit call to
 625         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 626
 627 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 628
 629         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 630         interrupt level number to match changed SignalExceptionInterrupt
 631         macro.
 632
 633 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 634
 635         * interp.c: #include "itable.h" if WITH_IGEN.
 636         (get_insn_name): New function.
 637         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 638         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 639
 640 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 641
 642         * configure: Rebuilt to inhale new common/aclocal.m4.
 643
 644 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 645
 646         * dv-tx3904sio.c: Include sim-assert.h.
 647
 648 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 649
 650         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 651         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 652         Reorganize target-specific sim-hardware checks.
 653         * configure: rebuilt.
 654         * interp.c (sim_open): For tx39 target boards, set
 655         OPERATING_ENVIRONMENT, add tx3904sio devices.
 656         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 657         ROM executables.  Install dv-sockser into sim-modules list.
 658
 659         * dv-tx3904irc.c: Compiler warning clean-up.
 660         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 661         frequent hw-trace messages.
 662
 663 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 664
 665         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 666
 667 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 668
 669         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 670
 671         * vr.igen: New file.
 672         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 673         * mips.igen: Define vr4100 model. Include vr.igen.
 674 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 675
 676         * mips.igen (check_mf_hilo): Correct check.
 677
 678 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 679
 680         * sim-main.h (interrupt_event): Add prototype.
 681
 682         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 683         register_ptr, register_value.
 684         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 685
 686         * sim-main.h (tracefh): Make extern.
 687
 688 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 689
 690         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 691         Reduce unnecessarily high timer event frequency.
 692         * dv-tx3904cpu.c: Ditto for interrupt event.
 693
 694 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 695
 696         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 697         to allay warnings.
 698         (interrupt_event): Made non-static.
 699
 700         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 701         interchange of configuration values for external vs. internal
 702         clock dividers.
 703
 704 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 705
 706         * mips.igen (BREAK): Moved code to here for
 707         simulator-reserved break instructions.
 708         * gencode.c (build_instruction): Ditto.
 709         * interp.c (signal_exception): Code moved from here.  Non-
 710         reserved instructions now use exception vector, rather
 711         than halting sim.
 712         * sim-main.h: Moved magic constants to here.
 713
 714 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 715
 716         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 717         register upon non-zero interrupt event level, clear upon zero
 718         event value.
 719         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 720         by passing zero event value.
 721         (*_io_{read,write}_buffer): Endianness fixes.
 722         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 723         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 724
 725         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 726         serial I/O and timer module at base address 0xFFFF0000.
 727
 728 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 729
 730         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 731         and BigEndianCPU.
 732
 733 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 734
 735         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 736         parts.
 737         * configure: Update.
 738
 739 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 740
 741         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 742         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 743         * configure.in: Include tx3904tmr in hw_device list.
 744         * configure: Rebuilt.
 745         * interp.c (sim_open): Instantiate three timer instances.
 746         Fix address typo of tx3904irc instance.
 747
 748 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 749
 750         * interp.c (signal_exception): SystemCall exception now uses
 751         the exception vector.
 752
 753 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 754
 755         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 756         to allay warnings.
 757
 758 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 759
 760         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 761
 762 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 763
 764         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 765
 766         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 767         sim-main.h. Declare a struct hw_descriptor instead of struct
 768         hw_device_descriptor.
 769
 770 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 771
 772         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 773         right bits and then re-align left hand bytes to correct byte
 774         lanes.  Fix incorrect computation in do_store_left when loading
 775         bytes from second word.
 776
 777 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 778
 779         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 780         * interp.c (sim_open): Only create a device tree when HW is
 781         enabled.
 782
 783         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 784         * interp.c (signal_exception): Ditto.
 785
 786 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 787
 788         * gencode.c: Mark BEGEZALL as LIKELY.
 789
 790 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 791
 792         * sim-main.h (ALU32_END): Sign extend 32 bit results.
 793         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
 794
 795 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
 796
 797         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 798         modules.  Recognize TX39 target with "mips*tx39" pattern.
 799         * configure: Rebuilt.
 800         * sim-main.h (*): Added many macros defining bits in
 801         TX39 control registers.
 802         (SignalInterrupt): Send actual PC instead of NULL.
 803         (SignalNMIReset): New exception type.
 804         * interp.c (board): New variable for future use to identify
 805         a particular board being simulated.
 806         (mips_option_handler,mips_options): Added "--board" option.
 807         (interrupt_event): Send actual PC.
 808         (sim_open): Make memory layout conditional on board setting.
 809         (signal_exception): Initial implementation of hardware interrupt
 810         handling.  Accept another break instruction variant for simulator
 811         exit.
 812         (decode_coproc): Implement RFE instruction for TX39.
 813         (mips.igen): Decode RFE instruction as such.
 814         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
 815         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
 816         bbegin to implement memory map.
 817         * dv-tx3904cpu.c: New file.
 818         * dv-tx3904irc.c: New file.
 819
 820 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
 821
 822         * mips.igen (check_mt_hilo): Create a separate r3900 version.
 823
 824 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
 825
 826         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
 827         with calls to check_div_hilo.
 828
 829 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
 830
 831         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
 832         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
 833         Add special r3900 version of do_mult_hilo.
 834         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
 835         with calls to check_mult_hilo.
 836         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
 837         with calls to check_div_hilo.
 838
 839 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 840
 841         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
 842         Document a replacement.
 843
 844 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
 845
 846         * interp.c (sim_monitor): Make mon_printf work.
 847
 848 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
 849
 850         * sim-main.h (INSN_NAME): New arg `cpu'.
 851
 852 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
 853
 854         * configure: Regenerated to track ../common/aclocal.m4 changes.
 855
 856 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
 857
 858         * configure: Regenerated to track ../common/aclocal.m4 changes.
 859         * config.in: Ditto.
 860
 861 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
 862
 863         * acconfig.h: New file.
 864         * configure.in: Reverted change of Apr 24; use sinclude again.
 865
 866 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
 867
 868         * configure: Regenerated to track ../common/aclocal.m4 changes.
 869         * config.in: Ditto.
 870
 871 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
 872
 873         * configure.in: Don't call sinclude.
 874
 875 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
 876
 877         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
 878
 879 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 880
 881         * mips.igen (ERET): Implement.
 882
 883         * interp.c (decode_coproc): Return sign-extended EPC.
 884
 885         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
 886
 887         * interp.c (signal_exception): Do not ignore Trap.
 888         (signal_exception): On TRAP, restart at exception address.
 889         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
 890         (signal_exception): Update.
 891         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
 892         so that TRAP instructions are caught.
 893
 894 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 895
 896         * sim-main.h (struct hilo_access, struct hilo_history): Define,
 897         contains HI/LO access history.
 898         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
 899         (HIACCESS, LOACCESS): Delete, replace with
 900         (HIHISTORY, LOHISTORY): New macros.
 901         (CHECKHILO): Delete all, moved to mips.igen
 902
 903         * gencode.c (build_instruction): Do not generate checks for
 904         correct HI/LO register usage.
 905
 906         * interp.c (old_engine_run): Delete checks for correct HI/LO
 907         register usage.
 908
 909         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
 910         check_mf_cycles): New functions.
 911         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
 912         do_divu, domultx, do_mult, do_multu): Use.
 913
 914         * tx.igen ("madd", "maddu"): Use.
 915
 916 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 917
 918         * mips.igen (DSRAV): Use function do_dsrav.
 919         (SRAV): Use new function do_srav.
 920
 921         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
 922         (B): Sign extend 11 bit immediate.
 923         (EXT-B*): Shift 16 bit immediate left by 1.
 924         (ADDIU*): Don't sign extend immediate value.
 925
 926 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 927
 928         * m16run.c (sim_engine_run): Restore CIA after handling an event.
 929
 930         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
 931         functions.
 932
 933         * mips.igen (delayslot32, nullify_next_insn): New functions.
 934         (m16.igen): Always include.
 935         (do_*): Add more tracing.
 936
 937         * m16.igen (delayslot16): Add NIA argument, could be called by a
 938         32 bit MIPS16 instruction.
 939
 940         * interp.c (ifetch16): Move function from here.
 941         * sim-main.c (ifetch16): To here.
 942
 943         * sim-main.c (ifetch16, ifetch32): Update to match current
 944         implementations of LH, LW.
 945         (signal_exception): Don't print out incorrect hex value of illegal
 946         instruction.
 947
 948 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 949
 950         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
 951         instruction.
 952
 953         * m16.igen: Implement MIPS16 instructions.
 954
 955         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
 956         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
 957         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
 958         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
 959         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
 960         bodies of corresponding code from 32 bit insn to these.  Also used
 961         by MIPS16 versions of functions.
 962
 963         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
 964         (IMEM16): Drop NR argument from macro.
 965
 966 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 967
 968         * Makefile.in (SIM_OBJS): Add sim-main.o.
 969
 970         * sim-main.h (address_translation, load_memory, store_memory,
 971         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
 972         as INLINE_SIM_MAIN.
 973         (pr_addr, pr_uword64): Declare.
 974         (sim-main.c): Include when H_REVEALS_MODULE_P.
 975
 976         * interp.c (address_translation, load_memory, store_memory,
 977         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
 978         from here.
 979         * sim-main.c: To here. Fix compilation problems.
 980
 981         * configure.in: Enable inlining.
 982         * configure: Re-config.
 983
 984 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 985
 986         * configure: Regenerated to track ../common/aclocal.m4 changes.
 987
 988 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 989
 990         * mips.igen: Include tx.igen.
 991         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
 992         * tx.igen: New file, contains MADD and MADDU.
 993
 994         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
 995         the hardwired constant `7'.
 996         (store_memory): Ditto.
 997         (LOADDRMASK): Move definition to sim-main.h.
 998
 999         mips.igen (MTC0): Enable for r3900.
1000         (ADDU): Add trace.
1001
1002         mips.igen (do_load_byte): Delete.
1003         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1004         do_store_right): New functions.
1005         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1006
1007         configure.in: Let the tx39 use igen again.
1008         configure: Update.
1009
1010 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1011
1012         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1013         not an address sized quantity.  Return zero for cache sizes.
1014
1015 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1016
1017         * mips.igen (r3900): r3900 does not support 64 bit integer
1018         operations.
1019
1020 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1021
1022         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1023         than igen one.
1024         * configure : Rebuild.
1025
1026 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1027
1028         * configure: Regenerated to track ../common/aclocal.m4 changes.
1029
1030 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1031
1032         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1033
1034 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1035
1036         * configure: Regenerated to track ../common/aclocal.m4 changes.
1037         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1038
1039 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1040
1041         * configure: Regenerated to track ../common/aclocal.m4 changes.
1042
1043 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1044
1045         * interp.c (Max, Min): Comment out functions. Not yet used.
1046
1047 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1048
1049         * configure: Regenerated to track ../common/aclocal.m4 changes.
1050
1051 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1052
1053         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1054         configurable settings for stand-alone simulator.
1055
1056         * configure.in: Added X11 search, just in case.
1057
1058         * configure: Regenerated.
1059
1060 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1061
1062         * interp.c (sim_write, sim_read, load_memory, store_memory):
1063         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1064
1065 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1066
1067         * sim-main.h (GETFCC): Return an unsigned value.
1068
1069 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1070
1071         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1072         (DADD): Result destination is RD not RT.
1073
1074 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1075
1076         * sim-main.h (HIACCESS, LOACCESS): Always define.
1077
1078         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1079
1080         * interp.c (sim_info): Delete.
1081
1082 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1083
1084         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1085         (mips_option_handler): New argument `cpu'.
1086         (sim_open): Update call to sim_add_option_table.
1087
1088 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1089
1090         * mips.igen (CxC1): Add tracing.
1091
1092 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1093
1094         * sim-main.h (Max, Min): Declare.
1095
1096         * interp.c (Max, Min): New functions.
1097
1098         * mips.igen (BC1): Add tracing.
1099
1100 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1101
1102         * interp.c Added memory map for stack in vr4100
1103
1104 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1105
1106         * interp.c (load_memory): Add missing "break"'s.
1107
1108 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1109
1110         * interp.c (sim_store_register, sim_fetch_register): Pass in
1111         length parameter.  Return -1.
1112
1113 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1114
1115         * interp.c: Added hardware init hook, fixed warnings.
1116
1117 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1118
1119         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1120
1121 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1122
1123         * interp.c (ifetch16): New function.
1124
1125         * sim-main.h (IMEM32): Rename IMEM.
1126         (IMEM16_IMMED): Define.
1127         (IMEM16): Define.
1128         (DELAY_SLOT): Update.
1129
1130         * m16run.c (sim_engine_run): New file.
1131
1132         * m16.igen: All instructions except LB.
1133         (LB): Call do_load_byte.
1134         * mips.igen (do_load_byte): New function.
1135         (LB): Call do_load_byte.
1136
1137         * mips.igen: Move spec for insn bit size and high bit from here.
1138         * Makefile.in (tmp-igen, tmp-m16): To here.
1139
1140         * m16.dc: New file, decode mips16 instructions.
1141
1142         * Makefile.in (SIM_NO_ALL): Define.
1143         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1144
1145 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1146
1147         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1148         point unit to 32 bit registers.
1149         * configure: Re-generate.
1150
1151 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1152
1153         * configure.in (sim_use_gen): Make IGEN the default simulator
1154         generator for generic 32 and 64 bit mips targets.
1155         * configure: Re-generate.
1156
1157 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1158
1159         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1160         bitsize.
1161
1162         * interp.c (sim_fetch_register, sim_store_register): Read/write
1163         FGR from correct location.
1164         (sim_open): Set size of FGR's according to
1165         WITH_TARGET_FLOATING_POINT_BITSIZE.
1166
1167         * sim-main.h (FGR): Store floating point registers in a separate
1168         array.
1169
1170 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1171
1172         * configure: Regenerated to track ../common/aclocal.m4 changes.
1173
1174 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1175
1176         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1177
1178         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1179
1180         * interp.c (pending_tick): New function.  Deliver pending writes.
1181
1182         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1183         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1184         it can handle mixed sized quantites and single bits.
1185
1186 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1187
1188         * interp.c (oengine.h): Do not include when building with IGEN.
1189         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1190         (sim_info): Ditto for PROCESSOR_64BIT.
1191         (sim_monitor): Replace ut_reg with unsigned_word.
1192         (*): Ditto for t_reg.
1193         (LOADDRMASK): Define.
1194         (sim_open): Remove defunct check that host FP is IEEE compliant,
1195         using software to emulate floating point.
1196         (value_fpr, ...): Always compile, was conditional on HASFPU.
1197
1198 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1199
1200         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1201         size.
1202
1203         * interp.c (SD, CPU): Define.
1204         (mips_option_handler): Set flags in each CPU.
1205         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1206         (sim_close): Do not clear STATE, deleted anyway.
1207         (sim_write, sim_read): Assume CPU zero's vm should be used for
1208         data transfers.
1209         (sim_create_inferior): Set the PC for all processors.
1210         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1211         argument.
1212         (mips16_entry): Pass correct nr of args to store_word, load_word.
1213         (ColdReset): Cold reset all cpu's.
1214         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1215         (sim_monitor, load_memory, store_memory, signal_exception): Use
1216         `CPU' instead of STATE_CPU.
1217
1218
1219         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1220         SD or CPU_.
1221
1222         * sim-main.h (signal_exception): Add sim_cpu arg.
1223         (SignalException*): Pass both SD and CPU to signal_exception.
1224         * interp.c (signal_exception): Update.
1225
1226         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1227         Ditto
1228         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1229         address_translation): Ditto
1230         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1231
1232 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1233
1234         * configure: Regenerated to track ../common/aclocal.m4 changes.
1235
1236 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1237
1238         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1239
1240         * mips.igen (model): Map processor names onto BFD name.
1241
1242         * sim-main.h (CPU_CIA): Delete.
1243         (SET_CIA, GET_CIA): Define
1244
1245 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1246
1247         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1248         regiser.
1249
1250         * configure.in (default_endian): Configure a big-endian simulator
1251         by default.
1252         * configure: Re-generate.
1253
1254 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1255
1256         * configure: Regenerated to track ../common/aclocal.m4 changes.
1257
1258 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1259
1260         * interp.c (sim_monitor): Handle Densan monitor outbyte
1261         and inbyte functions.
1262
1263 1997-12-29  Felix Lee  <flee@cygnus.com>
1264
1265         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1266
1267 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1268
1269         * Makefile.in (tmp-igen): Arrange for $zero to always be
1270         reset to zero after every instruction.
1271
1272 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1273
1274         * configure: Regenerated to track ../common/aclocal.m4 changes.
1275         * config.in: Ditto.
1276
1277 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1278
1279         * mips.igen (MSUB): Fix to work like MADD.
1280         * gencode.c (MSUB): Similarly.
1281
1282 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1283
1284         * configure: Regenerated to track ../common/aclocal.m4 changes.
1285
1286 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1287
1288         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1289
1290 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1291
1292         * sim-main.h (sim-fpu.h): Include.
1293
1294         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1295         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1296         using host independant sim_fpu module.
1297
1298 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1299
1300         * interp.c (signal_exception): Report internal errors with SIGABRT
1301         not SIGQUIT.
1302
1303         * sim-main.h (C0_CONFIG): New register.
1304         (signal.h): No longer include.
1305
1306         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1307
1308 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1309
1310         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1311
1312 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1313
1314         * mips.igen: Tag vr5000 instructions.
1315         (ANDI): Was missing mipsIV model, fix assembler syntax.
1316         (do_c_cond_fmt): New function.
1317         (C.cond.fmt): Handle mips I-III which do not support CC field
1318         separatly.
1319         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1320         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1321         in IV3.2 spec.
1322         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1323         vr5000 which saves LO in a GPR separatly.
1324
1325         * configure.in (enable-sim-igen): For vr5000, select vr5000
1326         specific instructions.
1327         * configure: Re-generate.
1328
1329 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1330
1331         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1332
1333         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1334         fmt_uninterpreted_64 bit cases to switch.  Convert to
1335         fmt_formatted,
1336
1337         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1338
1339         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1340         as specified in IV3.2 spec.
1341         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1342
1343 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1344
1345         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1346         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1347         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1348         PENDING_FILL versions of instructions.  Simplify.
1349         (X): New function.
1350         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1351         instructions.
1352         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1353         a signed value.
1354         (MTHI, MFHI): Disable code checking HI-LO.
1355
1356         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1357         global.
1358         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1359
1360 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1361
1362         * gencode.c (build_mips16_operands): Replace IPC with cia.
1363
1364         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1365         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1366         IPC to `cia'.
1367         (UndefinedResult): Replace function with macro/function
1368         combination.
1369         (sim_engine_run): Don't save PC in IPC.
1370
1371         * sim-main.h (IPC): Delete.
1372
1373
1374         * interp.c (signal_exception, store_word, load_word,
1375         address_translation, load_memory, store_memory, cache_op,
1376         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1377         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1378         current instruction address - cia - argument.
1379         (sim_read, sim_write): Call address_translation directly.
1380         (sim_engine_run): Rename variable vaddr to cia.
1381         (signal_exception): Pass cia to sim_monitor
1382
1383         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1384         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1385         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1386
1387         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1388         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1389         SIM_ASSERT.
1390
1391         * interp.c (signal_exception): Pass restart address to
1392         sim_engine_restart.
1393
1394         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1395         idecode.o): Add dependency.
1396
1397         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1398         Delete definitions
1399         (DELAY_SLOT): Update NIA not PC with branch address.
1400         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1401
1402         * mips.igen: Use CIA not PC in branch calculations.
1403         (illegal): Call SignalException.
1404         (BEQ, ADDIU): Fix assembler.
1405
1406 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1407
1408         * m16.igen (JALX): Was missing.
1409
1410         * configure.in (enable-sim-igen): New configuration option.
1411         * configure: Re-generate.
1412
1413         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1414
1415         * interp.c (load_memory, store_memory): Delete parameter RAW.
1416         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1417         bypassing {load,store}_memory.
1418
1419         * sim-main.h (ByteSwapMem): Delete definition.
1420
1421         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1422
1423         * interp.c (sim_do_command, sim_commands): Delete mips specific
1424         commands.  Handled by module sim-options.
1425
1426         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1427         (WITH_MODULO_MEMORY): Define.
1428
1429         * interp.c (sim_info): Delete code printing memory size.
1430
1431         * interp.c (mips_size): Nee sim_size, delete function.
1432         (power2): Delete.
1433         (monitor, monitor_base, monitor_size): Delete global variables.
1434         (sim_open, sim_close): Delete code creating monitor and other
1435         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1436         manage memory regions.
1437         (load_memory, store_memory): Use sim-core for memory model.
1438
1439         * interp.c (address_translation): Delete all memory map code
1440         except line forcing 32 bit addresses.
1441
1442 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1443
1444         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1445         trace options.
1446
1447         * interp.c (logfh, logfile): Delete globals.
1448         (sim_open, sim_close): Delete code opening & closing log file.
1449         (mips_option_handler): Delete -l and -n options.
1450         (OPTION mips_options): Ditto.
1451
1452         * interp.c (OPTION mips_options): Rename option trace to dinero.
1453         (mips_option_handler): Update.
1454
1455 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1456
1457         * interp.c (fetch_str): New function.
1458         (sim_monitor): Rewrite using sim_read & sim_write.
1459         (sim_open): Check magic number.
1460         (sim_open): Write monitor vectors into memory using sim_write.
1461         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1462         (sim_read, sim_write): Simplify - transfer data one byte at a
1463         time.
1464         (load_memory, store_memory): Clarify meaning of parameter RAW.
1465
1466         * sim-main.h (isHOST): Defete definition.
1467         (isTARGET): Mark as depreciated.
1468         (address_translation): Delete parameter HOST.
1469
1470         * interp.c (address_translation): Delete parameter HOST.
1471
1472 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1473
1474         * mips.igen:
1475
1476         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1477         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1478
1479 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1480
1481         * mips.igen: Add model filter field to records.
1482
1483 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1484
1485         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1486
1487         interp.c (sim_engine_run): Do not compile function sim_engine_run
1488         when WITH_IGEN == 1.
1489
1490         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1491         target architecture.
1492
1493         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1494         igen. Replace with configuration variables sim_igen_flags /
1495         sim_m16_flags.
1496
1497         * m16.igen: New file.  Copy mips16 insns here.
1498         * mips.igen: From here.
1499
1500 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1501
1502         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1503         to top.
1504         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1505
1506 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1507
1508         * gencode.c (build_instruction): Follow sim_write's lead in using
1509         BigEndianMem instead of !ByteSwapMem.
1510
1511 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1512
1513         * configure.in (sim_gen): Dependent on target, select type of
1514         generator.  Always select old style generator.
1515
1516         configure: Re-generate.
1517
1518         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1519         targets.
1520         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1521         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1522         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1523         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1524         SIM_@sim_gen@_*, set by autoconf.
1525
1526 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1527
1528         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1529
1530         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1531         CURRENT_FLOATING_POINT instead.
1532
1533         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1534         (address_translation): Raise exception InstructionFetch when
1535         translation fails and isINSTRUCTION.
1536
1537         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1538         sim_engine_run): Change type of of vaddr and paddr to
1539         address_word.
1540         (address_translation, prefetch, load_memory, store_memory,
1541         cache_op): Change type of vAddr and pAddr to address_word.
1542
1543         * gencode.c (build_instruction): Change type of vaddr and paddr to
1544         address_word.
1545
1546 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1547
1548         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1549         macro to obtain result of ALU op.
1550
1551 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1552
1553         * interp.c (sim_info): Call profile_print.
1554
1555 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1556
1557         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1558
1559         * sim-main.h (WITH_PROFILE): Do not define, defined in
1560         common/sim-config.h.  Use sim-profile module.
1561         (simPROFILE): Delete defintion.
1562
1563         * interp.c (PROFILE): Delete definition.
1564         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1565         (sim_close): Delete code writing profile histogram.
1566         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1567         Delete.
1568         (sim_engine_run): Delete code profiling the PC.
1569
1570 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1571
1572         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1573
1574         * interp.c (sim_monitor): Make register pointers of type
1575         unsigned_word*.
1576
1577         * sim-main.h: Make registers of type unsigned_word not
1578         signed_word.
1579
1580 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1581
1582         * interp.c (sync_operation): Rename from SyncOperation, make
1583         global, add SD argument.
1584         (prefetch): Rename from Prefetch, make global, add SD argument.
1585         (decode_coproc): Make global.
1586
1587         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1588
1589         * gencode.c (build_instruction): Generate DecodeCoproc not
1590         decode_coproc calls.
1591
1592         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1593         (SizeFGR): Move to sim-main.h
1594         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1595         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1596         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1597         sim-main.h.
1598         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1599         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1600         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1601         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1602         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1603         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1604
1605         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1606         exception.
1607         (sim-alu.h): Include.
1608         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1609         (sim_cia): Typedef to instruction_address.
1610
1611 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1612
1613         * Makefile.in (interp.o): Rename generated file engine.c to
1614         oengine.c.
1615
1616         * interp.c: Update.
1617
1618 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1619
1620         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1621
1622 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1623
1624         * gencode.c (build_instruction): For "FPSQRT", output correct
1625         number of arguments to Recip.
1626
1627 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1628
1629         * Makefile.in (interp.o): Depends on sim-main.h
1630
1631         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1632
1633         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1634         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1635         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1636         STATE, DSSTATE): Define
1637         (GPR, FGRIDX, ..): Define.
1638
1639         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1640         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1641         (GPR, FGRIDX, ...): Delete macros.
1642
1643         * interp.c: Update names to match defines from sim-main.h
1644
1645 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1646
1647         * interp.c (sim_monitor): Add SD argument.
1648         (sim_warning): Delete.  Replace calls with calls to
1649         sim_io_eprintf.
1650         (sim_error): Delete. Replace calls with sim_io_error.
1651         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1652         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1653         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1654         argument.
1655         (mips_size): Rename from sim_size. Add SD argument.
1656
1657         * interp.c (simulator): Delete global variable.
1658         (callback): Delete global variable.
1659         (mips_option_handler, sim_open, sim_write, sim_read,
1660         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1661         sim_size,sim_monitor): Use sim_io_* not callback->*.
1662         (sim_open): ZALLOC simulator struct.
1663         (PROFILE): Do not define.
1664
1665 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1666
1667         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1668         support.h with corresponding code.
1669
1670         * sim-main.h (word64, uword64), support.h: Move definition to
1671         sim-main.h.
1672         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1673
1674         * support.h: Delete
1675         * Makefile.in: Update dependencies
1676         * interp.c: Do not include.
1677
1678 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1679
1680         * interp.c (address_translation, load_memory, store_memory,
1681         cache_op): Rename to from AddressTranslation et.al., make global,
1682         add SD argument
1683
1684         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1685         CacheOp): Define.
1686
1687         * interp.c (SignalException): Rename to signal_exception, make
1688         global.
1689
1690         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1691
1692         * sim-main.h (SignalException, SignalExceptionInterrupt,
1693         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1694         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1695         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1696         Define.
1697
1698         * interp.c, support.h: Use.
1699
1700 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1701
1702         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1703         to value_fpr / store_fpr. Add SD argument.
1704         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1705         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1706
1707         * sim-main.h (ValueFPR, StoreFPR): Define.
1708
1709 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1710
1711         * interp.c (sim_engine_run): Check consistency between configure
1712         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1713         and HASFPU.
1714
1715         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1716         (mips_fpu): Configure WITH_FLOATING_POINT.
1717         (mips_endian): Configure WITH_TARGET_ENDIAN.
1718         * configure: Update.
1719
1720 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1721
1722         * configure: Regenerated to track ../common/aclocal.m4 changes.
1723
1724 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1725
1726         * configure: Regenerated.
1727
1728 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1729
1730         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1731
1732 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1733
1734         * gencode.c (print_igen_insn_models): Assume certain architectures
1735         include all mips* instructions.
1736         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1737         instruction.
1738
1739         * Makefile.in (tmp.igen): Add target. Generate igen input from
1740         gencode file.
1741
1742         * gencode.c (FEATURE_IGEN): Define.
1743         (main): Add --igen option.  Generate output in igen format.
1744         (process_instructions): Format output according to igen option.
1745         (print_igen_insn_format): New function.
1746         (print_igen_insn_models): New function.
1747         (process_instructions): Only issue warnings and ignore
1748         instructions when no FEATURE_IGEN.
1749
1750 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1751
1752         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1753         MIPS targets.
1754
1755 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1756
1757         * configure: Regenerated to track ../common/aclocal.m4 changes.
1758
1759 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1760
1761         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1762         SIM_RESERVED_BITS): Delete, moved to common.
1763         (SIM_EXTRA_CFLAGS): Update.
1764
1765 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1766
1767         * configure.in: Configure non-strict memory alignment.
1768         * configure: Regenerated to track ../common/aclocal.m4 changes.
1769
1770 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1771
1772         * configure: Regenerated to track ../common/aclocal.m4 changes.
1773
1774 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1775
1776         * gencode.c (SDBBP,DERET): Added (3900) insns.
1777         (RFE): Turn on for 3900.
1778         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1779         (dsstate): Made global.
1780         (SUBTARGET_R3900): Added.
1781         (CANCELDELAYSLOT): New.
1782         (SignalException): Ignore SystemCall rather than ignore and
1783         terminate.  Add DebugBreakPoint handling.
1784         (decode_coproc): New insns RFE, DERET; and new registers Debug
1785         and DEPC protected by SUBTARGET_R3900.
1786         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1787         bits explicitly.
1788         * Makefile.in,configure.in: Add mips subtarget option.
1789         * configure: Update.
1790
1791 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
1792
1793         * gencode.c: Add r3900 (tx39).
1794
1795
1796 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
1797
1798         * gencode.c (build_instruction): Don't need to subtract 4 for
1799         JALR, just 2.
1800
1801 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
1802
1803         * interp.c: Correct some HASFPU problems.
1804
1805 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1806
1807         * configure: Regenerated to track ../common/aclocal.m4 changes.
1808
1809 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1810
1811         * interp.c (mips_options): Fix samples option short form, should
1812         be `x'.
1813
1814 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1815
1816         * interp.c (sim_info): Enable info code.  Was just returning.
1817
1818 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1819
1820         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1821         MFC0.
1822
1823 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1824
1825         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1826         constants.
1827         (build_instruction): Ditto for LL.
1828
1829 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
1830
1831         * configure: Regenerated to track ../common/aclocal.m4 changes.
1832
1833 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1834
1835         * configure: Regenerated to track ../common/aclocal.m4 changes.
1836         * config.in: Ditto.
1837
1838 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1839
1840         * interp.c (sim_open): Add call to sim_analyze_program, update
1841         call to sim_config.
1842
1843 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1844
1845         * interp.c (sim_kill): Delete.
1846         (sim_create_inferior): Add ABFD argument. Set PC from same.
1847         (sim_load): Move code initializing trap handlers from here.
1848         (sim_open): To here.
1849         (sim_load): Delete, use sim-hload.c.
1850
1851         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1852
1853 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1854
1855         * configure: Regenerated to track ../common/aclocal.m4 changes.
1856         * config.in: Ditto.
1857
1858 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1859
1860         * interp.c (sim_open): Add ABFD argument.
1861         (sim_load): Move call to sim_config from here.
1862         (sim_open): To here.  Check return status.
1863
1864 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
1865
1866         * gencode.c (build_instruction): Two arg MADD should
1867         not assign result to $0.
1868
1869 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
1870
1871         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1872         * sim/mips/configure.in: Regenerate.
1873
1874 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
1875
1876         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1877         signed8, unsigned8 et.al. types.
1878
1879         * interp.c (SUB_REG_FETCH): Handle both little and big endian
1880         hosts when selecting subreg.
1881
1882 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
1883
1884         * interp.c (sim_engine_run): Reset the ZERO register to zero
1885         regardless of FEATURE_WARN_ZERO.
1886         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1887
1888 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1889
1890         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1891         (SignalException): For BreakPoints ignore any mode bits and just
1892         save the PC.
1893         (SignalException): Always set the CAUSE register.
1894
1895 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1896
1897         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1898         exception has been taken.
1899
1900         * interp.c: Implement the ERET and mt/f sr instructions.
1901
1902 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1903
1904         * interp.c (SignalException): Don't bother restarting an
1905         interrupt.
1906
1907 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1908
1909         * interp.c (SignalException): Really take an interrupt.
1910         (interrupt_event): Only deliver interrupts when enabled.
1911
1912 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1913
1914         * interp.c (sim_info): Only print info when verbose.
1915         (sim_info) Use sim_io_printf for output.
1916
1917 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1918
1919         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1920         mips architectures.
1921
1922 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1923
1924         * interp.c (sim_do_command): Check for common commands if a
1925         simulator specific command fails.
1926
1927 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
1928
1929         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1930         and simBE when DEBUG is defined.
1931
1932 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1933
1934         * interp.c (interrupt_event): New function.  Pass exception event
1935         onto exception handler.
1936
1937         * configure.in: Check for stdlib.h.
1938         * configure: Regenerate.
1939
1940         * gencode.c (build_instruction): Add UNUSED attribute to tempS
1941         variable declaration.
1942         (build_instruction): Initialize memval1.
1943         (build_instruction): Add UNUSED attribute to byte, bigend,
1944         reverse.
1945         (build_operands): Ditto.
1946
1947         * interp.c: Fix GCC warnings.
1948         (sim_get_quit_code): Delete.
1949
1950         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1951         * Makefile.in: Ditto.
1952         * configure: Re-generate.
1953
1954         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1955
1956 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1957
1958         * interp.c (mips_option_handler): New function parse argumes using
1959         sim-options.
1960         (myname): Replace with STATE_MY_NAME.
1961         (sim_open): Delete check for host endianness - performed by
1962         sim_config.
1963         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1964         (sim_open): Move much of the initialization from here.
1965         (sim_load): To here.  After the image has been loaded and
1966         endianness set.
1967         (sim_open): Move ColdReset from here.
1968         (sim_create_inferior): To here.
1969         (sim_open): Make FP check less dependant on host endianness.
1970
1971         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1972         run.
1973         * interp.c (sim_set_callbacks): Delete.
1974
1975         * interp.c (membank, membank_base, membank_size): Replace with
1976         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1977         (sim_open): Remove call to callback->init. gdb/run do this.
1978
1979         * interp.c: Update
1980
1981         * sim-main.h (SIM_HAVE_FLATMEM): Define.
1982
1983         * interp.c (big_endian_p): Delete, replaced by
1984         current_target_byte_order.
1985
1986 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1987
1988         * interp.c (host_read_long, host_read_word, host_swap_word,
1989         host_swap_long): Delete. Using common sim-endian.
1990         (sim_fetch_register, sim_store_register): Use H2T.
1991         (pipeline_ticks): Delete.  Handled by sim-events.
1992         (sim_info): Update.
1993         (sim_engine_run): Update.
1994
1995 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1996
1997         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1998         reason from here.
1999         (SignalException): To here. Signal using sim_engine_halt.
2000         (sim_stop_reason): Delete, moved to common.
2001
2002 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2003
2004         * interp.c (sim_open): Add callback argument.
2005         (sim_set_callbacks): Delete SIM_DESC argument.
2006         (sim_size): Ditto.
2007
2008 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2009
2010         * Makefile.in (SIM_OBJS): Add common modules.
2011
2012         * interp.c (sim_set_callbacks): Also set SD callback.
2013         (set_endianness, xfer_*, swap_*): Delete.
2014         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2015         Change to functions using sim-endian macros.
2016         (control_c, sim_stop): Delete, use common version.
2017         (simulate): Convert into.
2018         (sim_engine_run): This function.
2019         (sim_resume): Delete.
2020
2021         * interp.c (simulation): New variable - the simulator object.
2022         (sim_kind): Delete global - merged into simulation.
2023         (sim_load): Cleanup.  Move PC assignment from here.
2024         (sim_create_inferior): To here.
2025
2026         * sim-main.h: New file.
2027         * interp.c (sim-main.h): Include.
2028
2029 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2030
2031         * configure: Regenerated to track ../common/aclocal.m4 changes.
2032
2033 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2034
2035         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2036
2037 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2038
2039         * gencode.c (build_instruction): DIV instructions: check
2040         for division by zero and integer overflow before using
2041         host's division operation.
2042
2043 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2044
2045         * Makefile.in (SIM_OBJS): Add sim-load.o.
2046         * interp.c: #include bfd.h.
2047         (target_byte_order): Delete.
2048         (sim_kind, myname, big_endian_p): New static locals.
2049         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2050         after argument parsing.  Recognize -E arg, set endianness accordingly.
2051         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2052         load file into simulator.  Set PC from bfd.
2053         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2054         (set_endianness): Use big_endian_p instead of target_byte_order.
2055
2056 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2057
2058         * interp.c (sim_size): Delete prototype - conflicts with
2059         definition in remote-sim.h.  Correct definition.
2060
2061 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2062
2063         * configure: Regenerated to track ../common/aclocal.m4 changes.
2064         * config.in: Ditto.
2065
2066 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2067
2068         * interp.c (sim_open): New arg `kind'.
2069
2070         * configure: Regenerated to track ../common/aclocal.m4 changes.
2071
2072 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2073
2074         * configure: Regenerated to track ../common/aclocal.m4 changes.
2075
2076 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2077
2078         * interp.c (sim_open): Set optind to 0 before calling getopt.
2079
2080 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2081
2082         * configure: Regenerated to track ../common/aclocal.m4 changes.
2083
2084 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2085
2086         * interp.c : Replace uses of pr_addr with pr_uword64
2087         where the bit length is always 64 independent of SIM_ADDR.
2088         (pr_uword64) : added.
2089
2090 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2091
2092         * configure: Re-generate.
2093
2094 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2095
2096         * configure: Regenerate to track ../common/aclocal.m4 changes.
2097
2098 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2099
2100         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2101         in argv form.
2102         (other sim_*): New SIM_DESC argument.
2103
2104 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2105
2106         * interp.c: Fix printing of addresses for non-64-bit targets.
2107         (pr_addr): Add function to print address based on size.
2108
2109 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2110
2111         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2112
2113 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2114
2115         * gencode.c (build_mips16_operands): Correct computation of base
2116         address for extended PC relative instruction.
2117
2118 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2119
2120         * interp.c (mips16_entry): Add support for floating point cases.
2121         (SignalException): Pass floating point cases to mips16_entry.
2122         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2123         registers.
2124         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2125         or fmt_word.
2126         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2127         and then set the state to fmt_uninterpreted.
2128         (COP_SW): Temporarily set the state to fmt_word while calling
2129         ValueFPR.
2130
2131 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2132
2133         * gencode.c (build_instruction): The high order may be set in the
2134         comparison flags at any ISA level, not just ISA 4.
2135
2136 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2137
2138         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2139         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2140         * configure.in: sinclude ../common/aclocal.m4.
2141         * configure: Regenerated.
2142
2143 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2144
2145         * configure: Rebuild after change to aclocal.m4.
2146
2147 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2148
2149         * configure configure.in Makefile.in:  Update to new configure
2150         scheme which is more compatible with WinGDB builds.
2151         * configure.in:  Improve comment on how to run autoconf.
2152         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2153         * Makefile.in:  Use autoconf substitution to install common
2154         makefile fragment.
2155
2156 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2157
2158         * gencode.c (build_instruction): Use BigEndianCPU instead of
2159         ByteSwapMem.
2160
2161 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2162
2163         * interp.c (sim_monitor): Make output to stdout visible in
2164         wingdb's I/O log window.
2165
2166 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2167
2168         * support.h: Undo previous change to SIGTRAP
2169         and SIGQUIT values.
2170
2171 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2172
2173         * interp.c (store_word, load_word): New static functions.
2174         (mips16_entry): New static function.
2175         (SignalException): Look for mips16 entry and exit instructions.
2176         (simulate): Use the correct index when setting fpr_state after
2177         doing a pending move.
2178
2179 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2180
2181         * interp.c: Fix byte-swapping code throughout to work on
2182         both little- and big-endian hosts.
2183
2184 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2185
2186         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2187         with gdb/config/i386/xm-windows.h.
2188
2189 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2190
2191         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2192         that messes up arithmetic shifts.
2193
2194 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2195
2196         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2197         SIGTRAP and SIGQUIT for _WIN32.
2198
2199 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2200
2201         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2202         force a 64 bit multiplication.
2203         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2204         destination register is 0, since that is the default mips16 nop
2205         instruction.
2206
2207 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2208
2209         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2210         (build_endian_shift): Don't check proc64.
2211         (build_instruction): Always set memval to uword64.  Cast op2 to
2212         uword64 when shifting it left in memory instructions.  Always use
2213         the same code for stores--don't special case proc64.
2214
2215         * gencode.c (build_mips16_operands): Fix base PC value for PC
2216         relative operands.
2217         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2218         jal instruction.
2219         * interp.c (simJALDELAYSLOT): Define.
2220         (JALDELAYSLOT): Define.
2221         (INDELAYSLOT, INJALDELAYSLOT): Define.
2222         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2223
2224 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2225
2226         * interp.c (sim_open): add flush_cache as a PMON routine
2227         (sim_monitor): handle flush_cache by ignoring it
2228
2229 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2230
2231         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2232         BigEndianMem.
2233         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2234         (BigEndianMem): Rename to ByteSwapMem and change sense.
2235         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2236         BigEndianMem references to !ByteSwapMem.
2237         (set_endianness): New function, with prototype.
2238         (sim_open): Call set_endianness.
2239         (sim_info): Use simBE instead of BigEndianMem.
2240         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2241         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2242         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2243         ifdefs, keeping the prototype declaration.
2244         (swap_word): Rewrite correctly.
2245         (ColdReset): Delete references to CONFIG.  Delete endianness related
2246         code; moved to set_endianness.
2247
2248 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2249
2250         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2251         * interp.c (CHECKHILO): Define away.
2252         (simSIGINT): New macro.
2253         (membank_size): Increase from 1MB to 2MB.
2254         (control_c): New function.
2255         (sim_resume): Rename parameter signal to signal_number.  Add local
2256         variable prev.  Call signal before and after simulate.
2257         (sim_stop_reason): Add simSIGINT support.
2258         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2259         functions always.
2260         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2261         if logfh is NULL.
2262         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2263         a call to sim_warning.
2264
2265 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2266
2267         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2268         16 bit instructions.
2269
2270 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2271
2272         Add support for mips16 (16 bit MIPS implementation):
2273         * gencode.c (inst_type): Add mips16 instruction encoding types.
2274         (GETDATASIZEINSN): Define.
2275         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2276         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2277         mtlo.
2278         (MIPS16_DECODE): New table, for mips16 instructions.
2279         (bitmap_val): New static function.
2280         (struct mips16_op): Define.
2281         (mips16_op_table): New table, for mips16 operands.
2282         (build_mips16_operands): New static function.
2283         (process_instructions): If PC is odd, decode a mips16
2284         instruction.  Break out instruction handling into new
2285         build_instruction function.
2286         (build_instruction): New static function, broken out of
2287         process_instructions.  Check modifiers rather than flags for SHIFT
2288         bit count and m[ft]{hi,lo} direction.
2289         (usage): Pass program name to fprintf.
2290         (main): Remove unused variable this_option_optind.  Change
2291         ``*loptarg++'' to ``loptarg++''.
2292         (my_strtoul): Parenthesize && within ||.
2293         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2294         (simulate): If PC is odd, fetch a 16 bit instruction, and
2295         increment PC by 2 rather than 4.
2296         * configure.in: Add case for mips16*-*-*.
2297         * configure: Rebuild.
2298
2299 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2300
2301         * interp.c: Allow -t to enable tracing in standalone simulator.
2302         Fix garbage output in trace file and error messages.
2303
2304 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2305
2306         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2307         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2308         * configure.in: Simplify using macros in ../common/aclocal.m4.
2309         * configure: Regenerated.
2310         * tconfig.in: New file.
2311
2312 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2313
2314         * interp.c: Fix bugs in 64-bit port.
2315         Use ansi function declarations for msvc compiler.
2316         Initialize and test file pointer in trace code.
2317         Prevent duplicate definition of LAST_EMED_REGNUM.
2318
2319 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2320
2321         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2322
2323 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2324
2325         * interp.c (SignalException): Check for explicit terminating
2326         breakpoint value.
2327         * gencode.c: Pass instruction value through SignalException()
2328         calls for Trap, Breakpoint and Syscall.
2329
2330 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2331
2332         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2333         only used on those hosts that provide it.
2334         * configure.in: Add sqrt() to list of functions to be checked for.
2335         * config.in: Re-generated.
2336         * configure: Re-generated.
2337
2338 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2339
2340         * gencode.c (process_instructions): Call build_endian_shift when
2341         expanding STORE RIGHT, to fix swr.
2342         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2343         clear the high bits.
2344         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2345         Fix float to int conversions to produce signed values.
2346
2347 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2348
2349         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2350         (process_instructions): Correct handling of nor instruction.
2351         Correct shift count for 32 bit shift instructions. Correct sign
2352         extension for arithmetic shifts to not shift the number of bits in
2353         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2354         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2355         Fix madd.
2356         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2357         It's OK to have a mult follow a mult.  What's not OK is to have a
2358         mult follow an mfhi.
2359         (Convert): Comment out incorrect rounding code.
2360
2361 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2362
2363         * interp.c (sim_monitor): Improved monitor printf
2364         simulation. Tidied up simulator warnings, and added "--log" option
2365         for directing warning message output.
2366         * gencode.c: Use sim_warning() rather than WARNING macro.
2367
2368 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2369
2370         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2371         getopt1.o, rather than on gencode.c.  Link objects together.
2372         Don't link against -liberty.
2373         (gencode.o, getopt.o, getopt1.o): New targets.
2374         * gencode.c: Include <ctype.h> and "ansidecl.h".
2375         (AND): Undefine after including "ansidecl.h".
2376         (ULONG_MAX): Define if not defined.
2377         (OP_*): Don't define macros; now defined in opcode/mips.h.
2378         (main): Call my_strtoul rather than strtoul.
2379         (my_strtoul): New static function.
2380
2381 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2382
2383         * gencode.c (process_instructions):  Generate word64 and uword64
2384         instead of `long long' and `unsigned long long' data types.
2385         * interp.c:  #include sysdep.h to get signals, and define default
2386         for SIGBUS.
2387         * (Convert):  Work around for Visual-C++ compiler bug with type
2388         conversion.
2389         * support.h:  Make things compile under Visual-C++ by using
2390         __int64 instead of `long long'.  Change many refs to long long
2391         into word64/uword64 typedefs.
2392
2393 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2394
2395         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2396         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2397         (docdir): Removed.
2398         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2399         (AC_PROG_INSTALL): Added.
2400         (AC_PROG_CC): Moved to before configure.host call.
2401         * configure: Rebuilt.
2402
2403 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2404
2405         * configure.in: Define @SIMCONF@ depending on mips target.
2406         * configure: Rebuild.
2407         * Makefile.in (run): Add @SIMCONF@ to control simulator
2408         construction.
2409         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2410         * interp.c: Remove some debugging, provide more detailed error
2411         messages, update memory accesses to use LOADDRMASK.
2412
2413 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2414
2415         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2416         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2417         stamp-h.
2418         * configure: Rebuild.
2419         * config.in: New file, generated by autoheader.
2420         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2421         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2422         HAVE_ANINT and HAVE_AINT, as appropriate.
2423         * Makefile.in (run): Use @LIBS@ rather than -lm.
2424         (interp.o): Depend upon config.h.
2425         (Makefile): Just rebuild Makefile.
2426         (clean): Remove stamp-h.
2427         (mostlyclean): Make the same as clean, not as distclean.
2428         (config.h, stamp-h): New targets.
2429
2430 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2431
2432         * interp.c (ColdReset): Fix boolean test. Make all simulator
2433         globals static.
2434
2435 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2436
2437         * interp.c (xfer_direct_word, xfer_direct_long,
2438         swap_direct_word, swap_direct_long, xfer_big_word,
2439         xfer_big_long, xfer_little_word, xfer_little_long,
2440         swap_word,swap_long): Added.
2441         * interp.c (ColdReset): Provide function indirection to
2442         host<->simulated_target transfer routines.
2443         * interp.c (sim_store_register, sim_fetch_register): Updated to
2444         make use of indirected transfer routines.
2445
2446 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2447
2448         * gencode.c (process_instructions): Ensure FP ABS instruction
2449         recognised.
2450         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2451         system call support.
2452
2453 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2454
2455         * interp.c (sim_do_command): Complain if callback structure not
2456         initialised.
2457
2458 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2459
2460         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2461         support for Sun hosts.
2462         * Makefile.in (gencode): Ensure the host compiler and libraries
2463         used for cross-hosted build.
2464
2465 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2466
2467         * interp.c, gencode.c: Some more (TODO) tidying.
2468
2469 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2470
2471         * gencode.c, interp.c: Replaced explicit long long references with
2472         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2473         * support.h (SET64LO, SET64HI): Macros added.
2474
2475 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2476
2477         * configure: Regenerate with autoconf 2.7.
2478
2479 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2480
2481         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2482         * support.h: Remove superfluous "1" from #if.
2483         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2484
2485 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2486
2487         * interp.c (StoreFPR): Control UndefinedResult() call on
2488         WARN_RESULT manifest.
2489
2490 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2491
2492         * gencode.c: Tidied instruction decoding, and added FP instruction
2493         support.
2494
2495         * interp.c: Added dineroIII, and BSD profiling support. Also
2496         run-time FP handling.
2497
2498 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2499
2500         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2501         gencode.c, interp.c, support.h: created.