sim/mips/ChangeLog

   1 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
   2
   3         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
   4         instruction-printing string.
   5         (LWU): Use '64' as the filter flag.
   6
   7 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
   8
   9         * mips.igen (SDXC1): Fix instruction-printing string.
  10
  11 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
  12
  13         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
  14         filter flags "32,f".
  15
  16 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
  17
  18         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
  19         as the filter flag.
  20
  21 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
  22
  23         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
  24         add a comma) so that it more closely match the MIPS ISA
  25         documentation opcode partitioning.
  26         (PREF): Put useful names on opcode fields, and include
  27         instruction-printing string.
  28
  29 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
  30
  31         * mips.igen (check_u64): New function which in the future will
  32         check whether 64-bit instructions are usable and signal an
  33         exception if not.  Currently a no-op.
  34         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
  35         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
  36         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
  37         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
  38
  39         * mips.igen (check_fpu): New function which in the future will
  40         check whether FPU instructions are usable and signal an exception
  41         if not.  Currently a no-op.
  42         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
  43         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
  44         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
  45         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
  46         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
  47         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
  48         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
  49         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
  50
  51 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
  52
  53         * mips.igen (do_load_left, do_load_right): Move to be immediately
  54         following do_load.
  55         (do_store_left, do_store_right): Move to be immediately following
  56         do_store.
  57
  58 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
  59
  60         * mips.igen (mipsV): New model name.  Also, add it to
  61         all instructions and functions where it is appropriate.
  62
  63 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
  64
  65         * mips.igen: For all functions and instructions, list model
  66         names that support that instruction one per line.
  67
  68 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
  69
  70         * mips.igen: Add some additional comments about supported
  71         models, and about which instructions go where.
  72         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
  73         order as is used in the rest of the file.
  74
  75 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
  76
  77         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
  78         indicating that ALU32_END or ALU64_END are there to check
  79         for overflow.
  80         (DADD): Likewise, but also remove previous comment about
  81         overflow checking.
  82
  83 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
  84
  85         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
  86         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
  87         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
  88         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
  89         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
  90         fields (i.e., add and move commas) so that they more closely
  91         match the MIPS ISA documentation opcode partitioning.
  92
  93 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
  94
  95         * mips.igen (ADDI): Print immediate value.
  96         (BREAK): Print code.
  97         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
  98         (SLL): Print "nop" specially, and don't run the code
  99         that does the shift for the "nop" case.
 100
 101 2001-11-17  Fred Fish  <fnf@redhat.com>
 102
 103         * sim-main.h (float_operation): Move enum declaration outside
 104         of _sim_cpu struct declaration.
 105
 106 2001-04-12  Jim Blandy  <jimb@redhat.com>
 107
 108         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 109         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 110         set of the FCSR.
 111         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 112         PENDING_FILL, and you can get the intended effect gracefully by
 113         calling PENDING_SCHED directly.
 114
 115 2001-02-23  Ben Elliston  <bje@redhat.com>
 116
 117         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 118         already defined elsewhere.
 119
 120 2001-02-19  Ben Elliston  <bje@redhat.com>
 121
 122         * sim-main.h (sim_monitor): Return an int.
 123         * interp.c (sim_monitor): Add return values.
 124         (signal_exception): Handle error conditions from sim_monitor.
 125
 126 2001-02-08  Ben Elliston  <bje@redhat.com>
 127
 128         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 129         (store_memory): Likewise, pass cia to sim_core_write*.
 130
 131 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 132
 133         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 134         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 135
 136 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 137
 138         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 139         * Makefile.in: Don't delete *.igen when cleaning directory.
 140
 141 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 142
 143         * m16.igen (break): Call SignalException not sim_engine_halt.
 144
 145 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 146
 147         From Jason Eckhardt:
 148         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 149
 150 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 151
 152         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 153
 154 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 155
 156         * mips.igen (do_dmultx): Fix typo.
 157
 158 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 159
 160         * configure: Regenerated to track ../common/aclocal.m4 changes.
 161
 162 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 163
 164         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 165
 166 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 167
 168         * sim-main.h (GPR_CLEAR): Define macro.
 169
 170 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 171
 172         * interp.c (decode_coproc): Output long using %lx and not %s.
 173
 174 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 175
 176         * interp.c (sim_open): Sort & extend dummy memory regions for
 177         --board=jmr3904 for eCos.
 178
 179 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 180
 181         * configure: Regenerated.
 182
 183 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 184
 185         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 186         calls, conditional on the simulator being in verbose mode.
 187
 188 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 189
 190         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 191         cache don't get ReservedInstruction traps.
 192
 193 1999-11-29  Mark Salter  <msalter@cygnus.com>
 194
 195         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 196         to clear status bits in sdisr register. This is how the hardware works.
 197
 198         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 199         being used by cygmon.
 200
 201 1999-11-11  Andrew Haley  <aph@cygnus.com>
 202
 203         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 204         instructions.
 205
 206 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 207
 208         * mips.igen (MULT): Correct previous mis-applied patch.
 209
 210 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 211
 212         * mips.igen (delayslot32): Handle sequence like
 213         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 214         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 215         (MULT): Actually pass the third register...
 216
 217 1999-09-03  Mark Salter  <msalter@cygnus.com>
 218
 219         * interp.c (sim_open): Added more memory aliases for additional
 220         hardware being touched by cygmon on jmr3904 board.
 221
 222 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 223
 224         * configure: Regenerated to track ../common/aclocal.m4 changes.
 225
 226 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 227
 228         * interp.c (sim_store_register): Handle case where client - GDB -
 229         specifies that a 4 byte register is 8 bytes in size.
 230         (sim_fetch_register): Ditto.
 231
 232 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 233
 234         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 235         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 236         (idt_monitor_base): Base address for IDT monitor traps.
 237         (pmon_monitor_base): Ditto for PMON.
 238         (lsipmon_monitor_base): Ditto for LSI PMON.
 239         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 240         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 241         (sim_firmware_command): New function.
 242         (mips_option_handler): Call it for OPTION_FIRMWARE.
 243         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 244         option was given, add no monitor by default.  Add BREAK hooks only if
 245         monitors are also there.
 246
 247 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 248
 249         * interp.c (sim_monitor): Flush output before reading input.
 250
 251 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 252
 253         * tconfig.in (SIM_HANDLES_LMA): Always define.
 254
 255 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 256
 257         From Mark Salter <msalter@cygnus.com>:
 258         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 259         (sim_open): Add setup for BSP board.
 260
 261 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 262
 263         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 264         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 265         them as unimplemented.
 266
 267 1999-05-08  Felix Lee  <flee@cygnus.com>
 268
 269         * configure: Regenerated to track ../common/aclocal.m4 changes.
 270
 271 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 272
 273         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 274
 275 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 276
 277         * configure.in: Any mips64vr5*-*-* target should have
 278         -DTARGET_ENABLE_FR=1.
 279         (default_endian): Any mips64vr*el-*-* target should default to
 280         LITTLE_ENDIAN.
 281         * configure: Re-generate.
 282
 283 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 284
 285         * mips.igen (ldl): Extend from _16_, not 32.
 286
 287 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 288
 289         * interp.c (sim_store_register): Force registers written to by GDB
 290         into an un-interpreted state.
 291
 292 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 293
 294         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 295         CPU, start periodic background I/O polls.
 296         (tx3904sio_poll): New function: periodic I/O poller.
 297
 298 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 299
 300         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 301
 302 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 303
 304         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 305         case statement.
 306
 307 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 308
 309         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 310         (load_word): Call SIM_CORE_SIGNAL hook on error.
 311         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 312         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 313         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 314         * sim-main.h (COP0_BADVADDR): Define.
 315         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 316         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 317         (_sim_cpu): Add exc_* fields to store register value snapshots.
 318         * mips.igen (*): Replace memory-related SignalException* calls
 319         with references to SIM_CORE_SIGNAL hook.
 320
 321         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 322         fix.
 323         * sim-main.c (*): Minor warning cleanups.
 324
 325 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 326
 327         * m16.igen (DADDIU5): Correct type-o.
 328
 329 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 330
 331         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 332         variables.
 333
 334 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 335
 336         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 337         to include path.
 338         (interp.o): Add dependency on itable.h
 339         (oengine.c, gencode): Delete remaining references.
 340         (BUILT_SRC_FROM_GEN): Clean up.
 341
 342 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 343
 344         * vr4run.c: New.
 345         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 346         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 347         tmp-run-hack) : New.
 348         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 349         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 350         Drop the "64" qualifier to get the HACK generator working.
 351         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 352         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 353         qualifier to get the hack generator working.
 354         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 355         (DSLL): Use do_dsll.
 356         (DSLLV): Use do_dsllv.
 357         (DSRA): Use do_dsra.
 358         (DSRL): Use do_dsrl.
 359         (DSRLV): Use do_dsrlv.
 360         (BC1): Move *vr4100 to get the HACK generator working.
 361         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 362         get the HACK generator working.
 363         (MACC) Rename to get the HACK generator working.
 364         (DMACC,MACCS,DMACCS): Add the 64.
 365
 366 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 367
 368         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 369         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 370
 371 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 372
 373     * mips/interp.c (DEBUG): Cleanups.
 374
 375 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 376
 377         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 378         (tx3904sio_tickle): fflush after a stdout character output.
 379
 380 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 381
 382         * interp.c (sim_close): Uninstall modules.
 383
 384 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 385
 386         * sim-main.h, interp.c (sim_monitor): Change to global
 387         function.
 388
 389 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 390
 391         * configure.in (vr4100): Only include vr4100 instructions in
 392         simulator.
 393         * configure: Re-generate.
 394         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 395
 396 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 397
 398         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 399         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 400         true alternative.
 401
 402         * configure.in (sim_default_gen, sim_use_gen): Replace with
 403         sim_gen.
 404         (--enable-sim-igen): Delete config option. Always using IGEN.
 405         * configure: Re-generate.
 406
 407         * Makefile.in (gencode): Kill, kill, kill.
 408         * gencode.c: Ditto.
 409
 410 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 411
 412         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 413         bit mips16 igen simulator.
 414         * configure: Re-generate.
 415
 416         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 417         as part of vr4100 ISA.
 418         * vr.igen: Mark all instructions as 64 bit only.
 419
 420 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 421
 422         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 423         Pacify GCC.
 424
 425 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 426
 427         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 428         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 429         * configure: Re-generate.
 430
 431         * m16.igen (BREAK): Define breakpoint instruction.
 432         (JALX32): Mark instruction as mips16 and not r3900.
 433         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 434
 435         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 436
 437 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 438
 439         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 440         insn as a debug breakpoint.
 441
 442         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 443         pending.slot_size.
 444         (PENDING_SCHED): Clean up trace statement.
 445         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 446         (PENDING_FILL): Delay write by only one cycle.
 447         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 448
 449         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 450         of pending writes.
 451         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 452         32 & 64.
 453         (pending_tick): Move incrementing of index to FOR statement.
 454         (pending_tick): Only update PENDING_OUT after a write has occured.
 455
 456         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 457         build simulator.
 458         * configure: Re-generate.
 459
 460         * interp.c (sim_engine_run OLD): Delete explicit call to
 461         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 462
 463 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 464
 465         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 466         interrupt level number to match changed SignalExceptionInterrupt
 467         macro.
 468
 469 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 470
 471         * interp.c: #include "itable.h" if WITH_IGEN.
 472         (get_insn_name): New function.
 473         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 474         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 475
 476 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 477
 478         * configure: Rebuilt to inhale new common/aclocal.m4.
 479
 480 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 481
 482         * dv-tx3904sio.c: Include sim-assert.h.
 483
 484 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 485
 486         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 487         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 488         Reorganize target-specific sim-hardware checks.
 489         * configure: rebuilt.
 490         * interp.c (sim_open): For tx39 target boards, set
 491         OPERATING_ENVIRONMENT, add tx3904sio devices.
 492         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 493         ROM executables.  Install dv-sockser into sim-modules list.
 494
 495         * dv-tx3904irc.c: Compiler warning clean-up.
 496         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 497         frequent hw-trace messages.
 498
 499 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 500
 501         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 502
 503 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 504
 505         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 506
 507         * vr.igen: New file.
 508         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 509         * mips.igen: Define vr4100 model. Include vr.igen.
 510 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 511
 512         * mips.igen (check_mf_hilo): Correct check.
 513
 514 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 515
 516         * sim-main.h (interrupt_event): Add prototype.
 517
 518         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 519         register_ptr, register_value.
 520         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 521
 522         * sim-main.h (tracefh): Make extern.
 523
 524 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 525
 526         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 527         Reduce unnecessarily high timer event frequency.
 528         * dv-tx3904cpu.c: Ditto for interrupt event.
 529
 530 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 531
 532         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 533         to allay warnings.
 534         (interrupt_event): Made non-static.
 535
 536         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 537         interchange of configuration values for external vs. internal
 538         clock dividers.
 539
 540 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 541
 542         * mips.igen (BREAK): Moved code to here for
 543         simulator-reserved break instructions.
 544         * gencode.c (build_instruction): Ditto.
 545         * interp.c (signal_exception): Code moved from here.  Non-
 546         reserved instructions now use exception vector, rather
 547         than halting sim.
 548         * sim-main.h: Moved magic constants to here.
 549
 550 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 551
 552         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 553         register upon non-zero interrupt event level, clear upon zero
 554         event value.
 555         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 556         by passing zero event value.
 557         (*_io_{read,write}_buffer): Endianness fixes.
 558         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 559         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 560
 561         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 562         serial I/O and timer module at base address 0xFFFF0000.
 563
 564 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 565
 566         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 567         and BigEndianCPU.
 568
 569 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 570
 571         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 572         parts.
 573         * configure: Update.
 574
 575 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 576
 577         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 578         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 579         * configure.in: Include tx3904tmr in hw_device list.
 580         * configure: Rebuilt.
 581         * interp.c (sim_open): Instantiate three timer instances.
 582         Fix address typo of tx3904irc instance.
 583
 584 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 585
 586         * interp.c (signal_exception): SystemCall exception now uses
 587         the exception vector.
 588
 589 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 590
 591         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 592         to allay warnings.
 593
 594 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 595
 596         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 597
 598 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 599
 600         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 601
 602         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 603         sim-main.h. Declare a struct hw_descriptor instead of struct
 604         hw_device_descriptor.
 605
 606 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 607
 608         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 609         right bits and then re-align left hand bytes to correct byte
 610         lanes.  Fix incorrect computation in do_store_left when loading
 611         bytes from second word.
 612
 613 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 614
 615         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 616         * interp.c (sim_open): Only create a device tree when HW is
 617         enabled.
 618
 619         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 620         * interp.c (signal_exception): Ditto.
 621
 622 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 623
 624         * gencode.c: Mark BEGEZALL as LIKELY.
 625
 626 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 627
 628         * sim-main.h (ALU32_END): Sign extend 32 bit results.
 629         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
 630
 631 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
 632
 633         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 634         modules.  Recognize TX39 target with "mips*tx39" pattern.
 635         * configure: Rebuilt.
 636         * sim-main.h (*): Added many macros defining bits in
 637         TX39 control registers.
 638         (SignalInterrupt): Send actual PC instead of NULL.
 639         (SignalNMIReset): New exception type.
 640         * interp.c (board): New variable for future use to identify
 641         a particular board being simulated.
 642         (mips_option_handler,mips_options): Added "--board" option.
 643         (interrupt_event): Send actual PC.
 644         (sim_open): Make memory layout conditional on board setting.
 645         (signal_exception): Initial implementation of hardware interrupt
 646         handling.  Accept another break instruction variant for simulator
 647         exit.
 648         (decode_coproc): Implement RFE instruction for TX39.
 649         (mips.igen): Decode RFE instruction as such.
 650         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
 651         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
 652         bbegin to implement memory map.
 653         * dv-tx3904cpu.c: New file.
 654         * dv-tx3904irc.c: New file.
 655
 656 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
 657
 658         * mips.igen (check_mt_hilo): Create a separate r3900 version.
 659
 660 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
 661
 662         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
 663         with calls to check_div_hilo.
 664
 665 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
 666
 667         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
 668         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
 669         Add special r3900 version of do_mult_hilo.
 670         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
 671         with calls to check_mult_hilo.
 672         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
 673         with calls to check_div_hilo.
 674
 675 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 676
 677         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
 678         Document a replacement.
 679
 680 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
 681
 682         * interp.c (sim_monitor): Make mon_printf work.
 683
 684 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
 685
 686         * sim-main.h (INSN_NAME): New arg `cpu'.
 687
 688 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
 689
 690         * configure: Regenerated to track ../common/aclocal.m4 changes.
 691
 692 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
 693
 694         * configure: Regenerated to track ../common/aclocal.m4 changes.
 695         * config.in: Ditto.
 696
 697 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
 698
 699         * acconfig.h: New file.
 700         * configure.in: Reverted change of Apr 24; use sinclude again.
 701
 702 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
 703
 704         * configure: Regenerated to track ../common/aclocal.m4 changes.
 705         * config.in: Ditto.
 706
 707 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
 708
 709         * configure.in: Don't call sinclude.
 710
 711 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
 712
 713         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
 714
 715 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 716
 717         * mips.igen (ERET): Implement.
 718
 719         * interp.c (decode_coproc): Return sign-extended EPC.
 720
 721         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
 722
 723         * interp.c (signal_exception): Do not ignore Trap.
 724         (signal_exception): On TRAP, restart at exception address.
 725         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
 726         (signal_exception): Update.
 727         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
 728         so that TRAP instructions are caught.
 729
 730 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 731
 732         * sim-main.h (struct hilo_access, struct hilo_history): Define,
 733         contains HI/LO access history.
 734         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
 735         (HIACCESS, LOACCESS): Delete, replace with
 736         (HIHISTORY, LOHISTORY): New macros.
 737         (CHECKHILO): Delete all, moved to mips.igen
 738
 739         * gencode.c (build_instruction): Do not generate checks for
 740         correct HI/LO register usage.
 741
 742         * interp.c (old_engine_run): Delete checks for correct HI/LO
 743         register usage.
 744
 745         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
 746         check_mf_cycles): New functions.
 747         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
 748         do_divu, domultx, do_mult, do_multu): Use.
 749
 750         * tx.igen ("madd", "maddu"): Use.
 751
 752 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 753
 754         * mips.igen (DSRAV): Use function do_dsrav.
 755         (SRAV): Use new function do_srav.
 756
 757         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
 758         (B): Sign extend 11 bit immediate.
 759         (EXT-B*): Shift 16 bit immediate left by 1.
 760         (ADDIU*): Don't sign extend immediate value.
 761
 762 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 763
 764         * m16run.c (sim_engine_run): Restore CIA after handling an event.
 765
 766         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
 767         functions.
 768
 769         * mips.igen (delayslot32, nullify_next_insn): New functions.
 770         (m16.igen): Always include.
 771         (do_*): Add more tracing.
 772
 773         * m16.igen (delayslot16): Add NIA argument, could be called by a
 774         32 bit MIPS16 instruction.
 775
 776         * interp.c (ifetch16): Move function from here.
 777         * sim-main.c (ifetch16): To here.
 778
 779         * sim-main.c (ifetch16, ifetch32): Update to match current
 780         implementations of LH, LW.
 781         (signal_exception): Don't print out incorrect hex value of illegal
 782         instruction.
 783
 784 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 785
 786         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
 787         instruction.
 788
 789         * m16.igen: Implement MIPS16 instructions.
 790
 791         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
 792         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
 793         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
 794         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
 795         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
 796         bodies of corresponding code from 32 bit insn to these.  Also used
 797         by MIPS16 versions of functions.
 798
 799         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
 800         (IMEM16): Drop NR argument from macro.
 801
 802 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 803
 804         * Makefile.in (SIM_OBJS): Add sim-main.o.
 805
 806         * sim-main.h (address_translation, load_memory, store_memory,
 807         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
 808         as INLINE_SIM_MAIN.
 809         (pr_addr, pr_uword64): Declare.
 810         (sim-main.c): Include when H_REVEALS_MODULE_P.
 811
 812         * interp.c (address_translation, load_memory, store_memory,
 813         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
 814         from here.
 815         * sim-main.c: To here. Fix compilation problems.
 816
 817         * configure.in: Enable inlining.
 818         * configure: Re-config.
 819
 820 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 821
 822         * configure: Regenerated to track ../common/aclocal.m4 changes.
 823
 824 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 825
 826         * mips.igen: Include tx.igen.
 827         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
 828         * tx.igen: New file, contains MADD and MADDU.
 829
 830         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
 831         the hardwired constant `7'.
 832         (store_memory): Ditto.
 833         (LOADDRMASK): Move definition to sim-main.h.
 834
 835         mips.igen (MTC0): Enable for r3900.
 836         (ADDU): Add trace.
 837
 838         mips.igen (do_load_byte): Delete.
 839         (do_load, do_store, do_load_left, do_load_write, do_store_left,
 840         do_store_right): New functions.
 841         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
 842
 843         configure.in: Let the tx39 use igen again.
 844         configure: Update.
 845
 846 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 847
 848         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
 849         not an address sized quantity.  Return zero for cache sizes.
 850
 851 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 852
 853         * mips.igen (r3900): r3900 does not support 64 bit integer
 854         operations.
 855
 856 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
 857
 858         * configure.in (mipstx39*-*-*): Use gencode simulator rather
 859         than igen one.
 860         * configure : Rebuild.
 861
 862 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 863
 864         * configure: Regenerated to track ../common/aclocal.m4 changes.
 865
 866 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 867
 868         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
 869
 870 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
 871
 872         * configure: Regenerated to track ../common/aclocal.m4 changes.
 873         * config.in: Regenerated to track ../common/aclocal.m4 changes.
 874
 875 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 876
 877         * configure: Regenerated to track ../common/aclocal.m4 changes.
 878
 879 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 880
 881         * interp.c (Max, Min): Comment out functions. Not yet used.
 882
 883 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 884
 885         * configure: Regenerated to track ../common/aclocal.m4 changes.
 886
 887 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
 888
 889         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
 890         configurable settings for stand-alone simulator.
 891
 892         * configure.in: Added X11 search, just in case.
 893
 894         * configure: Regenerated.
 895
 896 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 897
 898         * interp.c (sim_write, sim_read, load_memory, store_memory):
 899         Replace sim_core_*_map with read_map, write_map, exec_map resp.
 900
 901 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 902
 903         * sim-main.h (GETFCC): Return an unsigned value.
 904
 905 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 906
 907         * mips.igen (DIV): Fix check for -1 / MIN_INT.
 908         (DADD): Result destination is RD not RT.
 909
 910 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 911
 912         * sim-main.h (HIACCESS, LOACCESS): Always define.
 913
 914         * mdmx.igen (Maxi, Mini): Rename Max, Min.
 915
 916         * interp.c (sim_info): Delete.
 917
 918 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
 919
 920         * interp.c (DECLARE_OPTION_HANDLER): Use it.
 921         (mips_option_handler): New argument `cpu'.
 922         (sim_open): Update call to sim_add_option_table.
 923
 924 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 925
 926         * mips.igen (CxC1): Add tracing.
 927
 928 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 929
 930         * sim-main.h (Max, Min): Declare.
 931
 932         * interp.c (Max, Min): New functions.
 933
 934         * mips.igen (BC1): Add tracing.
 935
 936 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
 937
 938         * interp.c Added memory map for stack in vr4100
 939
 940 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
 941
 942         * interp.c (load_memory): Add missing "break"'s.
 943
 944 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 945
 946         * interp.c (sim_store_register, sim_fetch_register): Pass in
 947         length parameter.  Return -1.
 948
 949 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
 950
 951         * interp.c: Added hardware init hook, fixed warnings.
 952
 953 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 954
 955         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
 956
 957 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 958
 959         * interp.c (ifetch16): New function.
 960
 961         * sim-main.h (IMEM32): Rename IMEM.
 962         (IMEM16_IMMED): Define.
 963         (IMEM16): Define.
 964         (DELAY_SLOT): Update.
 965
 966         * m16run.c (sim_engine_run): New file.
 967
 968         * m16.igen: All instructions except LB.
 969         (LB): Call do_load_byte.
 970         * mips.igen (do_load_byte): New function.
 971         (LB): Call do_load_byte.
 972
 973         * mips.igen: Move spec for insn bit size and high bit from here.
 974         * Makefile.in (tmp-igen, tmp-m16): To here.
 975
 976         * m16.dc: New file, decode mips16 instructions.
 977
 978         * Makefile.in (SIM_NO_ALL): Define.
 979         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
 980
 981 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 982
 983         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
 984         point unit to 32 bit registers.
 985         * configure: Re-generate.
 986
 987 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 988
 989         * configure.in (sim_use_gen): Make IGEN the default simulator
 990         generator for generic 32 and 64 bit mips targets.
 991         * configure: Re-generate.
 992
 993 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 994
 995         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
 996         bitsize.
 997
 998         * interp.c (sim_fetch_register, sim_store_register): Read/write
 999         FGR from correct location.
1000         (sim_open): Set size of FGR's according to
1001         WITH_TARGET_FLOATING_POINT_BITSIZE.
1002
1003         * sim-main.h (FGR): Store floating point registers in a separate
1004         array.
1005
1006 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1007
1008         * configure: Regenerated to track ../common/aclocal.m4 changes.
1009
1010 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1011
1012         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1013
1014         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1015
1016         * interp.c (pending_tick): New function.  Deliver pending writes.
1017
1018         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1019         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1020         it can handle mixed sized quantites and single bits.
1021
1022 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1023
1024         * interp.c (oengine.h): Do not include when building with IGEN.
1025         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1026         (sim_info): Ditto for PROCESSOR_64BIT.
1027         (sim_monitor): Replace ut_reg with unsigned_word.
1028         (*): Ditto for t_reg.
1029         (LOADDRMASK): Define.
1030         (sim_open): Remove defunct check that host FP is IEEE compliant,
1031         using software to emulate floating point.
1032         (value_fpr, ...): Always compile, was conditional on HASFPU.
1033
1034 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1035
1036         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1037         size.
1038
1039         * interp.c (SD, CPU): Define.
1040         (mips_option_handler): Set flags in each CPU.
1041         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1042         (sim_close): Do not clear STATE, deleted anyway.
1043         (sim_write, sim_read): Assume CPU zero's vm should be used for
1044         data transfers.
1045         (sim_create_inferior): Set the PC for all processors.
1046         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1047         argument.
1048         (mips16_entry): Pass correct nr of args to store_word, load_word.
1049         (ColdReset): Cold reset all cpu's.
1050         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1051         (sim_monitor, load_memory, store_memory, signal_exception): Use
1052         `CPU' instead of STATE_CPU.
1053
1054
1055         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1056         SD or CPU_.
1057
1058         * sim-main.h (signal_exception): Add sim_cpu arg.
1059         (SignalException*): Pass both SD and CPU to signal_exception.
1060         * interp.c (signal_exception): Update.
1061
1062         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1063         Ditto
1064         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1065         address_translation): Ditto
1066         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1067
1068 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1069
1070         * configure: Regenerated to track ../common/aclocal.m4 changes.
1071
1072 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1073
1074         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1075
1076         * mips.igen (model): Map processor names onto BFD name.
1077
1078         * sim-main.h (CPU_CIA): Delete.
1079         (SET_CIA, GET_CIA): Define
1080
1081 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1082
1083         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1084         regiser.
1085
1086         * configure.in (default_endian): Configure a big-endian simulator
1087         by default.
1088         * configure: Re-generate.
1089
1090 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1091
1092         * configure: Regenerated to track ../common/aclocal.m4 changes.
1093
1094 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1095
1096         * interp.c (sim_monitor): Handle Densan monitor outbyte
1097         and inbyte functions.
1098
1099 1997-12-29  Felix Lee  <flee@cygnus.com>
1100
1101         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1102
1103 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1104
1105         * Makefile.in (tmp-igen): Arrange for $zero to always be
1106         reset to zero after every instruction.
1107
1108 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1109
1110         * configure: Regenerated to track ../common/aclocal.m4 changes.
1111         * config.in: Ditto.
1112
1113 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1114
1115         * mips.igen (MSUB): Fix to work like MADD.
1116         * gencode.c (MSUB): Similarly.
1117
1118 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1119
1120         * configure: Regenerated to track ../common/aclocal.m4 changes.
1121
1122 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1123
1124         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1125
1126 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1127
1128         * sim-main.h (sim-fpu.h): Include.
1129
1130         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1131         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1132         using host independant sim_fpu module.
1133
1134 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1135
1136         * interp.c (signal_exception): Report internal errors with SIGABRT
1137         not SIGQUIT.
1138
1139         * sim-main.h (C0_CONFIG): New register.
1140         (signal.h): No longer include.
1141
1142         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1143
1144 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1145
1146         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1147
1148 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1149
1150         * mips.igen: Tag vr5000 instructions.
1151         (ANDI): Was missing mipsIV model, fix assembler syntax.
1152         (do_c_cond_fmt): New function.
1153         (C.cond.fmt): Handle mips I-III which do not support CC field
1154         separatly.
1155         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1156         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1157         in IV3.2 spec.
1158         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1159         vr5000 which saves LO in a GPR separatly.
1160
1161         * configure.in (enable-sim-igen): For vr5000, select vr5000
1162         specific instructions.
1163         * configure: Re-generate.
1164
1165 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1166
1167         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1168
1169         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1170         fmt_uninterpreted_64 bit cases to switch.  Convert to
1171         fmt_formatted,
1172
1173         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1174
1175         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1176         as specified in IV3.2 spec.
1177         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1178
1179 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1180
1181         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1182         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1183         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1184         PENDING_FILL versions of instructions.  Simplify.
1185         (X): New function.
1186         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1187         instructions.
1188         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1189         a signed value.
1190         (MTHI, MFHI): Disable code checking HI-LO.
1191
1192         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1193         global.
1194         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1195
1196 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1197
1198         * gencode.c (build_mips16_operands): Replace IPC with cia.
1199
1200         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1201         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1202         IPC to `cia'.
1203         (UndefinedResult): Replace function with macro/function
1204         combination.
1205         (sim_engine_run): Don't save PC in IPC.
1206
1207         * sim-main.h (IPC): Delete.
1208
1209
1210         * interp.c (signal_exception, store_word, load_word,
1211         address_translation, load_memory, store_memory, cache_op,
1212         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1213         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1214         current instruction address - cia - argument.
1215         (sim_read, sim_write): Call address_translation directly.
1216         (sim_engine_run): Rename variable vaddr to cia.
1217         (signal_exception): Pass cia to sim_monitor
1218
1219         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1220         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1221         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1222
1223         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1224         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1225         SIM_ASSERT.
1226
1227         * interp.c (signal_exception): Pass restart address to
1228         sim_engine_restart.
1229
1230         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1231         idecode.o): Add dependency.
1232
1233         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1234         Delete definitions
1235         (DELAY_SLOT): Update NIA not PC with branch address.
1236         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1237
1238         * mips.igen: Use CIA not PC in branch calculations.
1239         (illegal): Call SignalException.
1240         (BEQ, ADDIU): Fix assembler.
1241
1242 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1243
1244         * m16.igen (JALX): Was missing.
1245
1246         * configure.in (enable-sim-igen): New configuration option.
1247         * configure: Re-generate.
1248
1249         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1250
1251         * interp.c (load_memory, store_memory): Delete parameter RAW.
1252         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1253         bypassing {load,store}_memory.
1254
1255         * sim-main.h (ByteSwapMem): Delete definition.
1256
1257         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1258
1259         * interp.c (sim_do_command, sim_commands): Delete mips specific
1260         commands.  Handled by module sim-options.
1261
1262         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1263         (WITH_MODULO_MEMORY): Define.
1264
1265         * interp.c (sim_info): Delete code printing memory size.
1266
1267         * interp.c (mips_size): Nee sim_size, delete function.
1268         (power2): Delete.
1269         (monitor, monitor_base, monitor_size): Delete global variables.
1270         (sim_open, sim_close): Delete code creating monitor and other
1271         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1272         manage memory regions.
1273         (load_memory, store_memory): Use sim-core for memory model.
1274
1275         * interp.c (address_translation): Delete all memory map code
1276         except line forcing 32 bit addresses.
1277
1278 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1279
1280         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1281         trace options.
1282
1283         * interp.c (logfh, logfile): Delete globals.
1284         (sim_open, sim_close): Delete code opening & closing log file.
1285         (mips_option_handler): Delete -l and -n options.
1286         (OPTION mips_options): Ditto.
1287
1288         * interp.c (OPTION mips_options): Rename option trace to dinero.
1289         (mips_option_handler): Update.
1290
1291 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1292
1293         * interp.c (fetch_str): New function.
1294         (sim_monitor): Rewrite using sim_read & sim_write.
1295         (sim_open): Check magic number.
1296         (sim_open): Write monitor vectors into memory using sim_write.
1297         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1298         (sim_read, sim_write): Simplify - transfer data one byte at a
1299         time.
1300         (load_memory, store_memory): Clarify meaning of parameter RAW.
1301
1302         * sim-main.h (isHOST): Defete definition.
1303         (isTARGET): Mark as depreciated.
1304         (address_translation): Delete parameter HOST.
1305
1306         * interp.c (address_translation): Delete parameter HOST.
1307
1308 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1309
1310         * mips.igen:
1311
1312         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1313         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1314
1315 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1316
1317         * mips.igen: Add model filter field to records.
1318
1319 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1320
1321         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1322
1323         interp.c (sim_engine_run): Do not compile function sim_engine_run
1324         when WITH_IGEN == 1.
1325
1326         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1327         target architecture.
1328
1329         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1330         igen. Replace with configuration variables sim_igen_flags /
1331         sim_m16_flags.
1332
1333         * m16.igen: New file.  Copy mips16 insns here.
1334         * mips.igen: From here.
1335
1336 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1337
1338         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1339         to top.
1340         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1341
1342 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1343
1344         * gencode.c (build_instruction): Follow sim_write's lead in using
1345         BigEndianMem instead of !ByteSwapMem.
1346
1347 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1348
1349         * configure.in (sim_gen): Dependent on target, select type of
1350         generator.  Always select old style generator.
1351
1352         configure: Re-generate.
1353
1354         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1355         targets.
1356         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1357         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1358         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1359         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1360         SIM_@sim_gen@_*, set by autoconf.
1361
1362 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1363
1364         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1365
1366         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1367         CURRENT_FLOATING_POINT instead.
1368
1369         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1370         (address_translation): Raise exception InstructionFetch when
1371         translation fails and isINSTRUCTION.
1372
1373         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1374         sim_engine_run): Change type of of vaddr and paddr to
1375         address_word.
1376         (address_translation, prefetch, load_memory, store_memory,
1377         cache_op): Change type of vAddr and pAddr to address_word.
1378
1379         * gencode.c (build_instruction): Change type of vaddr and paddr to
1380         address_word.
1381
1382 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1383
1384         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1385         macro to obtain result of ALU op.
1386
1387 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1388
1389         * interp.c (sim_info): Call profile_print.
1390
1391 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1392
1393         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1394
1395         * sim-main.h (WITH_PROFILE): Do not define, defined in
1396         common/sim-config.h.  Use sim-profile module.
1397         (simPROFILE): Delete defintion.
1398
1399         * interp.c (PROFILE): Delete definition.
1400         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1401         (sim_close): Delete code writing profile histogram.
1402         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1403         Delete.
1404         (sim_engine_run): Delete code profiling the PC.
1405
1406 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1407
1408         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1409
1410         * interp.c (sim_monitor): Make register pointers of type
1411         unsigned_word*.
1412
1413         * sim-main.h: Make registers of type unsigned_word not
1414         signed_word.
1415
1416 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1417
1418         * interp.c (sync_operation): Rename from SyncOperation, make
1419         global, add SD argument.
1420         (prefetch): Rename from Prefetch, make global, add SD argument.
1421         (decode_coproc): Make global.
1422
1423         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1424
1425         * gencode.c (build_instruction): Generate DecodeCoproc not
1426         decode_coproc calls.
1427
1428         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1429         (SizeFGR): Move to sim-main.h
1430         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1431         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1432         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1433         sim-main.h.
1434         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1435         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1436         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1437         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1438         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1439         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1440
1441         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1442         exception.
1443         (sim-alu.h): Include.
1444         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1445         (sim_cia): Typedef to instruction_address.
1446
1447 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1448
1449         * Makefile.in (interp.o): Rename generated file engine.c to
1450         oengine.c.
1451
1452         * interp.c: Update.
1453
1454 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1455
1456         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1457
1458 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1459
1460         * gencode.c (build_instruction): For "FPSQRT", output correct
1461         number of arguments to Recip.
1462
1463 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1464
1465         * Makefile.in (interp.o): Depends on sim-main.h
1466
1467         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1468
1469         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1470         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1471         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1472         STATE, DSSTATE): Define
1473         (GPR, FGRIDX, ..): Define.
1474
1475         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1476         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1477         (GPR, FGRIDX, ...): Delete macros.
1478
1479         * interp.c: Update names to match defines from sim-main.h
1480
1481 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1482
1483         * interp.c (sim_monitor): Add SD argument.
1484         (sim_warning): Delete.  Replace calls with calls to
1485         sim_io_eprintf.
1486         (sim_error): Delete. Replace calls with sim_io_error.
1487         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1488         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1489         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1490         argument.
1491         (mips_size): Rename from sim_size. Add SD argument.
1492
1493         * interp.c (simulator): Delete global variable.
1494         (callback): Delete global variable.
1495         (mips_option_handler, sim_open, sim_write, sim_read,
1496         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1497         sim_size,sim_monitor): Use sim_io_* not callback->*.
1498         (sim_open): ZALLOC simulator struct.
1499         (PROFILE): Do not define.
1500
1501 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1502
1503         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1504         support.h with corresponding code.
1505
1506         * sim-main.h (word64, uword64), support.h: Move definition to
1507         sim-main.h.
1508         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1509
1510         * support.h: Delete
1511         * Makefile.in: Update dependencies
1512         * interp.c: Do not include.
1513
1514 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1515
1516         * interp.c (address_translation, load_memory, store_memory,
1517         cache_op): Rename to from AddressTranslation et.al., make global,
1518         add SD argument
1519
1520         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1521         CacheOp): Define.
1522
1523         * interp.c (SignalException): Rename to signal_exception, make
1524         global.
1525
1526         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1527
1528         * sim-main.h (SignalException, SignalExceptionInterrupt,
1529         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1530         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1531         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1532         Define.
1533
1534         * interp.c, support.h: Use.
1535
1536 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1537
1538         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1539         to value_fpr / store_fpr. Add SD argument.
1540         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1541         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1542
1543         * sim-main.h (ValueFPR, StoreFPR): Define.
1544
1545 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1546
1547         * interp.c (sim_engine_run): Check consistency between configure
1548         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1549         and HASFPU.
1550
1551         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1552         (mips_fpu): Configure WITH_FLOATING_POINT.
1553         (mips_endian): Configure WITH_TARGET_ENDIAN.
1554         * configure: Update.
1555
1556 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1557
1558         * configure: Regenerated to track ../common/aclocal.m4 changes.
1559
1560 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1561
1562         * configure: Regenerated.
1563
1564 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1565
1566         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1567
1568 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1569
1570         * gencode.c (print_igen_insn_models): Assume certain architectures
1571         include all mips* instructions.
1572         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1573         instruction.
1574
1575         * Makefile.in (tmp.igen): Add target. Generate igen input from
1576         gencode file.
1577
1578         * gencode.c (FEATURE_IGEN): Define.
1579         (main): Add --igen option.  Generate output in igen format.
1580         (process_instructions): Format output according to igen option.
1581         (print_igen_insn_format): New function.
1582         (print_igen_insn_models): New function.
1583         (process_instructions): Only issue warnings and ignore
1584         instructions when no FEATURE_IGEN.
1585
1586 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1587
1588         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1589         MIPS targets.
1590
1591 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1592
1593         * configure: Regenerated to track ../common/aclocal.m4 changes.
1594
1595 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1596
1597         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1598         SIM_RESERVED_BITS): Delete, moved to common.
1599         (SIM_EXTRA_CFLAGS): Update.
1600
1601 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1602
1603         * configure.in: Configure non-strict memory alignment.
1604         * configure: Regenerated to track ../common/aclocal.m4 changes.
1605
1606 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1607
1608         * configure: Regenerated to track ../common/aclocal.m4 changes.
1609
1610 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1611
1612         * gencode.c (SDBBP,DERET): Added (3900) insns.
1613         (RFE): Turn on for 3900.
1614         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1615         (dsstate): Made global.
1616         (SUBTARGET_R3900): Added.
1617         (CANCELDELAYSLOT): New.
1618         (SignalException): Ignore SystemCall rather than ignore and
1619         terminate.  Add DebugBreakPoint handling.
1620         (decode_coproc): New insns RFE, DERET; and new registers Debug
1621         and DEPC protected by SUBTARGET_R3900.
1622         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1623         bits explicitly.
1624         * Makefile.in,configure.in: Add mips subtarget option.
1625         * configure: Update.
1626
1627 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
1628
1629         * gencode.c: Add r3900 (tx39).
1630
1631
1632 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
1633
1634         * gencode.c (build_instruction): Don't need to subtract 4 for
1635         JALR, just 2.
1636
1637 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
1638
1639         * interp.c: Correct some HASFPU problems.
1640
1641 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1642
1643         * configure: Regenerated to track ../common/aclocal.m4 changes.
1644
1645 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1646
1647         * interp.c (mips_options): Fix samples option short form, should
1648         be `x'.
1649
1650 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1651
1652         * interp.c (sim_info): Enable info code.  Was just returning.
1653
1654 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1655
1656         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1657         MFC0.
1658
1659 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1660
1661         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1662         constants.
1663         (build_instruction): Ditto for LL.
1664
1665 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
1666
1667         * configure: Regenerated to track ../common/aclocal.m4 changes.
1668
1669 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1670
1671         * configure: Regenerated to track ../common/aclocal.m4 changes.
1672         * config.in: Ditto.
1673
1674 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1675
1676         * interp.c (sim_open): Add call to sim_analyze_program, update
1677         call to sim_config.
1678
1679 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1680
1681         * interp.c (sim_kill): Delete.
1682         (sim_create_inferior): Add ABFD argument. Set PC from same.
1683         (sim_load): Move code initializing trap handlers from here.
1684         (sim_open): To here.
1685         (sim_load): Delete, use sim-hload.c.
1686
1687         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1688
1689 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1690
1691         * configure: Regenerated to track ../common/aclocal.m4 changes.
1692         * config.in: Ditto.
1693
1694 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1695
1696         * interp.c (sim_open): Add ABFD argument.
1697         (sim_load): Move call to sim_config from here.
1698         (sim_open): To here.  Check return status.
1699
1700 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
1701
1702         * gencode.c (build_instruction): Two arg MADD should
1703         not assign result to $0.
1704
1705 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
1706
1707         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1708         * sim/mips/configure.in: Regenerate.
1709
1710 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
1711
1712         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1713         signed8, unsigned8 et.al. types.
1714
1715         * interp.c (SUB_REG_FETCH): Handle both little and big endian
1716         hosts when selecting subreg.
1717
1718 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
1719
1720         * interp.c (sim_engine_run): Reset the ZERO register to zero
1721         regardless of FEATURE_WARN_ZERO.
1722         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1723
1724 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1725
1726         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1727         (SignalException): For BreakPoints ignore any mode bits and just
1728         save the PC.
1729         (SignalException): Always set the CAUSE register.
1730
1731 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1732
1733         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1734         exception has been taken.
1735
1736         * interp.c: Implement the ERET and mt/f sr instructions.
1737
1738 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1739
1740         * interp.c (SignalException): Don't bother restarting an
1741         interrupt.
1742
1743 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1744
1745         * interp.c (SignalException): Really take an interrupt.
1746         (interrupt_event): Only deliver interrupts when enabled.
1747
1748 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1749
1750         * interp.c (sim_info): Only print info when verbose.
1751         (sim_info) Use sim_io_printf for output.
1752
1753 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1754
1755         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1756         mips architectures.
1757
1758 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1759
1760         * interp.c (sim_do_command): Check for common commands if a
1761         simulator specific command fails.
1762
1763 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
1764
1765         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1766         and simBE when DEBUG is defined.
1767
1768 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1769
1770         * interp.c (interrupt_event): New function.  Pass exception event
1771         onto exception handler.
1772
1773         * configure.in: Check for stdlib.h.
1774         * configure: Regenerate.
1775
1776         * gencode.c (build_instruction): Add UNUSED attribute to tempS
1777         variable declaration.
1778         (build_instruction): Initialize memval1.
1779         (build_instruction): Add UNUSED attribute to byte, bigend,
1780         reverse.
1781         (build_operands): Ditto.
1782
1783         * interp.c: Fix GCC warnings.
1784         (sim_get_quit_code): Delete.
1785
1786         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1787         * Makefile.in: Ditto.
1788         * configure: Re-generate.
1789
1790         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1791
1792 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1793
1794         * interp.c (mips_option_handler): New function parse argumes using
1795         sim-options.
1796         (myname): Replace with STATE_MY_NAME.
1797         (sim_open): Delete check for host endianness - performed by
1798         sim_config.
1799         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1800         (sim_open): Move much of the initialization from here.
1801         (sim_load): To here.  After the image has been loaded and
1802         endianness set.
1803         (sim_open): Move ColdReset from here.
1804         (sim_create_inferior): To here.
1805         (sim_open): Make FP check less dependant on host endianness.
1806
1807         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1808         run.
1809         * interp.c (sim_set_callbacks): Delete.
1810
1811         * interp.c (membank, membank_base, membank_size): Replace with
1812         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1813         (sim_open): Remove call to callback->init. gdb/run do this.
1814
1815         * interp.c: Update
1816
1817         * sim-main.h (SIM_HAVE_FLATMEM): Define.
1818
1819         * interp.c (big_endian_p): Delete, replaced by
1820         current_target_byte_order.
1821
1822 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1823
1824         * interp.c (host_read_long, host_read_word, host_swap_word,
1825         host_swap_long): Delete. Using common sim-endian.
1826         (sim_fetch_register, sim_store_register): Use H2T.
1827         (pipeline_ticks): Delete.  Handled by sim-events.
1828         (sim_info): Update.
1829         (sim_engine_run): Update.
1830
1831 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1832
1833         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1834         reason from here.
1835         (SignalException): To here. Signal using sim_engine_halt.
1836         (sim_stop_reason): Delete, moved to common.
1837
1838 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
1839
1840         * interp.c (sim_open): Add callback argument.
1841         (sim_set_callbacks): Delete SIM_DESC argument.
1842         (sim_size): Ditto.
1843
1844 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1845
1846         * Makefile.in (SIM_OBJS): Add common modules.
1847
1848         * interp.c (sim_set_callbacks): Also set SD callback.
1849         (set_endianness, xfer_*, swap_*): Delete.
1850         (host_read_word, host_read_long, host_swap_word, host_swap_long):
1851         Change to functions using sim-endian macros.
1852         (control_c, sim_stop): Delete, use common version.
1853         (simulate): Convert into.
1854         (sim_engine_run): This function.
1855         (sim_resume): Delete.
1856
1857         * interp.c (simulation): New variable - the simulator object.
1858         (sim_kind): Delete global - merged into simulation.
1859         (sim_load): Cleanup.  Move PC assignment from here.
1860         (sim_create_inferior): To here.
1861
1862         * sim-main.h: New file.
1863         * interp.c (sim-main.h): Include.
1864
1865 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
1866
1867         * configure: Regenerated to track ../common/aclocal.m4 changes.
1868
1869 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
1870
1871         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1872
1873 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
1874
1875         * gencode.c (build_instruction): DIV instructions: check
1876         for division by zero and integer overflow before using
1877         host's division operation.
1878
1879 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
1880
1881         * Makefile.in (SIM_OBJS): Add sim-load.o.
1882         * interp.c: #include bfd.h.
1883         (target_byte_order): Delete.
1884         (sim_kind, myname, big_endian_p): New static locals.
1885         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
1886         after argument parsing.  Recognize -E arg, set endianness accordingly.
1887         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
1888         load file into simulator.  Set PC from bfd.
1889         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
1890         (set_endianness): Use big_endian_p instead of target_byte_order.
1891
1892 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1893
1894         * interp.c (sim_size): Delete prototype - conflicts with
1895         definition in remote-sim.h.  Correct definition.
1896
1897 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1898
1899         * configure: Regenerated to track ../common/aclocal.m4 changes.
1900         * config.in: Ditto.
1901
1902 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
1903
1904         * interp.c (sim_open): New arg `kind'.
1905
1906         * configure: Regenerated to track ../common/aclocal.m4 changes.
1907
1908 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1909
1910         * configure: Regenerated to track ../common/aclocal.m4 changes.
1911
1912 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
1913
1914         * interp.c (sim_open): Set optind to 0 before calling getopt.
1915
1916 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1917
1918         * configure: Regenerated to track ../common/aclocal.m4 changes.
1919
1920 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
1921
1922         * interp.c : Replace uses of pr_addr with pr_uword64
1923         where the bit length is always 64 independent of SIM_ADDR.
1924         (pr_uword64) : added.
1925
1926 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1927
1928         * configure: Re-generate.
1929
1930 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
1931
1932         * configure: Regenerate to track ../common/aclocal.m4 changes.
1933
1934 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
1935
1936         * interp.c (sim_open): New SIM_DESC result.  Argument is now
1937         in argv form.
1938         (other sim_*): New SIM_DESC argument.
1939
1940 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
1941
1942         * interp.c: Fix printing of addresses for non-64-bit targets.
1943         (pr_addr): Add function to print address based on size.
1944
1945 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
1946
1947         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1948
1949 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
1950
1951         * gencode.c (build_mips16_operands): Correct computation of base
1952         address for extended PC relative instruction.
1953
1954 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
1955
1956         * interp.c (mips16_entry): Add support for floating point cases.
1957         (SignalException): Pass floating point cases to mips16_entry.
1958         (ValueFPR): Don't restrict fmt_single and fmt_word to even
1959         registers.
1960         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
1961         or fmt_word.
1962         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1963         and then set the state to fmt_uninterpreted.
1964         (COP_SW): Temporarily set the state to fmt_word while calling
1965         ValueFPR.
1966
1967 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
1968
1969         * gencode.c (build_instruction): The high order may be set in the
1970         comparison flags at any ISA level, not just ISA 4.
1971
1972 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
1973
1974         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1975         COMMON_{PRE,POST}_CONFIG_FRAG instead.
1976         * configure.in: sinclude ../common/aclocal.m4.
1977         * configure: Regenerated.
1978
1979 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
1980
1981         * configure: Rebuild after change to aclocal.m4.
1982
1983 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
1984
1985         * configure configure.in Makefile.in:  Update to new configure
1986         scheme which is more compatible with WinGDB builds.
1987         * configure.in:  Improve comment on how to run autoconf.
1988         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
1989         * Makefile.in:  Use autoconf substitution to install common
1990         makefile fragment.
1991
1992 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
1993
1994         * gencode.c (build_instruction): Use BigEndianCPU instead of
1995         ByteSwapMem.
1996
1997 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
1998
1999         * interp.c (sim_monitor): Make output to stdout visible in
2000         wingdb's I/O log window.
2001
2002 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2003
2004         * support.h: Undo previous change to SIGTRAP
2005         and SIGQUIT values.
2006
2007 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2008
2009         * interp.c (store_word, load_word): New static functions.
2010         (mips16_entry): New static function.
2011         (SignalException): Look for mips16 entry and exit instructions.
2012         (simulate): Use the correct index when setting fpr_state after
2013         doing a pending move.
2014
2015 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2016
2017         * interp.c: Fix byte-swapping code throughout to work on
2018         both little- and big-endian hosts.
2019
2020 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2021
2022         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2023         with gdb/config/i386/xm-windows.h.
2024
2025 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2026
2027         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2028         that messes up arithmetic shifts.
2029
2030 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2031
2032         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2033         SIGTRAP and SIGQUIT for _WIN32.
2034
2035 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2036
2037         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2038         force a 64 bit multiplication.
2039         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2040         destination register is 0, since that is the default mips16 nop
2041         instruction.
2042
2043 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2044
2045         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2046         (build_endian_shift): Don't check proc64.
2047         (build_instruction): Always set memval to uword64.  Cast op2 to
2048         uword64 when shifting it left in memory instructions.  Always use
2049         the same code for stores--don't special case proc64.
2050
2051         * gencode.c (build_mips16_operands): Fix base PC value for PC
2052         relative operands.
2053         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2054         jal instruction.
2055         * interp.c (simJALDELAYSLOT): Define.
2056         (JALDELAYSLOT): Define.
2057         (INDELAYSLOT, INJALDELAYSLOT): Define.
2058         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2059
2060 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2061
2062         * interp.c (sim_open): add flush_cache as a PMON routine
2063         (sim_monitor): handle flush_cache by ignoring it
2064
2065 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2066
2067         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2068         BigEndianMem.
2069         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2070         (BigEndianMem): Rename to ByteSwapMem and change sense.
2071         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2072         BigEndianMem references to !ByteSwapMem.
2073         (set_endianness): New function, with prototype.
2074         (sim_open): Call set_endianness.
2075         (sim_info): Use simBE instead of BigEndianMem.
2076         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2077         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2078         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2079         ifdefs, keeping the prototype declaration.
2080         (swap_word): Rewrite correctly.
2081         (ColdReset): Delete references to CONFIG.  Delete endianness related
2082         code; moved to set_endianness.
2083
2084 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2085
2086         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2087         * interp.c (CHECKHILO): Define away.
2088         (simSIGINT): New macro.
2089         (membank_size): Increase from 1MB to 2MB.
2090         (control_c): New function.
2091         (sim_resume): Rename parameter signal to signal_number.  Add local
2092         variable prev.  Call signal before and after simulate.
2093         (sim_stop_reason): Add simSIGINT support.
2094         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2095         functions always.
2096         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2097         if logfh is NULL.
2098         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2099         a call to sim_warning.
2100
2101 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2102
2103         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2104         16 bit instructions.
2105
2106 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2107
2108         Add support for mips16 (16 bit MIPS implementation):
2109         * gencode.c (inst_type): Add mips16 instruction encoding types.
2110         (GETDATASIZEINSN): Define.
2111         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2112         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2113         mtlo.
2114         (MIPS16_DECODE): New table, for mips16 instructions.
2115         (bitmap_val): New static function.
2116         (struct mips16_op): Define.
2117         (mips16_op_table): New table, for mips16 operands.
2118         (build_mips16_operands): New static function.
2119         (process_instructions): If PC is odd, decode a mips16
2120         instruction.  Break out instruction handling into new
2121         build_instruction function.
2122         (build_instruction): New static function, broken out of
2123         process_instructions.  Check modifiers rather than flags for SHIFT
2124         bit count and m[ft]{hi,lo} direction.
2125         (usage): Pass program name to fprintf.
2126         (main): Remove unused variable this_option_optind.  Change
2127         ``*loptarg++'' to ``loptarg++''.
2128         (my_strtoul): Parenthesize && within ||.
2129         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2130         (simulate): If PC is odd, fetch a 16 bit instruction, and
2131         increment PC by 2 rather than 4.
2132         * configure.in: Add case for mips16*-*-*.
2133         * configure: Rebuild.
2134
2135 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2136
2137         * interp.c: Allow -t to enable tracing in standalone simulator.
2138         Fix garbage output in trace file and error messages.
2139
2140 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2141
2142         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2143         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2144         * configure.in: Simplify using macros in ../common/aclocal.m4.
2145         * configure: Regenerated.
2146         * tconfig.in: New file.
2147
2148 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2149
2150         * interp.c: Fix bugs in 64-bit port.
2151         Use ansi function declarations for msvc compiler.
2152         Initialize and test file pointer in trace code.
2153         Prevent duplicate definition of LAST_EMED_REGNUM.
2154
2155 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2156
2157         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2158
2159 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2160
2161         * interp.c (SignalException): Check for explicit terminating
2162         breakpoint value.
2163         * gencode.c: Pass instruction value through SignalException()
2164         calls for Trap, Breakpoint and Syscall.
2165
2166 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2167
2168         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2169         only used on those hosts that provide it.
2170         * configure.in: Add sqrt() to list of functions to be checked for.
2171         * config.in: Re-generated.
2172         * configure: Re-generated.
2173
2174 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2175
2176         * gencode.c (process_instructions): Call build_endian_shift when
2177         expanding STORE RIGHT, to fix swr.
2178         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2179         clear the high bits.
2180         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2181         Fix float to int conversions to produce signed values.
2182
2183 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2184
2185         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2186         (process_instructions): Correct handling of nor instruction.
2187         Correct shift count for 32 bit shift instructions. Correct sign
2188         extension for arithmetic shifts to not shift the number of bits in
2189         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2190         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2191         Fix madd.
2192         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2193         It's OK to have a mult follow a mult.  What's not OK is to have a
2194         mult follow an mfhi.
2195         (Convert): Comment out incorrect rounding code.
2196
2197 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2198
2199         * interp.c (sim_monitor): Improved monitor printf
2200         simulation. Tidied up simulator warnings, and added "--log" option
2201         for directing warning message output.
2202         * gencode.c: Use sim_warning() rather than WARNING macro.
2203
2204 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2205
2206         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2207         getopt1.o, rather than on gencode.c.  Link objects together.
2208         Don't link against -liberty.
2209         (gencode.o, getopt.o, getopt1.o): New targets.
2210         * gencode.c: Include <ctype.h> and "ansidecl.h".
2211         (AND): Undefine after including "ansidecl.h".
2212         (ULONG_MAX): Define if not defined.
2213         (OP_*): Don't define macros; now defined in opcode/mips.h.
2214         (main): Call my_strtoul rather than strtoul.
2215         (my_strtoul): New static function.
2216
2217 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2218
2219         * gencode.c (process_instructions):  Generate word64 and uword64
2220         instead of `long long' and `unsigned long long' data types.
2221         * interp.c:  #include sysdep.h to get signals, and define default
2222         for SIGBUS.
2223         * (Convert):  Work around for Visual-C++ compiler bug with type
2224         conversion.
2225         * support.h:  Make things compile under Visual-C++ by using
2226         __int64 instead of `long long'.  Change many refs to long long
2227         into word64/uword64 typedefs.
2228
2229 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2230
2231         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2232         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2233         (docdir): Removed.
2234         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2235         (AC_PROG_INSTALL): Added.
2236         (AC_PROG_CC): Moved to before configure.host call.
2237         * configure: Rebuilt.
2238
2239 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2240
2241         * configure.in: Define @SIMCONF@ depending on mips target.
2242         * configure: Rebuild.
2243         * Makefile.in (run): Add @SIMCONF@ to control simulator
2244         construction.
2245         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2246         * interp.c: Remove some debugging, provide more detailed error
2247         messages, update memory accesses to use LOADDRMASK.
2248
2249 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2250
2251         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2252         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2253         stamp-h.
2254         * configure: Rebuild.
2255         * config.in: New file, generated by autoheader.
2256         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2257         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2258         HAVE_ANINT and HAVE_AINT, as appropriate.
2259         * Makefile.in (run): Use @LIBS@ rather than -lm.
2260         (interp.o): Depend upon config.h.
2261         (Makefile): Just rebuild Makefile.
2262         (clean): Remove stamp-h.
2263         (mostlyclean): Make the same as clean, not as distclean.
2264         (config.h, stamp-h): New targets.
2265
2266 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2267
2268         * interp.c (ColdReset): Fix boolean test. Make all simulator
2269         globals static.
2270
2271 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2272
2273         * interp.c (xfer_direct_word, xfer_direct_long,
2274         swap_direct_word, swap_direct_long, xfer_big_word,
2275         xfer_big_long, xfer_little_word, xfer_little_long,
2276         swap_word,swap_long): Added.
2277         * interp.c (ColdReset): Provide function indirection to
2278         host<->simulated_target transfer routines.
2279         * interp.c (sim_store_register, sim_fetch_register): Updated to
2280         make use of indirected transfer routines.
2281
2282 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2283
2284         * gencode.c (process_instructions): Ensure FP ABS instruction
2285         recognised.
2286         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2287         system call support.
2288
2289 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2290
2291         * interp.c (sim_do_command): Complain if callback structure not
2292         initialised.
2293
2294 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2295
2296         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2297         support for Sun hosts.
2298         * Makefile.in (gencode): Ensure the host compiler and libraries
2299         used for cross-hosted build.
2300
2301 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2302
2303         * interp.c, gencode.c: Some more (TODO) tidying.
2304
2305 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2306
2307         * gencode.c, interp.c: Replaced explicit long long references with
2308         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2309         * support.h (SET64LO, SET64HI): Macros added.
2310
2311 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2312
2313         * configure: Regenerate with autoconf 2.7.
2314
2315 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2316
2317         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2318         * support.h: Remove superfluous "1" from #if.
2319         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2320
2321 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2322
2323         * interp.c (StoreFPR): Control UndefinedResult() call on
2324         WARN_RESULT manifest.
2325
2326 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2327
2328         * gencode.c: Tidied instruction decoding, and added FP instruction
2329         support.
2330
2331         * interp.c: Added dineroIII, and BSD profiling support. Also
2332         run-time FP handling.
2333
2334 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2335
2336         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2337         gencode.c, interp.c, support.h: created.