sim/mips/ChangeLog

   1 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
   2             Ed Satterthwaite  <ehs@broadcom.com>
   3
   4         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
   5         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
   6         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
   7         (convert): Note that this function is not used for paired-single
   8         format conversions.
   9         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
  10         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
  11         (check_fmt_p): Enable paired-single support.
  12         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
  13         (PUU.PS): New instructions.
  14         (CVT.S.fmt): Don't use this instruction for paired-single format
  15         destinations.
  16         * sim-main.h (FP_formats): New value 'fmt_ps.'
  17         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
  18         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
  19
  20 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
  21
  22         * mips.igen: Fix formatting of function calls in
  23         many FP operations.
  24
  25 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
  26
  27         * mips.igen (MOVN, MOVZ): Trace result.
  28         (TNEI): Print "tnei" as the opcode name in traces.
  29         (CEIL.W): Add disassembly string for traces.
  30         (RSQRT.fmt): Make location of disassembly string consistent
  31         with other instructions.
  32
  33 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
  34
  35         * mips.igen (X): Delete unused function.
  36
  37 2002-06-08  Andrew Cagney  <cagney@redhat.com>
  38
  39         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
  40
  41 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  42             Ed Satterthwaite  <ehs@broadcom.com>
  43
  44         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
  45         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
  46         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
  47         (fp_nmsub): New prototypes.
  48         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
  49         (NegMultiplySub): New defines.
  50         * mips.igen (RSQRT.fmt): Use RSquareRoot().
  51         (MADD.D, MADD.S): Replace with...
  52         (MADD.fmt): New instruction.
  53         (MSUB.D, MSUB.S): Replace with...
  54         (MSUB.fmt): New instruction.
  55         (NMADD.D, NMADD.S): Replace with...
  56         (NMADD.fmt): New instruction.
  57         (NMSUB.D, MSUB.S): Replace with...
  58         (NMSUB.fmt): New instruction.
  59
  60 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  61             Ed Satterthwaite  <ehs@broadcom.com>
  62
  63         * cp1.c: Fix more comment spelling and formatting.
  64         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
  65         (denorm_mode): New function.
  66         (fpu_unary, fpu_binary): Round results after operation, collect
  67         status from rounding operations, and update the FCSR.
  68         (convert): Collect status from integer conversions and rounding
  69         operations, and update the FCSR.  Adjust NaN values that result
  70         from conversions.  Convert to use sim_io_eprintf rather than
  71         fprintf, and remove some debugging code.
  72         * cp1.h (fenr_FS): New define.
  73
  74 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  75
  76         * cp1.c (convert): Remove unusable debugging code, and move MIPS
  77         rounding mode to sim FP rounding mode flag conversion code into...
  78         (rounding_mode): New function.
  79
  80 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  81
  82         * cp1.c: Clean up formatting of a few comments.
  83         (value_fpr): Reformat switch statement.
  84
  85 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
  86             Ed Satterthwaite  <ehs@broadcom.com>
  87
  88         * cp1.h: New file.
  89         * sim-main.h: Include cp1.h.
  90         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
  91         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
  92         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
  93         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
  94         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
  95         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
  96         * cp1.c: Don't include sim-fpu.h; already included by
  97         sim-main.h.  Clean up formatting of some comments.
  98         (NaN, Equal, Less): Remove.
  99         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 100         (fp_cmp): New functions.
 101         * mips.igen (do_c_cond_fmt): Remove.
 102         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 103         Compare.  Add result tracing.
 104         (CxC1): Remove, replace with...
 105         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 106         (DMxC1): Remove, replace with...
 107         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 108         (MxC1): Remove, replace with...
 109         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 110
 111 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 112
 113         * sim-main.h (FGRIDX): Remove, replace all uses with...
 114         (FGR_BASE): New macro.
 115         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 116         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 117         (NR_FGR, FGR): Likewise.
 118         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 119         * mips.igen: Likewise.
 120
 121 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 122
 123         * cp1.c: Add an FSF Copyright notice to this file.
 124
 125 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 126             Ed Satterthwaite  <ehs@broadcom.com>
 127
 128         * cp1.c (Infinity): Remove.
 129         * sim-main.h (Infinity): Likewise.
 130
 131         * cp1.c (fp_unary, fp_binary): New functions.
 132         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 133         (fp_sqrt): New functions, implemented in terms of the above.
 134         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 135         (Recip, SquareRoot): Remove (replaced by functions above).
 136         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 137         (fp_recip, fp_sqrt): New prototypes.
 138         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 139         (Recip, SquareRoot): Replace prototypes with #defines which
 140         invoke the functions above.
 141
 142 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 143
 144         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 145         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 146         file, remove PARAMS from prototypes.
 147         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 148         simulator state arguments.
 149         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 150         pass simulator state arguments.
 151         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 152         (store_fpr, convert): Remove 'sd' argument.
 153         (value_fpr): Likewise.  Convert to use 'SD' instead.
 154
 155 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 156
 157         * cp1.c (Min, Max): Remove #if 0'd functions.
 158         * sim-main.h (Min, Max): Remove.
 159
 160 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 161
 162         * cp1.c: fix formatting of switch case and default labels.
 163         * interp.c: Likewise.
 164         * sim-main.c: Likewise.
 165
 166 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 167
 168         * cp1.c: Clean up comments which describe FP formats.
 169          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 170
 171 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 172             Ed Satterthwaite  <ehs@broadcom.com>
 173
 174         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 175         Broadcom SiByte SB-1 processor configurations.
 176         * configure: Regenerate.
 177         * sb1.igen: New file.
 178         * mips.igen: Include sb1.igen.
 179         (sb1): New model.
 180         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 181         * mdmx.igen: Add "sb1" model to all appropriate functions and
 182         instructions.
 183         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 184         (ob_func, ob_acc): Reference the above.
 185         (qh_acc): Adjust to keep the same size as ob_acc.
 186         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 187         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 188
 189 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 190
 191         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 192
 193 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 194             Ed Satterthwaite  <ehs@broadcom.com>
 195
 196         * mips.igen (mdmx): New (pseudo-)model.
 197         * mdmx.c, mdmx.igen: New files.
 198         * Makefile.in (SIM_OBJS): Add mdmx.o.
 199         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 200         New typedefs.
 201         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 202         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 203         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 204         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 205         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 206         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 207         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 208         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 209         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 210         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 211         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 212         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 213         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 214         (qh_fmtsel): New macros.
 215         (_sim_cpu): New member "acc".
 216         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 217         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 218
 219 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 220
 221         * interp.c: Use 'deprecated' rather than 'depreciated.'
 222         * sim-main.h: Likewise.
 223
 224 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 225
 226         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 227         which wouldn't compile anyway.
 228         * sim-main.h (unpredictable_action): New function prototype.
 229         (Unpredictable): Define to call igen function unpredictable().
 230         (NotWordValue): New macro to call igen function not_word_value().
 231         (UndefinedResult): Remove.
 232         * interp.c (undefined_result): Remove.
 233         (unpredictable_action): New function.
 234         * mips.igen (not_word_value, unpredictable): New functions.
 235         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 236         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 237         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 238         NotWordValue() to check for unpredictable inputs, then
 239         Unpredictable() to handle them.
 240
 241 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 242
 243         * mips.igen: Fix formatting of calls to Unpredictable().
 244
 245 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 246
 247         * interp.c (sim_open): Revert previous change.
 248
 249 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 250
 251         * interp.c (sim_open): Disable chunk of code that wrote code in
 252         vector table entries.
 253
 254 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 255
 256         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 257         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 258         unused definitions.
 259
 260 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 261
 262         * cp1.c: Fix many formatting issues.
 263
 264 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 265
 266         * cp1.c (fpu_format_name): New function to replace...
 267         (DOFMT): This.  Delete, and update all callers.
 268         (fpu_rounding_mode_name): New function to replace...
 269         (RMMODE): This.  Delete, and update all callers.
 270
 271 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 272
 273         * interp.c: Move FPU support routines from here to...
 274         * cp1.c: Here.  New file.
 275         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 276         (cp1.o): New target.
 277
 278 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 279
 280         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 281         * mips.igen (mips32, mips64): New models, add to all instructions
 282         and functions as appropriate.
 283         (loadstore_ea, check_u64): New variant for model mips64.
 284         (check_fmt_p): New variant for models mipsV and mips64, remove
 285         mipsV model marking fro other variant.
 286         (SLL) Rename to...
 287         (SLLa) this.
 288         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 289         for mips32 and mips64.
 290         (DCLO, DCLZ): New instructions for mips64.
 291
 292 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 293
 294         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 295         immediate or code as a hex value with the "%#lx" format.
 296         (ANDI): Likewise, and fix printed instruction name.
 297
 298 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 299
 300         * sim-main.h (UndefinedResult, Unpredictable): New macros
 301         which currently do nothing.
 302
 303 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 304
 305         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 306         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 307         (status_CU3): New definitions.
 308
 309         * sim-main.h (ExceptionCause): Add new values for MIPS32
 310         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 311         for DebugBreakPoint and NMIReset to note their status in
 312         MIPS32 and MIPS64.
 313         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 314         (SignalExceptionCacheErr): New exception macros.
 315
 316 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 317
 318         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 319         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 320         is always enabled.
 321         (SignalExceptionCoProcessorUnusable): Take as argument the
 322         unusable coprocessor number.
 323
 324 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 325
 326         * mips.igen: Fix formatting of all SignalException calls.
 327
 328 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 329
 330         * sim-main.h (SIGNEXTEND): Remove.
 331
 332 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 333
 334         * mips.igen: Remove gencode comment from top of file, fix
 335         spelling in another comment.
 336
 337 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 338
 339         * mips.igen (check_fmt, check_fmt_p): New functions to check
 340         whether specific floating point formats are usable.
 341         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 342         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 343         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 344         Use the new functions.
 345         (do_c_cond_fmt): Remove format checks...
 346         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 347
 348 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 349
 350         * mips.igen: Fix formatting of check_fpu calls.
 351
 352 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 353
 354         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 355
 356 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 357
 358         * mips.igen: Remove whitespace at end of lines.
 359
 360 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 361
 362         * mips.igen (loadstore_ea): New function to do effective
 363         address calculations.
 364         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 365         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 366         CACHE): Use loadstore_ea to do effective address computations.
 367
 368 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 369
 370         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 371         * mips.igen (LL, CxC1, MxC1): Likewise.
 372
 373 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 374
 375         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 376         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 377         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 378         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 379         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 380         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 381         Don't split opcode fields by hand, use the opcode field values
 382         provided by igen.
 383
 384 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 385
 386         * mips.igen (do_divu): Fix spacing.
 387
 388         * mips.igen (do_dsllv): Move to be right before DSLLV,
 389         to match the rest of the do_<shift> functions.
 390
 391 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 392
 393         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 394         DSRL32, do_dsrlv): Trace inputs and results.
 395
 396 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 397
 398         * mips.igen (CACHE): Provide instruction-printing string.
 399
 400         * interp.c (signal_exception): Comment tokens after #endif.
 401
 402 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 403
 404         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 405         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 406         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 407         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 408         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 409         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 410         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 411         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 412
 413 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 414
 415         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 416         instruction-printing string.
 417         (LWU): Use '64' as the filter flag.
 418
 419 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 420
 421         * mips.igen (SDXC1): Fix instruction-printing string.
 422
 423 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 424
 425         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 426         filter flags "32,f".
 427
 428 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 429
 430         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 431         as the filter flag.
 432
 433 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 434
 435         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 436         add a comma) so that it more closely match the MIPS ISA
 437         documentation opcode partitioning.
 438         (PREF): Put useful names on opcode fields, and include
 439         instruction-printing string.
 440
 441 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 442
 443         * mips.igen (check_u64): New function which in the future will
 444         check whether 64-bit instructions are usable and signal an
 445         exception if not.  Currently a no-op.
 446         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 447         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 448         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 449         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 450
 451         * mips.igen (check_fpu): New function which in the future will
 452         check whether FPU instructions are usable and signal an exception
 453         if not.  Currently a no-op.
 454         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 455         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 456         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 457         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 458         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 459         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 460         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 461         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 462
 463 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 464
 465         * mips.igen (do_load_left, do_load_right): Move to be immediately
 466         following do_load.
 467         (do_store_left, do_store_right): Move to be immediately following
 468         do_store.
 469
 470 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 471
 472         * mips.igen (mipsV): New model name.  Also, add it to
 473         all instructions and functions where it is appropriate.
 474
 475 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 476
 477         * mips.igen: For all functions and instructions, list model
 478         names that support that instruction one per line.
 479
 480 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 481
 482         * mips.igen: Add some additional comments about supported
 483         models, and about which instructions go where.
 484         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 485         order as is used in the rest of the file.
 486
 487 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 488
 489         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 490         indicating that ALU32_END or ALU64_END are there to check
 491         for overflow.
 492         (DADD): Likewise, but also remove previous comment about
 493         overflow checking.
 494
 495 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 496
 497         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 498         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 499         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 500         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 501         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 502         fields (i.e., add and move commas) so that they more closely
 503         match the MIPS ISA documentation opcode partitioning.
 504
 505 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 506
 507         * mips.igen (ADDI): Print immediate value.
 508         (BREAK): Print code.
 509         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 510         (SLL): Print "nop" specially, and don't run the code
 511         that does the shift for the "nop" case.
 512
 513 2001-11-17  Fred Fish  <fnf@redhat.com>
 514
 515         * sim-main.h (float_operation): Move enum declaration outside
 516         of _sim_cpu struct declaration.
 517
 518 2001-04-12  Jim Blandy  <jimb@redhat.com>
 519
 520         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 521         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 522         set of the FCSR.
 523         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 524         PENDING_FILL, and you can get the intended effect gracefully by
 525         calling PENDING_SCHED directly.
 526
 527 2001-02-23  Ben Elliston  <bje@redhat.com>
 528
 529         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 530         already defined elsewhere.
 531
 532 2001-02-19  Ben Elliston  <bje@redhat.com>
 533
 534         * sim-main.h (sim_monitor): Return an int.
 535         * interp.c (sim_monitor): Add return values.
 536         (signal_exception): Handle error conditions from sim_monitor.
 537
 538 2001-02-08  Ben Elliston  <bje@redhat.com>
 539
 540         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 541         (store_memory): Likewise, pass cia to sim_core_write*.
 542
 543 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 544
 545         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 546         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 547
 548 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 549
 550         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 551         * Makefile.in: Don't delete *.igen when cleaning directory.
 552
 553 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 554
 555         * m16.igen (break): Call SignalException not sim_engine_halt.
 556
 557 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 558
 559         From Jason Eckhardt:
 560         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 561
 562 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 563
 564         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 565
 566 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 567
 568         * mips.igen (do_dmultx): Fix typo.
 569
 570 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 571
 572         * configure: Regenerated to track ../common/aclocal.m4 changes.
 573
 574 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 575
 576         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 577
 578 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 579
 580         * sim-main.h (GPR_CLEAR): Define macro.
 581
 582 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 583
 584         * interp.c (decode_coproc): Output long using %lx and not %s.
 585
 586 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 587
 588         * interp.c (sim_open): Sort & extend dummy memory regions for
 589         --board=jmr3904 for eCos.
 590
 591 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 592
 593         * configure: Regenerated.
 594
 595 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 596
 597         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 598         calls, conditional on the simulator being in verbose mode.
 599
 600 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 601
 602         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 603         cache don't get ReservedInstruction traps.
 604
 605 1999-11-29  Mark Salter  <msalter@cygnus.com>
 606
 607         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 608         to clear status bits in sdisr register. This is how the hardware works.
 609
 610         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 611         being used by cygmon.
 612
 613 1999-11-11  Andrew Haley  <aph@cygnus.com>
 614
 615         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 616         instructions.
 617
 618 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 619
 620         * mips.igen (MULT): Correct previous mis-applied patch.
 621
 622 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 623
 624         * mips.igen (delayslot32): Handle sequence like
 625         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 626         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 627         (MULT): Actually pass the third register...
 628
 629 1999-09-03  Mark Salter  <msalter@cygnus.com>
 630
 631         * interp.c (sim_open): Added more memory aliases for additional
 632         hardware being touched by cygmon on jmr3904 board.
 633
 634 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 635
 636         * configure: Regenerated to track ../common/aclocal.m4 changes.
 637
 638 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 639
 640         * interp.c (sim_store_register): Handle case where client - GDB -
 641         specifies that a 4 byte register is 8 bytes in size.
 642         (sim_fetch_register): Ditto.
 643
 644 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 645
 646         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 647         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 648         (idt_monitor_base): Base address for IDT monitor traps.
 649         (pmon_monitor_base): Ditto for PMON.
 650         (lsipmon_monitor_base): Ditto for LSI PMON.
 651         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 652         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 653         (sim_firmware_command): New function.
 654         (mips_option_handler): Call it for OPTION_FIRMWARE.
 655         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 656         option was given, add no monitor by default.  Add BREAK hooks only if
 657         monitors are also there.
 658
 659 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 660
 661         * interp.c (sim_monitor): Flush output before reading input.
 662
 663 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 664
 665         * tconfig.in (SIM_HANDLES_LMA): Always define.
 666
 667 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 668
 669         From Mark Salter <msalter@cygnus.com>:
 670         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 671         (sim_open): Add setup for BSP board.
 672
 673 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 674
 675         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 676         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 677         them as unimplemented.
 678
 679 1999-05-08  Felix Lee  <flee@cygnus.com>
 680
 681         * configure: Regenerated to track ../common/aclocal.m4 changes.
 682
 683 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 684
 685         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 686
 687 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 688
 689         * configure.in: Any mips64vr5*-*-* target should have
 690         -DTARGET_ENABLE_FR=1.
 691         (default_endian): Any mips64vr*el-*-* target should default to
 692         LITTLE_ENDIAN.
 693         * configure: Re-generate.
 694
 695 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 696
 697         * mips.igen (ldl): Extend from _16_, not 32.
 698
 699 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 700
 701         * interp.c (sim_store_register): Force registers written to by GDB
 702         into an un-interpreted state.
 703
 704 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 705
 706         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 707         CPU, start periodic background I/O polls.
 708         (tx3904sio_poll): New function: periodic I/O poller.
 709
 710 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 711
 712         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 713
 714 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 715
 716         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 717         case statement.
 718
 719 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 720
 721         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 722         (load_word): Call SIM_CORE_SIGNAL hook on error.
 723         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 724         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 725         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 726         * sim-main.h (COP0_BADVADDR): Define.
 727         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 728         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 729         (_sim_cpu): Add exc_* fields to store register value snapshots.
 730         * mips.igen (*): Replace memory-related SignalException* calls
 731         with references to SIM_CORE_SIGNAL hook.
 732
 733         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 734         fix.
 735         * sim-main.c (*): Minor warning cleanups.
 736
 737 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 738
 739         * m16.igen (DADDIU5): Correct type-o.
 740
 741 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 742
 743         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 744         variables.
 745
 746 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 747
 748         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 749         to include path.
 750         (interp.o): Add dependency on itable.h
 751         (oengine.c, gencode): Delete remaining references.
 752         (BUILT_SRC_FROM_GEN): Clean up.
 753
 754 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 755
 756         * vr4run.c: New.
 757         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 758         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 759         tmp-run-hack) : New.
 760         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 761         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 762         Drop the "64" qualifier to get the HACK generator working.
 763         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 764         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 765         qualifier to get the hack generator working.
 766         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 767         (DSLL): Use do_dsll.
 768         (DSLLV): Use do_dsllv.
 769         (DSRA): Use do_dsra.
 770         (DSRL): Use do_dsrl.
 771         (DSRLV): Use do_dsrlv.
 772         (BC1): Move *vr4100 to get the HACK generator working.
 773         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 774         get the HACK generator working.
 775         (MACC) Rename to get the HACK generator working.
 776         (DMACC,MACCS,DMACCS): Add the 64.
 777
 778 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 779
 780         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 781         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 782
 783 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 784
 785     * mips/interp.c (DEBUG): Cleanups.
 786
 787 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 788
 789         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 790         (tx3904sio_tickle): fflush after a stdout character output.
 791
 792 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 793
 794         * interp.c (sim_close): Uninstall modules.
 795
 796 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 797
 798         * sim-main.h, interp.c (sim_monitor): Change to global
 799         function.
 800
 801 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 802
 803         * configure.in (vr4100): Only include vr4100 instructions in
 804         simulator.
 805         * configure: Re-generate.
 806         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 807
 808 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 809
 810         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 811         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 812         true alternative.
 813
 814         * configure.in (sim_default_gen, sim_use_gen): Replace with
 815         sim_gen.
 816         (--enable-sim-igen): Delete config option. Always using IGEN.
 817         * configure: Re-generate.
 818
 819         * Makefile.in (gencode): Kill, kill, kill.
 820         * gencode.c: Ditto.
 821
 822 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 823
 824         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 825         bit mips16 igen simulator.
 826         * configure: Re-generate.
 827
 828         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 829         as part of vr4100 ISA.
 830         * vr.igen: Mark all instructions as 64 bit only.
 831
 832 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 833
 834         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 835         Pacify GCC.
 836
 837 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 838
 839         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 840         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 841         * configure: Re-generate.
 842
 843         * m16.igen (BREAK): Define breakpoint instruction.
 844         (JALX32): Mark instruction as mips16 and not r3900.
 845         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 846
 847         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 848
 849 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 850
 851         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 852         insn as a debug breakpoint.
 853
 854         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 855         pending.slot_size.
 856         (PENDING_SCHED): Clean up trace statement.
 857         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 858         (PENDING_FILL): Delay write by only one cycle.
 859         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 860
 861         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 862         of pending writes.
 863         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 864         32 & 64.
 865         (pending_tick): Move incrementing of index to FOR statement.
 866         (pending_tick): Only update PENDING_OUT after a write has occured.
 867
 868         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 869         build simulator.
 870         * configure: Re-generate.
 871
 872         * interp.c (sim_engine_run OLD): Delete explicit call to
 873         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 874
 875 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 876
 877         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 878         interrupt level number to match changed SignalExceptionInterrupt
 879         macro.
 880
 881 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 882
 883         * interp.c: #include "itable.h" if WITH_IGEN.
 884         (get_insn_name): New function.
 885         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 886         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 887
 888 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 889
 890         * configure: Rebuilt to inhale new common/aclocal.m4.
 891
 892 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 893
 894         * dv-tx3904sio.c: Include sim-assert.h.
 895
 896 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 897
 898         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 899         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 900         Reorganize target-specific sim-hardware checks.
 901         * configure: rebuilt.
 902         * interp.c (sim_open): For tx39 target boards, set
 903         OPERATING_ENVIRONMENT, add tx3904sio devices.
 904         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 905         ROM executables.  Install dv-sockser into sim-modules list.
 906
 907         * dv-tx3904irc.c: Compiler warning clean-up.
 908         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 909         frequent hw-trace messages.
 910
 911 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 912
 913         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 914
 915 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 916
 917         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 918
 919         * vr.igen: New file.
 920         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 921         * mips.igen: Define vr4100 model. Include vr.igen.
 922 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 923
 924         * mips.igen (check_mf_hilo): Correct check.
 925
 926 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 927
 928         * sim-main.h (interrupt_event): Add prototype.
 929
 930         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 931         register_ptr, register_value.
 932         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 933
 934         * sim-main.h (tracefh): Make extern.
 935
 936 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 937
 938         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 939         Reduce unnecessarily high timer event frequency.
 940         * dv-tx3904cpu.c: Ditto for interrupt event.
 941
 942 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 943
 944         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 945         to allay warnings.
 946         (interrupt_event): Made non-static.
 947
 948         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 949         interchange of configuration values for external vs. internal
 950         clock dividers.
 951
 952 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 953
 954         * mips.igen (BREAK): Moved code to here for
 955         simulator-reserved break instructions.
 956         * gencode.c (build_instruction): Ditto.
 957         * interp.c (signal_exception): Code moved from here.  Non-
 958         reserved instructions now use exception vector, rather
 959         than halting sim.
 960         * sim-main.h: Moved magic constants to here.
 961
 962 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 963
 964         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 965         register upon non-zero interrupt event level, clear upon zero
 966         event value.
 967         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 968         by passing zero event value.
 969         (*_io_{read,write}_buffer): Endianness fixes.
 970         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 971         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 972
 973         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 974         serial I/O and timer module at base address 0xFFFF0000.
 975
 976 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 977
 978         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 979         and BigEndianCPU.
 980
 981 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 982
 983         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 984         parts.
 985         * configure: Update.
 986
 987 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 988
 989         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 990         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 991         * configure.in: Include tx3904tmr in hw_device list.
 992         * configure: Rebuilt.
 993         * interp.c (sim_open): Instantiate three timer instances.
 994         Fix address typo of tx3904irc instance.
 995
 996 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 997
 998         * interp.c (signal_exception): SystemCall exception now uses
 999         the exception vector.
1000
1001 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1002
1003         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1004         to allay warnings.
1005
1006 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1007
1008         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1009
1010 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1011
1012         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1013
1014         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1015         sim-main.h. Declare a struct hw_descriptor instead of struct
1016         hw_device_descriptor.
1017
1018 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1019
1020         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1021         right bits and then re-align left hand bytes to correct byte
1022         lanes.  Fix incorrect computation in do_store_left when loading
1023         bytes from second word.
1024
1025 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1026
1027         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1028         * interp.c (sim_open): Only create a device tree when HW is
1029         enabled.
1030
1031         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1032         * interp.c (signal_exception): Ditto.
1033
1034 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1035
1036         * gencode.c: Mark BEGEZALL as LIKELY.
1037
1038 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1039
1040         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1041         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1042
1043 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1044
1045         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1046         modules.  Recognize TX39 target with "mips*tx39" pattern.
1047         * configure: Rebuilt.
1048         * sim-main.h (*): Added many macros defining bits in
1049         TX39 control registers.
1050         (SignalInterrupt): Send actual PC instead of NULL.
1051         (SignalNMIReset): New exception type.
1052         * interp.c (board): New variable for future use to identify
1053         a particular board being simulated.
1054         (mips_option_handler,mips_options): Added "--board" option.
1055         (interrupt_event): Send actual PC.
1056         (sim_open): Make memory layout conditional on board setting.
1057         (signal_exception): Initial implementation of hardware interrupt
1058         handling.  Accept another break instruction variant for simulator
1059         exit.
1060         (decode_coproc): Implement RFE instruction for TX39.
1061         (mips.igen): Decode RFE instruction as such.
1062         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1063         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1064         bbegin to implement memory map.
1065         * dv-tx3904cpu.c: New file.
1066         * dv-tx3904irc.c: New file.
1067
1068 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1069
1070         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1071
1072 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1073
1074         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1075         with calls to check_div_hilo.
1076
1077 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1078
1079         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1080         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1081         Add special r3900 version of do_mult_hilo.
1082         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1083         with calls to check_mult_hilo.
1084         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1085         with calls to check_div_hilo.
1086
1087 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1088
1089         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1090         Document a replacement.
1091
1092 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1093
1094         * interp.c (sim_monitor): Make mon_printf work.
1095
1096 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1097
1098         * sim-main.h (INSN_NAME): New arg `cpu'.
1099
1100 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1101
1102         * configure: Regenerated to track ../common/aclocal.m4 changes.
1103
1104 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1105
1106         * configure: Regenerated to track ../common/aclocal.m4 changes.
1107         * config.in: Ditto.
1108
1109 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1110
1111         * acconfig.h: New file.
1112         * configure.in: Reverted change of Apr 24; use sinclude again.
1113
1114 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1115
1116         * configure: Regenerated to track ../common/aclocal.m4 changes.
1117         * config.in: Ditto.
1118
1119 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1120
1121         * configure.in: Don't call sinclude.
1122
1123 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1124
1125         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1126
1127 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1128
1129         * mips.igen (ERET): Implement.
1130
1131         * interp.c (decode_coproc): Return sign-extended EPC.
1132
1133         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1134
1135         * interp.c (signal_exception): Do not ignore Trap.
1136         (signal_exception): On TRAP, restart at exception address.
1137         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1138         (signal_exception): Update.
1139         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1140         so that TRAP instructions are caught.
1141
1142 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1143
1144         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1145         contains HI/LO access history.
1146         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1147         (HIACCESS, LOACCESS): Delete, replace with
1148         (HIHISTORY, LOHISTORY): New macros.
1149         (CHECKHILO): Delete all, moved to mips.igen
1150
1151         * gencode.c (build_instruction): Do not generate checks for
1152         correct HI/LO register usage.
1153
1154         * interp.c (old_engine_run): Delete checks for correct HI/LO
1155         register usage.
1156
1157         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1158         check_mf_cycles): New functions.
1159         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1160         do_divu, domultx, do_mult, do_multu): Use.
1161
1162         * tx.igen ("madd", "maddu"): Use.
1163
1164 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1165
1166         * mips.igen (DSRAV): Use function do_dsrav.
1167         (SRAV): Use new function do_srav.
1168
1169         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1170         (B): Sign extend 11 bit immediate.
1171         (EXT-B*): Shift 16 bit immediate left by 1.
1172         (ADDIU*): Don't sign extend immediate value.
1173
1174 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1175
1176         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1177
1178         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1179         functions.
1180
1181         * mips.igen (delayslot32, nullify_next_insn): New functions.
1182         (m16.igen): Always include.
1183         (do_*): Add more tracing.
1184
1185         * m16.igen (delayslot16): Add NIA argument, could be called by a
1186         32 bit MIPS16 instruction.
1187
1188         * interp.c (ifetch16): Move function from here.
1189         * sim-main.c (ifetch16): To here.
1190
1191         * sim-main.c (ifetch16, ifetch32): Update to match current
1192         implementations of LH, LW.
1193         (signal_exception): Don't print out incorrect hex value of illegal
1194         instruction.
1195
1196 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1197
1198         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1199         instruction.
1200
1201         * m16.igen: Implement MIPS16 instructions.
1202
1203         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1204         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1205         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1206         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1207         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1208         bodies of corresponding code from 32 bit insn to these.  Also used
1209         by MIPS16 versions of functions.
1210
1211         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1212         (IMEM16): Drop NR argument from macro.
1213
1214 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1215
1216         * Makefile.in (SIM_OBJS): Add sim-main.o.
1217
1218         * sim-main.h (address_translation, load_memory, store_memory,
1219         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1220         as INLINE_SIM_MAIN.
1221         (pr_addr, pr_uword64): Declare.
1222         (sim-main.c): Include when H_REVEALS_MODULE_P.
1223
1224         * interp.c (address_translation, load_memory, store_memory,
1225         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1226         from here.
1227         * sim-main.c: To here. Fix compilation problems.
1228
1229         * configure.in: Enable inlining.
1230         * configure: Re-config.
1231
1232 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1233
1234         * configure: Regenerated to track ../common/aclocal.m4 changes.
1235
1236 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1237
1238         * mips.igen: Include tx.igen.
1239         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1240         * tx.igen: New file, contains MADD and MADDU.
1241
1242         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1243         the hardwired constant `7'.
1244         (store_memory): Ditto.
1245         (LOADDRMASK): Move definition to sim-main.h.
1246
1247         mips.igen (MTC0): Enable for r3900.
1248         (ADDU): Add trace.
1249
1250         mips.igen (do_load_byte): Delete.
1251         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1252         do_store_right): New functions.
1253         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1254
1255         configure.in: Let the tx39 use igen again.
1256         configure: Update.
1257
1258 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1259
1260         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1261         not an address sized quantity.  Return zero for cache sizes.
1262
1263 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1264
1265         * mips.igen (r3900): r3900 does not support 64 bit integer
1266         operations.
1267
1268 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1269
1270         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1271         than igen one.
1272         * configure : Rebuild.
1273
1274 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1275
1276         * configure: Regenerated to track ../common/aclocal.m4 changes.
1277
1278 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1279
1280         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1281
1282 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1283
1284         * configure: Regenerated to track ../common/aclocal.m4 changes.
1285         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1286
1287 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1288
1289         * configure: Regenerated to track ../common/aclocal.m4 changes.
1290
1291 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1292
1293         * interp.c (Max, Min): Comment out functions. Not yet used.
1294
1295 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1296
1297         * configure: Regenerated to track ../common/aclocal.m4 changes.
1298
1299 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1300
1301         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1302         configurable settings for stand-alone simulator.
1303
1304         * configure.in: Added X11 search, just in case.
1305
1306         * configure: Regenerated.
1307
1308 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1309
1310         * interp.c (sim_write, sim_read, load_memory, store_memory):
1311         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1312
1313 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1314
1315         * sim-main.h (GETFCC): Return an unsigned value.
1316
1317 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1318
1319         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1320         (DADD): Result destination is RD not RT.
1321
1322 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1323
1324         * sim-main.h (HIACCESS, LOACCESS): Always define.
1325
1326         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1327
1328         * interp.c (sim_info): Delete.
1329
1330 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1331
1332         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1333         (mips_option_handler): New argument `cpu'.
1334         (sim_open): Update call to sim_add_option_table.
1335
1336 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1337
1338         * mips.igen (CxC1): Add tracing.
1339
1340 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1341
1342         * sim-main.h (Max, Min): Declare.
1343
1344         * interp.c (Max, Min): New functions.
1345
1346         * mips.igen (BC1): Add tracing.
1347
1348 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1349
1350         * interp.c Added memory map for stack in vr4100
1351
1352 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1353
1354         * interp.c (load_memory): Add missing "break"'s.
1355
1356 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1357
1358         * interp.c (sim_store_register, sim_fetch_register): Pass in
1359         length parameter.  Return -1.
1360
1361 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1362
1363         * interp.c: Added hardware init hook, fixed warnings.
1364
1365 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1366
1367         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1368
1369 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1370
1371         * interp.c (ifetch16): New function.
1372
1373         * sim-main.h (IMEM32): Rename IMEM.
1374         (IMEM16_IMMED): Define.
1375         (IMEM16): Define.
1376         (DELAY_SLOT): Update.
1377
1378         * m16run.c (sim_engine_run): New file.
1379
1380         * m16.igen: All instructions except LB.
1381         (LB): Call do_load_byte.
1382         * mips.igen (do_load_byte): New function.
1383         (LB): Call do_load_byte.
1384
1385         * mips.igen: Move spec for insn bit size and high bit from here.
1386         * Makefile.in (tmp-igen, tmp-m16): To here.
1387
1388         * m16.dc: New file, decode mips16 instructions.
1389
1390         * Makefile.in (SIM_NO_ALL): Define.
1391         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1392
1393 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1394
1395         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1396         point unit to 32 bit registers.
1397         * configure: Re-generate.
1398
1399 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1400
1401         * configure.in (sim_use_gen): Make IGEN the default simulator
1402         generator for generic 32 and 64 bit mips targets.
1403         * configure: Re-generate.
1404
1405 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1406
1407         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1408         bitsize.
1409
1410         * interp.c (sim_fetch_register, sim_store_register): Read/write
1411         FGR from correct location.
1412         (sim_open): Set size of FGR's according to
1413         WITH_TARGET_FLOATING_POINT_BITSIZE.
1414
1415         * sim-main.h (FGR): Store floating point registers in a separate
1416         array.
1417
1418 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1419
1420         * configure: Regenerated to track ../common/aclocal.m4 changes.
1421
1422 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1423
1424         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1425
1426         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1427
1428         * interp.c (pending_tick): New function.  Deliver pending writes.
1429
1430         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1431         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1432         it can handle mixed sized quantites and single bits.
1433
1434 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1435
1436         * interp.c (oengine.h): Do not include when building with IGEN.
1437         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1438         (sim_info): Ditto for PROCESSOR_64BIT.
1439         (sim_monitor): Replace ut_reg with unsigned_word.
1440         (*): Ditto for t_reg.
1441         (LOADDRMASK): Define.
1442         (sim_open): Remove defunct check that host FP is IEEE compliant,
1443         using software to emulate floating point.
1444         (value_fpr, ...): Always compile, was conditional on HASFPU.
1445
1446 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1447
1448         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1449         size.
1450
1451         * interp.c (SD, CPU): Define.
1452         (mips_option_handler): Set flags in each CPU.
1453         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1454         (sim_close): Do not clear STATE, deleted anyway.
1455         (sim_write, sim_read): Assume CPU zero's vm should be used for
1456         data transfers.
1457         (sim_create_inferior): Set the PC for all processors.
1458         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1459         argument.
1460         (mips16_entry): Pass correct nr of args to store_word, load_word.
1461         (ColdReset): Cold reset all cpu's.
1462         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1463         (sim_monitor, load_memory, store_memory, signal_exception): Use
1464         `CPU' instead of STATE_CPU.
1465
1466
1467         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1468         SD or CPU_.
1469
1470         * sim-main.h (signal_exception): Add sim_cpu arg.
1471         (SignalException*): Pass both SD and CPU to signal_exception.
1472         * interp.c (signal_exception): Update.
1473
1474         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1475         Ditto
1476         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1477         address_translation): Ditto
1478         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1479
1480 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1481
1482         * configure: Regenerated to track ../common/aclocal.m4 changes.
1483
1484 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1485
1486         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1487
1488         * mips.igen (model): Map processor names onto BFD name.
1489
1490         * sim-main.h (CPU_CIA): Delete.
1491         (SET_CIA, GET_CIA): Define
1492
1493 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1494
1495         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1496         regiser.
1497
1498         * configure.in (default_endian): Configure a big-endian simulator
1499         by default.
1500         * configure: Re-generate.
1501
1502 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1503
1504         * configure: Regenerated to track ../common/aclocal.m4 changes.
1505
1506 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1507
1508         * interp.c (sim_monitor): Handle Densan monitor outbyte
1509         and inbyte functions.
1510
1511 1997-12-29  Felix Lee  <flee@cygnus.com>
1512
1513         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1514
1515 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1516
1517         * Makefile.in (tmp-igen): Arrange for $zero to always be
1518         reset to zero after every instruction.
1519
1520 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1521
1522         * configure: Regenerated to track ../common/aclocal.m4 changes.
1523         * config.in: Ditto.
1524
1525 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1526
1527         * mips.igen (MSUB): Fix to work like MADD.
1528         * gencode.c (MSUB): Similarly.
1529
1530 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1531
1532         * configure: Regenerated to track ../common/aclocal.m4 changes.
1533
1534 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1535
1536         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1537
1538 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1539
1540         * sim-main.h (sim-fpu.h): Include.
1541
1542         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1543         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1544         using host independant sim_fpu module.
1545
1546 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1547
1548         * interp.c (signal_exception): Report internal errors with SIGABRT
1549         not SIGQUIT.
1550
1551         * sim-main.h (C0_CONFIG): New register.
1552         (signal.h): No longer include.
1553
1554         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1555
1556 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1557
1558         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1559
1560 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1561
1562         * mips.igen: Tag vr5000 instructions.
1563         (ANDI): Was missing mipsIV model, fix assembler syntax.
1564         (do_c_cond_fmt): New function.
1565         (C.cond.fmt): Handle mips I-III which do not support CC field
1566         separatly.
1567         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1568         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1569         in IV3.2 spec.
1570         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1571         vr5000 which saves LO in a GPR separatly.
1572
1573         * configure.in (enable-sim-igen): For vr5000, select vr5000
1574         specific instructions.
1575         * configure: Re-generate.
1576
1577 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1578
1579         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1580
1581         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1582         fmt_uninterpreted_64 bit cases to switch.  Convert to
1583         fmt_formatted,
1584
1585         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1586
1587         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1588         as specified in IV3.2 spec.
1589         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1590
1591 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1592
1593         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1594         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1595         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1596         PENDING_FILL versions of instructions.  Simplify.
1597         (X): New function.
1598         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1599         instructions.
1600         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1601         a signed value.
1602         (MTHI, MFHI): Disable code checking HI-LO.
1603
1604         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1605         global.
1606         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1607
1608 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1609
1610         * gencode.c (build_mips16_operands): Replace IPC with cia.
1611
1612         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1613         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1614         IPC to `cia'.
1615         (UndefinedResult): Replace function with macro/function
1616         combination.
1617         (sim_engine_run): Don't save PC in IPC.
1618
1619         * sim-main.h (IPC): Delete.
1620
1621
1622         * interp.c (signal_exception, store_word, load_word,
1623         address_translation, load_memory, store_memory, cache_op,
1624         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1625         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1626         current instruction address - cia - argument.
1627         (sim_read, sim_write): Call address_translation directly.
1628         (sim_engine_run): Rename variable vaddr to cia.
1629         (signal_exception): Pass cia to sim_monitor
1630
1631         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1632         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1633         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1634
1635         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1636         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1637         SIM_ASSERT.
1638
1639         * interp.c (signal_exception): Pass restart address to
1640         sim_engine_restart.
1641
1642         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1643         idecode.o): Add dependency.
1644
1645         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1646         Delete definitions
1647         (DELAY_SLOT): Update NIA not PC with branch address.
1648         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1649
1650         * mips.igen: Use CIA not PC in branch calculations.
1651         (illegal): Call SignalException.
1652         (BEQ, ADDIU): Fix assembler.
1653
1654 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1655
1656         * m16.igen (JALX): Was missing.
1657
1658         * configure.in (enable-sim-igen): New configuration option.
1659         * configure: Re-generate.
1660
1661         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1662
1663         * interp.c (load_memory, store_memory): Delete parameter RAW.
1664         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1665         bypassing {load,store}_memory.
1666
1667         * sim-main.h (ByteSwapMem): Delete definition.
1668
1669         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1670
1671         * interp.c (sim_do_command, sim_commands): Delete mips specific
1672         commands.  Handled by module sim-options.
1673
1674         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1675         (WITH_MODULO_MEMORY): Define.
1676
1677         * interp.c (sim_info): Delete code printing memory size.
1678
1679         * interp.c (mips_size): Nee sim_size, delete function.
1680         (power2): Delete.
1681         (monitor, monitor_base, monitor_size): Delete global variables.
1682         (sim_open, sim_close): Delete code creating monitor and other
1683         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1684         manage memory regions.
1685         (load_memory, store_memory): Use sim-core for memory model.
1686
1687         * interp.c (address_translation): Delete all memory map code
1688         except line forcing 32 bit addresses.
1689
1690 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1691
1692         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1693         trace options.
1694
1695         * interp.c (logfh, logfile): Delete globals.
1696         (sim_open, sim_close): Delete code opening & closing log file.
1697         (mips_option_handler): Delete -l and -n options.
1698         (OPTION mips_options): Ditto.
1699
1700         * interp.c (OPTION mips_options): Rename option trace to dinero.
1701         (mips_option_handler): Update.
1702
1703 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1704
1705         * interp.c (fetch_str): New function.
1706         (sim_monitor): Rewrite using sim_read & sim_write.
1707         (sim_open): Check magic number.
1708         (sim_open): Write monitor vectors into memory using sim_write.
1709         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1710         (sim_read, sim_write): Simplify - transfer data one byte at a
1711         time.
1712         (load_memory, store_memory): Clarify meaning of parameter RAW.
1713
1714         * sim-main.h (isHOST): Defete definition.
1715         (isTARGET): Mark as depreciated.
1716         (address_translation): Delete parameter HOST.
1717
1718         * interp.c (address_translation): Delete parameter HOST.
1719
1720 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1721
1722         * mips.igen:
1723
1724         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1725         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1726
1727 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1728
1729         * mips.igen: Add model filter field to records.
1730
1731 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1732
1733         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1734
1735         interp.c (sim_engine_run): Do not compile function sim_engine_run
1736         when WITH_IGEN == 1.
1737
1738         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1739         target architecture.
1740
1741         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1742         igen. Replace with configuration variables sim_igen_flags /
1743         sim_m16_flags.
1744
1745         * m16.igen: New file.  Copy mips16 insns here.
1746         * mips.igen: From here.
1747
1748 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1749
1750         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1751         to top.
1752         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1753
1754 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1755
1756         * gencode.c (build_instruction): Follow sim_write's lead in using
1757         BigEndianMem instead of !ByteSwapMem.
1758
1759 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1760
1761         * configure.in (sim_gen): Dependent on target, select type of
1762         generator.  Always select old style generator.
1763
1764         configure: Re-generate.
1765
1766         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1767         targets.
1768         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1769         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1770         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1771         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1772         SIM_@sim_gen@_*, set by autoconf.
1773
1774 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1775
1776         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1777
1778         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1779         CURRENT_FLOATING_POINT instead.
1780
1781         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1782         (address_translation): Raise exception InstructionFetch when
1783         translation fails and isINSTRUCTION.
1784
1785         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1786         sim_engine_run): Change type of of vaddr and paddr to
1787         address_word.
1788         (address_translation, prefetch, load_memory, store_memory,
1789         cache_op): Change type of vAddr and pAddr to address_word.
1790
1791         * gencode.c (build_instruction): Change type of vaddr and paddr to
1792         address_word.
1793
1794 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1795
1796         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1797         macro to obtain result of ALU op.
1798
1799 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1800
1801         * interp.c (sim_info): Call profile_print.
1802
1803 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1804
1805         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1806
1807         * sim-main.h (WITH_PROFILE): Do not define, defined in
1808         common/sim-config.h.  Use sim-profile module.
1809         (simPROFILE): Delete defintion.
1810
1811         * interp.c (PROFILE): Delete definition.
1812         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1813         (sim_close): Delete code writing profile histogram.
1814         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1815         Delete.
1816         (sim_engine_run): Delete code profiling the PC.
1817
1818 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1819
1820         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1821
1822         * interp.c (sim_monitor): Make register pointers of type
1823         unsigned_word*.
1824
1825         * sim-main.h: Make registers of type unsigned_word not
1826         signed_word.
1827
1828 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1829
1830         * interp.c (sync_operation): Rename from SyncOperation, make
1831         global, add SD argument.
1832         (prefetch): Rename from Prefetch, make global, add SD argument.
1833         (decode_coproc): Make global.
1834
1835         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1836
1837         * gencode.c (build_instruction): Generate DecodeCoproc not
1838         decode_coproc calls.
1839
1840         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1841         (SizeFGR): Move to sim-main.h
1842         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1843         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1844         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1845         sim-main.h.
1846         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1847         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1848         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1849         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1850         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1851         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1852
1853         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1854         exception.
1855         (sim-alu.h): Include.
1856         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1857         (sim_cia): Typedef to instruction_address.
1858
1859 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1860
1861         * Makefile.in (interp.o): Rename generated file engine.c to
1862         oengine.c.
1863
1864         * interp.c: Update.
1865
1866 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1867
1868         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1869
1870 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1871
1872         * gencode.c (build_instruction): For "FPSQRT", output correct
1873         number of arguments to Recip.
1874
1875 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1876
1877         * Makefile.in (interp.o): Depends on sim-main.h
1878
1879         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1880
1881         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1882         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1883         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1884         STATE, DSSTATE): Define
1885         (GPR, FGRIDX, ..): Define.
1886
1887         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1888         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1889         (GPR, FGRIDX, ...): Delete macros.
1890
1891         * interp.c: Update names to match defines from sim-main.h
1892
1893 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1894
1895         * interp.c (sim_monitor): Add SD argument.
1896         (sim_warning): Delete.  Replace calls with calls to
1897         sim_io_eprintf.
1898         (sim_error): Delete. Replace calls with sim_io_error.
1899         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1900         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1901         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1902         argument.
1903         (mips_size): Rename from sim_size. Add SD argument.
1904
1905         * interp.c (simulator): Delete global variable.
1906         (callback): Delete global variable.
1907         (mips_option_handler, sim_open, sim_write, sim_read,
1908         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1909         sim_size,sim_monitor): Use sim_io_* not callback->*.
1910         (sim_open): ZALLOC simulator struct.
1911         (PROFILE): Do not define.
1912
1913 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1914
1915         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1916         support.h with corresponding code.
1917
1918         * sim-main.h (word64, uword64), support.h: Move definition to
1919         sim-main.h.
1920         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1921
1922         * support.h: Delete
1923         * Makefile.in: Update dependencies
1924         * interp.c: Do not include.
1925
1926 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1927
1928         * interp.c (address_translation, load_memory, store_memory,
1929         cache_op): Rename to from AddressTranslation et.al., make global,
1930         add SD argument
1931
1932         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1933         CacheOp): Define.
1934
1935         * interp.c (SignalException): Rename to signal_exception, make
1936         global.
1937
1938         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1939
1940         * sim-main.h (SignalException, SignalExceptionInterrupt,
1941         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1942         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1943         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1944         Define.
1945
1946         * interp.c, support.h: Use.
1947
1948 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1949
1950         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1951         to value_fpr / store_fpr. Add SD argument.
1952         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1953         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1954
1955         * sim-main.h (ValueFPR, StoreFPR): Define.
1956
1957 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1958
1959         * interp.c (sim_engine_run): Check consistency between configure
1960         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1961         and HASFPU.
1962
1963         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1964         (mips_fpu): Configure WITH_FLOATING_POINT.
1965         (mips_endian): Configure WITH_TARGET_ENDIAN.
1966         * configure: Update.
1967
1968 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1969
1970         * configure: Regenerated to track ../common/aclocal.m4 changes.
1971
1972 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1973
1974         * configure: Regenerated.
1975
1976 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1977
1978         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1979
1980 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1981
1982         * gencode.c (print_igen_insn_models): Assume certain architectures
1983         include all mips* instructions.
1984         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1985         instruction.
1986
1987         * Makefile.in (tmp.igen): Add target. Generate igen input from
1988         gencode file.
1989
1990         * gencode.c (FEATURE_IGEN): Define.
1991         (main): Add --igen option.  Generate output in igen format.
1992         (process_instructions): Format output according to igen option.
1993         (print_igen_insn_format): New function.
1994         (print_igen_insn_models): New function.
1995         (process_instructions): Only issue warnings and ignore
1996         instructions when no FEATURE_IGEN.
1997
1998 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1999
2000         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2001         MIPS targets.
2002
2003 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2004
2005         * configure: Regenerated to track ../common/aclocal.m4 changes.
2006
2007 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2008
2009         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2010         SIM_RESERVED_BITS): Delete, moved to common.
2011         (SIM_EXTRA_CFLAGS): Update.
2012
2013 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2014
2015         * configure.in: Configure non-strict memory alignment.
2016         * configure: Regenerated to track ../common/aclocal.m4 changes.
2017
2018 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2019
2020         * configure: Regenerated to track ../common/aclocal.m4 changes.
2021
2022 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2023
2024         * gencode.c (SDBBP,DERET): Added (3900) insns.
2025         (RFE): Turn on for 3900.
2026         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2027         (dsstate): Made global.
2028         (SUBTARGET_R3900): Added.
2029         (CANCELDELAYSLOT): New.
2030         (SignalException): Ignore SystemCall rather than ignore and
2031         terminate.  Add DebugBreakPoint handling.
2032         (decode_coproc): New insns RFE, DERET; and new registers Debug
2033         and DEPC protected by SUBTARGET_R3900.
2034         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2035         bits explicitly.
2036         * Makefile.in,configure.in: Add mips subtarget option.
2037         * configure: Update.
2038
2039 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2040
2041         * gencode.c: Add r3900 (tx39).
2042
2043
2044 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2045
2046         * gencode.c (build_instruction): Don't need to subtract 4 for
2047         JALR, just 2.
2048
2049 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2050
2051         * interp.c: Correct some HASFPU problems.
2052
2053 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2054
2055         * configure: Regenerated to track ../common/aclocal.m4 changes.
2056
2057 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2058
2059         * interp.c (mips_options): Fix samples option short form, should
2060         be `x'.
2061
2062 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2063
2064         * interp.c (sim_info): Enable info code.  Was just returning.
2065
2066 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2067
2068         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2069         MFC0.
2070
2071 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2072
2073         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2074         constants.
2075         (build_instruction): Ditto for LL.
2076
2077 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2078
2079         * configure: Regenerated to track ../common/aclocal.m4 changes.
2080
2081 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2082
2083         * configure: Regenerated to track ../common/aclocal.m4 changes.
2084         * config.in: Ditto.
2085
2086 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2087
2088         * interp.c (sim_open): Add call to sim_analyze_program, update
2089         call to sim_config.
2090
2091 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2092
2093         * interp.c (sim_kill): Delete.
2094         (sim_create_inferior): Add ABFD argument. Set PC from same.
2095         (sim_load): Move code initializing trap handlers from here.
2096         (sim_open): To here.
2097         (sim_load): Delete, use sim-hload.c.
2098
2099         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2100
2101 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2102
2103         * configure: Regenerated to track ../common/aclocal.m4 changes.
2104         * config.in: Ditto.
2105
2106 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2107
2108         * interp.c (sim_open): Add ABFD argument.
2109         (sim_load): Move call to sim_config from here.
2110         (sim_open): To here.  Check return status.
2111
2112 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2113
2114         * gencode.c (build_instruction): Two arg MADD should
2115         not assign result to $0.
2116
2117 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2118
2119         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2120         * sim/mips/configure.in: Regenerate.
2121
2122 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2123
2124         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2125         signed8, unsigned8 et.al. types.
2126
2127         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2128         hosts when selecting subreg.
2129
2130 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2131
2132         * interp.c (sim_engine_run): Reset the ZERO register to zero
2133         regardless of FEATURE_WARN_ZERO.
2134         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2135
2136 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2137
2138         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2139         (SignalException): For BreakPoints ignore any mode bits and just
2140         save the PC.
2141         (SignalException): Always set the CAUSE register.
2142
2143 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2144
2145         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2146         exception has been taken.
2147
2148         * interp.c: Implement the ERET and mt/f sr instructions.
2149
2150 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2151
2152         * interp.c (SignalException): Don't bother restarting an
2153         interrupt.
2154
2155 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2156
2157         * interp.c (SignalException): Really take an interrupt.
2158         (interrupt_event): Only deliver interrupts when enabled.
2159
2160 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2161
2162         * interp.c (sim_info): Only print info when verbose.
2163         (sim_info) Use sim_io_printf for output.
2164
2165 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2166
2167         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2168         mips architectures.
2169
2170 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2171
2172         * interp.c (sim_do_command): Check for common commands if a
2173         simulator specific command fails.
2174
2175 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2176
2177         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2178         and simBE when DEBUG is defined.
2179
2180 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2181
2182         * interp.c (interrupt_event): New function.  Pass exception event
2183         onto exception handler.
2184
2185         * configure.in: Check for stdlib.h.
2186         * configure: Regenerate.
2187
2188         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2189         variable declaration.
2190         (build_instruction): Initialize memval1.
2191         (build_instruction): Add UNUSED attribute to byte, bigend,
2192         reverse.
2193         (build_operands): Ditto.
2194
2195         * interp.c: Fix GCC warnings.
2196         (sim_get_quit_code): Delete.
2197
2198         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2199         * Makefile.in: Ditto.
2200         * configure: Re-generate.
2201
2202         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2203
2204 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2205
2206         * interp.c (mips_option_handler): New function parse argumes using
2207         sim-options.
2208         (myname): Replace with STATE_MY_NAME.
2209         (sim_open): Delete check for host endianness - performed by
2210         sim_config.
2211         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2212         (sim_open): Move much of the initialization from here.
2213         (sim_load): To here.  After the image has been loaded and
2214         endianness set.
2215         (sim_open): Move ColdReset from here.
2216         (sim_create_inferior): To here.
2217         (sim_open): Make FP check less dependant on host endianness.
2218
2219         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2220         run.
2221         * interp.c (sim_set_callbacks): Delete.
2222
2223         * interp.c (membank, membank_base, membank_size): Replace with
2224         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2225         (sim_open): Remove call to callback->init. gdb/run do this.
2226
2227         * interp.c: Update
2228
2229         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2230
2231         * interp.c (big_endian_p): Delete, replaced by
2232         current_target_byte_order.
2233
2234 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2235
2236         * interp.c (host_read_long, host_read_word, host_swap_word,
2237         host_swap_long): Delete. Using common sim-endian.
2238         (sim_fetch_register, sim_store_register): Use H2T.
2239         (pipeline_ticks): Delete.  Handled by sim-events.
2240         (sim_info): Update.
2241         (sim_engine_run): Update.
2242
2243 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2244
2245         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2246         reason from here.
2247         (SignalException): To here. Signal using sim_engine_halt.
2248         (sim_stop_reason): Delete, moved to common.
2249
2250 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2251
2252         * interp.c (sim_open): Add callback argument.
2253         (sim_set_callbacks): Delete SIM_DESC argument.
2254         (sim_size): Ditto.
2255
2256 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2257
2258         * Makefile.in (SIM_OBJS): Add common modules.
2259
2260         * interp.c (sim_set_callbacks): Also set SD callback.
2261         (set_endianness, xfer_*, swap_*): Delete.
2262         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2263         Change to functions using sim-endian macros.
2264         (control_c, sim_stop): Delete, use common version.
2265         (simulate): Convert into.
2266         (sim_engine_run): This function.
2267         (sim_resume): Delete.
2268
2269         * interp.c (simulation): New variable - the simulator object.
2270         (sim_kind): Delete global - merged into simulation.
2271         (sim_load): Cleanup.  Move PC assignment from here.
2272         (sim_create_inferior): To here.
2273
2274         * sim-main.h: New file.
2275         * interp.c (sim-main.h): Include.
2276
2277 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2278
2279         * configure: Regenerated to track ../common/aclocal.m4 changes.
2280
2281 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2282
2283         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2284
2285 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2286
2287         * gencode.c (build_instruction): DIV instructions: check
2288         for division by zero and integer overflow before using
2289         host's division operation.
2290
2291 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2292
2293         * Makefile.in (SIM_OBJS): Add sim-load.o.
2294         * interp.c: #include bfd.h.
2295         (target_byte_order): Delete.
2296         (sim_kind, myname, big_endian_p): New static locals.
2297         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2298         after argument parsing.  Recognize -E arg, set endianness accordingly.
2299         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2300         load file into simulator.  Set PC from bfd.
2301         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2302         (set_endianness): Use big_endian_p instead of target_byte_order.
2303
2304 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2305
2306         * interp.c (sim_size): Delete prototype - conflicts with
2307         definition in remote-sim.h.  Correct definition.
2308
2309 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2310
2311         * configure: Regenerated to track ../common/aclocal.m4 changes.
2312         * config.in: Ditto.
2313
2314 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2315
2316         * interp.c (sim_open): New arg `kind'.
2317
2318         * configure: Regenerated to track ../common/aclocal.m4 changes.
2319
2320 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2321
2322         * configure: Regenerated to track ../common/aclocal.m4 changes.
2323
2324 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2325
2326         * interp.c (sim_open): Set optind to 0 before calling getopt.
2327
2328 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2329
2330         * configure: Regenerated to track ../common/aclocal.m4 changes.
2331
2332 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2333
2334         * interp.c : Replace uses of pr_addr with pr_uword64
2335         where the bit length is always 64 independent of SIM_ADDR.
2336         (pr_uword64) : added.
2337
2338 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2339
2340         * configure: Re-generate.
2341
2342 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2343
2344         * configure: Regenerate to track ../common/aclocal.m4 changes.
2345
2346 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2347
2348         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2349         in argv form.
2350         (other sim_*): New SIM_DESC argument.
2351
2352 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2353
2354         * interp.c: Fix printing of addresses for non-64-bit targets.
2355         (pr_addr): Add function to print address based on size.
2356
2357 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2358
2359         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2360
2361 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2362
2363         * gencode.c (build_mips16_operands): Correct computation of base
2364         address for extended PC relative instruction.
2365
2366 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2367
2368         * interp.c (mips16_entry): Add support for floating point cases.
2369         (SignalException): Pass floating point cases to mips16_entry.
2370         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2371         registers.
2372         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2373         or fmt_word.
2374         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2375         and then set the state to fmt_uninterpreted.
2376         (COP_SW): Temporarily set the state to fmt_word while calling
2377         ValueFPR.
2378
2379 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2380
2381         * gencode.c (build_instruction): The high order may be set in the
2382         comparison flags at any ISA level, not just ISA 4.
2383
2384 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2385
2386         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2387         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2388         * configure.in: sinclude ../common/aclocal.m4.
2389         * configure: Regenerated.
2390
2391 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2392
2393         * configure: Rebuild after change to aclocal.m4.
2394
2395 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2396
2397         * configure configure.in Makefile.in:  Update to new configure
2398         scheme which is more compatible with WinGDB builds.
2399         * configure.in:  Improve comment on how to run autoconf.
2400         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2401         * Makefile.in:  Use autoconf substitution to install common
2402         makefile fragment.
2403
2404 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2405
2406         * gencode.c (build_instruction): Use BigEndianCPU instead of
2407         ByteSwapMem.
2408
2409 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2410
2411         * interp.c (sim_monitor): Make output to stdout visible in
2412         wingdb's I/O log window.
2413
2414 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2415
2416         * support.h: Undo previous change to SIGTRAP
2417         and SIGQUIT values.
2418
2419 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2420
2421         * interp.c (store_word, load_word): New static functions.
2422         (mips16_entry): New static function.
2423         (SignalException): Look for mips16 entry and exit instructions.
2424         (simulate): Use the correct index when setting fpr_state after
2425         doing a pending move.
2426
2427 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2428
2429         * interp.c: Fix byte-swapping code throughout to work on
2430         both little- and big-endian hosts.
2431
2432 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2433
2434         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2435         with gdb/config/i386/xm-windows.h.
2436
2437 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2438
2439         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2440         that messes up arithmetic shifts.
2441
2442 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2443
2444         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2445         SIGTRAP and SIGQUIT for _WIN32.
2446
2447 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2448
2449         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2450         force a 64 bit multiplication.
2451         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2452         destination register is 0, since that is the default mips16 nop
2453         instruction.
2454
2455 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2456
2457         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2458         (build_endian_shift): Don't check proc64.
2459         (build_instruction): Always set memval to uword64.  Cast op2 to
2460         uword64 when shifting it left in memory instructions.  Always use
2461         the same code for stores--don't special case proc64.
2462
2463         * gencode.c (build_mips16_operands): Fix base PC value for PC
2464         relative operands.
2465         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2466         jal instruction.
2467         * interp.c (simJALDELAYSLOT): Define.
2468         (JALDELAYSLOT): Define.
2469         (INDELAYSLOT, INJALDELAYSLOT): Define.
2470         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2471
2472 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2473
2474         * interp.c (sim_open): add flush_cache as a PMON routine
2475         (sim_monitor): handle flush_cache by ignoring it
2476
2477 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2478
2479         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2480         BigEndianMem.
2481         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2482         (BigEndianMem): Rename to ByteSwapMem and change sense.
2483         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2484         BigEndianMem references to !ByteSwapMem.
2485         (set_endianness): New function, with prototype.
2486         (sim_open): Call set_endianness.
2487         (sim_info): Use simBE instead of BigEndianMem.
2488         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2489         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2490         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2491         ifdefs, keeping the prototype declaration.
2492         (swap_word): Rewrite correctly.
2493         (ColdReset): Delete references to CONFIG.  Delete endianness related
2494         code; moved to set_endianness.
2495
2496 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2497
2498         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2499         * interp.c (CHECKHILO): Define away.
2500         (simSIGINT): New macro.
2501         (membank_size): Increase from 1MB to 2MB.
2502         (control_c): New function.
2503         (sim_resume): Rename parameter signal to signal_number.  Add local
2504         variable prev.  Call signal before and after simulate.
2505         (sim_stop_reason): Add simSIGINT support.
2506         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2507         functions always.
2508         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2509         if logfh is NULL.
2510         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2511         a call to sim_warning.
2512
2513 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2514
2515         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2516         16 bit instructions.
2517
2518 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2519
2520         Add support for mips16 (16 bit MIPS implementation):
2521         * gencode.c (inst_type): Add mips16 instruction encoding types.
2522         (GETDATASIZEINSN): Define.
2523         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2524         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2525         mtlo.
2526         (MIPS16_DECODE): New table, for mips16 instructions.
2527         (bitmap_val): New static function.
2528         (struct mips16_op): Define.
2529         (mips16_op_table): New table, for mips16 operands.
2530         (build_mips16_operands): New static function.
2531         (process_instructions): If PC is odd, decode a mips16
2532         instruction.  Break out instruction handling into new
2533         build_instruction function.
2534         (build_instruction): New static function, broken out of
2535         process_instructions.  Check modifiers rather than flags for SHIFT
2536         bit count and m[ft]{hi,lo} direction.
2537         (usage): Pass program name to fprintf.
2538         (main): Remove unused variable this_option_optind.  Change
2539         ``*loptarg++'' to ``loptarg++''.
2540         (my_strtoul): Parenthesize && within ||.
2541         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2542         (simulate): If PC is odd, fetch a 16 bit instruction, and
2543         increment PC by 2 rather than 4.
2544         * configure.in: Add case for mips16*-*-*.
2545         * configure: Rebuild.
2546
2547 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2548
2549         * interp.c: Allow -t to enable tracing in standalone simulator.
2550         Fix garbage output in trace file and error messages.
2551
2552 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2553
2554         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2555         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2556         * configure.in: Simplify using macros in ../common/aclocal.m4.
2557         * configure: Regenerated.
2558         * tconfig.in: New file.
2559
2560 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2561
2562         * interp.c: Fix bugs in 64-bit port.
2563         Use ansi function declarations for msvc compiler.
2564         Initialize and test file pointer in trace code.
2565         Prevent duplicate definition of LAST_EMED_REGNUM.
2566
2567 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2568
2569         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2570
2571 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2572
2573         * interp.c (SignalException): Check for explicit terminating
2574         breakpoint value.
2575         * gencode.c: Pass instruction value through SignalException()
2576         calls for Trap, Breakpoint and Syscall.
2577
2578 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2579
2580         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2581         only used on those hosts that provide it.
2582         * configure.in: Add sqrt() to list of functions to be checked for.
2583         * config.in: Re-generated.
2584         * configure: Re-generated.
2585
2586 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2587
2588         * gencode.c (process_instructions): Call build_endian_shift when
2589         expanding STORE RIGHT, to fix swr.
2590         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2591         clear the high bits.
2592         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2593         Fix float to int conversions to produce signed values.
2594
2595 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2596
2597         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2598         (process_instructions): Correct handling of nor instruction.
2599         Correct shift count for 32 bit shift instructions. Correct sign
2600         extension for arithmetic shifts to not shift the number of bits in
2601         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2602         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2603         Fix madd.
2604         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2605         It's OK to have a mult follow a mult.  What's not OK is to have a
2606         mult follow an mfhi.
2607         (Convert): Comment out incorrect rounding code.
2608
2609 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2610
2611         * interp.c (sim_monitor): Improved monitor printf
2612         simulation. Tidied up simulator warnings, and added "--log" option
2613         for directing warning message output.
2614         * gencode.c: Use sim_warning() rather than WARNING macro.
2615
2616 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2617
2618         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2619         getopt1.o, rather than on gencode.c.  Link objects together.
2620         Don't link against -liberty.
2621         (gencode.o, getopt.o, getopt1.o): New targets.
2622         * gencode.c: Include <ctype.h> and "ansidecl.h".
2623         (AND): Undefine after including "ansidecl.h".
2624         (ULONG_MAX): Define if not defined.
2625         (OP_*): Don't define macros; now defined in opcode/mips.h.
2626         (main): Call my_strtoul rather than strtoul.
2627         (my_strtoul): New static function.
2628
2629 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2630
2631         * gencode.c (process_instructions):  Generate word64 and uword64
2632         instead of `long long' and `unsigned long long' data types.
2633         * interp.c:  #include sysdep.h to get signals, and define default
2634         for SIGBUS.
2635         * (Convert):  Work around for Visual-C++ compiler bug with type
2636         conversion.
2637         * support.h:  Make things compile under Visual-C++ by using
2638         __int64 instead of `long long'.  Change many refs to long long
2639         into word64/uword64 typedefs.
2640
2641 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2642
2643         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2644         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2645         (docdir): Removed.
2646         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2647         (AC_PROG_INSTALL): Added.
2648         (AC_PROG_CC): Moved to before configure.host call.
2649         * configure: Rebuilt.
2650
2651 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2652
2653         * configure.in: Define @SIMCONF@ depending on mips target.
2654         * configure: Rebuild.
2655         * Makefile.in (run): Add @SIMCONF@ to control simulator
2656         construction.
2657         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2658         * interp.c: Remove some debugging, provide more detailed error
2659         messages, update memory accesses to use LOADDRMASK.
2660
2661 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2662
2663         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2664         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2665         stamp-h.
2666         * configure: Rebuild.
2667         * config.in: New file, generated by autoheader.
2668         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2669         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2670         HAVE_ANINT and HAVE_AINT, as appropriate.
2671         * Makefile.in (run): Use @LIBS@ rather than -lm.
2672         (interp.o): Depend upon config.h.
2673         (Makefile): Just rebuild Makefile.
2674         (clean): Remove stamp-h.
2675         (mostlyclean): Make the same as clean, not as distclean.
2676         (config.h, stamp-h): New targets.
2677
2678 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2679
2680         * interp.c (ColdReset): Fix boolean test. Make all simulator
2681         globals static.
2682
2683 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2684
2685         * interp.c (xfer_direct_word, xfer_direct_long,
2686         swap_direct_word, swap_direct_long, xfer_big_word,
2687         xfer_big_long, xfer_little_word, xfer_little_long,
2688         swap_word,swap_long): Added.
2689         * interp.c (ColdReset): Provide function indirection to
2690         host<->simulated_target transfer routines.
2691         * interp.c (sim_store_register, sim_fetch_register): Updated to
2692         make use of indirected transfer routines.
2693
2694 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2695
2696         * gencode.c (process_instructions): Ensure FP ABS instruction
2697         recognised.
2698         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2699         system call support.
2700
2701 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2702
2703         * interp.c (sim_do_command): Complain if callback structure not
2704         initialised.
2705
2706 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2707
2708         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2709         support for Sun hosts.
2710         * Makefile.in (gencode): Ensure the host compiler and libraries
2711         used for cross-hosted build.
2712
2713 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2714
2715         * interp.c, gencode.c: Some more (TODO) tidying.
2716
2717 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2718
2719         * gencode.c, interp.c: Replaced explicit long long references with
2720         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2721         * support.h (SET64LO, SET64HI): Macros added.
2722
2723 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2724
2725         * configure: Regenerate with autoconf 2.7.
2726
2727 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2728
2729         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2730         * support.h: Remove superfluous "1" from #if.
2731         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2732
2733 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2734
2735         * interp.c (StoreFPR): Control UndefinedResult() call on
2736         WARN_RESULT manifest.
2737
2738 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2739
2740         * gencode.c: Tidied instruction decoding, and added FP instruction
2741         support.
2742
2743         * interp.c: Added dineroIII, and BSD profiling support. Also
2744         run-time FP handling.
2745
2746 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2747
2748         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2749         gencode.c, interp.c, support.h: created.