2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
21 The IDT monitor (found on the VR4300 board), seems to lie about
22 register contents. It seems to treat the registers as sign-extended
23 32-bit values. This cause *REAL* problems when single-stepping 64-bit
28 /* The TRACE manifests enable the provision of extra features. If they
29 are not defined then a simpler (quicker) simulator is constructed
30 without the required run-time checks, etc. */
31 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
37 #include "sim-utils.h"
38 #include "sim-options.h"
39 #include "sim-assert.h"
65 #include "libiberty.h"
67 #include "callback.h" /* GDB simulator callback interface */
68 #include "remote-sim.h" /* GDB simulator interface */
76 char* pr_addr
PARAMS ((SIM_ADDR addr
));
77 char* pr_uword64
PARAMS ((uword64 addr
));
80 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
85 /* The following reserved instruction value is used when a simulator
86 trap is required. NOTE: Care must be taken, since this value may be
87 used in later revisions of the MIPS ISA. */
89 #define RSVD_INSTRUCTION (0x00000005)
90 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
92 #define RSVD_INSTRUCTION_ARG_SHIFT 6
93 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
96 /* Bits in the Debug register */
97 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
98 #define Debug_DM 0x40000000 /* Debug Mode */
99 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
101 /*---------------------------------------------------------------------------*/
102 /*-- GDB simulator interface ------------------------------------------------*/
103 /*---------------------------------------------------------------------------*/
105 static void ColdReset
PARAMS((SIM_DESC sd
));
107 /*---------------------------------------------------------------------------*/
111 #define DELAYSLOT() {\
112 if (STATE & simDELAYSLOT)\
113 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
114 STATE |= simDELAYSLOT;\
117 #define JALDELAYSLOT() {\
119 STATE |= simJALDELAYSLOT;\
123 STATE &= ~simDELAYSLOT;\
124 STATE |= simSKIPNEXT;\
127 #define CANCELDELAYSLOT() {\
129 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
132 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
133 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
135 /* Note that the monitor code essentially assumes this layout of memory.
136 If you change these, change the monitor code, too. */
137 #define K0BASE (0x80000000)
138 #define K0SIZE (0x20000000)
139 #define K1BASE (0xA0000000)
140 #define K1SIZE (0x20000000)
142 /* Simple run-time monitor support.
144 We emulate the monitor by placing magic reserved instructions at
145 the monitor's entry points; when we hit these instructions, instead
146 of raising an exception (as we would normally), we look at the
147 instruction and perform the appropriate monitory operation.
149 `*_monitor_base' are the physical addresses at which the corresponding
150 monitor vectors are located. `0' means none. By default,
152 The RSVD_INSTRUCTION... macros specify the magic instructions we
153 use at the monitor entry points. */
154 static int firmware_option_p
= 0;
155 static SIM_ADDR idt_monitor_base
= 0xBFC00000;
156 static SIM_ADDR pmon_monitor_base
= 0xBFC00500;
157 static SIM_ADDR lsipmon_monitor_base
= 0xBFC00200;
159 static SIM_RC
sim_firmware_command (SIM_DESC sd
, char* arg
);
162 #define MEM_SIZE (2 << 20)
166 static char *tracefile
= "trace.din"; /* default filename for trace log */
167 FILE *tracefh
= NULL
;
168 static void open_trace
PARAMS((SIM_DESC sd
));
171 static const char * get_insn_name (sim_cpu
*, int);
173 /* simulation target board. NULL=canonical */
174 static char* board
= NULL
;
177 static DECLARE_OPTION_HANDLER (mips_option_handler
);
180 OPTION_DINERO_TRACE
= OPTION_START
,
188 mips_option_handler (sd
, cpu
, opt
, arg
, is_command
)
198 case OPTION_DINERO_TRACE
: /* ??? */
200 /* Eventually the simTRACE flag could be treated as a toggle, to
201 allow external control of the program points being traced
202 (i.e. only from main onwards, excluding the run-time setup,
204 for (cpu_nr
= 0; cpu_nr
< MAX_NR_PROCESSORS
; cpu_nr
++)
206 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
209 else if (strcmp (arg
, "yes") == 0)
211 else if (strcmp (arg
, "no") == 0)
213 else if (strcmp (arg
, "on") == 0)
215 else if (strcmp (arg
, "off") == 0)
219 fprintf (stderr
, "Unrecognized dinero-trace option `%s'\n", arg
);
226 Simulator constructed without dinero tracing support (for performance).\n\
227 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
231 case OPTION_DINERO_FILE
:
233 if (optarg
!= NULL
) {
235 tmp
= (char *)malloc(strlen(optarg
) + 1);
238 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
244 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
250 case OPTION_FIRMWARE
:
251 return sim_firmware_command (sd
, arg
);
257 board
= zalloc(strlen(arg
) + 1);
268 static const OPTION mips_options
[] =
270 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
271 '\0', "on|off", "Enable dinero tracing",
272 mips_option_handler
},
273 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
274 '\0', "FILE", "Write dinero trace to FILE",
275 mips_option_handler
},
276 { {"firmware", required_argument
, NULL
, OPTION_FIRMWARE
},
277 '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
278 mips_option_handler
},
279 { {"board", required_argument
, NULL
, OPTION_BOARD
},
280 '\0', "none" /* rely on compile-time string concatenation for other options */
282 #define BOARD_JMR3904 "jmr3904"
284 #define BOARD_JMR3904_PAL "jmr3904pal"
285 "|" BOARD_JMR3904_PAL
286 #define BOARD_JMR3904_DEBUG "jmr3904debug"
287 "|" BOARD_JMR3904_DEBUG
288 #define BOARD_BSP "bsp"
291 , "Customize simulation for a particular board.", mips_option_handler
},
293 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
297 int interrupt_pending
;
300 interrupt_event (SIM_DESC sd
, void *data
)
302 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
303 address_word cia
= CIA_GET (cpu
);
306 interrupt_pending
= 0;
307 SignalExceptionInterrupt (1); /* interrupt "1" */
309 else if (!interrupt_pending
)
310 sim_events_schedule (sd
, 1, interrupt_event
, data
);
314 /*---------------------------------------------------------------------------*/
315 /*-- Device registration hook -----------------------------------------------*/
316 /*---------------------------------------------------------------------------*/
317 static void device_init(SIM_DESC sd
) {
319 extern void register_devices(SIM_DESC
);
320 register_devices(sd
);
324 /*---------------------------------------------------------------------------*/
325 /*-- GDB simulator interface ------------------------------------------------*/
326 /*---------------------------------------------------------------------------*/
329 sim_open (kind
, cb
, abfd
, argv
)
335 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
336 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
338 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
340 /* FIXME: watchpoints code shouldn't need this */
341 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
342 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
343 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
345 /* Initialize the mechanism for doing insn profiling. */
346 CPU_INSN_NAME (cpu
) = get_insn_name
;
347 CPU_MAX_INSNS (cpu
) = nr_itable_entries
;
351 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
353 sim_add_option_table (sd
, NULL
, mips_options
);
356 /* getopt will print the error message so we just have to exit if this fails.
357 FIXME: Hmmm... in the case of gdb we need getopt to call
359 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
361 /* Uninstall the modules to avoid memory leaks,
362 file descriptor leaks, etc. */
363 sim_module_uninstall (sd
);
367 /* handle board-specific memory maps */
370 /* Allocate core managed memory */
373 /* For compatibility with the old code - under this (at level one)
374 are the kernel spaces K0 & K1. Both of these map to a single
375 smaller sub region */
376 sim_do_command(sd
," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
377 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
379 MEM_SIZE
, /* actual size */
384 else if (board
!= NULL
385 && (strcmp(board
, BOARD_BSP
) == 0))
389 STATE_ENVIRONMENT (sd
) = OPERATING_ENVIRONMENT
;
391 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
392 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
394 4 * 1024 * 1024, /* 4 MB */
397 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
398 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
400 4 * 1024 * 1024, /* 4 MB */
403 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
404 for (i
=0; i
<8; i
++) /* 32 MB total */
406 unsigned size
= 4 * 1024 * 1024; /* 4 MB */
407 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
408 0x88000000 + (i
* size
),
410 0xA8000000 + (i
* size
));
414 else if (board
!= NULL
415 && (strcmp(board
, BOARD_JMR3904
) == 0 ||
416 strcmp(board
, BOARD_JMR3904_PAL
) == 0 ||
417 strcmp(board
, BOARD_JMR3904_DEBUG
) == 0))
419 /* match VIRTUAL memory layout of JMR-TX3904 board */
422 /* --- disable monitor unless forced on by user --- */
424 if (! firmware_option_p
)
426 idt_monitor_base
= 0;
427 pmon_monitor_base
= 0;
428 lsipmon_monitor_base
= 0;
431 /* --- environment --- */
433 STATE_ENVIRONMENT (sd
) = OPERATING_ENVIRONMENT
;
437 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
438 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
440 4 * 1024 * 1024, /* 4 MB */
443 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
444 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
446 4 * 1024 * 1024, /* 4 MB */
449 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
450 for (i
=0; i
<8; i
++) /* 32 MB total */
452 unsigned size
= 4 * 1024 * 1024; /* 4 MB */
453 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
454 0x88000000 + (i
* size
),
456 0xA8000000 + (i
* size
));
459 /* Dummy memory regions for unsimulated devices */
461 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFFE010, 0x00c); /* EBIF */
462 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
463 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
465 /* --- simulated devices --- */
466 sim_hw_parse (sd
, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
467 sim_hw_parse (sd
, "/tx3904cpu");
468 sim_hw_parse (sd
, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
469 sim_hw_parse (sd
, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
470 sim_hw_parse (sd
, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
471 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
473 /* FIXME: poking at dv-sockser internals, use tcp backend if
474 --sockser_addr option was given.*/
475 extern char* sockser_addr
;
476 if(sockser_addr
== NULL
)
477 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/backend stdio");
479 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/backend tcp");
481 sim_hw_parse (sd
, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
482 sim_hw_parse (sd
, "/tx3904sio@0xfffff400/backend stdio");
484 /* -- device connections --- */
485 sim_hw_parse (sd
, "/tx3904irc > ip level /tx3904cpu");
486 sim_hw_parse (sd
, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
487 sim_hw_parse (sd
, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
488 sim_hw_parse (sd
, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
489 sim_hw_parse (sd
, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
490 sim_hw_parse (sd
, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
492 /* add PAL timer & I/O module */
493 if(! strcmp(board
, BOARD_JMR3904_PAL
))
496 sim_hw_parse (sd
, "/pal@0xffff0000");
497 sim_hw_parse (sd
, "/pal@0xffff0000/reg 0xffff0000 64");
499 /* wire up interrupt ports to irc */
500 sim_hw_parse (sd
, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
501 sim_hw_parse (sd
, "/pal@0x31000000 > timer tmr1 /tx3904irc");
502 sim_hw_parse (sd
, "/pal@0x31000000 > int int0 /tx3904irc");
505 if(! strcmp(board
, BOARD_JMR3904_DEBUG
))
507 /* -- DEBUG: glue interrupt generators --- */
508 sim_hw_parse (sd
, "/glue@0xffff0000/reg 0xffff0000 0x50");
509 sim_hw_parse (sd
, "/glue@0xffff0000 > int0 int0 /tx3904irc");
510 sim_hw_parse (sd
, "/glue@0xffff0000 > int1 int1 /tx3904irc");
511 sim_hw_parse (sd
, "/glue@0xffff0000 > int2 int2 /tx3904irc");
512 sim_hw_parse (sd
, "/glue@0xffff0000 > int3 int3 /tx3904irc");
513 sim_hw_parse (sd
, "/glue@0xffff0000 > int4 int4 /tx3904irc");
514 sim_hw_parse (sd
, "/glue@0xffff0000 > int5 int5 /tx3904irc");
515 sim_hw_parse (sd
, "/glue@0xffff0000 > int6 int6 /tx3904irc");
516 sim_hw_parse (sd
, "/glue@0xffff0000 > int7 int7 /tx3904irc");
517 sim_hw_parse (sd
, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
518 sim_hw_parse (sd
, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
519 sim_hw_parse (sd
, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
520 sim_hw_parse (sd
, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
521 sim_hw_parse (sd
, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
522 sim_hw_parse (sd
, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
523 sim_hw_parse (sd
, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
524 sim_hw_parse (sd
, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
525 sim_hw_parse (sd
, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
526 sim_hw_parse (sd
, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
534 /* check for/establish the a reference program image */
535 if (sim_analyze_program (sd
,
536 (STATE_PROG_ARGV (sd
) != NULL
537 ? *STATE_PROG_ARGV (sd
)
541 sim_module_uninstall (sd
);
545 /* Configure/verify the target byte order and other runtime
546 configuration options */
547 if (sim_config (sd
) != SIM_RC_OK
)
549 sim_module_uninstall (sd
);
553 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
555 /* Uninstall the modules to avoid memory leaks,
556 file descriptor leaks, etc. */
557 sim_module_uninstall (sd
);
561 /* verify assumptions the simulator made about the host type system.
562 This macro does not return if there is a problem */
563 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
564 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
566 /* This is NASTY, in that we are assuming the size of specific
570 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++)
573 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
574 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ NR_FGR
)))
575 cpu
->register_widths
[rn
] = WITH_TARGET_FLOATING_POINT_BITSIZE
;
576 else if ((rn
>= 33) && (rn
<= 37))
577 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
578 else if ((rn
== SRIDX
)
581 || ((rn
>= 72) && (rn
<= 89)))
582 cpu
->register_widths
[rn
] = 32;
584 cpu
->register_widths
[rn
] = 0;
591 if (STATE
& simTRACE
)
596 sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
599 lsipmon_monitor_base);
602 /* Write the monitor trap address handlers into the monitor (eeprom)
603 address space. This can only be done once the target endianness
604 has been determined. */
605 if (idt_monitor_base
!= 0)
608 unsigned idt_monitor_size
= 1 << 11;
610 /* the default monitor region */
611 sim_do_commandf (sd
, "memory region 0x%x,0x%x",
612 idt_monitor_base
, idt_monitor_size
);
614 /* Entry into the IDT monitor is via fixed address vectors, and
615 not using machine instructions. To avoid clashing with use of
616 the MIPS TRAP system, we place our own (simulator specific)
617 "undefined" instructions into the relevant vector slots. */
618 for (loop
= 0; (loop
< idt_monitor_size
); loop
+= 4)
620 address_word vaddr
= (idt_monitor_base
+ loop
);
621 unsigned32 insn
= (RSVD_INSTRUCTION
|
622 (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
)
623 << RSVD_INSTRUCTION_ARG_SHIFT
));
625 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
629 if ((pmon_monitor_base
!= 0) || (lsipmon_monitor_base
!= 0))
631 /* The PMON monitor uses the same address space, but rather than
632 branching into it the address of a routine is loaded. We can
633 cheat for the moment, and direct the PMON routine to IDT style
634 instructions within the monitor space. This relies on the IDT
635 monitor not using the locations from 0xBFC00500 onwards as its
638 for (loop
= 0; (loop
< 24); loop
++)
640 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
656 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
658 case 8: /* cliexit */
661 case 11: /* flush_cache */
666 SIM_ASSERT (idt_monitor_base
!= 0);
667 value
= ((unsigned int) idt_monitor_base
+ (value
* 8));
670 if (pmon_monitor_base
!= 0)
672 address_word vaddr
= (pmon_monitor_base
+ (loop
* 4));
673 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
676 if (lsipmon_monitor_base
!= 0)
678 address_word vaddr
= (lsipmon_monitor_base
+ (loop
* 4));
679 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
683 /* Write an abort sequence into the TRAP (common) exception vector
684 addresses. This is to catch code executing a TRAP (et.al.)
685 instruction without installing a trap handler. */
686 if ((idt_monitor_base
!= 0) ||
687 (pmon_monitor_base
!= 0) ||
688 (lsipmon_monitor_base
!= 0))
690 unsigned32 halt
[2] = { 0x2404002f /* addiu r4, r0, 47 */,
691 HALT_INSTRUCTION
/* BREAK */ };
694 sim_write (sd
, 0x80000000, (char *) halt
, sizeof (halt
));
695 sim_write (sd
, 0x80000180, (char *) halt
, sizeof (halt
));
696 sim_write (sd
, 0x80000200, (char *) halt
, sizeof (halt
));
697 /* XXX: Write here unconditionally? */
698 sim_write (sd
, 0xBFC00200, (char *) halt
, sizeof (halt
));
699 sim_write (sd
, 0xBFC00380, (char *) halt
, sizeof (halt
));
700 sim_write (sd
, 0xBFC00400, (char *) halt
, sizeof (halt
));
714 tracefh
= fopen(tracefile
,"wb+");
717 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
723 /* Return name of an insn, used by insn profiling. */
725 get_insn_name (sim_cpu
*cpu
, int i
)
727 return itable
[i
].name
;
731 sim_close (sd
, quitting
)
736 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
740 /* "quitting" is non-zero if we cannot hang on errors */
742 /* shut down modules */
743 sim_module_uninstall (sd
);
745 /* Ensure that any resources allocated through the callback
746 mechanism are released: */
747 sim_io_shutdown (sd
);
750 if (tracefh
!= NULL
&& tracefh
!= stderr
)
755 /* FIXME - free SD */
762 sim_write (sd
,addr
,buffer
,size
)
765 unsigned char *buffer
;
769 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
771 /* Return the number of bytes written, or zero if error. */
773 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
776 /* We use raw read and write routines, since we do not want to count
777 the GDB memory accesses in our statistics gathering. */
779 for (index
= 0; index
< size
; index
++)
781 address_word vaddr
= (address_word
)addr
+ index
;
784 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
786 if (sim_core_write_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
794 sim_read (sd
,addr
,buffer
,size
)
797 unsigned char *buffer
;
801 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
803 /* Return the number of bytes read, or zero if error. */
805 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
808 for (index
= 0; (index
< size
); index
++)
810 address_word vaddr
= (address_word
)addr
+ index
;
813 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
815 if (sim_core_read_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
823 sim_store_register (sd
,rn
,memory
,length
)
826 unsigned char *memory
;
829 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
830 /* NOTE: gdb (the client) stores registers in target byte order
831 while the simulator uses host byte order */
833 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
836 /* Unfortunately this suffers from the same problem as the register
837 numbering one. We need to know what the width of each logical
838 register number is for the architecture being simulated. */
840 if (cpu
->register_widths
[rn
] == 0)
842 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
848 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
850 cpu
->fpr_state
[rn
- FGRIDX
] = fmt_uninterpreted
;
851 if (cpu
->register_widths
[rn
] == 32)
853 cpu
->fgr
[rn
- FGRIDX
] = T2H_4 (*(unsigned32
*)memory
);
858 cpu
->fgr
[rn
- FGRIDX
] = T2H_8 (*(unsigned64
*)memory
);
863 if (cpu
->register_widths
[rn
] == 32)
865 cpu
->registers
[rn
] = T2H_4 (*(unsigned32
*)memory
);
870 cpu
->registers
[rn
] = T2H_8 (*(unsigned64
*)memory
);
878 sim_fetch_register (sd
,rn
,memory
,length
)
881 unsigned char *memory
;
884 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
885 /* NOTE: gdb (the client) stores registers in target byte order
886 while the simulator uses host byte order */
888 #if 0 /* FIXME: doesn't compile */
889 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
893 if (cpu
->register_widths
[rn
] == 0)
895 sim_io_eprintf (sd
, "Invalid register width for %d (register fetch ignored)\n",rn
);
901 /* Any floating point register */
902 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
904 if (cpu
->register_widths
[rn
] == 32)
906 *(unsigned32
*)memory
= H2T_4 (cpu
->fgr
[rn
- FGRIDX
]);
911 *(unsigned64
*)memory
= H2T_8 (cpu
->fgr
[rn
- FGRIDX
]);
916 if (cpu
->register_widths
[rn
] == 32)
918 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
923 *(unsigned64
*)memory
= H2T_8 ((unsigned64
)(cpu
->registers
[rn
]));
932 sim_create_inferior (sd
, abfd
, argv
,env
)
940 #if 0 /* FIXME: doesn't compile */
941 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
950 /* override PC value set by ColdReset () */
952 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
954 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
955 CIA_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
959 #if 0 /* def DEBUG */
962 /* We should really place the argv slot values into the argument
963 registers, and onto the stack as required. However, this
964 assumes that we have a stack defined, which is not
965 necessarily true at the moment. */
967 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
968 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
969 printf("DBG: arg \"%s\"\n",*cptr
);
977 sim_do_command (sd
,cmd
)
981 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
982 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
986 /*---------------------------------------------------------------------------*/
987 /*-- Private simulator support interface ------------------------------------*/
988 /*---------------------------------------------------------------------------*/
990 /* Read a null terminated string from memory, return in a buffer */
992 fetch_str (SIM_DESC sd
,
998 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
1000 buf
= NZALLOC (char, nr
+ 1);
1001 sim_read (sd
, addr
, buf
, nr
);
1006 /* Implements the "sim firmware" command:
1007 sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
1008 NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
1009 defaults to the normal address for that monitor.
1010 sim firmware none --- don't emulate any ROM monitor. Useful
1011 if you need a clean address space. */
1013 sim_firmware_command (SIM_DESC sd
, char *arg
)
1015 int address_present
= 0;
1018 /* Signal occurrence of this option. */
1019 firmware_option_p
= 1;
1021 /* Parse out the address, if present. */
1023 char *p
= strchr (arg
, '@');
1027 address_present
= 1;
1028 p
++; /* skip over @ */
1030 address
= strtoul (p
, &q
, 0);
1033 sim_io_printf (sd
, "Invalid address given to the"
1034 "`sim firmware NAME@ADDRESS' command: %s\n",
1040 address_present
= 0;
1043 if (! strncmp (arg
, "idt", 3))
1045 idt_monitor_base
= address_present
? address
: 0xBFC00000;
1046 pmon_monitor_base
= 0;
1047 lsipmon_monitor_base
= 0;
1049 else if (! strncmp (arg
, "pmon", 4))
1051 /* pmon uses indirect calls. Hook into implied idt. */
1052 pmon_monitor_base
= address_present
? address
: 0xBFC00500;
1053 idt_monitor_base
= pmon_monitor_base
- 0x500;
1054 lsipmon_monitor_base
= 0;
1056 else if (! strncmp (arg
, "lsipmon", 7))
1058 /* lsipmon uses indirect calls. Hook into implied idt. */
1059 pmon_monitor_base
= 0;
1060 lsipmon_monitor_base
= address_present
? address
: 0xBFC00200;
1061 idt_monitor_base
= lsipmon_monitor_base
- 0x200;
1063 else if (! strncmp (arg
, "none", 4))
1065 if (address_present
)
1068 "The `sim firmware none' command does "
1069 "not take an `ADDRESS' argument.\n");
1072 idt_monitor_base
= 0;
1073 pmon_monitor_base
= 0;
1074 lsipmon_monitor_base
= 0;
1078 sim_io_printf (sd
, "\
1079 Unrecognized name given to the `sim firmware NAME' command: %s\n\
1080 Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
1090 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1092 sim_monitor (SIM_DESC sd
,
1095 unsigned int reason
)
1098 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
1101 /* The IDT monitor actually allows two instructions per vector
1102 slot. However, the simulator currently causes a trap on each
1103 individual instruction. We cheat, and lose the bottom bit. */
1106 /* The following callback functions are available, however the
1107 monitor we are simulating does not make use of them: get_errno,
1108 isatty, lseek, rename, system, time and unlink */
1112 case 6: /* int open(char *path,int flags) */
1114 char *path
= fetch_str (sd
, A0
);
1115 V0
= sim_io_open (sd
, path
, (int)A1
);
1120 case 7: /* int read(int file,char *ptr,int len) */
1124 char *buf
= zalloc (nr
);
1125 V0
= sim_io_read (sd
, fd
, buf
, nr
);
1126 sim_write (sd
, A1
, buf
, nr
);
1131 case 8: /* int write(int file,char *ptr,int len) */
1135 char *buf
= zalloc (nr
);
1136 sim_read (sd
, A1
, buf
, nr
);
1137 V0
= sim_io_write (sd
, fd
, buf
, nr
);
1142 case 10: /* int close(int file) */
1144 V0
= sim_io_close (sd
, (int)A0
);
1148 case 2: /* Densan monitor: char inbyte(int waitflag) */
1150 if (A0
== 0) /* waitflag == NOWAIT */
1151 V0
= (unsigned_word
)-1;
1153 /* Drop through to case 11 */
1155 case 11: /* char inbyte(void) */
1158 /* ensure that all output has gone... */
1159 sim_io_flush_stdout (sd
);
1160 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
1162 sim_io_error(sd
,"Invalid return from character read");
1163 V0
= (unsigned_word
)-1;
1166 V0
= (unsigned_word
)tmp
;
1170 case 3: /* Densan monitor: void co(char chr) */
1171 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1173 char tmp
= (char)(A0
& 0xFF);
1174 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
1178 case 17: /* void _exit() */
1180 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
1181 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
1182 (unsigned int)(A0
& 0xFFFFFFFF));
1186 case 28 : /* PMON flush_cache */
1189 case 55: /* void get_mem_info(unsigned int *ptr) */
1190 /* in: A0 = pointer to three word memory location */
1191 /* out: [A0 + 0] = size */
1192 /* [A0 + 4] = instruction cache size */
1193 /* [A0 + 8] = data cache size */
1195 unsigned_4 value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
1196 unsigned_4 zero
= 0;
1198 sim_write (sd
, A0
+ 0, (char *)&value
, 4);
1199 sim_write (sd
, A0
+ 4, (char *)&zero
, 4);
1200 sim_write (sd
, A0
+ 8, (char *)&zero
, 4);
1201 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1205 case 158 : /* PMON printf */
1206 /* in: A0 = pointer to format string */
1207 /* A1 = optional argument 1 */
1208 /* A2 = optional argument 2 */
1209 /* A3 = optional argument 3 */
1211 /* The following is based on the PMON printf source */
1213 address_word s
= A0
;
1215 signed_word
*ap
= &A1
; /* 1st argument */
1216 /* This isn't the quickest way, since we call the host print
1217 routine for every character almost. But it does avoid
1218 having to allocate and manage a temporary string buffer. */
1219 /* TODO: Include check that we only use three arguments (A1,
1221 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1226 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1227 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1228 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1230 if (strchr ("dobxXulscefg%", c
))
1245 else if (c
>= '1' && c
<= '9')
1249 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
1252 n
= (unsigned int)strtol(tmp
,NULL
,10);
1265 sim_io_printf (sd
, "%%");
1270 address_word p
= *ap
++;
1272 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
1273 sim_io_printf(sd
, "%c", ch
);
1276 sim_io_printf(sd
,"(null)");
1279 sim_io_printf (sd
, "%c", (int)*ap
++);
1284 sim_read (sd
, s
++, &c
, 1);
1288 sim_read (sd
, s
++, &c
, 1);
1291 if (strchr ("dobxXu", c
))
1293 word64 lv
= (word64
) *ap
++;
1295 sim_io_printf(sd
,"<binary not supported>");
1298 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
1300 sim_io_printf(sd
, tmp
, lv
);
1302 sim_io_printf(sd
, tmp
, (int)lv
);
1305 else if (strchr ("eEfgG", c
))
1307 double dbl
= *(double*)(ap
++);
1308 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
1309 sim_io_printf (sd
, tmp
, dbl
);
1315 sim_io_printf(sd
, "%c", c
);
1321 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1322 reason
, pr_addr(cia
));
1328 /* Store a word into memory. */
1331 store_word (SIM_DESC sd
,
1340 if ((vaddr
& 3) != 0)
1341 SignalExceptionAddressStore ();
1344 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1347 const uword64 mask
= 7;
1351 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1352 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1353 memval
= ((uword64
) val
) << (8 * byte
);
1354 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1360 /* Load a word from memory. */
1363 load_word (SIM_DESC sd
,
1368 if ((vaddr
& 3) != 0)
1370 SIM_CORE_SIGNAL (SD
, cpu
, cia
, read_map
, AccessLength_WORD
+1, vaddr
, read_transfer
, sim_core_unaligned_signal
);
1377 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1380 const uword64 mask
= 0x7;
1381 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1382 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1386 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1387 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1389 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1390 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1397 /* Simulate the mips16 entry and exit pseudo-instructions. These
1398 would normally be handled by the reserved instruction exception
1399 code, but for ease of simulation we just handle them directly. */
1402 mips16_entry (SIM_DESC sd
,
1407 int aregs
, sregs
, rreg
;
1410 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1413 aregs
= (insn
& 0x700) >> 8;
1414 sregs
= (insn
& 0x0c0) >> 6;
1415 rreg
= (insn
& 0x020) >> 5;
1417 /* This should be checked by the caller. */
1426 /* This is the entry pseudo-instruction. */
1428 for (i
= 0; i
< aregs
; i
++)
1429 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1437 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1440 for (i
= 0; i
< sregs
; i
++)
1443 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1451 /* This is the exit pseudo-instruction. */
1458 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1461 for (i
= 0; i
< sregs
; i
++)
1464 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1469 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1473 FGR
[0] = WORD64LO (GPR
[4]);
1474 FPR_STATE
[0] = fmt_uninterpreted
;
1476 else if (aregs
== 6)
1478 FGR
[0] = WORD64LO (GPR
[5]);
1479 FGR
[1] = WORD64LO (GPR
[4]);
1480 FPR_STATE
[0] = fmt_uninterpreted
;
1481 FPR_STATE
[1] = fmt_uninterpreted
;
1490 /*-- trace support ----------------------------------------------------------*/
1492 /* The TRACE support is provided (if required) in the memory accessing
1493 routines. Since we are also providing the architecture specific
1494 features, the architecture simulation code can also deal with
1495 notifying the TRACE world of cache flushes, etc. Similarly we do
1496 not need to provide profiling support in the simulator engine,
1497 since we can sample in the instruction fetch control loop. By
1498 defining the TRACE manifest, we add tracing as a run-time
1502 /* Tracing by default produces "din" format (as required by
1503 dineroIII). Each line of such a trace file *MUST* have a din label
1504 and address field. The rest of the line is ignored, so comments can
1505 be included if desired. The first field is the label which must be
1506 one of the following values:
1511 3 escape record (treated as unknown access type)
1512 4 escape record (causes cache flush)
1514 The address field is a 32bit (lower-case) hexadecimal address
1515 value. The address should *NOT* be preceded by "0x".
1517 The size of the memory transfer is not important when dealing with
1518 cache lines (as long as no more than a cache line can be
1519 transferred in a single operation :-), however more information
1520 could be given following the dineroIII requirement to allow more
1521 complete memory and cache simulators to provide better
1522 results. i.e. the University of Pisa has a cache simulator that can
1523 also take bus size and speed as (variable) inputs to calculate
1524 complete system performance (a much more useful ability when trying
1525 to construct an end product, rather than a processor). They
1526 currently have an ARM version of their tool called ChARM. */
1530 dotrace (SIM_DESC sd
,
1538 if (STATE
& simTRACE
) {
1540 fprintf(tracefh
,"%d %s ; width %d ; ",
1544 va_start(ap
,comment
);
1545 vfprintf(tracefh
,comment
,ap
);
1547 fprintf(tracefh
,"\n");
1549 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1550 we may be generating 64bit ones, we should put the hi-32bits of the
1551 address into the comment field. */
1553 /* TODO: Provide a buffer for the trace lines. We can then avoid
1554 performing writes until the buffer is filled, or the file is
1557 /* NOTE: We could consider adding a comment field to the "din" file
1558 produced using type 3 markers (unknown access). This would then
1559 allow information about the program that the "din" is for, and
1560 the MIPs world that was being simulated, to be placed into the
1567 /*---------------------------------------------------------------------------*/
1568 /*-- simulator engine -------------------------------------------------------*/
1569 /*---------------------------------------------------------------------------*/
1572 ColdReset (SIM_DESC sd
)
1575 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1577 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1578 /* RESET: Fixed PC address: */
1579 PC
= (unsigned_word
) UNSIGNED64 (0xFFFFFFFFBFC00000);
1580 /* The reset vector address is in the unmapped, uncached memory space. */
1582 SR
&= ~(status_SR
| status_TS
| status_RP
);
1583 SR
|= (status_ERL
| status_BEV
);
1585 /* Cheat and allow access to the complete register set immediately */
1586 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1587 && WITH_TARGET_WORD_BITSIZE
== 64)
1588 SR
|= status_FR
; /* 64bit registers */
1590 /* Ensure that any instructions with pending register updates are
1592 PENDING_INVALIDATE();
1594 /* Initialise the FPU registers to the unknown state */
1595 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1598 for (rn
= 0; (rn
< 32); rn
++)
1599 FPR_STATE
[rn
] = fmt_uninterpreted
;
1608 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1609 /* Signal an exception condition. This will result in an exception
1610 that aborts the instruction. The instruction operation pseudocode
1611 will never see a return from this function call. */
1614 signal_exception (SIM_DESC sd
,
1622 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1625 /* Ensure that any active atomic read/modify/write operation will fail: */
1628 /* Save registers before interrupt dispatching */
1629 #ifdef SIM_CPU_EXCEPTION_TRIGGER
1630 SIM_CPU_EXCEPTION_TRIGGER(sd
, cpu
, cia
);
1633 switch (exception
) {
1635 case DebugBreakPoint
:
1636 if (! (Debug
& Debug_DM
))
1642 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1643 DEPC
= cia
- 4; /* reference the branch instruction */
1647 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1651 Debug
|= Debug_DM
; /* in debugging mode */
1652 Debug
|= Debug_DBp
; /* raising a DBp exception */
1654 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1658 case ReservedInstruction
:
1661 unsigned int instruction
;
1662 va_start(ap
,exception
);
1663 instruction
= va_arg(ap
,unsigned int);
1665 /* Provide simple monitor support using ReservedInstruction
1666 exceptions. The following code simulates the fixed vector
1667 entry points into the IDT monitor by causing a simulator
1668 trap, performing the monitor operation, and returning to
1669 the address held in the $ra register (standard PCS return
1670 address). This means we only need to pre-load the vector
1671 space with suitable instruction values. For systems were
1672 actual trap instructions are used, we would not need to
1673 perform this magic. */
1674 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1676 sim_monitor (SD
, CPU
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1677 /* NOTE: This assumes that a branch-and-link style
1678 instruction was used to enter the vector (which is the
1679 case with the current IDT monitor). */
1680 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1682 /* Look for the mips16 entry and exit instructions, and
1683 simulate a handler for them. */
1684 else if ((cia
& 1) != 0
1685 && (instruction
& 0xf81f) == 0xe809
1686 && (instruction
& 0x0c0) != 0x0c0)
1688 mips16_entry (SD
, CPU
, cia
, instruction
);
1689 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1691 /* else fall through to normal exception processing */
1692 sim_io_eprintf(sd
,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia
));
1696 /* Store exception code into current exception id variable (used
1699 /* TODO: If not simulating exceptions then stop the simulator
1700 execution. At the moment we always stop the simulation. */
1702 #ifdef SUBTARGET_R3900
1703 /* update interrupt-related registers */
1705 /* insert exception code in bits 6:2 */
1706 CAUSE
= LSMASKED32(CAUSE
, 31, 7) | LSINSERTED32(exception
, 6, 2);
1707 /* shift IE/KU history bits left */
1708 SR
= LSMASKED32(SR
, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR
, 3, 0), 5, 2);
1710 if (STATE
& simDELAYSLOT
)
1712 STATE
&= ~simDELAYSLOT
;
1714 EPC
= (cia
- 4); /* reference the branch instruction */
1719 if (SR
& status_BEV
)
1720 PC
= (signed)0xBFC00000 + 0x180;
1722 PC
= (signed)0x80000000 + 0x080;
1724 /* See figure 5-17 for an outline of the code below */
1725 if (! (SR
& status_EXL
))
1727 CAUSE
= (exception
<< 2);
1728 if (STATE
& simDELAYSLOT
)
1730 STATE
&= ~simDELAYSLOT
;
1732 EPC
= (cia
- 4); /* reference the branch instruction */
1736 /* FIXME: TLB et.al. */
1737 /* vector = 0x180; */
1741 CAUSE
= (exception
<< 2);
1742 /* vector = 0x180; */
1745 /* Store exception code into current exception id variable (used
1748 if (SR
& status_BEV
)
1749 PC
= (signed)0xBFC00200 + 0x180;
1751 PC
= (signed)0x80000000 + 0x180;
1754 switch ((CAUSE
>> 2) & 0x1F)
1757 /* Interrupts arrive during event processing, no need to
1763 #ifdef SUBTARGET_3900
1764 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1765 PC
= (signed)0xBFC00000;
1766 #endif SUBTARGET_3900
1769 case TLBModification
:
1774 case InstructionFetch
:
1776 /* The following is so that the simulator will continue from the
1777 exception handler address. */
1778 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1779 sim_stopped
, SIM_SIGBUS
);
1781 case ReservedInstruction
:
1782 case CoProcessorUnusable
:
1784 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1785 sim_stopped
, SIM_SIGILL
);
1787 case IntegerOverflow
:
1789 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1790 sim_stopped
, SIM_SIGFPE
);
1793 sim_engine_halt (SD
, CPU
, NULL
, PC
, sim_stopped
, SIM_SIGTRAP
);
1798 sim_engine_restart (SD
, CPU
, NULL
, PC
);
1803 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1804 sim_stopped
, SIM_SIGTRAP
);
1806 default : /* Unknown internal exception */
1808 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1809 sim_stopped
, SIM_SIGABRT
);
1813 case SimulatorFault
:
1817 va_start(ap
,exception
);
1818 msg
= va_arg(ap
,char *);
1820 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1821 "FATAL: Simulator error \"%s\"\n",msg
);
1830 #if defined(WARN_RESULT)
1831 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1832 /* This function indicates that the result of the operation is
1833 undefined. However, this should not affect the instruction
1834 stream. All that is meant to happen is that the destination
1835 register is set to an undefined result. To keep the simulator
1836 simple, we just don't bother updating the destination register, so
1837 the overall result will be undefined. If desired we can stop the
1838 simulator by raising a pseudo-exception. */
1839 #define UndefinedResult() undefined_result (sd,cia)
1841 undefined_result(sd
,cia
)
1845 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
1846 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1851 #endif /* WARN_RESULT */
1853 /*-- FPU support routines ---------------------------------------------------*/
1855 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1856 formats conform to ANSI/IEEE Std 754-1985. */
1857 /* SINGLE precision floating:
1858 * seeeeeeeefffffffffffffffffffffff
1860 * e = 8bits = exponent
1861 * f = 23bits = fraction
1863 /* SINGLE precision fixed:
1864 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1866 * i = 31bits = integer
1868 /* DOUBLE precision floating:
1869 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1871 * e = 11bits = exponent
1872 * f = 52bits = fraction
1874 /* DOUBLE precision fixed:
1875 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1877 * i = 63bits = integer
1880 /* Extract sign-bit: */
1881 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
1882 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
1883 /* Extract biased exponent: */
1884 #define FP_S_be(v) (((v) >> 23) & 0xFF)
1885 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
1886 /* Extract unbiased Exponent: */
1887 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
1888 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1889 /* Extract complete fraction field: */
1890 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
1891 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
1892 /* Extract numbered fraction bit: */
1893 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1894 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1896 /* Explicit QNaN values used when value required: */
1897 #define FPQNaN_SINGLE (0x7FBFFFFF)
1898 #define FPQNaN_WORD (0x7FFFFFFF)
1899 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1900 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
1902 /* Explicit Infinity values used when required: */
1903 #define FPINF_SINGLE (0x7F800000)
1904 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
1906 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1907 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : (((v) == fmt_uninterpreted_32) ? "<uninterpreted_32>" : (((v) == fmt_uninterpreted_64) ? "<uninterpreted_64>" : "<format error>"))))))))
1910 value_fpr (SIM_DESC sd
,
1919 /* Treat unused register values, as fixed-point 64bit values: */
1920 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
1922 /* If request to read data as "uninterpreted", then use the current
1924 fmt
= FPR_STATE
[fpr
];
1929 /* For values not yet accessed, set to the desired format: */
1930 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
1931 FPR_STATE
[fpr
] = fmt
;
1933 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
1936 if (fmt
!= FPR_STATE
[fpr
]) {
1937 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
1938 FPR_STATE
[fpr
] = fmt_unknown
;
1941 if (FPR_STATE
[fpr
] == fmt_unknown
) {
1942 /* Set QNaN value: */
1945 value
= FPQNaN_SINGLE
;
1949 value
= FPQNaN_DOUBLE
;
1953 value
= FPQNaN_WORD
;
1957 value
= FPQNaN_LONG
;
1964 } else if (SizeFGR() == 64) {
1968 value
= (FGR
[fpr
] & 0xFFFFFFFF);
1971 case fmt_uninterpreted
:
1985 value
= (FGR
[fpr
] & 0xFFFFFFFF);
1988 case fmt_uninterpreted
:
1991 if ((fpr
& 1) == 0) { /* even registers only */
1993 printf("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n",
1994 fpr
+1, pr_uword64( (uword64
) FGR
[fpr
+1] ),
1995 fpr
, pr_uword64( (uword64
) FGR
[fpr
] ));
1997 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
1999 SignalException(ReservedInstruction
,0);
2010 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2013 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_uword64(value
),pr_addr(cia
),SizeFGR());
2020 store_fpr (SIM_DESC sd
,
2030 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d,\n",fpr
,DOFMT(fmt
),pr_uword64(value
),pr_addr(cia
),SizeFGR());
2033 if (SizeFGR() == 64) {
2035 case fmt_uninterpreted_32
:
2036 fmt
= fmt_uninterpreted
;
2039 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2040 FPR_STATE
[fpr
] = fmt
;
2043 case fmt_uninterpreted_64
:
2044 fmt
= fmt_uninterpreted
;
2045 case fmt_uninterpreted
:
2049 FPR_STATE
[fpr
] = fmt
;
2053 FPR_STATE
[fpr
] = fmt_unknown
;
2059 case fmt_uninterpreted_32
:
2060 fmt
= fmt_uninterpreted
;
2063 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2064 FPR_STATE
[fpr
] = fmt
;
2067 case fmt_uninterpreted_64
:
2068 fmt
= fmt_uninterpreted
;
2069 case fmt_uninterpreted
:
2072 if ((fpr
& 1) == 0) { /* even register number only */
2073 FGR
[fpr
+1] = (value
>> 32);
2074 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2075 FPR_STATE
[fpr
+ 1] = fmt
;
2076 FPR_STATE
[fpr
] = fmt
;
2078 FPR_STATE
[fpr
] = fmt_unknown
;
2079 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2080 SignalException(ReservedInstruction
,0);
2085 FPR_STATE
[fpr
] = fmt_unknown
;
2090 #if defined(WARN_RESULT)
2093 #endif /* WARN_RESULT */
2096 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2099 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_uword64(FGR
[fpr
]),DOFMT(fmt
));
2116 sim_fpu_32to (&wop
, op
);
2117 boolean
= sim_fpu_is_nan (&wop
);
2124 sim_fpu_64to (&wop
, op
);
2125 boolean
= sim_fpu_is_nan (&wop
);
2129 fprintf (stderr
, "Bad switch\n");
2134 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2148 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2155 sim_fpu_32to (&wop
, op
);
2156 boolean
= sim_fpu_is_infinity (&wop
);
2162 sim_fpu_64to (&wop
, op
);
2163 boolean
= sim_fpu_is_infinity (&wop
);
2167 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2172 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2186 /* Argument checking already performed by the FPCOMPARE code */
2189 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2192 /* The format type should already have been checked: */
2198 sim_fpu_32to (&wop1
, op1
);
2199 sim_fpu_32to (&wop2
, op2
);
2200 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2207 sim_fpu_64to (&wop1
, op1
);
2208 sim_fpu_64to (&wop2
, op2
);
2209 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2213 fprintf (stderr
, "Bad switch\n");
2218 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2232 /* Argument checking already performed by the FPCOMPARE code */
2235 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2238 /* The format type should already have been checked: */
2244 sim_fpu_32to (&wop1
, op1
);
2245 sim_fpu_32to (&wop2
, op2
);
2246 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2253 sim_fpu_64to (&wop1
, op1
);
2254 sim_fpu_64to (&wop2
, op2
);
2255 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2259 fprintf (stderr
, "Bad switch\n");
2264 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2271 AbsoluteValue(op
,fmt
)
2278 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2281 /* The format type should already have been checked: */
2287 sim_fpu_32to (&wop
, op
);
2288 sim_fpu_abs (&wop
, &wop
);
2289 sim_fpu_to32 (&ans
, &wop
);
2297 sim_fpu_64to (&wop
, op
);
2298 sim_fpu_abs (&wop
, &wop
);
2299 sim_fpu_to64 (&ans
, &wop
);
2304 fprintf (stderr
, "Bad switch\n");
2319 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2322 /* The format type should already have been checked: */
2328 sim_fpu_32to (&wop
, op
);
2329 sim_fpu_neg (&wop
, &wop
);
2330 sim_fpu_to32 (&ans
, &wop
);
2338 sim_fpu_64to (&wop
, op
);
2339 sim_fpu_neg (&wop
, &wop
);
2340 sim_fpu_to64 (&ans
, &wop
);
2345 fprintf (stderr
, "Bad switch\n");
2361 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2364 /* The registers must specify FPRs valid for operands of type
2365 "fmt". If they are not valid, the result is undefined. */
2367 /* The format type should already have been checked: */
2375 sim_fpu_32to (&wop1
, op1
);
2376 sim_fpu_32to (&wop2
, op2
);
2377 sim_fpu_add (&ans
, &wop1
, &wop2
);
2378 sim_fpu_to32 (&res
, &ans
);
2388 sim_fpu_64to (&wop1
, op1
);
2389 sim_fpu_64to (&wop2
, op2
);
2390 sim_fpu_add (&ans
, &wop1
, &wop2
);
2391 sim_fpu_to64 (&res
, &ans
);
2396 fprintf (stderr
, "Bad switch\n");
2401 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2416 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2419 /* The registers must specify FPRs valid for operands of type
2420 "fmt". If they are not valid, the result is undefined. */
2422 /* The format type should already have been checked: */
2430 sim_fpu_32to (&wop1
, op1
);
2431 sim_fpu_32to (&wop2
, op2
);
2432 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2433 sim_fpu_to32 (&res
, &ans
);
2443 sim_fpu_64to (&wop1
, op1
);
2444 sim_fpu_64to (&wop2
, op2
);
2445 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2446 sim_fpu_to64 (&res
, &ans
);
2451 fprintf (stderr
, "Bad switch\n");
2456 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2463 Multiply(op1
,op2
,fmt
)
2471 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2474 /* The registers must specify FPRs valid for operands of type
2475 "fmt". If they are not valid, the result is undefined. */
2477 /* The format type should already have been checked: */
2485 sim_fpu_32to (&wop1
, op1
);
2486 sim_fpu_32to (&wop2
, op2
);
2487 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2488 sim_fpu_to32 (&res
, &ans
);
2498 sim_fpu_64to (&wop1
, op1
);
2499 sim_fpu_64to (&wop2
, op2
);
2500 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2501 sim_fpu_to64 (&res
, &ans
);
2506 fprintf (stderr
, "Bad switch\n");
2511 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2526 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2529 /* The registers must specify FPRs valid for operands of type
2530 "fmt". If they are not valid, the result is undefined. */
2532 /* The format type should already have been checked: */
2540 sim_fpu_32to (&wop1
, op1
);
2541 sim_fpu_32to (&wop2
, op2
);
2542 sim_fpu_div (&ans
, &wop1
, &wop2
);
2543 sim_fpu_to32 (&res
, &ans
);
2553 sim_fpu_64to (&wop1
, op1
);
2554 sim_fpu_64to (&wop2
, op2
);
2555 sim_fpu_div (&ans
, &wop1
, &wop2
);
2556 sim_fpu_to64 (&res
, &ans
);
2561 fprintf (stderr
, "Bad switch\n");
2566 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2580 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2583 /* The registers must specify FPRs valid for operands of type
2584 "fmt". If they are not valid, the result is undefined. */
2586 /* The format type should already have been checked: */
2593 sim_fpu_32to (&wop
, op
);
2594 sim_fpu_inv (&ans
, &wop
);
2595 sim_fpu_to32 (&res
, &ans
);
2604 sim_fpu_64to (&wop
, op
);
2605 sim_fpu_inv (&ans
, &wop
);
2606 sim_fpu_to64 (&res
, &ans
);
2611 fprintf (stderr
, "Bad switch\n");
2616 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2630 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2633 /* The registers must specify FPRs valid for operands of type
2634 "fmt". If they are not valid, the result is undefined. */
2636 /* The format type should already have been checked: */
2643 sim_fpu_32to (&wop
, op
);
2644 sim_fpu_sqrt (&ans
, &wop
);
2645 sim_fpu_to32 (&res
, &ans
);
2654 sim_fpu_64to (&wop
, op
);
2655 sim_fpu_sqrt (&ans
, &wop
);
2656 sim_fpu_to64 (&res
, &ans
);
2661 fprintf (stderr
, "Bad switch\n");
2666 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2682 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2685 /* The registers must specify FPRs valid for operands of type
2686 "fmt". If they are not valid, the result is undefined. */
2688 /* The format type should already have been checked: */
2695 sim_fpu_32to (&wop1
, op1
);
2696 sim_fpu_32to (&wop2
, op2
);
2697 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2704 sim_fpu_64to (&wop1
, op1
);
2705 sim_fpu_64to (&wop2
, op2
);
2706 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2710 fprintf (stderr
, "Bad switch\n");
2716 case SIM_FPU_IS_SNAN
:
2717 case SIM_FPU_IS_QNAN
:
2719 case SIM_FPU_IS_NINF
:
2720 case SIM_FPU_IS_NNUMBER
:
2721 case SIM_FPU_IS_NDENORM
:
2722 case SIM_FPU_IS_NZERO
:
2723 result
= op2
; /* op1 - op2 < 0 */
2724 case SIM_FPU_IS_PINF
:
2725 case SIM_FPU_IS_PNUMBER
:
2726 case SIM_FPU_IS_PDENORM
:
2727 case SIM_FPU_IS_PZERO
:
2728 result
= op1
; /* op1 - op2 > 0 */
2730 fprintf (stderr
, "Bad switch\n");
2735 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2752 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2755 /* The registers must specify FPRs valid for operands of type
2756 "fmt". If they are not valid, the result is undefined. */
2758 /* The format type should already have been checked: */
2765 sim_fpu_32to (&wop1
, op1
);
2766 sim_fpu_32to (&wop2
, op2
);
2767 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2774 sim_fpu_64to (&wop1
, op1
);
2775 sim_fpu_64to (&wop2
, op2
);
2776 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2780 fprintf (stderr
, "Bad switch\n");
2786 case SIM_FPU_IS_SNAN
:
2787 case SIM_FPU_IS_QNAN
:
2789 case SIM_FPU_IS_NINF
:
2790 case SIM_FPU_IS_NNUMBER
:
2791 case SIM_FPU_IS_NDENORM
:
2792 case SIM_FPU_IS_NZERO
:
2793 result
= op1
; /* op1 - op2 < 0 */
2794 case SIM_FPU_IS_PINF
:
2795 case SIM_FPU_IS_PNUMBER
:
2796 case SIM_FPU_IS_PDENORM
:
2797 case SIM_FPU_IS_PZERO
:
2798 result
= op2
; /* op1 - op2 > 0 */
2800 fprintf (stderr
, "Bad switch\n");
2805 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2813 convert (SIM_DESC sd
,
2822 sim_fpu_round round
;
2823 unsigned32 result32
;
2824 unsigned64 result64
;
2827 #if 0 /* FIXME: doesn't compile */
2828 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
2835 /* Round result to nearest representable value. When two
2836 representable values are equally near, round to the value
2837 that has a least significant bit of zero (i.e. is even). */
2838 round
= sim_fpu_round_near
;
2841 /* Round result to the value closest to, and not greater in
2842 magnitude than, the result. */
2843 round
= sim_fpu_round_zero
;
2846 /* Round result to the value closest to, and not less than,
2848 round
= sim_fpu_round_up
;
2852 /* Round result to the value closest to, and not greater than,
2854 round
= sim_fpu_round_down
;
2858 fprintf (stderr
, "Bad switch\n");
2862 /* Convert the input to sim_fpu internal format */
2866 sim_fpu_64to (&wop
, op
);
2869 sim_fpu_32to (&wop
, op
);
2872 sim_fpu_i32to (&wop
, op
, round
);
2875 sim_fpu_i64to (&wop
, op
, round
);
2878 fprintf (stderr
, "Bad switch\n");
2882 /* Convert sim_fpu format into the output */
2883 /* The value WOP is converted to the destination format, rounding
2884 using mode RM. When the destination is a fixed-point format, then
2885 a source value of Infinity, NaN or one which would round to an
2886 integer outside the fixed point range then an IEEE Invalid
2887 Operation condition is raised. */
2891 sim_fpu_round_32 (&wop
, round
, 0);
2892 sim_fpu_to32 (&result32
, &wop
);
2893 result64
= result32
;
2896 sim_fpu_round_64 (&wop
, round
, 0);
2897 sim_fpu_to64 (&result64
, &wop
);
2900 sim_fpu_to32i (&result32
, &wop
, round
);
2901 result64
= result32
;
2904 sim_fpu_to64i (&result64
, &wop
, round
);
2908 fprintf (stderr
, "Bad switch\n");
2913 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
2920 /*-- co-processor support routines ------------------------------------------*/
2923 CoProcPresent(unsigned int coproc_number
)
2925 /* Return TRUE if simulator provides a model for the given co-processor number */
2930 cop_lw (SIM_DESC sd
,
2935 unsigned int memword
)
2940 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2943 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
2945 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
2946 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
2951 #if 0 /* this should be controlled by a configuration option */
2952 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
2961 cop_ld (SIM_DESC sd
,
2970 printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num
, coproc_reg
, pr_uword64(memword
), pr_addr(cia
) );
2973 switch (coproc_num
) {
2975 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2977 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
2982 #if 0 /* this message should be controlled by a configuration option */
2983 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
2995 cop_sw (SIM_DESC sd
,
3001 unsigned int value
= 0;
3006 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3009 hold
= FPR_STATE
[coproc_reg
];
3010 FPR_STATE
[coproc_reg
] = fmt_word
;
3011 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
3012 FPR_STATE
[coproc_reg
] = hold
;
3017 #if 0 /* should be controlled by configuration option */
3018 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3027 cop_sd (SIM_DESC sd
,
3037 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3039 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
3044 #if 0 /* should be controlled by configuration option */
3045 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3057 decode_coproc (SIM_DESC sd
,
3060 unsigned int instruction
)
3062 int coprocnum
= ((instruction
>> 26) & 3);
3066 case 0: /* standard CPU control and cache registers */
3068 int code
= ((instruction
>> 21) & 0x1F);
3069 int rt
= ((instruction
>> 16) & 0x1F);
3070 int rd
= ((instruction
>> 11) & 0x1F);
3071 int tail
= instruction
& 0x3ff;
3072 /* R4000 Users Manual (second edition) lists the following CP0
3074 CODE><-RT><RD-><--TAIL--->
3075 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3076 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3077 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3078 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3079 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3080 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3081 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3082 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3083 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3084 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3086 if (((code
== 0x00) || (code
== 0x04)) && tail
== 0)
3088 /* M[TF]C0 - 32 bit word */
3090 switch (rd
) /* NOTEs: Standard CP0 registers */
3092 /* 0 = Index R4000 VR4100 VR4300 */
3093 /* 1 = Random R4000 VR4100 VR4300 */
3094 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3095 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3096 /* 4 = Context R4000 VR4100 VR4300 */
3097 /* 5 = PageMask R4000 VR4100 VR4300 */
3098 /* 6 = Wired R4000 VR4100 VR4300 */
3099 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3100 /* 9 = Count R4000 VR4100 VR4300 */
3101 /* 10 = EntryHi R4000 VR4100 VR4300 */
3102 /* 11 = Compare R4000 VR4100 VR4300 */
3103 /* 12 = SR R4000 VR4100 VR4300 */
3104 #ifdef SUBTARGET_R3900
3106 /* 3 = Config R3900 */
3108 /* 7 = Cache R3900 */
3110 /* 15 = PRID R3900 */
3116 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3118 GPR
[rt
] = COP0_BADVADDR
;
3120 COP0_BADVADDR
= GPR
[rt
];
3123 #endif /* SUBTARGET_R3900 */
3130 /* 13 = Cause R4000 VR4100 VR4300 */
3137 /* 14 = EPC R4000 VR4100 VR4300 */
3140 GPR
[rt
] = (signed_word
) (signed_address
) EPC
;
3144 /* 15 = PRId R4000 VR4100 VR4300 */
3145 #ifdef SUBTARGET_R3900
3154 /* 16 = Config R4000 VR4100 VR4300 */
3157 GPR
[rt
] = C0_CONFIG
;
3159 C0_CONFIG
= GPR
[rt
];
3162 #ifdef SUBTARGET_R3900
3171 /* 17 = LLAddr R4000 VR4100 VR4300 */
3173 /* 18 = WatchLo R4000 VR4100 VR4300 */
3174 /* 19 = WatchHi R4000 VR4100 VR4300 */
3175 /* 20 = XContext R4000 VR4100 VR4300 */
3176 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3177 /* 27 = CacheErr R4000 VR4100 */
3178 /* 28 = TagLo R4000 VR4100 VR4300 */
3179 /* 29 = TagHi R4000 VR4100 VR4300 */
3180 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3181 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3182 /* CPR[0,rd] = GPR[rt]; */
3185 GPR
[rt
] = (signed_word
) (signed32
) COP0_GPR
[rd
];
3187 COP0_GPR
[rd
] = GPR
[rt
];
3190 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt
,rd
, (unsigned)cia
);
3192 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt
,rd
, (unsigned)cia
);
3196 else if (code
== 0x10 && (tail
& 0x3f) == 0x18)
3199 if (SR
& status_ERL
)
3201 /* Oops, not yet available */
3202 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3212 else if (code
== 0x10 && (tail
& 0x3f) == 0x10)
3215 #ifdef SUBTARGET_R3900
3216 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
3218 /* shift IE/KU history bits right */
3219 SR
= LSMASKED32(SR
, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR
, 5, 2), 3, 0);
3221 /* TODO: CACHE register */
3222 #endif /* SUBTARGET_R3900 */
3224 else if (code
== 0x10 && (tail
& 0x3f) == 0x1F)
3232 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3233 /* TODO: When executing an ERET or RFE instruction we should
3234 clear LLBIT, to ensure that any out-standing atomic
3235 read/modify/write sequence fails. */
3239 case 2: /* co-processor 2 */
3246 sim_io_eprintf(sd
, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
3247 instruction
,pr_addr(cia
));
3252 case 1: /* should not occur (FPU co-processor) */
3253 case 3: /* should not occur (FPU co-processor) */
3254 SignalException(ReservedInstruction
,instruction
);
3262 /* This code copied from gdb's utils.c. Would like to share this code,
3263 but don't know of a common place where both could get to it. */
3265 /* Temporary storage using circular buffer */
3271 static char buf
[NUMCELLS
][CELLSIZE
];
3273 if (++cell
>=NUMCELLS
) cell
=0;
3277 /* Print routines to handle variable size regs, etc */
3279 /* Eliminate warning from compiler on 32-bit systems */
3280 static int thirty_two
= 32;
3286 char *paddr_str
=get_cell();
3287 switch (sizeof(addr
))
3290 sprintf(paddr_str
,"%08lx%08lx",
3291 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3294 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3297 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3300 sprintf(paddr_str
,"%x",addr
);
3309 char *paddr_str
=get_cell();
3310 sprintf(paddr_str
,"%08lx%08lx",
3311 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3317 mips_core_signal (SIM_DESC sd
,
3323 transfer_type transfer
,
3324 sim_core_signals sig
)
3326 const char *copy
= (transfer
== read_transfer
? "read" : "write");
3327 address_word ip
= CIA_ADDR (cia
);
3331 case sim_core_unmapped_signal
:
3332 sim_io_eprintf (sd
, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
3334 (unsigned long) addr
, (unsigned long) ip
);
3335 COP0_BADVADDR
= addr
;
3336 SignalExceptionDataReference();
3339 case sim_core_unaligned_signal
:
3340 sim_io_eprintf (sd
, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
3342 (unsigned long) addr
, (unsigned long) ip
);
3343 COP0_BADVADDR
= addr
;
3344 if(transfer
== read_transfer
)
3345 SignalExceptionAddressLoad();
3347 SignalExceptionAddressStore();
3351 sim_engine_abort (sd
, cpu
, cia
,
3352 "mips_core_signal - internal error - bad switch");
3358 mips_cpu_exception_trigger(SIM_DESC sd
, sim_cpu
* cpu
, address_word cia
)
3360 ASSERT(cpu
!= NULL
);
3362 if(cpu
->exc_suspended
> 0)
3363 sim_io_eprintf(sd
, "Warning, nested exception triggered (%d)\n", cpu
->exc_suspended
);
3366 memcpy(cpu
->exc_trigger_registers
, cpu
->registers
, sizeof(cpu
->exc_trigger_registers
));
3367 cpu
->exc_suspended
= 0;
3371 mips_cpu_exception_suspend(SIM_DESC sd
, sim_cpu
* cpu
, int exception
)
3373 ASSERT(cpu
!= NULL
);
3375 if(cpu
->exc_suspended
> 0)
3376 sim_io_eprintf(sd
, "Warning, nested exception signal (%d then %d)\n",
3377 cpu
->exc_suspended
, exception
);
3379 memcpy(cpu
->exc_suspend_registers
, cpu
->registers
, sizeof(cpu
->exc_suspend_registers
));
3380 memcpy(cpu
->registers
, cpu
->exc_trigger_registers
, sizeof(cpu
->registers
));
3381 cpu
->exc_suspended
= exception
;
3385 mips_cpu_exception_resume(SIM_DESC sd
, sim_cpu
* cpu
, int exception
)
3387 ASSERT(cpu
!= NULL
);
3389 if(exception
== 0 && cpu
->exc_suspended
> 0)
3391 /* warn not for breakpoints */
3392 if(cpu
->exc_suspended
!= sim_signal_to_host(sd
, SIM_SIGTRAP
))
3393 sim_io_eprintf(sd
, "Warning, resuming but ignoring pending exception signal (%d)\n",
3394 cpu
->exc_suspended
);
3396 else if(exception
!= 0 && cpu
->exc_suspended
> 0)
3398 if(exception
!= cpu
->exc_suspended
)
3399 sim_io_eprintf(sd
, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
3400 cpu
->exc_suspended
, exception
);
3402 memcpy(cpu
->registers
, cpu
->exc_suspend_registers
, sizeof(cpu
->registers
));
3404 else if(exception
!= 0 && cpu
->exc_suspended
== 0)
3406 sim_io_eprintf(sd
, "Warning, ignoring spontanous exception signal (%d)\n", exception
);
3408 cpu
->exc_suspended
= 0;
3412 /*---------------------------------------------------------------------------*/
3413 /*> EOF interp.c <*/