2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
21 The IDT monitor (found on the VR4300 board), seems to lie about
22 register contents. It seems to treat the registers as sign-extended
23 32-bit values. This cause *REAL* problems when single-stepping 64-bit
28 /* The TRACE manifests enable the provision of extra features. If they
29 are not defined then a simpler (quicker) simulator is constructed
30 without the required run-time checks, etc. */
31 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
37 #include "sim-utils.h"
38 #include "sim-options.h"
39 #include "sim-assert.h"
65 #include "libiberty.h"
67 #include "callback.h" /* GDB simulator callback interface */
68 #include "remote-sim.h" /* GDB simulator interface */
76 char* pr_addr
PARAMS ((SIM_ADDR addr
));
77 char* pr_uword64
PARAMS ((uword64 addr
));
80 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
85 /* The following reserved instruction value is used when a simulator
86 trap is required. NOTE: Care must be taken, since this value may be
87 used in later revisions of the MIPS ISA. */
89 #define RSVD_INSTRUCTION (0x00000005)
90 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
92 #define RSVD_INSTRUCTION_ARG_SHIFT 6
93 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
96 /* Bits in the Debug register */
97 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
98 #define Debug_DM 0x40000000 /* Debug Mode */
99 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
101 /*---------------------------------------------------------------------------*/
102 /*-- GDB simulator interface ------------------------------------------------*/
103 /*---------------------------------------------------------------------------*/
105 static void ColdReset
PARAMS((SIM_DESC sd
));
107 /*---------------------------------------------------------------------------*/
111 #define DELAYSLOT() {\
112 if (STATE & simDELAYSLOT)\
113 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
114 STATE |= simDELAYSLOT;\
117 #define JALDELAYSLOT() {\
119 STATE |= simJALDELAYSLOT;\
123 STATE &= ~simDELAYSLOT;\
124 STATE |= simSKIPNEXT;\
127 #define CANCELDELAYSLOT() {\
129 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
132 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
133 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
135 #define K0BASE (0x80000000)
136 #define K0SIZE (0x20000000)
137 #define K1BASE (0xA0000000)
138 #define K1SIZE (0x20000000)
139 #define MONITOR_BASE (0xBFC00000)
140 #define MONITOR_SIZE (1 << 11)
141 #define MEM_SIZE (2 << 20)
145 static char *tracefile
= "trace.din"; /* default filename for trace log */
146 FILE *tracefh
= NULL
;
147 static void open_trace
PARAMS((SIM_DESC sd
));
150 static const char * get_insn_name (sim_cpu
*, int);
152 /* simulation target board. NULL=canonical */
153 static char* board
= NULL
;
156 static DECLARE_OPTION_HANDLER (mips_option_handler
);
159 OPTION_DINERO_TRACE
= OPTION_START
,
166 mips_option_handler (sd
, cpu
, opt
, arg
, is_command
)
176 case OPTION_DINERO_TRACE
: /* ??? */
178 /* Eventually the simTRACE flag could be treated as a toggle, to
179 allow external control of the program points being traced
180 (i.e. only from main onwards, excluding the run-time setup,
182 for (cpu_nr
= 0; cpu_nr
< MAX_NR_PROCESSORS
; cpu_nr
++)
184 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
187 else if (strcmp (arg
, "yes") == 0)
189 else if (strcmp (arg
, "no") == 0)
191 else if (strcmp (arg
, "on") == 0)
193 else if (strcmp (arg
, "off") == 0)
197 fprintf (stderr
, "Unrecognized dinero-trace option `%s'\n", arg
);
204 Simulator constructed without dinero tracing support (for performance).\n\
205 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
209 case OPTION_DINERO_FILE
:
211 if (optarg
!= NULL
) {
213 tmp
= (char *)malloc(strlen(optarg
) + 1);
216 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
222 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
232 board
= zalloc(strlen(arg
) + 1);
243 static const OPTION mips_options
[] =
245 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
246 '\0', "on|off", "Enable dinero tracing",
247 mips_option_handler
},
248 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
249 '\0', "FILE", "Write dinero trace to FILE",
250 mips_option_handler
},
251 { {"board", required_argument
, NULL
, OPTION_BOARD
},
252 '\0', "none" /* rely on compile-time string concatenation for other options */
254 #define BOARD_JMR3904 "jmr3904"
256 #define BOARD_JMR3904_PAL "jmr3904pal"
257 "|" BOARD_JMR3904_PAL
258 #define BOARD_JMR3904_DEBUG "jmr3904debug"
259 "|" BOARD_JMR3904_DEBUG
261 , "Customize simulation for a particular board.", mips_option_handler
},
263 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
267 int interrupt_pending
;
270 interrupt_event (SIM_DESC sd
, void *data
)
272 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
273 address_word cia
= CIA_GET (cpu
);
276 interrupt_pending
= 0;
277 SignalExceptionInterrupt (1); /* interrupt "1" */
279 else if (!interrupt_pending
)
280 sim_events_schedule (sd
, 1, interrupt_event
, data
);
284 /*---------------------------------------------------------------------------*/
285 /*-- Device registration hook -----------------------------------------------*/
286 /*---------------------------------------------------------------------------*/
287 static void device_init(SIM_DESC sd
) {
289 extern void register_devices(SIM_DESC
);
290 register_devices(sd
);
294 /*---------------------------------------------------------------------------*/
295 /*-- GDB simulator interface ------------------------------------------------*/
296 /*---------------------------------------------------------------------------*/
299 sim_open (kind
, cb
, abfd
, argv
)
305 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
306 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
308 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
310 /* FIXME: watchpoints code shouldn't need this */
311 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
312 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
313 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
315 /* Initialize the mechanism for doing insn profiling. */
316 CPU_INSN_NAME (cpu
) = get_insn_name
;
317 CPU_MAX_INSNS (cpu
) = nr_itable_entries
;
321 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
323 sim_add_option_table (sd
, NULL
, mips_options
);
326 /* getopt will print the error message so we just have to exit if this fails.
327 FIXME: Hmmm... in the case of gdb we need getopt to call
329 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
331 /* Uninstall the modules to avoid memory leaks,
332 file descriptor leaks, etc. */
333 sim_module_uninstall (sd
);
337 /* handle board-specific memory maps */
340 /* Allocate core managed memory */
343 sim_do_commandf (sd
, "memory region 0x%lx,0x%lx", MONITOR_BASE
, MONITOR_SIZE
);
344 /* For compatibility with the old code - under this (at level one)
345 are the kernel spaces K0 & K1. Both of these map to a single
346 smaller sub region */
347 sim_do_command(sd
," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
348 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
350 MEM_SIZE
, /* actual size */
358 && (strcmp(board
, BOARD_JMR3904
) == 0 ||
359 strcmp(board
, BOARD_JMR3904_PAL
) == 0 ||
360 strcmp(board
, BOARD_JMR3904_DEBUG
) == 0))
362 /* match VIRTUAL memory layout of JMR-TX3904 board */
365 /* --- environment --- */
367 STATE_ENVIRONMENT (sd
) = OPERATING_ENVIRONMENT
;
371 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
372 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
374 4 * 1024 * 1024, /* 4 MB */
377 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
378 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
380 4 * 1024 * 1024, /* 4 MB */
383 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
384 for (i
=0; i
<8; i
++) /* 32 MB total */
386 unsigned size
= 4 * 1024 * 1024; /* 4 MB */
387 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
388 0x88000000 + (i
* size
),
390 0xA8000000 + (i
* size
));
393 /* Dummy memory regions for unsimulated devices */
395 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFFE010, 0x00c); /* EBIF */
396 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
397 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
399 /* --- simulated devices --- */
400 sim_hw_parse (sd
, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
401 sim_hw_parse (sd
, "/tx3904cpu");
402 sim_hw_parse (sd
, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
403 sim_hw_parse (sd
, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
404 sim_hw_parse (sd
, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
405 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
407 /* FIXME: poking at dv-sockser internals, use tcp backend if
408 --sockser_addr option was given.*/
409 extern char* sockser_addr
;
410 if(sockser_addr
== NULL
)
411 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/backend stdio");
413 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/backend tcp");
415 sim_hw_parse (sd
, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
416 sim_hw_parse (sd
, "/tx3904sio@0xfffff400/backend stdio");
418 /* -- device connections --- */
419 sim_hw_parse (sd
, "/tx3904irc > ip level /tx3904cpu");
420 sim_hw_parse (sd
, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
421 sim_hw_parse (sd
, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
422 sim_hw_parse (sd
, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
423 sim_hw_parse (sd
, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
424 sim_hw_parse (sd
, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
426 /* add PAL timer & I/O module */
427 if(! strcmp(board
, BOARD_JMR3904_PAL
))
430 sim_hw_parse (sd
, "/pal@0xffff0000");
431 sim_hw_parse (sd
, "/pal@0xffff0000/reg 0xffff0000 64");
433 /* wire up interrupt ports to irc */
434 sim_hw_parse (sd
, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
435 sim_hw_parse (sd
, "/pal@0x31000000 > timer tmr1 /tx3904irc");
436 sim_hw_parse (sd
, "/pal@0x31000000 > int int0 /tx3904irc");
439 if(! strcmp(board
, BOARD_JMR3904_DEBUG
))
441 /* -- DEBUG: glue interrupt generators --- */
442 sim_hw_parse (sd
, "/glue@0xffff0000/reg 0xffff0000 0x50");
443 sim_hw_parse (sd
, "/glue@0xffff0000 > int0 int0 /tx3904irc");
444 sim_hw_parse (sd
, "/glue@0xffff0000 > int1 int1 /tx3904irc");
445 sim_hw_parse (sd
, "/glue@0xffff0000 > int2 int2 /tx3904irc");
446 sim_hw_parse (sd
, "/glue@0xffff0000 > int3 int3 /tx3904irc");
447 sim_hw_parse (sd
, "/glue@0xffff0000 > int4 int4 /tx3904irc");
448 sim_hw_parse (sd
, "/glue@0xffff0000 > int5 int5 /tx3904irc");
449 sim_hw_parse (sd
, "/glue@0xffff0000 > int6 int6 /tx3904irc");
450 sim_hw_parse (sd
, "/glue@0xffff0000 > int7 int7 /tx3904irc");
451 sim_hw_parse (sd
, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
452 sim_hw_parse (sd
, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
453 sim_hw_parse (sd
, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
454 sim_hw_parse (sd
, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
455 sim_hw_parse (sd
, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
456 sim_hw_parse (sd
, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
457 sim_hw_parse (sd
, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
458 sim_hw_parse (sd
, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
459 sim_hw_parse (sd
, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
460 sim_hw_parse (sd
, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
468 /* check for/establish the a reference program image */
469 if (sim_analyze_program (sd
,
470 (STATE_PROG_ARGV (sd
) != NULL
471 ? *STATE_PROG_ARGV (sd
)
475 sim_module_uninstall (sd
);
479 /* Configure/verify the target byte order and other runtime
480 configuration options */
481 if (sim_config (sd
) != SIM_RC_OK
)
483 sim_module_uninstall (sd
);
487 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
489 /* Uninstall the modules to avoid memory leaks,
490 file descriptor leaks, etc. */
491 sim_module_uninstall (sd
);
495 /* verify assumptions the simulator made about the host type system.
496 This macro does not return if there is a problem */
497 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
498 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
500 /* This is NASTY, in that we are assuming the size of specific
504 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++)
507 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
508 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ NR_FGR
)))
509 cpu
->register_widths
[rn
] = WITH_TARGET_FLOATING_POINT_BITSIZE
;
510 else if ((rn
>= 33) && (rn
<= 37))
511 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
512 else if ((rn
== SRIDX
)
515 || ((rn
>= 72) && (rn
<= 89)))
516 cpu
->register_widths
[rn
] = 32;
518 cpu
->register_widths
[rn
] = 0;
525 if (STATE
& simTRACE
)
529 /* Write an abort sequence into the TRAP (common) exception vector
530 addresses. This is to catch code executing a TRAP (et.al.)
531 instruction without installing a trap handler. */
533 unsigned32 halt
[2] = { 0x2404002f /* addiu r4, r0, 47 */,
534 HALT_INSTRUCTION
/* BREAK */ };
537 sim_write (sd
, 0x80000000, (char *) halt
, sizeof (halt
));
538 sim_write (sd
, 0x80000180, (char *) halt
, sizeof (halt
));
539 sim_write (sd
, 0x80000200, (char *) halt
, sizeof (halt
));
540 sim_write (sd
, 0xBFC00200, (char *) halt
, sizeof (halt
));
541 sim_write (sd
, 0xBFC00380, (char *) halt
, sizeof (halt
));
542 sim_write (sd
, 0xBFC00400, (char *) halt
, sizeof (halt
));
546 /* Write the monitor trap address handlers into the monitor (eeprom)
547 address space. This can only be done once the target endianness
548 has been determined. */
551 /* Entry into the IDT monitor is via fixed address vectors, and
552 not using machine instructions. To avoid clashing with use of
553 the MIPS TRAP system, we place our own (simulator specific)
554 "undefined" instructions into the relevant vector slots. */
555 for (loop
= 0; (loop
< MONITOR_SIZE
); loop
+= 4)
557 address_word vaddr
= (MONITOR_BASE
+ loop
);
558 unsigned32 insn
= (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
));
560 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
562 /* The PMON monitor uses the same address space, but rather than
563 branching into it the address of a routine is loaded. We can
564 cheat for the moment, and direct the PMON routine to IDT style
565 instructions within the monitor space. This relies on the IDT
566 monitor not using the locations from 0xBFC00500 onwards as its
568 for (loop
= 0; (loop
< 24); loop
++)
570 address_word vaddr
= (MONITOR_BASE
+ 0x500 + (loop
* 4));
571 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
587 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
589 case 8: /* cliexit */
592 case 11: /* flush_cache */
596 /* FIXME - should monitor_base be SIM_ADDR?? */
597 value
= ((unsigned int)MONITOR_BASE
+ (value
* 8));
599 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
601 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
603 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
617 tracefh
= fopen(tracefile
,"wb+");
620 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
626 /* Return name of an insn, used by insn profiling. */
628 get_insn_name (sim_cpu
*cpu
, int i
)
630 return itable
[i
].name
;
634 sim_close (sd
, quitting
)
639 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
643 /* "quitting" is non-zero if we cannot hang on errors */
645 /* shut down modules */
646 sim_module_uninstall (sd
);
648 /* Ensure that any resources allocated through the callback
649 mechanism are released: */
650 sim_io_shutdown (sd
);
653 if (tracefh
!= NULL
&& tracefh
!= stderr
)
658 /* FIXME - free SD */
665 sim_write (sd
,addr
,buffer
,size
)
668 unsigned char *buffer
;
672 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
674 /* Return the number of bytes written, or zero if error. */
676 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
679 /* We use raw read and write routines, since we do not want to count
680 the GDB memory accesses in our statistics gathering. */
682 for (index
= 0; index
< size
; index
++)
684 address_word vaddr
= (address_word
)addr
+ index
;
687 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
689 if (sim_core_write_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
697 sim_read (sd
,addr
,buffer
,size
)
700 unsigned char *buffer
;
704 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
706 /* Return the number of bytes read, or zero if error. */
708 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
711 for (index
= 0; (index
< size
); index
++)
713 address_word vaddr
= (address_word
)addr
+ index
;
716 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
718 if (sim_core_read_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
726 sim_store_register (sd
,rn
,memory
,length
)
729 unsigned char *memory
;
732 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
733 /* NOTE: gdb (the client) stores registers in target byte order
734 while the simulator uses host byte order */
736 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
739 /* Unfortunately this suffers from the same problem as the register
740 numbering one. We need to know what the width of each logical
741 register number is for the architecture being simulated. */
743 if (cpu
->register_widths
[rn
] == 0)
745 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
751 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
753 cpu
->fpr_state
[rn
- FGRIDX
] = fmt_uninterpreted
;
754 if (cpu
->register_widths
[rn
] == 32)
756 cpu
->fgr
[rn
- FGRIDX
] = T2H_4 (*(unsigned32
*)memory
);
761 cpu
->fgr
[rn
- FGRIDX
] = T2H_8 (*(unsigned64
*)memory
);
766 if (cpu
->register_widths
[rn
] == 32)
768 cpu
->registers
[rn
] = T2H_4 (*(unsigned32
*)memory
);
773 cpu
->registers
[rn
] = T2H_8 (*(unsigned64
*)memory
);
781 sim_fetch_register (sd
,rn
,memory
,length
)
784 unsigned char *memory
;
787 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
788 /* NOTE: gdb (the client) stores registers in target byte order
789 while the simulator uses host byte order */
791 #if 0 /* FIXME: doesn't compile */
792 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
796 if (cpu
->register_widths
[rn
] == 0)
798 sim_io_eprintf (sd
, "Invalid register width for %d (register fetch ignored)\n",rn
);
804 /* Any floating point register */
805 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
807 if (cpu
->register_widths
[rn
] == 32)
809 *(unsigned32
*)memory
= H2T_4 (cpu
->fgr
[rn
- FGRIDX
]);
814 *(unsigned64
*)memory
= H2T_8 (cpu
->fgr
[rn
- FGRIDX
]);
819 if (cpu
->register_widths
[rn
] == 32)
821 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
826 *(unsigned64
*)memory
= H2T_8 ((unsigned64
)(cpu
->registers
[rn
]));
835 sim_create_inferior (sd
, abfd
, argv
,env
)
843 #if 0 /* FIXME: doesn't compile */
844 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
853 /* override PC value set by ColdReset () */
855 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
857 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
858 CIA_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
862 #if 0 /* def DEBUG */
865 /* We should really place the argv slot values into the argument
866 registers, and onto the stack as required. However, this
867 assumes that we have a stack defined, which is not
868 necessarily true at the moment. */
870 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
871 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
872 printf("DBG: arg \"%s\"\n",*cptr
);
880 sim_do_command (sd
,cmd
)
884 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
885 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
889 /*---------------------------------------------------------------------------*/
890 /*-- Private simulator support interface ------------------------------------*/
891 /*---------------------------------------------------------------------------*/
893 /* Read a null terminated string from memory, return in a buffer */
895 fetch_str (SIM_DESC sd
,
901 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
903 buf
= NZALLOC (char, nr
+ 1);
904 sim_read (sd
, addr
, buf
, nr
);
908 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
910 sim_monitor (SIM_DESC sd
,
916 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
919 /* The IDT monitor actually allows two instructions per vector
920 slot. However, the simulator currently causes a trap on each
921 individual instruction. We cheat, and lose the bottom bit. */
924 /* The following callback functions are available, however the
925 monitor we are simulating does not make use of them: get_errno,
926 isatty, lseek, rename, system, time and unlink */
930 case 6: /* int open(char *path,int flags) */
932 char *path
= fetch_str (sd
, A0
);
933 V0
= sim_io_open (sd
, path
, (int)A1
);
938 case 7: /* int read(int file,char *ptr,int len) */
942 char *buf
= zalloc (nr
);
943 V0
= sim_io_read (sd
, fd
, buf
, nr
);
944 sim_write (sd
, A1
, buf
, nr
);
949 case 8: /* int write(int file,char *ptr,int len) */
953 char *buf
= zalloc (nr
);
954 sim_read (sd
, A1
, buf
, nr
);
955 V0
= sim_io_write (sd
, fd
, buf
, nr
);
960 case 10: /* int close(int file) */
962 V0
= sim_io_close (sd
, (int)A0
);
966 case 2: /* Densan monitor: char inbyte(int waitflag) */
968 if (A0
== 0) /* waitflag == NOWAIT */
969 V0
= (unsigned_word
)-1;
971 /* Drop through to case 11 */
973 case 11: /* char inbyte(void) */
976 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
978 sim_io_error(sd
,"Invalid return from character read");
979 V0
= (unsigned_word
)-1;
982 V0
= (unsigned_word
)tmp
;
986 case 3: /* Densan monitor: void co(char chr) */
987 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
989 char tmp
= (char)(A0
& 0xFF);
990 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
994 case 17: /* void _exit() */
996 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
997 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
998 (unsigned int)(A0
& 0xFFFFFFFF));
1002 case 28 : /* PMON flush_cache */
1005 case 55: /* void get_mem_info(unsigned int *ptr) */
1006 /* in: A0 = pointer to three word memory location */
1007 /* out: [A0 + 0] = size */
1008 /* [A0 + 4] = instruction cache size */
1009 /* [A0 + 8] = data cache size */
1011 unsigned_4 value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
1012 unsigned_4 zero
= 0;
1014 sim_write (sd
, A0
+ 0, (char *)&value
, 4);
1015 sim_write (sd
, A0
+ 4, (char *)&zero
, 4);
1016 sim_write (sd
, A0
+ 8, (char *)&zero
, 4);
1017 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1021 case 158 : /* PMON printf */
1022 /* in: A0 = pointer to format string */
1023 /* A1 = optional argument 1 */
1024 /* A2 = optional argument 2 */
1025 /* A3 = optional argument 3 */
1027 /* The following is based on the PMON printf source */
1029 address_word s
= A0
;
1031 signed_word
*ap
= &A1
; /* 1st argument */
1032 /* This isn't the quickest way, since we call the host print
1033 routine for every character almost. But it does avoid
1034 having to allocate and manage a temporary string buffer. */
1035 /* TODO: Include check that we only use three arguments (A1,
1037 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1042 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1043 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1044 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1046 if (strchr ("dobxXulscefg%", c
))
1061 else if (c
>= '1' && c
<= '9')
1065 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
1068 n
= (unsigned int)strtol(tmp
,NULL
,10);
1081 sim_io_printf (sd
, "%%");
1086 address_word p
= *ap
++;
1088 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
1089 sim_io_printf(sd
, "%c", ch
);
1092 sim_io_printf(sd
,"(null)");
1095 sim_io_printf (sd
, "%c", (int)*ap
++);
1100 sim_read (sd
, s
++, &c
, 1);
1104 sim_read (sd
, s
++, &c
, 1);
1107 if (strchr ("dobxXu", c
))
1109 word64 lv
= (word64
) *ap
++;
1111 sim_io_printf(sd
,"<binary not supported>");
1114 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
1116 sim_io_printf(sd
, tmp
, lv
);
1118 sim_io_printf(sd
, tmp
, (int)lv
);
1121 else if (strchr ("eEfgG", c
))
1123 double dbl
= *(double*)(ap
++);
1124 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
1125 sim_io_printf (sd
, tmp
, dbl
);
1131 sim_io_printf(sd
, "%c", c
);
1137 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1138 reason
, pr_addr(cia
));
1144 /* Store a word into memory. */
1147 store_word (SIM_DESC sd
,
1156 if ((vaddr
& 3) != 0)
1157 SignalExceptionAddressStore ();
1160 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1163 const uword64 mask
= 7;
1167 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1168 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1169 memval
= ((uword64
) val
) << (8 * byte
);
1170 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1176 /* Load a word from memory. */
1179 load_word (SIM_DESC sd
,
1184 if ((vaddr
& 3) != 0)
1186 SIM_CORE_SIGNAL (SD
, cpu
, cia
, read_map
, AccessLength_WORD
+1, vaddr
, read_transfer
, sim_core_unaligned_signal
);
1193 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1196 const uword64 mask
= 0x7;
1197 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1198 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1202 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1203 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1205 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1206 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1213 /* Simulate the mips16 entry and exit pseudo-instructions. These
1214 would normally be handled by the reserved instruction exception
1215 code, but for ease of simulation we just handle them directly. */
1218 mips16_entry (SIM_DESC sd
,
1223 int aregs
, sregs
, rreg
;
1226 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1229 aregs
= (insn
& 0x700) >> 8;
1230 sregs
= (insn
& 0x0c0) >> 6;
1231 rreg
= (insn
& 0x020) >> 5;
1233 /* This should be checked by the caller. */
1242 /* This is the entry pseudo-instruction. */
1244 for (i
= 0; i
< aregs
; i
++)
1245 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1253 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1256 for (i
= 0; i
< sregs
; i
++)
1259 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1267 /* This is the exit pseudo-instruction. */
1274 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1277 for (i
= 0; i
< sregs
; i
++)
1280 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1285 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1289 FGR
[0] = WORD64LO (GPR
[4]);
1290 FPR_STATE
[0] = fmt_uninterpreted
;
1292 else if (aregs
== 6)
1294 FGR
[0] = WORD64LO (GPR
[5]);
1295 FGR
[1] = WORD64LO (GPR
[4]);
1296 FPR_STATE
[0] = fmt_uninterpreted
;
1297 FPR_STATE
[1] = fmt_uninterpreted
;
1306 /*-- trace support ----------------------------------------------------------*/
1308 /* The TRACE support is provided (if required) in the memory accessing
1309 routines. Since we are also providing the architecture specific
1310 features, the architecture simulation code can also deal with
1311 notifying the TRACE world of cache flushes, etc. Similarly we do
1312 not need to provide profiling support in the simulator engine,
1313 since we can sample in the instruction fetch control loop. By
1314 defining the TRACE manifest, we add tracing as a run-time
1318 /* Tracing by default produces "din" format (as required by
1319 dineroIII). Each line of such a trace file *MUST* have a din label
1320 and address field. The rest of the line is ignored, so comments can
1321 be included if desired. The first field is the label which must be
1322 one of the following values:
1327 3 escape record (treated as unknown access type)
1328 4 escape record (causes cache flush)
1330 The address field is a 32bit (lower-case) hexadecimal address
1331 value. The address should *NOT* be preceded by "0x".
1333 The size of the memory transfer is not important when dealing with
1334 cache lines (as long as no more than a cache line can be
1335 transferred in a single operation :-), however more information
1336 could be given following the dineroIII requirement to allow more
1337 complete memory and cache simulators to provide better
1338 results. i.e. the University of Pisa has a cache simulator that can
1339 also take bus size and speed as (variable) inputs to calculate
1340 complete system performance (a much more useful ability when trying
1341 to construct an end product, rather than a processor). They
1342 currently have an ARM version of their tool called ChARM. */
1346 dotrace (SIM_DESC sd
,
1354 if (STATE
& simTRACE
) {
1356 fprintf(tracefh
,"%d %s ; width %d ; ",
1360 va_start(ap
,comment
);
1361 vfprintf(tracefh
,comment
,ap
);
1363 fprintf(tracefh
,"\n");
1365 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1366 we may be generating 64bit ones, we should put the hi-32bits of the
1367 address into the comment field. */
1369 /* TODO: Provide a buffer for the trace lines. We can then avoid
1370 performing writes until the buffer is filled, or the file is
1373 /* NOTE: We could consider adding a comment field to the "din" file
1374 produced using type 3 markers (unknown access). This would then
1375 allow information about the program that the "din" is for, and
1376 the MIPs world that was being simulated, to be placed into the
1383 /*---------------------------------------------------------------------------*/
1384 /*-- simulator engine -------------------------------------------------------*/
1385 /*---------------------------------------------------------------------------*/
1388 ColdReset (SIM_DESC sd
)
1391 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1393 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1394 /* RESET: Fixed PC address: */
1395 PC
= (unsigned_word
) UNSIGNED64 (0xFFFFFFFFBFC00000);
1396 /* The reset vector address is in the unmapped, uncached memory space. */
1398 SR
&= ~(status_SR
| status_TS
| status_RP
);
1399 SR
|= (status_ERL
| status_BEV
);
1401 /* Cheat and allow access to the complete register set immediately */
1402 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1403 && WITH_TARGET_WORD_BITSIZE
== 64)
1404 SR
|= status_FR
; /* 64bit registers */
1406 /* Ensure that any instructions with pending register updates are
1408 PENDING_INVALIDATE();
1410 /* Initialise the FPU registers to the unknown state */
1411 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1414 for (rn
= 0; (rn
< 32); rn
++)
1415 FPR_STATE
[rn
] = fmt_uninterpreted
;
1424 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1425 /* Signal an exception condition. This will result in an exception
1426 that aborts the instruction. The instruction operation pseudocode
1427 will never see a return from this function call. */
1430 signal_exception (SIM_DESC sd
,
1438 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1441 /* Ensure that any active atomic read/modify/write operation will fail: */
1444 /* Save registers before interrupt dispatching */
1445 #ifdef SIM_CPU_EXCEPTION_TRIGGER
1446 SIM_CPU_EXCEPTION_TRIGGER(sd
, cpu
, cia
);
1449 switch (exception
) {
1451 case DebugBreakPoint
:
1452 if (! (Debug
& Debug_DM
))
1458 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1459 DEPC
= cia
- 4; /* reference the branch instruction */
1463 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1467 Debug
|= Debug_DM
; /* in debugging mode */
1468 Debug
|= Debug_DBp
; /* raising a DBp exception */
1470 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1474 case ReservedInstruction
:
1477 unsigned int instruction
;
1478 va_start(ap
,exception
);
1479 instruction
= va_arg(ap
,unsigned int);
1481 /* Provide simple monitor support using ReservedInstruction
1482 exceptions. The following code simulates the fixed vector
1483 entry points into the IDT monitor by causing a simulator
1484 trap, performing the monitor operation, and returning to
1485 the address held in the $ra register (standard PCS return
1486 address). This means we only need to pre-load the vector
1487 space with suitable instruction values. For systems were
1488 actual trap instructions are used, we would not need to
1489 perform this magic. */
1490 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1492 sim_monitor (SD
, CPU
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1493 /* NOTE: This assumes that a branch-and-link style
1494 instruction was used to enter the vector (which is the
1495 case with the current IDT monitor). */
1496 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1498 /* Look for the mips16 entry and exit instructions, and
1499 simulate a handler for them. */
1500 else if ((cia
& 1) != 0
1501 && (instruction
& 0xf81f) == 0xe809
1502 && (instruction
& 0x0c0) != 0x0c0)
1504 mips16_entry (SD
, CPU
, cia
, instruction
);
1505 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1507 /* else fall through to normal exception processing */
1508 sim_io_eprintf(sd
,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia
));
1512 /* Store exception code into current exception id variable (used
1515 /* TODO: If not simulating exceptions then stop the simulator
1516 execution. At the moment we always stop the simulation. */
1518 #ifdef SUBTARGET_R3900
1519 /* update interrupt-related registers */
1521 /* insert exception code in bits 6:2 */
1522 CAUSE
= LSMASKED32(CAUSE
, 31, 7) | LSINSERTED32(exception
, 6, 2);
1523 /* shift IE/KU history bits left */
1524 SR
= LSMASKED32(SR
, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR
, 3, 0), 5, 2);
1526 if (STATE
& simDELAYSLOT
)
1528 STATE
&= ~simDELAYSLOT
;
1530 EPC
= (cia
- 4); /* reference the branch instruction */
1535 if (SR
& status_BEV
)
1536 PC
= (signed)0xBFC00000 + 0x180;
1538 PC
= (signed)0x80000000 + 0x080;
1540 /* See figure 5-17 for an outline of the code below */
1541 if (! (SR
& status_EXL
))
1543 CAUSE
= (exception
<< 2);
1544 if (STATE
& simDELAYSLOT
)
1546 STATE
&= ~simDELAYSLOT
;
1548 EPC
= (cia
- 4); /* reference the branch instruction */
1552 /* FIXME: TLB et.al. */
1553 /* vector = 0x180; */
1557 CAUSE
= (exception
<< 2);
1558 /* vector = 0x180; */
1561 /* Store exception code into current exception id variable (used
1564 if (SR
& status_BEV
)
1565 PC
= (signed)0xBFC00200 + 0x180;
1567 PC
= (signed)0x80000000 + 0x180;
1570 switch ((CAUSE
>> 2) & 0x1F)
1573 /* Interrupts arrive during event processing, no need to
1579 #ifdef SUBTARGET_3900
1580 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1581 PC
= (signed)0xBFC00000;
1582 #endif SUBTARGET_3900
1585 case TLBModification
:
1590 case InstructionFetch
:
1592 /* The following is so that the simulator will continue from the
1593 exception handler address. */
1594 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1595 sim_stopped
, SIM_SIGBUS
);
1597 case ReservedInstruction
:
1598 case CoProcessorUnusable
:
1600 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1601 sim_stopped
, SIM_SIGILL
);
1603 case IntegerOverflow
:
1605 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1606 sim_stopped
, SIM_SIGFPE
);
1609 sim_engine_halt (SD
, CPU
, NULL
, PC
, sim_stopped
, SIM_SIGTRAP
);
1614 sim_engine_restart (SD
, CPU
, NULL
, PC
);
1619 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1620 sim_stopped
, SIM_SIGTRAP
);
1622 default : /* Unknown internal exception */
1624 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1625 sim_stopped
, SIM_SIGABRT
);
1629 case SimulatorFault
:
1633 va_start(ap
,exception
);
1634 msg
= va_arg(ap
,char *);
1636 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1637 "FATAL: Simulator error \"%s\"\n",msg
);
1646 #if defined(WARN_RESULT)
1647 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1648 /* This function indicates that the result of the operation is
1649 undefined. However, this should not affect the instruction
1650 stream. All that is meant to happen is that the destination
1651 register is set to an undefined result. To keep the simulator
1652 simple, we just don't bother updating the destination register, so
1653 the overall result will be undefined. If desired we can stop the
1654 simulator by raising a pseudo-exception. */
1655 #define UndefinedResult() undefined_result (sd,cia)
1657 undefined_result(sd
,cia
)
1661 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
1662 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1667 #endif /* WARN_RESULT */
1669 /*-- FPU support routines ---------------------------------------------------*/
1671 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1672 formats conform to ANSI/IEEE Std 754-1985. */
1673 /* SINGLE precision floating:
1674 * seeeeeeeefffffffffffffffffffffff
1676 * e = 8bits = exponent
1677 * f = 23bits = fraction
1679 /* SINGLE precision fixed:
1680 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1682 * i = 31bits = integer
1684 /* DOUBLE precision floating:
1685 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1687 * e = 11bits = exponent
1688 * f = 52bits = fraction
1690 /* DOUBLE precision fixed:
1691 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1693 * i = 63bits = integer
1696 /* Extract sign-bit: */
1697 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
1698 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
1699 /* Extract biased exponent: */
1700 #define FP_S_be(v) (((v) >> 23) & 0xFF)
1701 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
1702 /* Extract unbiased Exponent: */
1703 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
1704 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1705 /* Extract complete fraction field: */
1706 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
1707 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
1708 /* Extract numbered fraction bit: */
1709 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1710 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1712 /* Explicit QNaN values used when value required: */
1713 #define FPQNaN_SINGLE (0x7FBFFFFF)
1714 #define FPQNaN_WORD (0x7FFFFFFF)
1715 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1716 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
1718 /* Explicit Infinity values used when required: */
1719 #define FPINF_SINGLE (0x7F800000)
1720 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
1722 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1723 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : (((v) == fmt_uninterpreted_32) ? "<uninterpreted_32>" : (((v) == fmt_uninterpreted_64) ? "<uninterpreted_64>" : "<format error>"))))))))
1726 value_fpr (SIM_DESC sd
,
1735 /* Treat unused register values, as fixed-point 64bit values: */
1736 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
1738 /* If request to read data as "uninterpreted", then use the current
1740 fmt
= FPR_STATE
[fpr
];
1745 /* For values not yet accessed, set to the desired format: */
1746 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
1747 FPR_STATE
[fpr
] = fmt
;
1749 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
1752 if (fmt
!= FPR_STATE
[fpr
]) {
1753 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
1754 FPR_STATE
[fpr
] = fmt_unknown
;
1757 if (FPR_STATE
[fpr
] == fmt_unknown
) {
1758 /* Set QNaN value: */
1761 value
= FPQNaN_SINGLE
;
1765 value
= FPQNaN_DOUBLE
;
1769 value
= FPQNaN_WORD
;
1773 value
= FPQNaN_LONG
;
1780 } else if (SizeFGR() == 64) {
1784 value
= (FGR
[fpr
] & 0xFFFFFFFF);
1787 case fmt_uninterpreted
:
1801 value
= (FGR
[fpr
] & 0xFFFFFFFF);
1804 case fmt_uninterpreted
:
1807 if ((fpr
& 1) == 0) { /* even registers only */
1809 printf("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n",
1810 fpr
+1, pr_uword64( (uword64
) FGR
[fpr
+1] ),
1811 fpr
, pr_uword64( (uword64
) FGR
[fpr
] ));
1813 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
1815 SignalException(ReservedInstruction
,0);
1826 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
1829 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_uword64(value
),pr_addr(cia
),SizeFGR());
1836 store_fpr (SIM_DESC sd
,
1846 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d,\n",fpr
,DOFMT(fmt
),pr_uword64(value
),pr_addr(cia
),SizeFGR());
1849 if (SizeFGR() == 64) {
1851 case fmt_uninterpreted_32
:
1852 fmt
= fmt_uninterpreted
;
1855 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
1856 FPR_STATE
[fpr
] = fmt
;
1859 case fmt_uninterpreted_64
:
1860 fmt
= fmt_uninterpreted
;
1861 case fmt_uninterpreted
:
1865 FPR_STATE
[fpr
] = fmt
;
1869 FPR_STATE
[fpr
] = fmt_unknown
;
1875 case fmt_uninterpreted_32
:
1876 fmt
= fmt_uninterpreted
;
1879 FGR
[fpr
] = (value
& 0xFFFFFFFF);
1880 FPR_STATE
[fpr
] = fmt
;
1883 case fmt_uninterpreted_64
:
1884 fmt
= fmt_uninterpreted
;
1885 case fmt_uninterpreted
:
1888 if ((fpr
& 1) == 0) { /* even register number only */
1889 FGR
[fpr
+1] = (value
>> 32);
1890 FGR
[fpr
] = (value
& 0xFFFFFFFF);
1891 FPR_STATE
[fpr
+ 1] = fmt
;
1892 FPR_STATE
[fpr
] = fmt
;
1894 FPR_STATE
[fpr
] = fmt_unknown
;
1895 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
1896 SignalException(ReservedInstruction
,0);
1901 FPR_STATE
[fpr
] = fmt_unknown
;
1906 #if defined(WARN_RESULT)
1909 #endif /* WARN_RESULT */
1912 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
1915 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_uword64(FGR
[fpr
]),DOFMT(fmt
));
1932 sim_fpu_32to (&wop
, op
);
1933 boolean
= sim_fpu_is_nan (&wop
);
1940 sim_fpu_64to (&wop
, op
);
1941 boolean
= sim_fpu_is_nan (&wop
);
1945 fprintf (stderr
, "Bad switch\n");
1950 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
1964 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
1971 sim_fpu_32to (&wop
, op
);
1972 boolean
= sim_fpu_is_infinity (&wop
);
1978 sim_fpu_64to (&wop
, op
);
1979 boolean
= sim_fpu_is_infinity (&wop
);
1983 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
1988 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2002 /* Argument checking already performed by the FPCOMPARE code */
2005 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2008 /* The format type should already have been checked: */
2014 sim_fpu_32to (&wop1
, op1
);
2015 sim_fpu_32to (&wop2
, op2
);
2016 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2023 sim_fpu_64to (&wop1
, op1
);
2024 sim_fpu_64to (&wop2
, op2
);
2025 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2029 fprintf (stderr
, "Bad switch\n");
2034 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2048 /* Argument checking already performed by the FPCOMPARE code */
2051 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2054 /* The format type should already have been checked: */
2060 sim_fpu_32to (&wop1
, op1
);
2061 sim_fpu_32to (&wop2
, op2
);
2062 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2069 sim_fpu_64to (&wop1
, op1
);
2070 sim_fpu_64to (&wop2
, op2
);
2071 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2075 fprintf (stderr
, "Bad switch\n");
2080 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2087 AbsoluteValue(op
,fmt
)
2094 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2097 /* The format type should already have been checked: */
2103 sim_fpu_32to (&wop
, op
);
2104 sim_fpu_abs (&wop
, &wop
);
2105 sim_fpu_to32 (&ans
, &wop
);
2113 sim_fpu_64to (&wop
, op
);
2114 sim_fpu_abs (&wop
, &wop
);
2115 sim_fpu_to64 (&ans
, &wop
);
2120 fprintf (stderr
, "Bad switch\n");
2135 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2138 /* The format type should already have been checked: */
2144 sim_fpu_32to (&wop
, op
);
2145 sim_fpu_neg (&wop
, &wop
);
2146 sim_fpu_to32 (&ans
, &wop
);
2154 sim_fpu_64to (&wop
, op
);
2155 sim_fpu_neg (&wop
, &wop
);
2156 sim_fpu_to64 (&ans
, &wop
);
2161 fprintf (stderr
, "Bad switch\n");
2177 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2180 /* The registers must specify FPRs valid for operands of type
2181 "fmt". If they are not valid, the result is undefined. */
2183 /* The format type should already have been checked: */
2191 sim_fpu_32to (&wop1
, op1
);
2192 sim_fpu_32to (&wop2
, op2
);
2193 sim_fpu_add (&ans
, &wop1
, &wop2
);
2194 sim_fpu_to32 (&res
, &ans
);
2204 sim_fpu_64to (&wop1
, op1
);
2205 sim_fpu_64to (&wop2
, op2
);
2206 sim_fpu_add (&ans
, &wop1
, &wop2
);
2207 sim_fpu_to64 (&res
, &ans
);
2212 fprintf (stderr
, "Bad switch\n");
2217 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2232 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2235 /* The registers must specify FPRs valid for operands of type
2236 "fmt". If they are not valid, the result is undefined. */
2238 /* The format type should already have been checked: */
2246 sim_fpu_32to (&wop1
, op1
);
2247 sim_fpu_32to (&wop2
, op2
);
2248 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2249 sim_fpu_to32 (&res
, &ans
);
2259 sim_fpu_64to (&wop1
, op1
);
2260 sim_fpu_64to (&wop2
, op2
);
2261 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2262 sim_fpu_to64 (&res
, &ans
);
2267 fprintf (stderr
, "Bad switch\n");
2272 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2279 Multiply(op1
,op2
,fmt
)
2287 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2290 /* The registers must specify FPRs valid for operands of type
2291 "fmt". If they are not valid, the result is undefined. */
2293 /* The format type should already have been checked: */
2301 sim_fpu_32to (&wop1
, op1
);
2302 sim_fpu_32to (&wop2
, op2
);
2303 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2304 sim_fpu_to32 (&res
, &ans
);
2314 sim_fpu_64to (&wop1
, op1
);
2315 sim_fpu_64to (&wop2
, op2
);
2316 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2317 sim_fpu_to64 (&res
, &ans
);
2322 fprintf (stderr
, "Bad switch\n");
2327 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2342 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2345 /* The registers must specify FPRs valid for operands of type
2346 "fmt". If they are not valid, the result is undefined. */
2348 /* The format type should already have been checked: */
2356 sim_fpu_32to (&wop1
, op1
);
2357 sim_fpu_32to (&wop2
, op2
);
2358 sim_fpu_div (&ans
, &wop1
, &wop2
);
2359 sim_fpu_to32 (&res
, &ans
);
2369 sim_fpu_64to (&wop1
, op1
);
2370 sim_fpu_64to (&wop2
, op2
);
2371 sim_fpu_div (&ans
, &wop1
, &wop2
);
2372 sim_fpu_to64 (&res
, &ans
);
2377 fprintf (stderr
, "Bad switch\n");
2382 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2396 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2399 /* The registers must specify FPRs valid for operands of type
2400 "fmt". If they are not valid, the result is undefined. */
2402 /* The format type should already have been checked: */
2409 sim_fpu_32to (&wop
, op
);
2410 sim_fpu_inv (&ans
, &wop
);
2411 sim_fpu_to32 (&res
, &ans
);
2420 sim_fpu_64to (&wop
, op
);
2421 sim_fpu_inv (&ans
, &wop
);
2422 sim_fpu_to64 (&res
, &ans
);
2427 fprintf (stderr
, "Bad switch\n");
2432 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2446 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2449 /* The registers must specify FPRs valid for operands of type
2450 "fmt". If they are not valid, the result is undefined. */
2452 /* The format type should already have been checked: */
2459 sim_fpu_32to (&wop
, op
);
2460 sim_fpu_sqrt (&ans
, &wop
);
2461 sim_fpu_to32 (&res
, &ans
);
2470 sim_fpu_64to (&wop
, op
);
2471 sim_fpu_sqrt (&ans
, &wop
);
2472 sim_fpu_to64 (&res
, &ans
);
2477 fprintf (stderr
, "Bad switch\n");
2482 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2498 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2501 /* The registers must specify FPRs valid for operands of type
2502 "fmt". If they are not valid, the result is undefined. */
2504 /* The format type should already have been checked: */
2511 sim_fpu_32to (&wop1
, op1
);
2512 sim_fpu_32to (&wop2
, op2
);
2513 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2520 sim_fpu_64to (&wop1
, op1
);
2521 sim_fpu_64to (&wop2
, op2
);
2522 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2526 fprintf (stderr
, "Bad switch\n");
2532 case SIM_FPU_IS_SNAN
:
2533 case SIM_FPU_IS_QNAN
:
2535 case SIM_FPU_IS_NINF
:
2536 case SIM_FPU_IS_NNUMBER
:
2537 case SIM_FPU_IS_NDENORM
:
2538 case SIM_FPU_IS_NZERO
:
2539 result
= op2
; /* op1 - op2 < 0 */
2540 case SIM_FPU_IS_PINF
:
2541 case SIM_FPU_IS_PNUMBER
:
2542 case SIM_FPU_IS_PDENORM
:
2543 case SIM_FPU_IS_PZERO
:
2544 result
= op1
; /* op1 - op2 > 0 */
2546 fprintf (stderr
, "Bad switch\n");
2551 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2568 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2571 /* The registers must specify FPRs valid for operands of type
2572 "fmt". If they are not valid, the result is undefined. */
2574 /* The format type should already have been checked: */
2581 sim_fpu_32to (&wop1
, op1
);
2582 sim_fpu_32to (&wop2
, op2
);
2583 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2590 sim_fpu_64to (&wop1
, op1
);
2591 sim_fpu_64to (&wop2
, op2
);
2592 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2596 fprintf (stderr
, "Bad switch\n");
2602 case SIM_FPU_IS_SNAN
:
2603 case SIM_FPU_IS_QNAN
:
2605 case SIM_FPU_IS_NINF
:
2606 case SIM_FPU_IS_NNUMBER
:
2607 case SIM_FPU_IS_NDENORM
:
2608 case SIM_FPU_IS_NZERO
:
2609 result
= op1
; /* op1 - op2 < 0 */
2610 case SIM_FPU_IS_PINF
:
2611 case SIM_FPU_IS_PNUMBER
:
2612 case SIM_FPU_IS_PDENORM
:
2613 case SIM_FPU_IS_PZERO
:
2614 result
= op2
; /* op1 - op2 > 0 */
2616 fprintf (stderr
, "Bad switch\n");
2621 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2629 convert (SIM_DESC sd
,
2638 sim_fpu_round round
;
2639 unsigned32 result32
;
2640 unsigned64 result64
;
2643 #if 0 /* FIXME: doesn't compile */
2644 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
2651 /* Round result to nearest representable value. When two
2652 representable values are equally near, round to the value
2653 that has a least significant bit of zero (i.e. is even). */
2654 round
= sim_fpu_round_near
;
2657 /* Round result to the value closest to, and not greater in
2658 magnitude than, the result. */
2659 round
= sim_fpu_round_zero
;
2662 /* Round result to the value closest to, and not less than,
2664 round
= sim_fpu_round_up
;
2668 /* Round result to the value closest to, and not greater than,
2670 round
= sim_fpu_round_down
;
2674 fprintf (stderr
, "Bad switch\n");
2678 /* Convert the input to sim_fpu internal format */
2682 sim_fpu_64to (&wop
, op
);
2685 sim_fpu_32to (&wop
, op
);
2688 sim_fpu_i32to (&wop
, op
, round
);
2691 sim_fpu_i64to (&wop
, op
, round
);
2694 fprintf (stderr
, "Bad switch\n");
2698 /* Convert sim_fpu format into the output */
2699 /* The value WOP is converted to the destination format, rounding
2700 using mode RM. When the destination is a fixed-point format, then
2701 a source value of Infinity, NaN or one which would round to an
2702 integer outside the fixed point range then an IEEE Invalid
2703 Operation condition is raised. */
2707 sim_fpu_round_32 (&wop
, round
, 0);
2708 sim_fpu_to32 (&result32
, &wop
);
2709 result64
= result32
;
2712 sim_fpu_round_64 (&wop
, round
, 0);
2713 sim_fpu_to64 (&result64
, &wop
);
2716 sim_fpu_to32i (&result32
, &wop
, round
);
2717 result64
= result32
;
2720 sim_fpu_to64i (&result64
, &wop
, round
);
2724 fprintf (stderr
, "Bad switch\n");
2729 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
2736 /*-- co-processor support routines ------------------------------------------*/
2739 CoProcPresent(unsigned int coproc_number
)
2741 /* Return TRUE if simulator provides a model for the given co-processor number */
2746 cop_lw (SIM_DESC sd
,
2751 unsigned int memword
)
2756 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2759 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
2761 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
2762 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
2767 #if 0 /* this should be controlled by a configuration option */
2768 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
2777 cop_ld (SIM_DESC sd
,
2786 printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num
, coproc_reg
, pr_uword64(memword
), pr_addr(cia
) );
2789 switch (coproc_num
) {
2791 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2793 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
2798 #if 0 /* this message should be controlled by a configuration option */
2799 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
2811 cop_sw (SIM_DESC sd
,
2817 unsigned int value
= 0;
2822 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2825 hold
= FPR_STATE
[coproc_reg
];
2826 FPR_STATE
[coproc_reg
] = fmt_word
;
2827 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
2828 FPR_STATE
[coproc_reg
] = hold
;
2833 #if 0 /* should be controlled by configuration option */
2834 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2843 cop_sd (SIM_DESC sd
,
2853 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2855 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
2860 #if 0 /* should be controlled by configuration option */
2861 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2873 decode_coproc (SIM_DESC sd
,
2876 unsigned int instruction
)
2878 int coprocnum
= ((instruction
>> 26) & 3);
2882 case 0: /* standard CPU control and cache registers */
2884 int code
= ((instruction
>> 21) & 0x1F);
2885 int rt
= ((instruction
>> 16) & 0x1F);
2886 int rd
= ((instruction
>> 11) & 0x1F);
2887 int tail
= instruction
& 0x3ff;
2888 /* R4000 Users Manual (second edition) lists the following CP0
2890 CODE><-RT><RD-><--TAIL--->
2891 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2892 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2893 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2894 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2895 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2896 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2897 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2898 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2899 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2900 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2902 if (((code
== 0x00) || (code
== 0x04)) && tail
== 0)
2904 /* M[TF]C0 - 32 bit word */
2906 switch (rd
) /* NOTEs: Standard CP0 registers */
2908 /* 0 = Index R4000 VR4100 VR4300 */
2909 /* 1 = Random R4000 VR4100 VR4300 */
2910 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2911 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2912 /* 4 = Context R4000 VR4100 VR4300 */
2913 /* 5 = PageMask R4000 VR4100 VR4300 */
2914 /* 6 = Wired R4000 VR4100 VR4300 */
2915 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2916 /* 9 = Count R4000 VR4100 VR4300 */
2917 /* 10 = EntryHi R4000 VR4100 VR4300 */
2918 /* 11 = Compare R4000 VR4100 VR4300 */
2919 /* 12 = SR R4000 VR4100 VR4300 */
2920 #ifdef SUBTARGET_R3900
2922 /* 3 = Config R3900 */
2924 /* 7 = Cache R3900 */
2926 /* 15 = PRID R3900 */
2932 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2934 GPR
[rt
] = COP0_BADVADDR
;
2936 COP0_BADVADDR
= GPR
[rt
];
2939 #endif /* SUBTARGET_R3900 */
2946 /* 13 = Cause R4000 VR4100 VR4300 */
2953 /* 14 = EPC R4000 VR4100 VR4300 */
2956 GPR
[rt
] = (signed_word
) (signed_address
) EPC
;
2960 /* 15 = PRId R4000 VR4100 VR4300 */
2961 #ifdef SUBTARGET_R3900
2970 /* 16 = Config R4000 VR4100 VR4300 */
2973 GPR
[rt
] = C0_CONFIG
;
2975 C0_CONFIG
= GPR
[rt
];
2978 #ifdef SUBTARGET_R3900
2987 /* 17 = LLAddr R4000 VR4100 VR4300 */
2989 /* 18 = WatchLo R4000 VR4100 VR4300 */
2990 /* 19 = WatchHi R4000 VR4100 VR4300 */
2991 /* 20 = XContext R4000 VR4100 VR4300 */
2992 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
2993 /* 27 = CacheErr R4000 VR4100 */
2994 /* 28 = TagLo R4000 VR4100 VR4300 */
2995 /* 29 = TagHi R4000 VR4100 VR4300 */
2996 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
2997 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
2998 /* CPR[0,rd] = GPR[rt]; */
3001 GPR
[rt
] = (signed_word
) (signed32
) COP0_GPR
[rd
];
3003 COP0_GPR
[rd
] = GPR
[rt
];
3006 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt
,rd
, (unsigned)cia
);
3008 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt
,rd
, (unsigned)cia
);
3012 else if (code
== 0x10 && (tail
& 0x3f) == 0x18)
3015 if (SR
& status_ERL
)
3017 /* Oops, not yet available */
3018 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3028 else if (code
== 0x10 && (tail
& 0x3f) == 0x10)
3031 #ifdef SUBTARGET_R3900
3032 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
3034 /* shift IE/KU history bits right */
3035 SR
= LSMASKED32(SR
, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR
, 5, 2), 3, 0);
3037 /* TODO: CACHE register */
3038 #endif /* SUBTARGET_R3900 */
3040 else if (code
== 0x10 && (tail
& 0x3f) == 0x1F)
3048 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3049 /* TODO: When executing an ERET or RFE instruction we should
3050 clear LLBIT, to ensure that any out-standing atomic
3051 read/modify/write sequence fails. */
3055 case 2: /* co-processor 2 */
3062 sim_io_eprintf(sd
, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
3063 instruction
,pr_addr(cia
));
3068 case 1: /* should not occur (FPU co-processor) */
3069 case 3: /* should not occur (FPU co-processor) */
3070 SignalException(ReservedInstruction
,instruction
);
3078 /* This code copied from gdb's utils.c. Would like to share this code,
3079 but don't know of a common place where both could get to it. */
3081 /* Temporary storage using circular buffer */
3087 static char buf
[NUMCELLS
][CELLSIZE
];
3089 if (++cell
>=NUMCELLS
) cell
=0;
3093 /* Print routines to handle variable size regs, etc */
3095 /* Eliminate warning from compiler on 32-bit systems */
3096 static int thirty_two
= 32;
3102 char *paddr_str
=get_cell();
3103 switch (sizeof(addr
))
3106 sprintf(paddr_str
,"%08lx%08lx",
3107 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3110 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3113 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3116 sprintf(paddr_str
,"%x",addr
);
3125 char *paddr_str
=get_cell();
3126 sprintf(paddr_str
,"%08lx%08lx",
3127 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3133 mips_core_signal (SIM_DESC sd
,
3139 transfer_type transfer
,
3140 sim_core_signals sig
)
3142 const char *copy
= (transfer
== read_transfer
? "read" : "write");
3143 address_word ip
= CIA_ADDR (cia
);
3147 case sim_core_unmapped_signal
:
3148 sim_io_eprintf (sd
, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
3150 (unsigned long) addr
, (unsigned long) ip
);
3151 COP0_BADVADDR
= addr
;
3152 SignalExceptionDataReference();
3155 case sim_core_unaligned_signal
:
3156 sim_io_eprintf (sd
, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
3158 (unsigned long) addr
, (unsigned long) ip
);
3159 COP0_BADVADDR
= addr
;
3160 if(transfer
== read_transfer
)
3161 SignalExceptionAddressLoad();
3163 SignalExceptionAddressStore();
3167 sim_engine_abort (sd
, cpu
, cia
,
3168 "mips_core_signal - internal error - bad switch");
3174 mips_cpu_exception_trigger(SIM_DESC sd
, sim_cpu
* cpu
, address_word cia
)
3176 ASSERT(cpu
!= NULL
);
3178 if(cpu
->exc_suspended
> 0)
3179 sim_io_eprintf(sd
, "Warning, nested exception triggered (%d)\n", cpu
->exc_suspended
);
3182 memcpy(cpu
->exc_trigger_registers
, cpu
->registers
, sizeof(cpu
->exc_trigger_registers
));
3183 cpu
->exc_suspended
= 0;
3187 mips_cpu_exception_suspend(SIM_DESC sd
, sim_cpu
* cpu
, int exception
)
3189 ASSERT(cpu
!= NULL
);
3191 if(cpu
->exc_suspended
> 0)
3192 sim_io_eprintf(sd
, "Warning, nested exception signal (%d then %d)\n",
3193 cpu
->exc_suspended
, exception
);
3195 memcpy(cpu
->exc_suspend_registers
, cpu
->registers
, sizeof(cpu
->exc_suspend_registers
));
3196 memcpy(cpu
->registers
, cpu
->exc_trigger_registers
, sizeof(cpu
->registers
));
3197 cpu
->exc_suspended
= exception
;
3201 mips_cpu_exception_resume(SIM_DESC sd
, sim_cpu
* cpu
, int exception
)
3203 ASSERT(cpu
!= NULL
);
3205 if(exception
== 0 && cpu
->exc_suspended
> 0)
3207 /* warn not for breakpoints */
3208 if(cpu
->exc_suspended
!= sim_signal_to_host(sd
, SIM_SIGTRAP
))
3209 sim_io_eprintf(sd
, "Warning, resuming but ignoring pending exception signal (%d)\n",
3210 cpu
->exc_suspended
);
3212 else if(exception
!= 0 && cpu
->exc_suspended
> 0)
3214 if(exception
!= cpu
->exc_suspended
)
3215 sim_io_eprintf(sd
, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
3216 cpu
->exc_suspended
, exception
);
3218 memcpy(cpu
->registers
, cpu
->exc_suspend_registers
, sizeof(cpu
->registers
));
3220 else if(exception
!= 0 && cpu
->exc_suspended
== 0)
3222 sim_io_eprintf(sd
, "Warning, ignoring spontanous exception signal (%d)\n", exception
);
3224 cpu
->exc_suspended
= 0;
3228 /*---------------------------------------------------------------------------*/
3229 /*> EOF interp.c <*/