2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22 The IDT monitor (found on the VR4300 board), seems to lie about
23 register contents. It seems to treat the registers as sign-extended
24 32-bit values. This cause *REAL* problems when single-stepping 64-bit
29 /* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
32 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
38 #include "sim-utils.h"
39 #include "sim-options.h"
40 #include "sim-assert.h"
62 #include "libiberty.h"
64 #include "callback.h" /* GDB simulator callback interface */
65 #include "remote-sim.h" /* GDB simulator interface */
73 char* pr_addr
PARAMS ((SIM_ADDR addr
));
74 char* pr_uword64
PARAMS ((uword64 addr
));
77 /* Get the simulator engine description, without including the code: */
79 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
86 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
91 /* The following reserved instruction value is used when a simulator
92 trap is required. NOTE: Care must be taken, since this value may be
93 used in later revisions of the MIPS ISA. */
94 #define RSVD_INSTRUCTION (0x00000005)
95 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
97 #define RSVD_INSTRUCTION_ARG_SHIFT 6
98 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
101 /* Bits in the Debug register */
102 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
103 #define Debug_DM 0x40000000 /* Debug Mode */
104 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
110 /*---------------------------------------------------------------------------*/
111 /*-- GDB simulator interface ------------------------------------------------*/
112 /*---------------------------------------------------------------------------*/
114 static void ColdReset
PARAMS((SIM_DESC sd
));
116 /*---------------------------------------------------------------------------*/
120 #define DELAYSLOT() {\
121 if (STATE & simDELAYSLOT)\
122 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
123 STATE |= simDELAYSLOT;\
126 #define JALDELAYSLOT() {\
128 STATE |= simJALDELAYSLOT;\
132 STATE &= ~simDELAYSLOT;\
133 STATE |= simSKIPNEXT;\
136 #define CANCELDELAYSLOT() {\
138 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
141 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
142 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
144 #define K0BASE (0x80000000)
145 #define K0SIZE (0x20000000)
146 #define K1BASE (0xA0000000)
147 #define K1SIZE (0x20000000)
148 #define MONITOR_BASE (0xBFC00000)
149 #define MONITOR_SIZE (1 << 11)
150 #define MEM_SIZE (2 << 20)
153 static char *tracefile
= "trace.din"; /* default filename for trace log */
154 FILE *tracefh
= NULL
;
155 static void open_trace
PARAMS((SIM_DESC sd
));
158 #define OPTION_DINERO_TRACE 200
159 #define OPTION_DINERO_FILE 201
162 mips_option_handler (sd
, opt
, arg
)
170 case OPTION_DINERO_TRACE
: /* ??? */
172 /* Eventually the simTRACE flag could be treated as a toggle, to
173 allow external control of the program points being traced
174 (i.e. only from main onwards, excluding the run-time setup,
176 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
178 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
181 else if (strcmp (arg
, "yes") == 0)
183 else if (strcmp (arg
, "no") == 0)
185 else if (strcmp (arg
, "on") == 0)
187 else if (strcmp (arg
, "off") == 0)
191 fprintf (stderr
, "Unreconized dinero-trace option `%s'\n", arg
);
198 Simulator constructed without dinero tracing support (for performance).\n\
199 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
203 case OPTION_DINERO_FILE
:
205 if (optarg
!= NULL
) {
207 tmp
= (char *)malloc(strlen(optarg
) + 1);
210 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
216 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
227 static const OPTION mips_options
[] =
229 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
230 '\0', "on|off", "Enable dinero tracing",
231 mips_option_handler
},
232 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
233 '\0', "FILE", "Write dinero trace to FILE",
234 mips_option_handler
},
235 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
239 int interrupt_pending
;
242 interrupt_event (SIM_DESC sd
, void *data
)
244 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
247 interrupt_pending
= 0;
248 SignalExceptionInterrupt ();
250 else if (!interrupt_pending
)
251 sim_events_schedule (sd
, 1, interrupt_event
, data
);
256 /*---------------------------------------------------------------------------*/
257 /*-- GDB simulator interface ------------------------------------------------*/
258 /*---------------------------------------------------------------------------*/
261 sim_open (kind
, cb
, abfd
, argv
)
267 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
268 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
270 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
272 /* FIXME: watchpoints code shouldn't need this */
273 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
274 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
275 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
279 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
281 sim_add_option_table (sd
, mips_options
);
283 /* Allocate core managed memory */
286 sim_do_commandf (sd
, "memory region 0x%lx,0x%lx", MONITOR_BASE
, MONITOR_SIZE
);
287 /* For compatibility with the old code - under this (at level one)
288 are the kernel spaces K0 & K1. Both of these map to a single
289 smaller sub region */
290 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
292 MEM_SIZE
, /* actual size */
295 /* getopt will print the error message so we just have to exit if this fails.
296 FIXME: Hmmm... in the case of gdb we need getopt to call
298 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
300 /* Uninstall the modules to avoid memory leaks,
301 file descriptor leaks, etc. */
302 sim_module_uninstall (sd
);
306 /* check for/establish the a reference program image */
307 if (sim_analyze_program (sd
,
308 (STATE_PROG_ARGV (sd
) != NULL
309 ? *STATE_PROG_ARGV (sd
)
313 sim_module_uninstall (sd
);
317 /* Configure/verify the target byte order and other runtime
318 configuration options */
319 if (sim_config (sd
) != SIM_RC_OK
)
321 sim_module_uninstall (sd
);
325 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
327 /* Uninstall the modules to avoid memory leaks,
328 file descriptor leaks, etc. */
329 sim_module_uninstall (sd
);
333 /* verify assumptions the simulator made about the host type system.
334 This macro does not return if there is a problem */
335 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
336 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
338 /* This is NASTY, in that we are assuming the size of specific
342 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++) {
344 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
345 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ 32)))
346 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
347 else if ((rn
>= 33) && (rn
<= 37))
348 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
349 else if ((rn
== SRIDX
) || (rn
== FCR0IDX
) || (rn
== FCR31IDX
) || ((rn
>= 72) && (rn
<= 89)))
350 cpu
->register_widths
[rn
] = 32;
352 cpu
->register_widths
[rn
] = 0;
354 /* start-sanitize-r5900 */
356 /* set the 5900 "upper" registers to 64 bits */
357 for( rn
= LAST_EMBED_REGNUM
+1; rn
< NUM_REGS
; rn
++)
358 cpu
->register_widths
[rn
] = 64;
359 /* end-sanitize-r5900 */
363 if (STATE
& simTRACE
)
367 /* Write the monitor trap address handlers into the monitor (eeprom)
368 address space. This can only be done once the target endianness
369 has been determined. */
372 /* Entry into the IDT monitor is via fixed address vectors, and
373 not using machine instructions. To avoid clashing with use of
374 the MIPS TRAP system, we place our own (simulator specific)
375 "undefined" instructions into the relevant vector slots. */
376 for (loop
= 0; (loop
< MONITOR_SIZE
); loop
+= 4)
378 address_word vaddr
= (MONITOR_BASE
+ loop
);
379 unsigned32 insn
= (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
));
381 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
383 /* The PMON monitor uses the same address space, but rather than
384 branching into it the address of a routine is loaded. We can
385 cheat for the moment, and direct the PMON routine to IDT style
386 instructions within the monitor space. This relies on the IDT
387 monitor not using the locations from 0xBFC00500 onwards as its
389 for (loop
= 0; (loop
< 24); loop
++)
391 address_word vaddr
= (MONITOR_BASE
+ 0x500 + (loop
* 4));
392 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
408 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
410 case 8: /* cliexit */
413 case 11: /* flush_cache */
417 /* FIXME - should monitor_base be SIM_ADDR?? */
418 value
= ((unsigned int)MONITOR_BASE
+ (value
* 8));
420 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
422 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
424 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
436 tracefh
= fopen(tracefile
,"wb+");
439 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
446 sim_close (sd
, quitting
)
451 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
454 /* "quitting" is non-zero if we cannot hang on errors */
456 /* Ensure that any resources allocated through the callback
457 mechanism are released: */
458 sim_io_shutdown (sd
);
461 if (tracefh
!= NULL
&& tracefh
!= stderr
)
466 /* FIXME - free SD */
473 sim_write (sd
,addr
,buffer
,size
)
476 unsigned char *buffer
;
480 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
482 /* Return the number of bytes written, or zero if error. */
484 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
487 /* We use raw read and write routines, since we do not want to count
488 the GDB memory accesses in our statistics gathering. */
490 for (index
= 0; index
< size
; index
++)
492 address_word vaddr
= (address_word
)addr
+ index
;
495 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
497 if (sim_core_write_buffer (SD
, CPU
, sim_core_read_map
, buffer
+ index
, paddr
, 1) != 1)
505 sim_read (sd
,addr
,buffer
,size
)
508 unsigned char *buffer
;
512 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
514 /* Return the number of bytes read, or zero if error. */
516 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
519 for (index
= 0; (index
< size
); index
++)
521 address_word vaddr
= (address_word
)addr
+ index
;
524 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
526 if (sim_core_read_buffer (SD
, CPU
, sim_core_read_map
, buffer
+ index
, paddr
, 1) != 1)
534 sim_store_register (sd
,rn
,memory
)
537 unsigned char *memory
;
539 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
540 /* NOTE: gdb (the client) stores registers in target byte order
541 while the simulator uses host byte order */
543 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
546 /* Unfortunately this suffers from the same problem as the register
547 numbering one. We need to know what the width of each logical
548 register number is for the architecture being simulated. */
550 if (cpu
->register_widths
[rn
] == 0)
551 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
552 /* start-sanitize-r5900 */
553 else if (rn
== REGISTER_SA
)
554 SA
= T2H_8(*(uword64
*)memory
);
555 else if (rn
> LAST_EMBED_REGNUM
)
556 cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1] = T2H_8(*(uword64
*)memory
);
557 /* end-sanitize-r5900 */
558 else if (cpu
->register_widths
[rn
] == 32)
559 cpu
->registers
[rn
] = T2H_4 (*(unsigned int*)memory
);
561 cpu
->registers
[rn
] = T2H_8 (*(uword64
*)memory
);
567 sim_fetch_register (sd
,rn
,memory
)
570 unsigned char *memory
;
572 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
573 /* NOTE: gdb (the client) stores registers in target byte order
574 while the simulator uses host byte order */
576 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
579 if (cpu
->register_widths
[rn
] == 0)
580 sim_io_eprintf(sd
,"Invalid register width for %d (register fetch ignored)\n",rn
);
581 /* start-sanitize-r5900 */
582 else if (rn
== REGISTER_SA
)
583 *((uword64
*)memory
) = H2T_8(SA
);
584 else if (rn
> LAST_EMBED_REGNUM
)
585 *((uword64
*)memory
) = H2T_8(cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1]);
586 /* end-sanitize-r5900 */
587 else if (cpu
->register_widths
[rn
] == 32)
588 *((unsigned int *)memory
) = H2T_4 ((unsigned int)(cpu
->registers
[rn
] & 0xFFFFFFFF));
589 else /* 64bit register */
590 *((uword64
*)memory
) = H2T_8 (cpu
->registers
[rn
]);
597 sim_info (sd
,verbose
)
601 /* Accessed from the GDB "info files" command: */
602 if (STATE_VERBOSE_P (sd
) || verbose
)
605 sim_io_printf (sd
, "MIPS %d-bit %s endian simulator\n",
606 WITH_TARGET_WORD_BITSIZE
,
607 (CURRENT_TARGET_BYTE_ORDER
== BIG_ENDIAN
? "Big" : "Little"));
609 #if !defined(FASTSIM)
610 /* It would be a useful feature, if when performing multi-cycle
611 simulations (rather than single-stepping) we keep the start and
612 end times of the execution, so that we can give a performance
613 figure for the simulator. */
614 #endif /* !FASTSIM */
615 sim_io_printf (sd
, "Number of execution cycles = %ld\n",
616 (long) sim_events_time (sd
));
618 /* print information pertaining to MIPS ISA and architecture being simulated */
619 /* things that may be interesting */
620 /* instructions executed - if available */
621 /* cycles executed - if available */
622 /* pipeline stalls - if available */
623 /* virtual time taken */
625 /* profiling frequency */
629 profile_print (sd
, STATE_VERBOSE_P (sd
), NULL
, NULL
);
634 sim_create_inferior (sd
, abfd
, argv
,env
)
642 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
650 /* override PC value set by ColdReset () */
652 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
654 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
655 CIA_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
659 #if 0 /* def DEBUG */
662 /* We should really place the argv slot values into the argument
663 registers, and onto the stack as required. However, this
664 assumes that we have a stack defined, which is not
665 necessarily true at the moment. */
667 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
668 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
669 printf("DBG: arg \"%s\"\n",*cptr
);
677 sim_do_command (sd
,cmd
)
681 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
682 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
686 /*---------------------------------------------------------------------------*/
687 /*-- Private simulator support interface ------------------------------------*/
688 /*---------------------------------------------------------------------------*/
690 /* Read a null terminated string from memory, return in a buffer */
699 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
701 buf
= NZALLOC (char, nr
+ 1);
702 sim_read (sd
, addr
, buf
, nr
);
706 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
708 sim_monitor (SIM_DESC sd
,
714 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
717 /* The IDT monitor actually allows two instructions per vector
718 slot. However, the simulator currently causes a trap on each
719 individual instruction. We cheat, and lose the bottom bit. */
722 /* The following callback functions are available, however the
723 monitor we are simulating does not make use of them: get_errno,
724 isatty, lseek, rename, system, time and unlink */
728 case 6: /* int open(char *path,int flags) */
730 char *path
= fetch_str (sd
, A0
);
731 V0
= sim_io_open (sd
, path
, (int)A1
);
736 case 7: /* int read(int file,char *ptr,int len) */
740 char *buf
= zalloc (nr
);
741 V0
= sim_io_read (sd
, fd
, buf
, nr
);
742 sim_write (sd
, A1
, buf
, nr
);
747 case 8: /* int write(int file,char *ptr,int len) */
751 char *buf
= zalloc (nr
);
752 sim_read (sd
, A1
, buf
, nr
);
753 V0
= sim_io_write (sd
, fd
, buf
, nr
);
758 case 10: /* int close(int file) */
760 V0
= sim_io_close (sd
, (int)A0
);
764 case 2: /* Densan monitor: char inbyte(int waitflag) */
766 if (A0
== 0) /* waitflag == NOWAIT */
767 V0
= (unsigned_word
)-1;
769 /* Drop through to case 11 */
771 case 11: /* char inbyte(void) */
774 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
776 sim_io_error(sd
,"Invalid return from character read");
777 V0
= (unsigned_word
)-1;
780 V0
= (unsigned_word
)tmp
;
784 case 3: /* Densan monitor: void co(char chr) */
785 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
787 char tmp
= (char)(A0
& 0xFF);
788 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
792 case 17: /* void _exit() */
794 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
795 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
796 (unsigned int)(A0
& 0xFFFFFFFF));
800 case 28 : /* PMON flush_cache */
803 case 55: /* void get_mem_info(unsigned int *ptr) */
804 /* in: A0 = pointer to three word memory location */
805 /* out: [A0 + 0] = size */
806 /* [A0 + 4] = instruction cache size */
807 /* [A0 + 8] = data cache size */
809 address_word value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
811 sim_write (sd
, A0
, (char *)&value
, sizeof (value
));
812 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
816 case 158 : /* PMON printf */
817 /* in: A0 = pointer to format string */
818 /* A1 = optional argument 1 */
819 /* A2 = optional argument 2 */
820 /* A3 = optional argument 3 */
822 /* The following is based on the PMON printf source */
826 signed_word
*ap
= &A1
; /* 1st argument */
827 /* This isn't the quickest way, since we call the host print
828 routine for every character almost. But it does avoid
829 having to allocate and manage a temporary string buffer. */
830 /* TODO: Include check that we only use three arguments (A1,
832 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
837 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
838 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
839 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
841 if (strchr ("dobxXulscefg%", s
))
856 else if (c
>= '1' && c
<= '9')
860 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
863 n
= (unsigned int)strtol(tmp
,NULL
,10);
876 sim_io_printf (sd
, "%%");
881 address_word p
= *ap
++;
883 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
884 sim_io_printf(sd
, "%c", ch
);
887 sim_io_printf(sd
,"(null)");
890 sim_io_printf (sd
, "%c", (int)*ap
++);
895 sim_read (sd
, s
++, &c
, 1);
899 sim_read (sd
, s
++, &c
, 1);
902 if (strchr ("dobxXu", c
))
904 word64 lv
= (word64
) *ap
++;
906 sim_io_printf(sd
,"<binary not supported>");
909 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
911 sim_io_printf(sd
, tmp
, lv
);
913 sim_io_printf(sd
, tmp
, (int)lv
);
916 else if (strchr ("eEfgG", c
))
918 double dbl
= *(double*)(ap
++);
919 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
920 sim_io_printf (sd
, tmp
, dbl
);
926 sim_io_printf(sd
, "%c", c
);
932 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
933 reason
, pr_addr(cia
));
939 /* Store a word into memory. */
942 store_word (SIM_DESC sd
,
951 if ((vaddr
& 3) != 0)
952 SignalExceptionAddressStore ();
955 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
958 const uword64 mask
= 7;
962 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
963 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
964 memval
= ((uword64
) val
) << (8 * byte
);
965 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
971 /* Load a word from memory. */
974 load_word (SIM_DESC sd
,
979 if ((vaddr
& 3) != 0)
980 SignalExceptionAddressLoad ();
986 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
989 const uword64 mask
= 0x7;
990 const unsigned int reverse
= ReverseEndian
? 1 : 0;
991 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
995 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
996 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
998 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
999 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1006 /* Simulate the mips16 entry and exit pseudo-instructions. These
1007 would normally be handled by the reserved instruction exception
1008 code, but for ease of simulation we just handle them directly. */
1011 mips16_entry (SIM_DESC sd
,
1016 int aregs
, sregs
, rreg
;
1019 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1022 aregs
= (insn
& 0x700) >> 8;
1023 sregs
= (insn
& 0x0c0) >> 6;
1024 rreg
= (insn
& 0x020) >> 5;
1026 /* This should be checked by the caller. */
1035 /* This is the entry pseudo-instruction. */
1037 for (i
= 0; i
< aregs
; i
++)
1038 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1046 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1049 for (i
= 0; i
< sregs
; i
++)
1052 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1060 /* This is the exit pseudo-instruction. */
1067 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1070 for (i
= 0; i
< sregs
; i
++)
1073 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1078 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1082 FGR
[0] = WORD64LO (GPR
[4]);
1083 FPR_STATE
[0] = fmt_uninterpreted
;
1085 else if (aregs
== 6)
1087 FGR
[0] = WORD64LO (GPR
[5]);
1088 FGR
[1] = WORD64LO (GPR
[4]);
1089 FPR_STATE
[0] = fmt_uninterpreted
;
1090 FPR_STATE
[1] = fmt_uninterpreted
;
1099 /*-- trace support ----------------------------------------------------------*/
1101 /* The TRACE support is provided (if required) in the memory accessing
1102 routines. Since we are also providing the architecture specific
1103 features, the architecture simulation code can also deal with
1104 notifying the TRACE world of cache flushes, etc. Similarly we do
1105 not need to provide profiling support in the simulator engine,
1106 since we can sample in the instruction fetch control loop. By
1107 defining the TRACE manifest, we add tracing as a run-time
1111 /* Tracing by default produces "din" format (as required by
1112 dineroIII). Each line of such a trace file *MUST* have a din label
1113 and address field. The rest of the line is ignored, so comments can
1114 be included if desired. The first field is the label which must be
1115 one of the following values:
1120 3 escape record (treated as unknown access type)
1121 4 escape record (causes cache flush)
1123 The address field is a 32bit (lower-case) hexadecimal address
1124 value. The address should *NOT* be preceded by "0x".
1126 The size of the memory transfer is not important when dealing with
1127 cache lines (as long as no more than a cache line can be
1128 transferred in a single operation :-), however more information
1129 could be given following the dineroIII requirement to allow more
1130 complete memory and cache simulators to provide better
1131 results. i.e. the University of Pisa has a cache simulator that can
1132 also take bus size and speed as (variable) inputs to calculate
1133 complete system performance (a much more useful ability when trying
1134 to construct an end product, rather than a processor). They
1135 currently have an ARM version of their tool called ChARM. */
1139 dotrace (SIM_DESC sd
,
1147 if (STATE
& simTRACE
) {
1149 fprintf(tracefh
,"%d %s ; width %d ; ",
1153 va_start(ap
,comment
);
1154 vfprintf(tracefh
,comment
,ap
);
1156 fprintf(tracefh
,"\n");
1158 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1159 we may be generating 64bit ones, we should put the hi-32bits of the
1160 address into the comment field. */
1162 /* TODO: Provide a buffer for the trace lines. We can then avoid
1163 performing writes until the buffer is filled, or the file is
1166 /* NOTE: We could consider adding a comment field to the "din" file
1167 produced using type 3 markers (unknown access). This would then
1168 allow information about the program that the "din" is for, and
1169 the MIPs world that was being simulated, to be placed into the
1176 /*---------------------------------------------------------------------------*/
1177 /*-- simulator engine -------------------------------------------------------*/
1178 /*---------------------------------------------------------------------------*/
1181 ColdReset (SIM_DESC sd
)
1184 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1186 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1187 /* RESET: Fixed PC address: */
1188 PC
= UNSIGNED64 (0xFFFFFFFFBFC00000);
1189 /* The reset vector address is in the unmapped, uncached memory space. */
1191 SR
&= ~(status_SR
| status_TS
| status_RP
);
1192 SR
|= (status_ERL
| status_BEV
);
1194 /* Cheat and allow access to the complete register set immediately */
1195 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1196 && WITH_TARGET_WORD_BITSIZE
== 64)
1197 SR
|= status_FR
; /* 64bit registers */
1199 /* Ensure that any instructions with pending register updates are
1203 for (loop
= 0; (loop
< PSLOTS
); loop
++)
1204 PENDING_SLOT_REG
[loop
] = (LAST_EMBED_REGNUM
+ 1);
1205 PENDING_IN
= PENDING_OUT
= PENDING_TOTAL
= 0;
1208 /* Initialise the FPU registers to the unknown state */
1209 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1212 for (rn
= 0; (rn
< 32); rn
++)
1213 FPR_STATE
[rn
] = fmt_uninterpreted
;
1219 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1221 /* Translate a virtual address to a physical address and cache
1222 coherence algorithm describing the mechanism used to resolve the
1223 memory reference. Given the virtual address vAddr, and whether the
1224 reference is to Instructions ot Data (IorD), find the corresponding
1225 physical address (pAddr) and the cache coherence algorithm (CCA)
1226 used to resolve the reference. If the virtual address is in one of
1227 the unmapped address spaces the physical address and the CCA are
1228 determined directly by the virtual address. If the virtual address
1229 is in one of the mapped address spaces then the TLB is used to
1230 determine the physical address and access type; if the required
1231 translation is not present in the TLB or the desired access is not
1232 permitted the function fails and an exception is taken.
1234 NOTE: Normally (RAW == 0), when address translation fails, this
1235 function raises an exception and does not return. */
1238 address_translation (SIM_DESC sd
,
1244 address_word
*pAddr
,
1248 int res
= -1; /* TRUE : Assume good return */
1251 sim_io_printf(sd
,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
1254 /* Check that the address is valid for this memory model */
1256 /* For a simple (flat) memory model, we simply pass virtual
1257 addressess through (mostly) unchanged. */
1258 vAddr
&= 0xFFFFFFFF;
1260 *pAddr
= vAddr
; /* default for isTARGET */
1261 *CCA
= Uncached
; /* not used for isHOST */
1266 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1268 /* Prefetch data from memory. Prefetch is an advisory instruction for
1269 which an implementation specific action is taken. The action taken
1270 may increase performance, but must not change the meaning of the
1271 program, or alter architecturally-visible state. */
1274 prefetch (SIM_DESC sd
,
1284 sim_io_printf(sd
,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA
,pr_addr(pAddr
),pr_addr(vAddr
),DATA
,hint
);
1287 /* For our simple memory model we do nothing */
1291 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1293 /* Load a value from memory. Use the cache and main memory as
1294 specified in the Cache Coherence Algorithm (CCA) and the sort of
1295 access (IorD) to find the contents of AccessLength memory bytes
1296 starting at physical location pAddr. The data is returned in the
1297 fixed width naturally-aligned memory element (MemElem). The
1298 low-order two (or three) bits of the address and the AccessLength
1299 indicate which of the bytes within MemElem needs to be given to the
1300 processor. If the memory access type of the reference is uncached
1301 then only the referenced bytes are read from memory and valid
1302 within the memory element. If the access type is cached, and the
1303 data is not present in cache, an implementation specific size and
1304 alignment block of memory is read and loaded into the cache to
1305 satisfy a load reference. At a minimum, the block is the entire
1308 load_memory (SIM_DESC sd
,
1323 sim_io_printf(sd
,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp
,memval1p
,CCA
,AccessLength
,pr_addr(pAddr
),pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"));
1326 #if defined(WARN_MEM)
1327 if (CCA
!= uncached
)
1328 sim_io_eprintf(sd
,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1329 #endif /* WARN_MEM */
1331 /* If instruction fetch then we need to check that the two lo-order
1332 bits are zero, otherwise raise a InstructionFetch exception: */
1333 if ((IorD
== isINSTRUCTION
)
1334 && ((pAddr
& 0x3) != 0)
1335 && (((pAddr
& 0x1) != 0) || ((vAddr
& 0x1) == 0)))
1336 SignalExceptionInstructionFetch ();
1338 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1340 /* In reality this should be a Bus Error */
1341 sim_io_error (sd
, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1343 (LOADDRMASK
+ 1) << 2,
1348 dotrace (SD
, CPU
, tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
1351 /* Read the specified number of bytes from memory. Adjust for
1352 host/target byte ordering/ Align the least significant byte
1355 switch (AccessLength
)
1357 case AccessLength_QUADWORD
:
1359 unsigned_16 val
= sim_core_read_aligned_16 (cpu
, NULL_CIA
,
1360 sim_core_read_map
, pAddr
);
1361 value1
= VH8_16 (val
);
1362 value
= VL8_16 (val
);
1365 case AccessLength_DOUBLEWORD
:
1366 value
= sim_core_read_aligned_8 (cpu
, NULL_CIA
,
1367 sim_core_read_map
, pAddr
);
1369 case AccessLength_SEPTIBYTE
:
1370 value
= sim_core_read_misaligned_7 (cpu
, NULL_CIA
,
1371 sim_core_read_map
, pAddr
);
1372 case AccessLength_SEXTIBYTE
:
1373 value
= sim_core_read_misaligned_6 (cpu
, NULL_CIA
,
1374 sim_core_read_map
, pAddr
);
1375 case AccessLength_QUINTIBYTE
:
1376 value
= sim_core_read_misaligned_5 (cpu
, NULL_CIA
,
1377 sim_core_read_map
, pAddr
);
1378 case AccessLength_WORD
:
1379 value
= sim_core_read_aligned_4 (cpu
, NULL_CIA
,
1380 sim_core_read_map
, pAddr
);
1382 case AccessLength_TRIPLEBYTE
:
1383 value
= sim_core_read_misaligned_3 (cpu
, NULL_CIA
,
1384 sim_core_read_map
, pAddr
);
1385 case AccessLength_HALFWORD
:
1386 value
= sim_core_read_aligned_2 (cpu
, NULL_CIA
,
1387 sim_core_read_map
, pAddr
);
1389 case AccessLength_BYTE
:
1390 value
= sim_core_read_aligned_1 (cpu
, NULL_CIA
,
1391 sim_core_read_map
, pAddr
);
1398 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1399 (int)(pAddr
& LOADDRMASK
),pr_uword64(value1
),pr_uword64(value
));
1402 /* See also store_memory. */
1403 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1406 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1407 shifted to the most significant byte position. */
1408 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1410 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1411 is already in the correct postition. */
1412 value
<<= ((pAddr
& LOADDRMASK
) * 8);
1416 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1417 pr_uword64(value1
),pr_uword64(value
));
1421 if (memval1p
) *memval1p
= value1
;
1425 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1427 /* Store a value to memory. The specified data is stored into the
1428 physical location pAddr using the memory hierarchy (data caches and
1429 main memory) as specified by the Cache Coherence Algorithm
1430 (CCA). The MemElem contains the data for an aligned, fixed-width
1431 memory element (word for 32-bit processors, doubleword for 64-bit
1432 processors), though only the bytes that will actually be stored to
1433 memory need to be valid. The low-order two (or three) bits of pAddr
1434 and the AccessLength field indicates which of the bytes within the
1435 MemElem data should actually be stored; only these bytes in memory
1439 store_memory (SIM_DESC sd
,
1445 uword64 MemElem1
, /* High order 64 bits */
1450 sim_io_printf(sd
,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA
,AccessLength
,pr_uword64(MemElem
),pr_uword64(MemElem1
),pr_addr(pAddr
),pr_addr(vAddr
));
1453 #if defined(WARN_MEM)
1454 if (CCA
!= uncached
)
1455 sim_io_eprintf(sd
,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1456 #endif /* WARN_MEM */
1458 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1459 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
1462 dotrace (SD
, CPU
, tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
1466 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr
& LOADDRMASK
),pr_uword64(MemElem1
),pr_uword64(MemElem
));
1469 /* See also load_memory */
1470 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1473 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1474 shifted to the most significant byte position. */
1475 MemElem
>>= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1477 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1478 is already in the correct postition. */
1479 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
1483 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift
,pr_uword64(MemElem1
),pr_uword64(MemElem
));
1486 switch (AccessLength
)
1488 case AccessLength_QUADWORD
:
1490 unsigned_16 val
= U16_8 (MemElem1
, MemElem
);
1491 sim_core_write_aligned_16 (cpu
, NULL_CIA
,
1492 sim_core_write_map
, pAddr
, val
);
1495 case AccessLength_DOUBLEWORD
:
1496 sim_core_write_aligned_8 (cpu
, NULL_CIA
,
1497 sim_core_write_map
, pAddr
, MemElem
);
1499 case AccessLength_SEPTIBYTE
:
1500 sim_core_write_misaligned_7 (cpu
, NULL_CIA
,
1501 sim_core_write_map
, pAddr
, MemElem
);
1503 case AccessLength_SEXTIBYTE
:
1504 sim_core_write_misaligned_6 (cpu
, NULL_CIA
,
1505 sim_core_write_map
, pAddr
, MemElem
);
1507 case AccessLength_QUINTIBYTE
:
1508 sim_core_write_misaligned_5 (cpu
, NULL_CIA
,
1509 sim_core_write_map
, pAddr
, MemElem
);
1511 case AccessLength_WORD
:
1512 sim_core_write_aligned_4 (cpu
, NULL_CIA
,
1513 sim_core_write_map
, pAddr
, MemElem
);
1515 case AccessLength_TRIPLEBYTE
:
1516 sim_core_write_misaligned_3 (cpu
, NULL_CIA
,
1517 sim_core_write_map
, pAddr
, MemElem
);
1519 case AccessLength_HALFWORD
:
1520 sim_core_write_aligned_2 (cpu
, NULL_CIA
,
1521 sim_core_write_map
, pAddr
, MemElem
);
1523 case AccessLength_BYTE
:
1524 sim_core_write_aligned_1 (cpu
, NULL_CIA
,
1525 sim_core_write_map
, pAddr
, MemElem
);
1536 ifetch32 (SIM_DESC sd
,
1541 /* Copy the action of the LW instruction */
1542 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1543 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1546 unsigned32 instruction
;
1549 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1550 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1551 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1552 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1553 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1558 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1559 /* Order loads and stores to synchronise shared memory. Perform the
1560 action necessary to make the effects of groups of synchronizable
1561 loads and stores indicated by stype occur in the same order for all
1564 sync_operation (SIM_DESC sd
,
1570 sim_io_printf(sd
,"SyncOperation(%d) : TODO\n",stype
);
1575 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1576 /* Signal an exception condition. This will result in an exception
1577 that aborts the instruction. The instruction operation pseudocode
1578 will never see a return from this function call. */
1581 signal_exception (SIM_DESC sd
,
1589 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1592 /* Ensure that any active atomic read/modify/write operation will fail: */
1595 switch (exception
) {
1596 /* TODO: For testing purposes I have been ignoring TRAPs. In
1597 reality we should either simulate them, or allow the user to
1598 ignore them at run-time.
1601 sim_io_eprintf(sd
,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia
));
1607 unsigned int instruction
;
1610 va_start(ap
,exception
);
1611 instruction
= va_arg(ap
,unsigned int);
1614 code
= (instruction
>> 6) & 0xFFFFF;
1616 sim_io_eprintf(sd
,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1617 code
, pr_addr(cia
));
1621 case DebugBreakPoint
:
1622 if (! (Debug
& Debug_DM
))
1628 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1629 DEPC
= cia
- 4; /* reference the branch instruction */
1633 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1637 Debug
|= Debug_DM
; /* in debugging mode */
1638 Debug
|= Debug_DBp
; /* raising a DBp exception */
1640 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1644 case ReservedInstruction
:
1647 unsigned int instruction
;
1648 va_start(ap
,exception
);
1649 instruction
= va_arg(ap
,unsigned int);
1651 /* Provide simple monitor support using ReservedInstruction
1652 exceptions. The following code simulates the fixed vector
1653 entry points into the IDT monitor by causing a simulator
1654 trap, performing the monitor operation, and returning to
1655 the address held in the $ra register (standard PCS return
1656 address). This means we only need to pre-load the vector
1657 space with suitable instruction values. For systems were
1658 actual trap instructions are used, we would not need to
1659 perform this magic. */
1660 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1662 sim_monitor (SD
, CPU
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1663 /* NOTE: This assumes that a branch-and-link style
1664 instruction was used to enter the vector (which is the
1665 case with the current IDT monitor). */
1666 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1668 /* Look for the mips16 entry and exit instructions, and
1669 simulate a handler for them. */
1670 else if ((cia
& 1) != 0
1671 && (instruction
& 0xf81f) == 0xe809
1672 && (instruction
& 0x0c0) != 0x0c0)
1674 mips16_entry (SD
, CPU
, cia
, instruction
);
1675 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1677 /* else fall through to normal exception processing */
1678 sim_io_eprintf(sd
,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction
,pr_addr(cia
));
1683 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1685 /* Keep a copy of the current A0 in-case this is the program exit
1689 unsigned int instruction
;
1690 va_start(ap
,exception
);
1691 instruction
= va_arg(ap
,unsigned int);
1693 /* Check for our special terminating BREAK: */
1694 if ((instruction
& 0x03FFFFC0) == 0x03ff0000) {
1695 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1696 sim_exited
, (unsigned int)(A0
& 0xFFFFFFFF));
1699 if (STATE
& simDELAYSLOT
)
1700 PC
= cia
- 4; /* reference the branch instruction */
1703 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1704 sim_stopped
, SIM_SIGTRAP
);
1707 /* Store exception code into current exception id variable (used
1710 /* TODO: If not simulating exceptions then stop the simulator
1711 execution. At the moment we always stop the simulation. */
1713 /* See figure 5-17 for an outline of the code below */
1714 if (! (SR
& status_EXL
))
1716 CAUSE
= (exception
<< 2);
1717 if (STATE
& simDELAYSLOT
)
1719 STATE
&= ~simDELAYSLOT
;
1721 EPC
= (cia
- 4); /* reference the branch instruction */
1725 /* FIXME: TLB et.al. */
1730 CAUSE
= (exception
<< 2);
1734 /* Store exception code into current exception id variable (used
1736 if (SR
& status_BEV
)
1737 PC
= (signed)0xBFC00200 + 0x180;
1739 PC
= (signed)0x80000000 + 0x180;
1741 switch ((CAUSE
>> 2) & 0x1F)
1744 /* Interrupts arrive during event processing, no need to
1748 case TLBModification
:
1753 case InstructionFetch
:
1755 /* The following is so that the simulator will continue from the
1756 exception address on breakpoint operations. */
1758 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1759 sim_stopped
, SIM_SIGBUS
);
1761 case ReservedInstruction
:
1762 case CoProcessorUnusable
:
1764 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1765 sim_stopped
, SIM_SIGILL
);
1767 case IntegerOverflow
:
1769 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1770 sim_stopped
, SIM_SIGFPE
);
1776 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1777 sim_stopped
, SIM_SIGTRAP
);
1781 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1782 "FATAL: Should not encounter a breakpoint\n");
1784 default : /* Unknown internal exception */
1786 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1787 sim_stopped
, SIM_SIGABRT
);
1791 case SimulatorFault
:
1795 va_start(ap
,exception
);
1796 msg
= va_arg(ap
,char *);
1798 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1799 "FATAL: Simulator error \"%s\"\n",msg
);
1806 #if defined(WARN_RESULT)
1807 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1808 /* This function indicates that the result of the operation is
1809 undefined. However, this should not affect the instruction
1810 stream. All that is meant to happen is that the destination
1811 register is set to an undefined result. To keep the simulator
1812 simple, we just don't bother updating the destination register, so
1813 the overall result will be undefined. If desired we can stop the
1814 simulator by raising a pseudo-exception. */
1815 #define UndefinedResult() undefined_result (sd,cia)
1817 undefined_result(sd
,cia
)
1821 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
1822 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1827 #endif /* WARN_RESULT */
1830 cache_op (SIM_DESC sd
,
1836 unsigned int instruction
)
1838 #if 1 /* stop warning message being displayed (we should really just remove the code) */
1839 static int icache_warning
= 1;
1840 static int dcache_warning
= 1;
1842 static int icache_warning
= 0;
1843 static int dcache_warning
= 0;
1846 /* If CP0 is not useable (User or Supervisor mode) and the CP0
1847 enable bit in the Status Register is clear - a coprocessor
1848 unusable exception is taken. */
1850 sim_io_printf(sd
,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia
));
1854 case 0: /* instruction cache */
1856 case 0: /* Index Invalidate */
1857 case 1: /* Index Load Tag */
1858 case 2: /* Index Store Tag */
1859 case 4: /* Hit Invalidate */
1861 case 6: /* Hit Writeback */
1862 if (!icache_warning
)
1864 sim_io_eprintf(sd
,"Instruction CACHE operation %d to be coded\n",(op
>> 2));
1870 SignalException(ReservedInstruction
,instruction
);
1875 case 1: /* data cache */
1877 case 0: /* Index Writeback Invalidate */
1878 case 1: /* Index Load Tag */
1879 case 2: /* Index Store Tag */
1880 case 3: /* Create Dirty */
1881 case 4: /* Hit Invalidate */
1882 case 5: /* Hit Writeback Invalidate */
1883 case 6: /* Hit Writeback */
1884 if (!dcache_warning
)
1886 sim_io_eprintf(sd
,"Data CACHE operation %d to be coded\n",(op
>> 2));
1892 SignalException(ReservedInstruction
,instruction
);
1897 default: /* unrecognised cache ID */
1898 SignalException(ReservedInstruction
,instruction
);
1905 /*-- FPU support routines ---------------------------------------------------*/
1907 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1908 formats conform to ANSI/IEEE Std 754-1985. */
1909 /* SINGLE precision floating:
1910 * seeeeeeeefffffffffffffffffffffff
1912 * e = 8bits = exponent
1913 * f = 23bits = fraction
1915 /* SINGLE precision fixed:
1916 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1918 * i = 31bits = integer
1920 /* DOUBLE precision floating:
1921 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1923 * e = 11bits = exponent
1924 * f = 52bits = fraction
1926 /* DOUBLE precision fixed:
1927 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1929 * i = 63bits = integer
1932 /* Extract sign-bit: */
1933 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
1934 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
1935 /* Extract biased exponent: */
1936 #define FP_S_be(v) (((v) >> 23) & 0xFF)
1937 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
1938 /* Extract unbiased Exponent: */
1939 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
1940 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1941 /* Extract complete fraction field: */
1942 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
1943 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
1944 /* Extract numbered fraction bit: */
1945 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1946 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1948 /* Explicit QNaN values used when value required: */
1949 #define FPQNaN_SINGLE (0x7FBFFFFF)
1950 #define FPQNaN_WORD (0x7FFFFFFF)
1951 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1952 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
1954 /* Explicit Infinity values used when required: */
1955 #define FPINF_SINGLE (0x7F800000)
1956 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
1958 #if 1 /* def DEBUG */
1959 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1960 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
1964 value_fpr (SIM_DESC sd
,
1973 /* Treat unused register values, as fixed-point 64bit values: */
1974 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
1976 /* If request to read data as "uninterpreted", then use the current
1978 fmt
= FPR_STATE
[fpr
];
1983 /* For values not yet accessed, set to the desired format: */
1984 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
1985 FPR_STATE
[fpr
] = fmt
;
1987 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
1990 if (fmt
!= FPR_STATE
[fpr
]) {
1991 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
1992 FPR_STATE
[fpr
] = fmt_unknown
;
1995 if (FPR_STATE
[fpr
] == fmt_unknown
) {
1996 /* Set QNaN value: */
1999 value
= FPQNaN_SINGLE
;
2003 value
= FPQNaN_DOUBLE
;
2007 value
= FPQNaN_WORD
;
2011 value
= FPQNaN_LONG
;
2018 } else if (SizeFGR() == 64) {
2022 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2025 case fmt_uninterpreted
:
2039 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2042 case fmt_uninterpreted
:
2045 if ((fpr
& 1) == 0) { /* even registers only */
2046 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2048 SignalException(ReservedInstruction
,0);
2059 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2062 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2069 store_fpr (SIM_DESC sd
,
2079 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2082 if (SizeFGR() == 64) {
2084 case fmt_uninterpreted_32
:
2085 fmt
= fmt_uninterpreted
;
2088 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2089 FPR_STATE
[fpr
] = fmt
;
2092 case fmt_uninterpreted_64
:
2093 fmt
= fmt_uninterpreted
;
2094 case fmt_uninterpreted
:
2098 FPR_STATE
[fpr
] = fmt
;
2102 FPR_STATE
[fpr
] = fmt_unknown
;
2108 case fmt_uninterpreted_32
:
2109 fmt
= fmt_uninterpreted
;
2112 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2113 FPR_STATE
[fpr
] = fmt
;
2116 case fmt_uninterpreted_64
:
2117 fmt
= fmt_uninterpreted
;
2118 case fmt_uninterpreted
:
2121 if ((fpr
& 1) == 0) { /* even register number only */
2122 FGR
[fpr
+1] = (value
>> 32);
2123 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2124 FPR_STATE
[fpr
+ 1] = fmt
;
2125 FPR_STATE
[fpr
] = fmt
;
2127 FPR_STATE
[fpr
] = fmt_unknown
;
2128 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2129 SignalException(ReservedInstruction
,0);
2134 FPR_STATE
[fpr
] = fmt_unknown
;
2139 #if defined(WARN_RESULT)
2142 #endif /* WARN_RESULT */
2145 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2148 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
2165 sim_fpu_32to (&wop
, op
);
2166 boolean
= sim_fpu_is_nan (&wop
);
2173 sim_fpu_64to (&wop
, op
);
2174 boolean
= sim_fpu_is_nan (&wop
);
2178 fprintf (stderr
, "Bad switch\n");
2183 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2197 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2204 sim_fpu_32to (&wop
, op
);
2205 boolean
= sim_fpu_is_infinity (&wop
);
2211 sim_fpu_64to (&wop
, op
);
2212 boolean
= sim_fpu_is_infinity (&wop
);
2216 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2221 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2235 /* Argument checking already performed by the FPCOMPARE code */
2238 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2241 /* The format type should already have been checked: */
2247 sim_fpu_32to (&wop1
, op1
);
2248 sim_fpu_32to (&wop2
, op2
);
2249 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2256 sim_fpu_64to (&wop1
, op1
);
2257 sim_fpu_64to (&wop2
, op2
);
2258 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2262 fprintf (stderr
, "Bad switch\n");
2267 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2281 /* Argument checking already performed by the FPCOMPARE code */
2284 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2287 /* The format type should already have been checked: */
2293 sim_fpu_32to (&wop1
, op1
);
2294 sim_fpu_32to (&wop2
, op2
);
2295 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2302 sim_fpu_64to (&wop1
, op1
);
2303 sim_fpu_64to (&wop2
, op2
);
2304 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2308 fprintf (stderr
, "Bad switch\n");
2313 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2320 AbsoluteValue(op
,fmt
)
2327 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2330 /* The format type should already have been checked: */
2336 sim_fpu_32to (&wop
, op
);
2337 sim_fpu_abs (&wop
, &wop
);
2338 sim_fpu_to32 (&ans
, &wop
);
2346 sim_fpu_64to (&wop
, op
);
2347 sim_fpu_abs (&wop
, &wop
);
2348 sim_fpu_to64 (&ans
, &wop
);
2353 fprintf (stderr
, "Bad switch\n");
2368 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2371 /* The format type should already have been checked: */
2377 sim_fpu_32to (&wop
, op
);
2378 sim_fpu_neg (&wop
, &wop
);
2379 sim_fpu_to32 (&ans
, &wop
);
2387 sim_fpu_64to (&wop
, op
);
2388 sim_fpu_neg (&wop
, &wop
);
2389 sim_fpu_to64 (&ans
, &wop
);
2394 fprintf (stderr
, "Bad switch\n");
2410 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2413 /* The registers must specify FPRs valid for operands of type
2414 "fmt". If they are not valid, the result is undefined. */
2416 /* The format type should already have been checked: */
2424 sim_fpu_32to (&wop1
, op1
);
2425 sim_fpu_32to (&wop2
, op2
);
2426 sim_fpu_add (&ans
, &wop1
, &wop2
);
2427 sim_fpu_to32 (&res
, &ans
);
2437 sim_fpu_64to (&wop1
, op1
);
2438 sim_fpu_64to (&wop2
, op2
);
2439 sim_fpu_add (&ans
, &wop1
, &wop2
);
2440 sim_fpu_to64 (&res
, &ans
);
2445 fprintf (stderr
, "Bad switch\n");
2450 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2465 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2468 /* The registers must specify FPRs valid for operands of type
2469 "fmt". If they are not valid, the result is undefined. */
2471 /* The format type should already have been checked: */
2479 sim_fpu_32to (&wop1
, op1
);
2480 sim_fpu_32to (&wop2
, op2
);
2481 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2482 sim_fpu_to32 (&res
, &ans
);
2492 sim_fpu_64to (&wop1
, op1
);
2493 sim_fpu_64to (&wop2
, op2
);
2494 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2495 sim_fpu_to64 (&res
, &ans
);
2500 fprintf (stderr
, "Bad switch\n");
2505 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2512 Multiply(op1
,op2
,fmt
)
2520 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2523 /* The registers must specify FPRs valid for operands of type
2524 "fmt". If they are not valid, the result is undefined. */
2526 /* The format type should already have been checked: */
2534 sim_fpu_32to (&wop1
, op1
);
2535 sim_fpu_32to (&wop2
, op2
);
2536 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2537 sim_fpu_to32 (&res
, &ans
);
2547 sim_fpu_64to (&wop1
, op1
);
2548 sim_fpu_64to (&wop2
, op2
);
2549 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2550 sim_fpu_to64 (&res
, &ans
);
2555 fprintf (stderr
, "Bad switch\n");
2560 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2575 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2578 /* The registers must specify FPRs valid for operands of type
2579 "fmt". If they are not valid, the result is undefined. */
2581 /* The format type should already have been checked: */
2589 sim_fpu_32to (&wop1
, op1
);
2590 sim_fpu_32to (&wop2
, op2
);
2591 sim_fpu_div (&ans
, &wop1
, &wop2
);
2592 sim_fpu_to32 (&res
, &ans
);
2602 sim_fpu_64to (&wop1
, op1
);
2603 sim_fpu_64to (&wop2
, op2
);
2604 sim_fpu_div (&ans
, &wop1
, &wop2
);
2605 sim_fpu_to64 (&res
, &ans
);
2610 fprintf (stderr
, "Bad switch\n");
2615 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2629 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2632 /* The registers must specify FPRs valid for operands of type
2633 "fmt". If they are not valid, the result is undefined. */
2635 /* The format type should already have been checked: */
2642 sim_fpu_32to (&wop
, op
);
2643 sim_fpu_inv (&ans
, &wop
);
2644 sim_fpu_to32 (&res
, &ans
);
2653 sim_fpu_64to (&wop
, op
);
2654 sim_fpu_inv (&ans
, &wop
);
2655 sim_fpu_to64 (&res
, &ans
);
2660 fprintf (stderr
, "Bad switch\n");
2665 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2679 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2682 /* The registers must specify FPRs valid for operands of type
2683 "fmt". If they are not valid, the result is undefined. */
2685 /* The format type should already have been checked: */
2692 sim_fpu_32to (&wop
, op
);
2693 sim_fpu_sqrt (&ans
, &wop
);
2694 sim_fpu_to32 (&res
, &ans
);
2703 sim_fpu_64to (&wop
, op
);
2704 sim_fpu_sqrt (&ans
, &wop
);
2705 sim_fpu_to64 (&res
, &ans
);
2710 fprintf (stderr
, "Bad switch\n");
2715 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2722 convert (SIM_DESC sd
,
2731 sim_fpu_round round
;
2732 unsigned32 result32
;
2733 unsigned64 result64
;
2736 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
2742 /* Round result to nearest representable value. When two
2743 representable values are equally near, round to the value
2744 that has a least significant bit of zero (i.e. is even). */
2745 round
= sim_fpu_round_near
;
2748 /* Round result to the value closest to, and not greater in
2749 magnitude than, the result. */
2750 round
= sim_fpu_round_zero
;
2753 /* Round result to the value closest to, and not less than,
2755 round
= sim_fpu_round_up
;
2759 /* Round result to the value closest to, and not greater than,
2761 round
= sim_fpu_round_down
;
2765 fprintf (stderr
, "Bad switch\n");
2769 /* Convert the input to sim_fpu internal format */
2773 sim_fpu_64to (&wop
, op
);
2776 sim_fpu_32to (&wop
, op
);
2779 sim_fpu_i32to (&wop
, op
, round
);
2782 sim_fpu_i64to (&wop
, op
, round
);
2785 fprintf (stderr
, "Bad switch\n");
2789 /* Convert sim_fpu format into the output */
2790 /* The value WOP is converted to the destination format, rounding
2791 using mode RM. When the destination is a fixed-point format, then
2792 a source value of Infinity, NaN or one which would round to an
2793 integer outside the fixed point range then an IEEE Invalid
2794 Operation condition is raised. */
2798 sim_fpu_round_32 (&wop
, round
, 0);
2799 sim_fpu_to32 (&result32
, &wop
);
2800 result64
= result32
;
2803 sim_fpu_round_64 (&wop
, round
, 0);
2804 sim_fpu_to64 (&result64
, &wop
);
2807 sim_fpu_to32i (&result32
, &wop
, round
);
2808 result64
= result32
;
2811 sim_fpu_to64i (&result64
, &wop
, round
);
2815 fprintf (stderr
, "Bad switch\n");
2820 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
2827 /*-- co-processor support routines ------------------------------------------*/
2830 CoProcPresent(coproc_number
)
2831 unsigned int coproc_number
;
2833 /* Return TRUE if simulator provides a model for the given co-processor number */
2838 cop_lw (SIM_DESC sd
,
2843 unsigned int memword
)
2848 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2851 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
2853 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
2854 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
2859 #if 0 /* this should be controlled by a configuration option */
2860 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
2869 cop_ld (SIM_DESC sd
,
2876 switch (coproc_num
) {
2878 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2880 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
2885 #if 0 /* this message should be controlled by a configuration option */
2886 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
2895 cop_sw (SIM_DESC sd
,
2901 unsigned int value
= 0;
2906 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2909 hold
= FPR_STATE
[coproc_reg
];
2910 FPR_STATE
[coproc_reg
] = fmt_word
;
2911 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
2912 FPR_STATE
[coproc_reg
] = hold
;
2917 #if 0 /* should be controlled by configuration option */
2918 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2927 cop_sd (SIM_DESC sd
,
2937 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2939 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
2944 #if 0 /* should be controlled by configuration option */
2945 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2954 decode_coproc (SIM_DESC sd
,
2957 unsigned int instruction
)
2959 int coprocnum
= ((instruction
>> 26) & 3);
2963 case 0: /* standard CPU control and cache registers */
2965 int code
= ((instruction
>> 21) & 0x1F);
2966 /* R4000 Users Manual (second edition) lists the following CP0
2968 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2969 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2970 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2971 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2972 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2973 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2974 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2975 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2976 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2977 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2979 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0))
2981 int rt
= ((instruction
>> 16) & 0x1F);
2982 int rd
= ((instruction
>> 11) & 0x1F);
2984 switch (rd
) /* NOTEs: Standard CP0 registers */
2986 /* 0 = Index R4000 VR4100 VR4300 */
2987 /* 1 = Random R4000 VR4100 VR4300 */
2988 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2989 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2990 /* 4 = Context R4000 VR4100 VR4300 */
2991 /* 5 = PageMask R4000 VR4100 VR4300 */
2992 /* 6 = Wired R4000 VR4100 VR4300 */
2993 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2994 /* 9 = Count R4000 VR4100 VR4300 */
2995 /* 10 = EntryHi R4000 VR4100 VR4300 */
2996 /* 11 = Compare R4000 VR4100 VR4300 */
2997 /* 12 = SR R4000 VR4100 VR4300 */
3004 /* 13 = Cause R4000 VR4100 VR4300 */
3011 /* 14 = EPC R4000 VR4100 VR4300 */
3012 /* 15 = PRId R4000 VR4100 VR4300 */
3013 #ifdef SUBTARGET_R3900
3022 /* 16 = Config R4000 VR4100 VR4300 */
3025 GPR
[rt
] = C0_CONFIG
;
3027 C0_CONFIG
= GPR
[rt
];
3030 #ifdef SUBTARGET_R3900
3039 /* 17 = LLAddr R4000 VR4100 VR4300 */
3041 /* 18 = WatchLo R4000 VR4100 VR4300 */
3042 /* 19 = WatchHi R4000 VR4100 VR4300 */
3043 /* 20 = XContext R4000 VR4100 VR4300 */
3044 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3045 /* 27 = CacheErr R4000 VR4100 */
3046 /* 28 = TagLo R4000 VR4100 VR4300 */
3047 /* 29 = TagHi R4000 VR4100 VR4300 */
3048 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3049 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3050 /* CPR[0,rd] = GPR[rt]; */
3053 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3055 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3058 else if (code
== 0x10 && (instruction
& 0x3f) == 0x18)
3061 if (SR
& status_ERL
)
3063 /* Oops, not yet available */
3064 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3074 else if (code
== 0x10 && (instruction
& 0x3f) == 0x10)
3078 else if (code
== 0x10 && (instruction
& 0x3f) == 0x1F)
3086 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3087 /* TODO: When executing an ERET or RFE instruction we should
3088 clear LLBIT, to ensure that any out-standing atomic
3089 read/modify/write sequence fails. */
3093 case 2: /* undefined co-processor */
3094 sim_io_eprintf(sd
,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3097 case 1: /* should not occur (FPU co-processor) */
3098 case 3: /* should not occur (FPU co-processor) */
3099 SignalException(ReservedInstruction
,instruction
);
3106 /*-- instruction simulation -------------------------------------------------*/
3108 /* When the IGEN simulator is being built, the function below is be
3109 replaced by a generated version. However, WITH_IGEN == 2 indicates
3110 that the fubction below should be compiled but under a different
3111 name (to allow backward compatibility) */
3113 #if (WITH_IGEN != 1)
3115 void old_engine_run
PARAMS ((SIM_DESC sd
, int next_cpu_nr
, int siggnal
));
3117 old_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3120 sim_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3123 int next_cpu_nr
; /* ignore */
3124 int nr_cpus
; /* ignore */
3125 int siggnal
; /* ignore */
3127 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* hardwire to cpu 0 */
3128 #if !defined(FASTSIM)
3129 unsigned int pipeline_count
= 1;
3133 if (STATE_MEMORY (sd
) == NULL
) {
3134 printf("DBG: simulate() entered with no memory\n");
3139 #if 0 /* Disabled to check that everything works OK */
3140 /* The VR4300 seems to sign-extend the PC on its first
3141 access. However, this may just be because it is currently
3142 configured in 32bit mode. However... */
3143 PC
= SIGNEXTEND(PC
,32);
3146 /* main controlling loop */
3148 /* vaddr is slowly being replaced with cia - current instruction
3150 address_word cia
= (uword64
)PC
;
3151 address_word vaddr
= cia
;
3154 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
3158 printf("DBG: state = 0x%08X :",state
);
3159 if (state
& simHALTEX
) printf(" simHALTEX");
3160 if (state
& simHALTIN
) printf(" simHALTIN");
3165 DSSTATE
= (STATE
& simDELAYSLOT
);
3168 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
3171 /* Fetch the next instruction from the simulator memory: */
3172 if (AddressTranslation(cia
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
3173 if ((vaddr
& 1) == 0) {
3174 /* Copy the action of the LW instruction */
3175 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
3176 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
3179 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
3180 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3181 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
3182 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3184 /* Copy the action of the LH instruction */
3185 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
3186 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
3189 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
3190 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
3191 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
3192 paddr
& ~ (uword64
) 1,
3193 vaddr
, isINSTRUCTION
, isREAL
);
3194 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
3195 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
3198 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
3203 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
3206 /* This is required by exception processing, to ensure that we can
3207 cope with exceptions in the delay slots of branches that may
3208 already have changed the PC. */
3209 if ((vaddr
& 1) == 0)
3210 PC
+= 4; /* increment ready for the next fetch */
3213 /* NOTE: If we perform a delay slot change to the PC, this
3214 increment is not requuired. However, it would make the
3215 simulator more complicated to try and avoid this small hit. */
3217 /* Currently this code provides a simple model. For more
3218 complicated models we could perform exception status checks at
3219 this point, and set the simSTOP state as required. This could
3220 also include processing any hardware interrupts raised by any
3221 I/O model attached to the simulator context.
3223 Support for "asynchronous" I/O events within the simulated world
3224 could be providing by managing a counter, and calling a I/O
3225 specific handler when a particular threshold is reached. On most
3226 architectures a decrement and check for zero operation is
3227 usually quicker than an increment and compare. However, the
3228 process of managing a known value decrement to zero, is higher
3229 than the cost of using an explicit value UINT_MAX into the
3230 future. Which system is used will depend on how complicated the
3231 I/O model is, and how much it is likely to affect the simulator
3234 If events need to be scheduled further in the future than
3235 UINT_MAX event ticks, then the I/O model should just provide its
3236 own counter, triggered from the event system. */
3238 /* MIPS pipeline ticks. To allow for future support where the
3239 pipeline hit of individual instructions is known, this control
3240 loop manages a "pipeline_count" variable. It is initialised to
3241 1 (one), and will only be changed by the simulator engine when
3242 executing an instruction. If the engine does not have access to
3243 pipeline cycle count information then all instructions will be
3244 treated as using a single cycle. NOTE: A standard system is not
3245 provided by the default simulator because different MIPS
3246 architectures have different cycle counts for the same
3249 [NOTE: pipeline_count has been replaced the event queue] */
3251 /* shuffle the floating point status pipeline state */
3252 ENGINE_ISSUE_PREFIX_HOOK();
3254 /* NOTE: For multi-context simulation environments the "instruction"
3255 variable should be local to this routine. */
3257 /* Shorthand accesses for engine. Note: If we wanted to use global
3258 variables (and a single-threaded simulator engine), then we can
3259 create the actual variables with these names. */
3261 if (!(STATE
& simSKIPNEXT
)) {
3262 /* Include the simulator engine */
3263 #include "oengine.c"
3264 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3265 #error "Mismatch between run-time simulator code and simulation engine"
3267 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3268 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3270 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3271 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3274 #if defined(WARN_LOHI)
3275 /* Decrement the HI/LO validity ticks */
3280 /* start-sanitize-r5900 */
3285 /* end-sanitize-r5900 */
3286 #endif /* WARN_LOHI */
3288 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3289 should check for it being changed. It is better doing it here,
3290 than within the simulator, since it will help keep the simulator
3293 #if defined(WARN_ZERO)
3294 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(cia
));
3295 #endif /* WARN_ZERO */
3296 ZERO
= 0; /* reset back to zero before next instruction */
3298 } else /* simSKIPNEXT check */
3299 STATE
&= ~simSKIPNEXT
;
3301 /* If the delay slot was active before the instruction is
3302 executed, then update the PC to its new value: */
3305 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
3311 if (MIPSISA
< 4) { /* The following is only required on pre MIPS IV processors: */
3312 /* Deal with pending register updates: */
3314 printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in
,pending_out
,pending_total
);
3316 if (PENDING_OUT
!= PENDING_IN
) {
3318 int index
= PENDING_OUT
;
3319 int total
= PENDING_TOTAL
;
3320 if (PENDING_TOTAL
== 0) {
3321 fprintf(stderr
,"FATAL: Mis-match on pending update pointers\n");
3324 for (loop
= 0; (loop
< total
); loop
++) {
3326 printf("DBG: BEFORE index = %d, loop = %d\n",index
,loop
);
3328 if (PENDING_SLOT_REG
[index
] != (LAST_EMBED_REGNUM
+ 1)) {
3330 printf("pending_slot_count[%d] = %d\n",index
,PENDING_SLOT_COUNT
[index
]);
3332 if (--(PENDING_SLOT_COUNT
[index
]) == 0) {
3334 printf("pending_slot_reg[%d] = %d\n",index
,PENDING_SLOT_REG
[index
]);
3335 printf("pending_slot_value[%d] = 0x%s\n",index
,pr_addr(PENDING_SLOT_VALUE
[index
]));
3337 if (PENDING_SLOT_REG
[index
] == COCIDX
)
3339 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3341 SETFCC(0,((FCR31
& (1 << 23)) ? 1 : 0));
3346 REGISTERS
[PENDING_SLOT_REG
[index
]] = PENDING_SLOT_VALUE
[index
];
3347 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3349 /* The only time we have PENDING updates to FPU
3350 registers, is when performing binary transfers. This
3351 means we should update the register type field. */
3352 if ((PENDING_SLOT_REG
[index
] >= FGRIDX
) && (PENDING_SLOT_REG
[index
] < (FGRIDX
+ 32)))
3353 FPR_STATE
[PENDING_SLOT_REG
[index
] - FGRIDX
] = fmt_uninterpreted
;
3357 printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG
[index
],pr_addr(REGISTERS
[PENDING_SLOT_REG
[index
]]));
3359 PENDING_SLOT_REG
[index
] = (LAST_EMBED_REGNUM
+ 1);
3361 if (PENDING_OUT
== PSLOTS
)
3367 printf("DBG: AFTER index = %d, loop = %d\n",index
,loop
);
3370 if (index
== PSLOTS
)
3375 printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN
,PENDING_OUT
,PENDING_TOTAL
);
3379 #if !defined(FASTSIM)
3380 if (sim_events_tickn (sd
, pipeline_count
))
3382 /* cpu->cia = cia; */
3383 sim_events_process (sd
);
3386 if (sim_events_tick (sd
))
3388 /* cpu->cia = cia; */
3389 sim_events_process (sd
);
3391 #endif /* FASTSIM */
3397 /* This code copied from gdb's utils.c. Would like to share this code,
3398 but don't know of a common place where both could get to it. */
3400 /* Temporary storage using circular buffer */
3406 static char buf
[NUMCELLS
][CELLSIZE
];
3408 if (++cell
>=NUMCELLS
) cell
=0;
3412 /* Print routines to handle variable size regs, etc */
3414 /* Eliminate warning from compiler on 32-bit systems */
3415 static int thirty_two
= 32;
3421 char *paddr_str
=get_cell();
3422 switch (sizeof(addr
))
3425 sprintf(paddr_str
,"%08lx%08lx",
3426 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3429 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3432 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3435 sprintf(paddr_str
,"%x",addr
);
3444 char *paddr_str
=get_cell();
3445 sprintf(paddr_str
,"%08lx%08lx",
3446 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3451 /*---------------------------------------------------------------------------*/
3452 /*> EOF interp.c <*/