projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
* sky-pke.c(read_pke_pc): return source address of current pc
[deliverable/binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 $Revision$
17 $Date$
18
19 NOTEs:
20
21 The IDT monitor (found on the VR4300 board), seems to lie about
22 register contents. It seems to treat the registers as sign-extended
23 32-bit values. This cause *REAL* problems when single-stepping 64-bit
24 code on the hardware.
25
26 */
27
28 /* The TRACE manifests enable the provision of extra features. If they
29 are not defined then a simpler (quicker) simulator is constructed
30 without the required run-time checks, etc. */
31 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
32 #define TRACE (1)
33 #endif
34
35 #include "bfd.h"
36 #include "sim-main.h"
37 #include "sim-utils.h"
38 #include "sim-options.h"
39 #include "sim-assert.h"
40 #include "sim-hw.h"
41
42 /* start-sanitize-sky */
43 #ifdef TARGET_SKY
44 #include "sky-vu.h"
45 #include "sky-vpe.h"
46 #include "sky-libvpe.h"
47 #include "sky-pke.h"
48 #include "idecode.h"
49 #include "support.h"
50 #include "sky-gdb.h"
51 #undef SD
52 #endif
53 /* end-sanitize-sky */
54
55 #include "config.h"
56
57 #include <stdio.h>
58 #include <stdarg.h>
59 #include <ansidecl.h>
60 #include <ctype.h>
61 #include <limits.h>
62 #include <math.h>
63 #ifdef HAVE_STDLIB_H
64 #include <stdlib.h>
65 #endif
66 #ifdef HAVE_STRING_H
67 #include <string.h>
68 #else
69 #ifdef HAVE_STRINGS_H
70 #include <strings.h>
71 #endif
72 #endif
73
74 #include "getopt.h"
75 #include "libiberty.h"
76 #include "bfd.h"
77 #include "callback.h" /* GDB simulator callback interface */
78 #include "remote-sim.h" /* GDB simulator interface */
79
80 #include "sysdep.h"
81
82 #ifndef PARAMS
83 #define PARAMS(x)
84 #endif
85
86 char* pr_addr PARAMS ((SIM_ADDR addr));
87 char* pr_uword64 PARAMS ((uword64 addr));
88
89
90 /* Get the simulator engine description, without including the code: */
91 #if !(WITH_IGEN)
92 #define SIM_MANIFESTS
93 #include "oengine.c"
94 #undef SIM_MANIFESTS
95 #endif
96
97 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
98 #define CPU cpu
99 #define SD sd
100
101
102 /* The following reserved instruction value is used when a simulator
103 trap is required. NOTE: Care must be taken, since this value may be
104 used in later revisions of the MIPS ISA. */
105
106 #define RSVD_INSTRUCTION (0x00000005)
107 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
108
109 #define RSVD_INSTRUCTION_ARG_SHIFT 6
110 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
111
112
113 /* Bits in the Debug register */
114 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
115 #define Debug_DM 0x40000000 /* Debug Mode */
116 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
117
118 /*---------------------------------------------------------------------------*/
119 /*-- GDB simulator interface ------------------------------------------------*/
120 /*---------------------------------------------------------------------------*/
121
122 static void ColdReset PARAMS((SIM_DESC sd));
123
124 /*---------------------------------------------------------------------------*/
125
126
127
128 #define DELAYSLOT() {\
129 if (STATE & simDELAYSLOT)\
130 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
131 STATE |= simDELAYSLOT;\
132 }
133
134 #define JALDELAYSLOT() {\
135 DELAYSLOT ();\
136 STATE |= simJALDELAYSLOT;\
137 }
138
139 #define NULLIFY() {\
140 STATE &= ~simDELAYSLOT;\
141 STATE |= simSKIPNEXT;\
142 }
143
144 #define CANCELDELAYSLOT() {\
145 DSSTATE = 0;\
146 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
147 }
148
149 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
150 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
151
152 #define K0BASE (0x80000000)
153 #define K0SIZE (0x20000000)
154 #define K1BASE (0xA0000000)
155 #define K1SIZE (0x20000000)
156 #define MONITOR_BASE (0xBFC00000)
157 #define MONITOR_SIZE (1 << 11)
158 #define MEM_SIZE (2 << 20)
159
160 /* start-sanitize-sky */
161 #ifdef TARGET_SKY
162 #undef MEM_SIZE
163 #define MEM_SIZE (16 << 20) /* 16 MB */
164 #endif
165 /* end-sanitize-sky */
166
167 #if defined(TRACE)
168 static char *tracefile = "trace.din"; /* default filename for trace log */
169 FILE *tracefh = NULL;
170 static void open_trace PARAMS((SIM_DESC sd));
171 #endif /* TRACE */
172
173 /* simulation target board. NULL=canonical */
174 static char* board = NULL;
175
176
177 static DECLARE_OPTION_HANDLER (mips_option_handler);
178
179 enum {
180 OPTION_DINERO_TRACE = OPTION_START,
181 OPTION_DINERO_FILE,
182 OPTION_BOARD
183 };
184
185
186 static SIM_RC
187 mips_option_handler (sd, cpu, opt, arg, is_command)
188 SIM_DESC sd;
189 sim_cpu *cpu;
190 int opt;
191 char *arg;
192 int is_command;
193 {
194 int cpu_nr;
195 switch (opt)
196 {
197 case OPTION_DINERO_TRACE: /* ??? */
198 #if defined(TRACE)
199 /* Eventually the simTRACE flag could be treated as a toggle, to
200 allow external control of the program points being traced
201 (i.e. only from main onwards, excluding the run-time setup,
202 etc.). */
203 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
204 {
205 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
206 if (arg == NULL)
207 STATE |= simTRACE;
208 else if (strcmp (arg, "yes") == 0)
209 STATE |= simTRACE;
210 else if (strcmp (arg, "no") == 0)
211 STATE &= ~simTRACE;
212 else if (strcmp (arg, "on") == 0)
213 STATE |= simTRACE;
214 else if (strcmp (arg, "off") == 0)
215 STATE &= ~simTRACE;
216 else
217 {
218 fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
219 return SIM_RC_FAIL;
220 }
221 }
222 return SIM_RC_OK;
223 #else /* !TRACE */
224 fprintf(stderr,"\
225 Simulator constructed without dinero tracing support (for performance).\n\
226 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
227 return SIM_RC_FAIL;
228 #endif /* !TRACE */
229
230 case OPTION_DINERO_FILE:
231 #if defined(TRACE)
232 if (optarg != NULL) {
233 char *tmp;
234 tmp = (char *)malloc(strlen(optarg) + 1);
235 if (tmp == NULL)
236 {
237 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
238 return SIM_RC_FAIL;
239 }
240 else {
241 strcpy(tmp,optarg);
242 tracefile = tmp;
243 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
244 }
245 }
246 #endif /* TRACE */
247 return SIM_RC_OK;
248
249 case OPTION_BOARD:
250 {
251 if (arg)
252 {
253 board = zalloc(strlen(arg) + 1);
254 strcpy(board, arg);
255 }
256 return SIM_RC_OK;
257 }
258 }
259
260 return SIM_RC_OK;
261 }
262
263
264 static const OPTION mips_options[] =
265 {
266 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
267 '\0', "on|off", "Enable dinero tracing",
268 mips_option_handler },
269 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
270 '\0', "FILE", "Write dinero trace to FILE",
271 mips_option_handler },
272 { {"board", required_argument, NULL, OPTION_BOARD},
273 '\0', "none" /* rely on compile-time string concatenation for other options */
274
275 /* start-sanitize-tx3904 */
276 #define BOARD_JMR3904 "jmr3904"
277 "|" BOARD_JMR3904
278 #define BOARD_JMR3904_PAL "jmr3904pal"
279 "|" BOARD_JMR3904_PAL
280 #define BOARD_JMR3904_DEBUG "jmr3904debug"
281 "|" BOARD_JMR3904_DEBUG
282 /* end-sanitize-tx3904 */
283
284 , "Customize simulation for a particular board.", mips_option_handler },
285
286 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
287 };
288
289
290 int interrupt_pending;
291
292 void
293 interrupt_event (SIM_DESC sd, void *data)
294 {
295 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
296 address_word cia = CIA_GET (cpu);
297 if (SR & status_IE)
298 {
299 interrupt_pending = 0;
300 SignalExceptionInterrupt ();
301 }
302 else if (!interrupt_pending)
303 sim_events_schedule (sd, 1, interrupt_event, data);
304 }
305
306
307 /*---------------------------------------------------------------------------*/
308 /*-- Device registration hook -----------------------------------------------*/
309 /*---------------------------------------------------------------------------*/
310 static void device_init(SIM_DESC sd) {
311 #ifdef DEVICE_INIT
312 extern void register_devices(SIM_DESC);
313 register_devices(sd);
314 #endif
315 }
316
317 /*---------------------------------------------------------------------------*/
318 /*-- GDB simulator interface ------------------------------------------------*/
319 /*---------------------------------------------------------------------------*/
320
321 SIM_DESC
322 sim_open (kind, cb, abfd, argv)
323 SIM_OPEN_KIND kind;
324 host_callback *cb;
325 struct _bfd *abfd;
326 char **argv;
327 {
328 SIM_DESC sd = sim_state_alloc (kind, cb);
329 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
330
331 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
332
333
334 /* FIXME: watchpoints code shouldn't need this */
335 STATE_WATCHPOINTS (sd)->pc = &(PC);
336 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
337 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
338
339 STATE = 0;
340
341 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
342 return 0;
343 sim_add_option_table (sd, NULL, mips_options);
344
345 /* start-sanitize-sky */
346 #ifdef TARGET_SKY
347 sky_command_options_open (sd);
348 #endif
349 /* end-sanitize-sky */
350
351 /* getopt will print the error message so we just have to exit if this fails.
352 FIXME: Hmmm... in the case of gdb we need getopt to call
353 print_filtered. */
354 if (sim_parse_args (sd, argv) != SIM_RC_OK)
355 {
356 /* Uninstall the modules to avoid memory leaks,
357 file descriptor leaks, etc. */
358 sim_module_uninstall (sd);
359 return 0;
360 }
361
362 /* handle board-specific memory maps */
363 if (board == NULL)
364 {
365 /* Allocate core managed memory */
366
367 /* start-sanitize-sky */
368 #ifndef TARGET_SKY
369 /* end-sanitize-sky */
370 /* the monitor */
371 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
372 /* For compatibility with the old code - under this (at level one)
373 are the kernel spaces K0 & K1. Both of these map to a single
374 smaller sub region */
375 sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
376 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
377 K1BASE, K0SIZE,
378 MEM_SIZE, /* actual size */
379 K0BASE);
380 /* start-sanitize-sky */
381 #else
382 /* the monitor */
383 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE - K1BASE, MONITOR_SIZE);
384 sim_do_command (sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
385 /* 16M @ 0x0. Aliases at 0x80000000 and 0xA0000000 are handled by
386 address_translation() */
387 sim_do_commandf (sd, "memory size 0x%lx", MEM_SIZE);
388 #endif
389 /* end-sanitize-sky */
390
391 device_init(sd);
392 }
393
394 /* start-sanitize-tx3904 */
395 #if (WITH_HW)
396 if (board != NULL
397 && (strcmp(board, BOARD_JMR3904) == 0 ||
398 strcmp(board, BOARD_JMR3904_PAL) == 0 ||
399 strcmp(board, BOARD_JMR3904_DEBUG) == 0))
400 {
401 /* match VIRTUAL memory layout of JMR-TX3904 board */
402
403 /* --- memory --- */
404
405 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
406 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
407 0x9FC00000,
408 4 * 1024 * 1024, /* 4 MB */
409 0xBFC00000);
410
411 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
412 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
413 0x80000000,
414 4 * 1024 * 1024, /* 4 MB */
415 0xA0000000);
416
417 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
418 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
419 0x88000000,
420 32 * 1024 * 1024, /* 32 MB */
421 0xA8000000);
422
423 /* --- simulated devices --- */
424 sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
425 sim_hw_parse (sd, "/tx3904cpu");
426 sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
427 sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
428 sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
429
430 /* -- device connections --- */
431 sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
432 sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
433 sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
434 sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
435
436 /* add PAL timer & I/O module */
437 if(! strcmp(board, BOARD_JMR3904_PAL))
438 {
439 /* the device */
440 sim_hw_parse (sd, "/pal@0xffff0000");
441 sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
442
443 /* wire up interrupt ports to irc */
444 sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
445 sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
446 sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
447 }
448
449 if(! strcmp(board, BOARD_JMR3904_DEBUG))
450 {
451 /* -- DEBUG: glue interrupt generators --- */
452 sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
453 sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
454 sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
455 sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
456 sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
457 sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
458 sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
459 sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
460 sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
461 sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
462 sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
463 sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
464 sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
465 sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
466 sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
467 sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
468 sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
469 sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
470 sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
471 }
472
473 device_init(sd);
474 }
475 #endif
476 /* end-sanitize-tx3904 */
477
478
479 /* check for/establish the a reference program image */
480 if (sim_analyze_program (sd,
481 (STATE_PROG_ARGV (sd) != NULL
482 ? *STATE_PROG_ARGV (sd)
483 : NULL),
484 abfd) != SIM_RC_OK)
485 {
486 sim_module_uninstall (sd);
487 return 0;
488 }
489
490 /* Configure/verify the target byte order and other runtime
491 configuration options */
492 if (sim_config (sd) != SIM_RC_OK)
493 {
494 sim_module_uninstall (sd);
495 return 0;
496 }
497
498 if (sim_post_argv_init (sd) != SIM_RC_OK)
499 {
500 /* Uninstall the modules to avoid memory leaks,
501 file descriptor leaks, etc. */
502 sim_module_uninstall (sd);
503 return 0;
504 }
505
506 /* verify assumptions the simulator made about the host type system.
507 This macro does not return if there is a problem */
508 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
509 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
510
511 /* This is NASTY, in that we are assuming the size of specific
512 registers: */
513 {
514 int rn;
515 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
516 {
517 if (rn < 32)
518 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
519 else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR)))
520 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
521 else if ((rn >= 33) && (rn <= 37))
522 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
523 else if ((rn == SRIDX)
524 || (rn == FCR0IDX)
525 || (rn == FCR31IDX)
526 || ((rn >= 72) && (rn <= 89)))
527 cpu->register_widths[rn] = 32;
528 else
529 cpu->register_widths[rn] = 0;
530 }
531 /* start-sanitize-r5900 */
532
533 /* set the 5900 "upper" registers to 64 bits */
534 for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
535 cpu->register_widths[rn] = 64;
536 /* end-sanitize-r5900 */
537
538 /* start-sanitize-sky */
539 #ifdef TARGET_SKY
540 /* Now the VU registers */
541 for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) {
542 cpu->register_widths[rn + NUM_R5900_REGS] = 16;
543 cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16;
544 }
545
546 for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) {
547 cpu->register_widths[rn + NUM_R5900_REGS] = 32;
548 cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32;
549 }
550
551 /* Finally the VIF registers */
552 for( rn = 2*NUM_VU_REGS; rn < 2*NUM_VU_REGS + 2*NUM_VIF_REGS; rn++ )
553 cpu->register_widths[rn + NUM_R5900_REGS] = 32;
554
555 cpu->cur_device = 0;
556 #endif
557 /* end-sanitize-sky */
558 }
559
560 #if defined(TRACE)
561 if (STATE & simTRACE)
562 open_trace(sd);
563 #endif /* TRACE */
564
565 /* Write an abort sequence into the TRAP (common) exception vector
566 addresses. This is to catch code executing a TRAP (et.al.)
567 instruction without installing a trap handler. */
568 {
569 unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
570 HALT_INSTRUCTION /* BREAK */ };
571 H2T (halt[0]);
572 H2T (halt[1]);
573 sim_write (sd, 0x80000180, (char *) halt, sizeof (halt));
574 sim_write (sd, 0xBFC00380, (char *) halt, sizeof (halt));
575 }
576
577
578 /* Write the monitor trap address handlers into the monitor (eeprom)
579 address space. This can only be done once the target endianness
580 has been determined. */
581 {
582 unsigned loop;
583 /* Entry into the IDT monitor is via fixed address vectors, and
584 not using machine instructions. To avoid clashing with use of
585 the MIPS TRAP system, we place our own (simulator specific)
586 "undefined" instructions into the relevant vector slots. */
587 for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
588 {
589 address_word vaddr = (MONITOR_BASE + loop);
590 unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
591 H2T (insn);
592 sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
593 }
594 /* The PMON monitor uses the same address space, but rather than
595 branching into it the address of a routine is loaded. We can
596 cheat for the moment, and direct the PMON routine to IDT style
597 instructions within the monitor space. This relies on the IDT
598 monitor not using the locations from 0xBFC00500 onwards as its
599 entry points.*/
600 for (loop = 0; (loop < 24); loop++)
601 {
602 address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
603 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
604 switch (loop)
605 {
606 case 0: /* read */
607 value = 7;
608 break;
609 case 1: /* write */
610 value = 8;
611 break;
612 case 2: /* open */
613 value = 6;
614 break;
615 case 3: /* close */
616 value = 10;
617 break;
618 case 5: /* printf */
619 value = ((0x500 - 16) / 8); /* not an IDT reason code */
620 break;
621 case 8: /* cliexit */
622 value = 17;
623 break;
624 case 11: /* flush_cache */
625 value = 28;
626 break;
627 }
628 /* FIXME - should monitor_base be SIM_ADDR?? */
629 value = ((unsigned int)MONITOR_BASE + (value * 8));
630 H2T (value);
631 sim_write (sd, vaddr, (char *)&value, sizeof (value));
632
633 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
634 vaddr -= 0x300;
635 sim_write (sd, vaddr, (char *)&value, sizeof (value));
636 }
637 }
638
639 return sd;
640 }
641
642 #if defined(TRACE)
643 static void
644 open_trace(sd)
645 SIM_DESC sd;
646 {
647 tracefh = fopen(tracefile,"wb+");
648 if (tracefh == NULL)
649 {
650 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
651 tracefh = stderr;
652 }
653 }
654 #endif /* TRACE */
655
656 void
657 sim_close (sd, quitting)
658 SIM_DESC sd;
659 int quitting;
660 {
661 #ifdef DEBUG
662 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
663 #endif
664
665 /* start-sanitize-sky */
666 #ifdef TARGET_SKY
667 sky_command_options_close (sd);
668 #endif
669 /* end-sanitize-sky */
670
671
672 /* "quitting" is non-zero if we cannot hang on errors */
673
674 /* Ensure that any resources allocated through the callback
675 mechanism are released: */
676 sim_io_shutdown (sd);
677
678 #if defined(TRACE)
679 if (tracefh != NULL && tracefh != stderr)
680 fclose(tracefh);
681 tracefh = NULL;
682 #endif /* TRACE */
683
684 /* FIXME - free SD */
685
686 return;
687 }
688
689
690 int
691 sim_write (sd,addr,buffer,size)
692 SIM_DESC sd;
693 SIM_ADDR addr;
694 unsigned char *buffer;
695 int size;
696 {
697 int index;
698 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
699
700 /* Return the number of bytes written, or zero if error. */
701 #ifdef DEBUG
702 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
703 #endif
704
705 /* We use raw read and write routines, since we do not want to count
706 the GDB memory accesses in our statistics gathering. */
707
708 for (index = 0; index < size; index++)
709 {
710 address_word vaddr = (address_word)addr + index;
711 address_word paddr;
712 int cca;
713 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
714 break;
715 if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
716 break;
717 }
718
719 return(index);
720 }
721
722 int
723 sim_read (sd,addr,buffer,size)
724 SIM_DESC sd;
725 SIM_ADDR addr;
726 unsigned char *buffer;
727 int size;
728 {
729 int index;
730 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
731
732 /* Return the number of bytes read, or zero if error. */
733 #ifdef DEBUG
734 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
735 #endif /* DEBUG */
736
737 for (index = 0; (index < size); index++)
738 {
739 address_word vaddr = (address_word)addr + index;
740 address_word paddr;
741 int cca;
742 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
743 break;
744 if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
745 break;
746 }
747
748 return(index);
749 }
750
751 int
752 sim_store_register (sd,rn,memory,length)
753 SIM_DESC sd;
754 int rn;
755 unsigned char *memory;
756 int length;
757 {
758 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
759 /* NOTE: gdb (the client) stores registers in target byte order
760 while the simulator uses host byte order */
761 #ifdef DEBUG
762 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
763 #endif /* DEBUG */
764
765 /* Unfortunately this suffers from the same problem as the register
766 numbering one. We need to know what the width of each logical
767 register number is for the architecture being simulated. */
768
769 if (cpu->register_widths[rn] == 0)
770 {
771 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
772 return 0;
773 }
774
775 /* start-sanitize-r5900 */
776 if (rn >= 90 && rn < 90 + 32)
777 {
778 GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory);
779 return 8;
780 }
781 switch (rn)
782 {
783 case REGISTER_SA:
784 SA = T2H_8(*(unsigned64*)memory);
785 return 8;
786 case 122: /* FIXME */
787 LO1 = T2H_8(*(unsigned64*)memory);
788 return 8;
789 case 123: /* FIXME */
790 HI1 = T2H_8(*(unsigned64*)memory);
791 return 8;
792 }
793 /* end-sanitize-r5900 */
794
795 /* start-sanitize-sky */
796 #ifdef TARGET_SKY
797 if (rn >= NUM_R5900_REGS)
798 {
799 rn = rn - NUM_R5900_REGS;
800
801 if( rn < NUM_VU_REGS )
802 {
803 if (rn < NUM_VU_INTEGER_REGS)
804 return write_vu_int_reg (&(vu0_device.regs), rn, memory);
805 else if (rn >= FIRST_VEC_REG)
806 {
807 rn -= FIRST_VEC_REG;
808 return write_vu_vec_reg (&(vu0_device.regs), rn>>2, rn&3,
809 memory);
810 }
811 else switch (rn - NUM_VU_INTEGER_REGS)
812 {
813 case 0:
814 return write_vu_special_reg (&vu0_device, VU_REG_CIA,
815 memory);
816 case 1:
817 return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
818 memory);
819 case 2: /* VU0 has no P register */
820 return 4;
821 case 3:
822 return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
823 memory);
824 case 4:
825 return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
826 memory);
827 default:
828 return write_vu_acc_reg (&(vu0_device.regs),
829 rn - (NUM_VU_INTEGER_REGS + 5),
830 memory);
831 }
832 }
833
834 rn = rn - NUM_VU_REGS;
835
836 if (rn < NUM_VU_REGS)
837 {
838 if (rn < NUM_VU_INTEGER_REGS)
839 return write_vu_int_reg (&(vu1_device.regs), rn, memory);
840 else if (rn >= FIRST_VEC_REG)
841 {
842 rn -= FIRST_VEC_REG;
843 return write_vu_vec_reg (&(vu1_device.regs),
844 rn >> 2, rn & 3, memory);
845 }
846 else switch (rn - NUM_VU_INTEGER_REGS)
847 {
848 case 0:
849 return write_vu_special_reg (&vu1_device, VU_REG_CIA,
850 memory);
851 case 1:
852 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MR,
853 memory);
854 case 2:
855 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MP,
856 memory);
857 case 3:
858 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MI,
859 memory);
860 case 4:
861 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MQ,
862 memory);
863 default:
864 return write_vu_acc_reg (&(vu1_device.regs),
865 rn - (NUM_VU_INTEGER_REGS + 5),
866 memory);
867 }
868 }
869
870 rn -= NUM_VU_REGS; /* VIF0 registers are next */
871
872 if (rn < NUM_VIF_REGS)
873 {
874 if (rn < NUM_VIF_REGS-1)
875 return write_pke_reg (&pke0_device, rn, memory);
876 else
877 {
878 sim_io_eprintf( sd, "Can't write vif0_pc (store ignored)\n" );
879 return 0;
880 }
881 }
882
883 rn -= NUM_VIF_REGS; /* VIF1 registers are last */
884
885 if (rn < NUM_VIF_REGS)
886 {
887 if (rn < NUM_VIF_REGS-1)
888 return write_pke_reg (&pke1_device, rn, memory);
889 else
890 {
891 sim_io_eprintf( sd, "Can't write vif1_pc (store ignored)\n" );
892 return 0;
893 }
894 }
895
896 sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
897 return 0;
898 }
899 #endif
900 /* end-sanitize-sky */
901
902 if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
903 {
904 if (cpu->register_widths[rn] == 32)
905 {
906 cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
907 return 4;
908 }
909 else
910 {
911 cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
912 return 8;
913 }
914 }
915
916 if (cpu->register_widths[rn] == 32)
917 {
918 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
919 return 4;
920 }
921 else
922 {
923 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
924 return 8;
925 }
926
927 return 0;
928 }
929
930 int
931 sim_fetch_register (sd,rn,memory,length)
932 SIM_DESC sd;
933 int rn;
934 unsigned char *memory;
935 int length;
936 {
937 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
938 /* NOTE: gdb (the client) stores registers in target byte order
939 while the simulator uses host byte order */
940 #ifdef DEBUG
941 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
942 #endif /* DEBUG */
943
944 if (cpu->register_widths[rn] == 0)
945 {
946 sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
947 return 0;
948 }
949
950 /* start-sanitize-r5900 */
951 if (rn >= 90 && rn < 90 + 32)
952 {
953 *((unsigned64*)memory) = H2T_8 (GPR1[rn - 90]);
954 return 8;
955 }
956 switch (rn)
957 {
958 case REGISTER_SA:
959 *((unsigned64*)memory) = H2T_8(SA);
960 return 8;
961 case 122: /* FIXME */
962 *((unsigned64*)memory) = H2T_8(LO1);
963 return 8;
964 case 123: /* FIXME */
965 *((unsigned64*)memory) = H2T_8(HI1);
966 return 8;
967 }
968 /* end-sanitize-r5900 */
969
970 /* start-sanitize-sky */
971 #ifdef TARGET_SKY
972 if (rn >= NUM_R5900_REGS)
973 {
974 rn = rn - NUM_R5900_REGS;
975
976 if (rn < NUM_VU_REGS)
977 {
978 if (rn < NUM_VU_INTEGER_REGS)
979 return read_vu_int_reg (&(vu0_device.regs), rn, memory);
980 else if (rn >= FIRST_VEC_REG)
981 {
982 rn -= FIRST_VEC_REG;
983 return read_vu_vec_reg (&(vu0_device.regs), rn>>2, rn & 3,
984 memory);
985 }
986 else switch (rn - NUM_VU_INTEGER_REGS)
987 {
988 case 0:
989 return read_vu_special_reg(&vu0_device, VU_REG_CIA, memory);
990 case 1:
991 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
992 memory);
993 case 2: /* VU0 has no P register */
994 *((int *) memory) = 0;
995 return 4;
996 case 3:
997 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
998 memory);
999 case 4:
1000 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
1001 memory);
1002 default:
1003 return read_vu_acc_reg (&(vu0_device.regs),
1004 rn - (NUM_VU_INTEGER_REGS + 5),
1005 memory);
1006 }
1007 }
1008
1009 rn -= NUM_VU_REGS; /* VU1 registers are next */
1010
1011 if (rn < NUM_VU_REGS)
1012 {
1013 if (rn < NUM_VU_INTEGER_REGS)
1014 return read_vu_int_reg (&(vu1_device.regs), rn, memory);
1015 else if (rn >= FIRST_VEC_REG)
1016 {
1017 rn -= FIRST_VEC_REG;
1018 return read_vu_vec_reg (&(vu1_device.regs),
1019 rn >> 2, rn & 3, memory);
1020 }
1021 else switch (rn - NUM_VU_INTEGER_REGS)
1022 {
1023 case 0:
1024 return read_vu_special_reg(&vu1_device, VU_REG_CIA, memory);
1025 case 1:
1026 return read_vu_misc_reg (&(vu1_device.regs),
1027 VU_REG_MR, memory);
1028 case 2:
1029 return read_vu_misc_reg (&(vu1_device.regs),
1030 VU_REG_MP, memory);
1031 case 3:
1032 return read_vu_misc_reg (&(vu1_device.regs),
1033 VU_REG_MI, memory);
1034 case 4:
1035 return read_vu_misc_reg (&(vu1_device.regs),
1036 VU_REG_MQ, memory);
1037 default:
1038 return read_vu_acc_reg (&(vu1_device.regs),
1039 rn - (NUM_VU_INTEGER_REGS + 5),
1040 memory);
1041 }
1042 }
1043
1044 rn -= NUM_VU_REGS; /* VIF0 registers are next */
1045
1046 if (rn < NUM_VIF_REGS)
1047 {
1048 if (rn < NUM_VIF_REGS-2)
1049 return read_pke_reg (&pke0_device, rn, memory);
1050 else if (rn == NUM_VIF_REGS-2)
1051 return read_pke_pc (&pke0_device, memory);
1052 else
1053 return read_pke_pcx (&pke0_device, memory);
1054 }
1055
1056 rn -= NUM_VIF_REGS; /* VIF1 registers are last */
1057
1058 if (rn < NUM_VIF_REGS)
1059 {
1060 if (rn < NUM_VIF_REGS-2)
1061 return read_pke_reg (&pke1_device, rn, memory);
1062 else if (rn == NUM_VIF_REGS-2)
1063 return read_pke_pc (&pke1_device, memory);
1064 else
1065 return read_pke_pcx (&pke1_device, memory);
1066 }
1067
1068 sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
1069 }
1070 #endif
1071 /* end-sanitize-sky */
1072
1073 /* Any floating point register */
1074 if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
1075 {
1076 if (cpu->register_widths[rn] == 32)
1077 {
1078 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
1079 return 4;
1080 }
1081 else
1082 {
1083 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
1084 return 8;
1085 }
1086 }
1087
1088 if (cpu->register_widths[rn] == 32)
1089 {
1090 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
1091 return 4;
1092 }
1093 else
1094 {
1095 *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
1096 return 8;
1097 }
1098
1099 return 0;
1100 }
1101
1102
1103 SIM_RC
1104 sim_create_inferior (sd, abfd, argv,env)
1105 SIM_DESC sd;
1106 struct _bfd *abfd;
1107 char **argv;
1108 char **env;
1109 {
1110
1111 #ifdef DEBUG
1112 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1113 pr_addr(PC));
1114 #endif /* DEBUG */
1115
1116 ColdReset(sd);
1117
1118 if (abfd != NULL)
1119 {
1120 /* override PC value set by ColdReset () */
1121 int cpu_nr;
1122 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1123 {
1124 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1125 CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
1126 }
1127 }
1128
1129 #if 0 /* def DEBUG */
1130 if (argv || env)
1131 {
1132 /* We should really place the argv slot values into the argument
1133 registers, and onto the stack as required. However, this
1134 assumes that we have a stack defined, which is not
1135 necessarily true at the moment. */
1136 char **cptr;
1137 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
1138 for (cptr = argv; (cptr && *cptr); cptr++)
1139 printf("DBG: arg \"%s\"\n",*cptr);
1140 }
1141 #endif /* DEBUG */
1142
1143 return SIM_RC_OK;
1144 }
1145
1146 void
1147 sim_do_command (sd,cmd)
1148 SIM_DESC sd;
1149 char *cmd;
1150 {
1151 if (sim_args_command (sd, cmd) != SIM_RC_OK)
1152 sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
1153 cmd);
1154 }
1155
1156 /*---------------------------------------------------------------------------*/
1157 /*-- Private simulator support interface ------------------------------------*/
1158 /*---------------------------------------------------------------------------*/
1159
1160 /* Read a null terminated string from memory, return in a buffer */
1161 static char *
1162 fetch_str (sd, addr)
1163 SIM_DESC sd;
1164 address_word addr;
1165 {
1166 char *buf;
1167 int nr = 0;
1168 char null;
1169 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
1170 nr++;
1171 buf = NZALLOC (char, nr + 1);
1172 sim_read (sd, addr, buf, nr);
1173 return buf;
1174 }
1175
1176 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1177 static void
1178 sim_monitor (SIM_DESC sd,
1179 sim_cpu *cpu,
1180 address_word cia,
1181 unsigned int reason)
1182 {
1183 #ifdef DEBUG
1184 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
1185 #endif /* DEBUG */
1186
1187 /* The IDT monitor actually allows two instructions per vector
1188 slot. However, the simulator currently causes a trap on each
1189 individual instruction. We cheat, and lose the bottom bit. */
1190 reason >>= 1;
1191
1192 /* The following callback functions are available, however the
1193 monitor we are simulating does not make use of them: get_errno,
1194 isatty, lseek, rename, system, time and unlink */
1195 switch (reason)
1196 {
1197
1198 case 6: /* int open(char *path,int flags) */
1199 {
1200 char *path = fetch_str (sd, A0);
1201 V0 = sim_io_open (sd, path, (int)A1);
1202 zfree (path);
1203 break;
1204 }
1205
1206 case 7: /* int read(int file,char *ptr,int len) */
1207 {
1208 int fd = A0;
1209 int nr = A2;
1210 char *buf = zalloc (nr);
1211 V0 = sim_io_read (sd, fd, buf, nr);
1212 sim_write (sd, A1, buf, nr);
1213 zfree (buf);
1214 }
1215 break;
1216
1217 case 8: /* int write(int file,char *ptr,int len) */
1218 {
1219 int fd = A0;
1220 int nr = A2;
1221 char *buf = zalloc (nr);
1222 sim_read (sd, A1, buf, nr);
1223 V0 = sim_io_write (sd, fd, buf, nr);
1224 zfree (buf);
1225 break;
1226 }
1227
1228 case 10: /* int close(int file) */
1229 {
1230 V0 = sim_io_close (sd, (int)A0);
1231 break;
1232 }
1233
1234 case 2: /* Densan monitor: char inbyte(int waitflag) */
1235 {
1236 if (A0 == 0) /* waitflag == NOWAIT */
1237 V0 = (unsigned_word)-1;
1238 }
1239 /* Drop through to case 11 */
1240
1241 case 11: /* char inbyte(void) */
1242 {
1243 char tmp;
1244 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
1245 {
1246 sim_io_error(sd,"Invalid return from character read");
1247 V0 = (unsigned_word)-1;
1248 }
1249 else
1250 V0 = (unsigned_word)tmp;
1251 break;
1252 }
1253
1254 case 3: /* Densan monitor: void co(char chr) */
1255 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1256 {
1257 char tmp = (char)(A0 & 0xFF);
1258 sim_io_write_stdout (sd, &tmp, sizeof(char));
1259 break;
1260 }
1261
1262 case 17: /* void _exit() */
1263 {
1264 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
1265 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
1266 (unsigned int)(A0 & 0xFFFFFFFF));
1267 break;
1268 }
1269
1270 case 28 : /* PMON flush_cache */
1271 break;
1272
1273 case 55: /* void get_mem_info(unsigned int *ptr) */
1274 /* in: A0 = pointer to three word memory location */
1275 /* out: [A0 + 0] = size */
1276 /* [A0 + 4] = instruction cache size */
1277 /* [A0 + 8] = data cache size */
1278 {
1279 unsigned_4 value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
1280 unsigned_4 zero = 0;
1281 H2T (value);
1282 sim_write (sd, A0 + 0, (char *)&value, 4);
1283 sim_write (sd, A0 + 4, (char *)&zero, 4);
1284 sim_write (sd, A0 + 8, (char *)&zero, 4);
1285 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1286 break;
1287 }
1288
1289 case 158 : /* PMON printf */
1290 /* in: A0 = pointer to format string */
1291 /* A1 = optional argument 1 */
1292 /* A2 = optional argument 2 */
1293 /* A3 = optional argument 3 */
1294 /* out: void */
1295 /* The following is based on the PMON printf source */
1296 {
1297 address_word s = A0;
1298 char c;
1299 signed_word *ap = &A1; /* 1st argument */
1300 /* This isn't the quickest way, since we call the host print
1301 routine for every character almost. But it does avoid
1302 having to allocate and manage a temporary string buffer. */
1303 /* TODO: Include check that we only use three arguments (A1,
1304 A2 and A3) */
1305 while (sim_read (sd, s++, &c, 1) && c != '\0')
1306 {
1307 if (c == '%')
1308 {
1309 char tmp[40];
1310 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
1311 int width = 0, trunc = 0, haddot = 0, longlong = 0;
1312 while (sim_read (sd, s++, &c, 1) && c != '\0')
1313 {
1314 if (strchr ("dobxXulscefg%", c))
1315 break;
1316 else if (c == '-')
1317 fmt = FMT_LJUST;
1318 else if (c == '0')
1319 fmt = FMT_RJUST0;
1320 else if (c == '~')
1321 fmt = FMT_CENTER;
1322 else if (c == '*')
1323 {
1324 if (haddot)
1325 trunc = (int)*ap++;
1326 else
1327 width = (int)*ap++;
1328 }
1329 else if (c >= '1' && c <= '9')
1330 {
1331 address_word t = s;
1332 unsigned int n;
1333 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
1334 tmp[s - t] = c;
1335 tmp[s - t] = '\0';
1336 n = (unsigned int)strtol(tmp,NULL,10);
1337 if (haddot)
1338 trunc = n;
1339 else
1340 width = n;
1341 s--;
1342 }
1343 else if (c == '.')
1344 haddot = 1;
1345 }
1346 switch (c)
1347 {
1348 case '%':
1349 sim_io_printf (sd, "%%");
1350 break;
1351 case 's':
1352 if ((int)*ap != 0)
1353 {
1354 address_word p = *ap++;
1355 char ch;
1356 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
1357 sim_io_printf(sd, "%c", ch);
1358 }
1359 else
1360 sim_io_printf(sd,"(null)");
1361 break;
1362 case 'c':
1363 sim_io_printf (sd, "%c", (int)*ap++);
1364 break;
1365 default:
1366 if (c == 'l')
1367 {
1368 sim_read (sd, s++, &c, 1);
1369 if (c == 'l')
1370 {
1371 longlong = 1;
1372 sim_read (sd, s++, &c, 1);
1373 }
1374 }
1375 if (strchr ("dobxXu", c))
1376 {
1377 word64 lv = (word64) *ap++;
1378 if (c == 'b')
1379 sim_io_printf(sd,"<binary not supported>");
1380 else
1381 {
1382 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
1383 if (longlong)
1384 sim_io_printf(sd, tmp, lv);
1385 else
1386 sim_io_printf(sd, tmp, (int)lv);
1387 }
1388 }
1389 else if (strchr ("eEfgG", c))
1390 {
1391 double dbl = *(double*)(ap++);
1392 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
1393 sim_io_printf (sd, tmp, dbl);
1394 trunc = 0;
1395 }
1396 }
1397 }
1398 else
1399 sim_io_printf(sd, "%c", c);
1400 }
1401 break;
1402 }
1403
1404 default:
1405 sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1406 reason, pr_addr(cia));
1407 break;
1408 }
1409 return;
1410 }
1411
1412 /* Store a word into memory. */
1413
1414 static void
1415 store_word (SIM_DESC sd,
1416 sim_cpu *cpu,
1417 address_word cia,
1418 uword64 vaddr,
1419 signed_word val)
1420 {
1421 address_word paddr;
1422 int uncached;
1423
1424 if ((vaddr & 3) != 0)
1425 SignalExceptionAddressStore ();
1426 else
1427 {
1428 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
1429 isTARGET, isREAL))
1430 {
1431 const uword64 mask = 7;
1432 uword64 memval;
1433 unsigned int byte;
1434
1435 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
1436 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
1437 memval = ((uword64) val) << (8 * byte);
1438 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
1439 isREAL);
1440 }
1441 }
1442 }
1443
1444 /* Load a word from memory. */
1445
1446 static signed_word
1447 load_word (SIM_DESC sd,
1448 sim_cpu *cpu,
1449 address_word cia,
1450 uword64 vaddr)
1451 {
1452 if ((vaddr & 3) != 0)
1453 SignalExceptionAddressLoad ();
1454 else
1455 {
1456 address_word paddr;
1457 int uncached;
1458
1459 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
1460 isTARGET, isREAL))
1461 {
1462 const uword64 mask = 0x7;
1463 const unsigned int reverse = ReverseEndian ? 1 : 0;
1464 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1465 uword64 memval;
1466 unsigned int byte;
1467
1468 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1469 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
1470 isDATA, isREAL);
1471 byte = (vaddr & mask) ^ (bigend << 2);
1472 return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
1473 }
1474 }
1475
1476 return 0;
1477 }
1478
1479 /* Simulate the mips16 entry and exit pseudo-instructions. These
1480 would normally be handled by the reserved instruction exception
1481 code, but for ease of simulation we just handle them directly. */
1482
1483 static void
1484 mips16_entry (SIM_DESC sd,
1485 sim_cpu *cpu,
1486 address_word cia,
1487 unsigned int insn)
1488 {
1489 int aregs, sregs, rreg;
1490
1491 #ifdef DEBUG
1492 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1493 #endif /* DEBUG */
1494
1495 aregs = (insn & 0x700) >> 8;
1496 sregs = (insn & 0x0c0) >> 6;
1497 rreg = (insn & 0x020) >> 5;
1498
1499 /* This should be checked by the caller. */
1500 if (sregs == 3)
1501 abort ();
1502
1503 if (aregs < 5)
1504 {
1505 int i;
1506 signed_word tsp;
1507
1508 /* This is the entry pseudo-instruction. */
1509
1510 for (i = 0; i < aregs; i++)
1511 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1512
1513 tsp = SP;
1514 SP -= 32;
1515
1516 if (rreg)
1517 {
1518 tsp -= 4;
1519 store_word (SD, CPU, cia, (uword64) tsp, RA);
1520 }
1521
1522 for (i = 0; i < sregs; i++)
1523 {
1524 tsp -= 4;
1525 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1526 }
1527 }
1528 else
1529 {
1530 int i;
1531 signed_word tsp;
1532
1533 /* This is the exit pseudo-instruction. */
1534
1535 tsp = SP + 32;
1536
1537 if (rreg)
1538 {
1539 tsp -= 4;
1540 RA = load_word (SD, CPU, cia, (uword64) tsp);
1541 }
1542
1543 for (i = 0; i < sregs; i++)
1544 {
1545 tsp -= 4;
1546 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1547 }
1548
1549 SP += 32;
1550
1551 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1552 {
1553 if (aregs == 5)
1554 {
1555 FGR[0] = WORD64LO (GPR[4]);
1556 FPR_STATE[0] = fmt_uninterpreted;
1557 }
1558 else if (aregs == 6)
1559 {
1560 FGR[0] = WORD64LO (GPR[5]);
1561 FGR[1] = WORD64LO (GPR[4]);
1562 FPR_STATE[0] = fmt_uninterpreted;
1563 FPR_STATE[1] = fmt_uninterpreted;
1564 }
1565 }
1566
1567 PC = RA;
1568 }
1569
1570 }
1571
1572 /*-- trace support ----------------------------------------------------------*/
1573
1574 /* The TRACE support is provided (if required) in the memory accessing
1575 routines. Since we are also providing the architecture specific
1576 features, the architecture simulation code can also deal with
1577 notifying the TRACE world of cache flushes, etc. Similarly we do
1578 not need to provide profiling support in the simulator engine,
1579 since we can sample in the instruction fetch control loop. By
1580 defining the TRACE manifest, we add tracing as a run-time
1581 option. */
1582
1583 #if defined(TRACE)
1584 /* Tracing by default produces "din" format (as required by
1585 dineroIII). Each line of such a trace file *MUST* have a din label
1586 and address field. The rest of the line is ignored, so comments can
1587 be included if desired. The first field is the label which must be
1588 one of the following values:
1589
1590 0 read data
1591 1 write data
1592 2 instruction fetch
1593 3 escape record (treated as unknown access type)
1594 4 escape record (causes cache flush)
1595
1596 The address field is a 32bit (lower-case) hexadecimal address
1597 value. The address should *NOT* be preceded by "0x".
1598
1599 The size of the memory transfer is not important when dealing with
1600 cache lines (as long as no more than a cache line can be
1601 transferred in a single operation :-), however more information
1602 could be given following the dineroIII requirement to allow more
1603 complete memory and cache simulators to provide better
1604 results. i.e. the University of Pisa has a cache simulator that can
1605 also take bus size and speed as (variable) inputs to calculate
1606 complete system performance (a much more useful ability when trying
1607 to construct an end product, rather than a processor). They
1608 currently have an ARM version of their tool called ChARM. */
1609
1610
1611 void
1612 dotrace (SIM_DESC sd,
1613 sim_cpu *cpu,
1614 FILE *tracefh,
1615 int type,
1616 SIM_ADDR address,
1617 int width,
1618 char *comment,...)
1619 {
1620 if (STATE & simTRACE) {
1621 va_list ap;
1622 fprintf(tracefh,"%d %s ; width %d ; ",
1623 type,
1624 pr_addr(address),
1625 width);
1626 va_start(ap,comment);
1627 vfprintf(tracefh,comment,ap);
1628 va_end(ap);
1629 fprintf(tracefh,"\n");
1630 }
1631 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1632 we may be generating 64bit ones, we should put the hi-32bits of the
1633 address into the comment field. */
1634
1635 /* TODO: Provide a buffer for the trace lines. We can then avoid
1636 performing writes until the buffer is filled, or the file is
1637 being closed. */
1638
1639 /* NOTE: We could consider adding a comment field to the "din" file
1640 produced using type 3 markers (unknown access). This would then
1641 allow information about the program that the "din" is for, and
1642 the MIPs world that was being simulated, to be placed into the
1643 trace file. */
1644
1645 return;
1646 }
1647 #endif /* TRACE */
1648
1649 /*---------------------------------------------------------------------------*/
1650 /*-- simulator engine -------------------------------------------------------*/
1651 /*---------------------------------------------------------------------------*/
1652
1653 static void
1654 ColdReset (SIM_DESC sd)
1655 {
1656 int cpu_nr;
1657 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1658 {
1659 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1660 /* RESET: Fixed PC address: */
1661 PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
1662 /* The reset vector address is in the unmapped, uncached memory space. */
1663
1664 SR &= ~(status_SR | status_TS | status_RP);
1665 SR |= (status_ERL | status_BEV);
1666
1667 /* Cheat and allow access to the complete register set immediately */
1668 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1669 && WITH_TARGET_WORD_BITSIZE == 64)
1670 SR |= status_FR; /* 64bit registers */
1671
1672 /* Ensure that any instructions with pending register updates are
1673 cleared: */
1674 PENDING_INVALIDATE();
1675
1676 /* Initialise the FPU registers to the unknown state */
1677 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1678 {
1679 int rn;
1680 for (rn = 0; (rn < 32); rn++)
1681 FPR_STATE[rn] = fmt_uninterpreted;
1682 }
1683
1684 }
1685 }
1686
1687 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1688 /* Signal an exception condition. This will result in an exception
1689 that aborts the instruction. The instruction operation pseudocode
1690 will never see a return from this function call. */
1691
1692 void
1693 signal_exception (SIM_DESC sd,
1694 sim_cpu *cpu,
1695 address_word cia,
1696 int exception,...)
1697 {
1698 /* int vector; */
1699
1700 #ifdef DEBUG
1701 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1702 #endif /* DEBUG */
1703
1704 /* Ensure that any active atomic read/modify/write operation will fail: */
1705 LLBIT = 0;
1706
1707 switch (exception) {
1708
1709 case DebugBreakPoint :
1710 if (! (Debug & Debug_DM))
1711 {
1712 if (INDELAYSLOT())
1713 {
1714 CANCELDELAYSLOT();
1715
1716 Debug |= Debug_DBD; /* signaled from within in delay slot */
1717 DEPC = cia - 4; /* reference the branch instruction */
1718 }
1719 else
1720 {
1721 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1722 DEPC = cia;
1723 }
1724
1725 Debug |= Debug_DM; /* in debugging mode */
1726 Debug |= Debug_DBp; /* raising a DBp exception */
1727 PC = 0xBFC00200;
1728 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1729 }
1730 break;
1731
1732 case ReservedInstruction :
1733 {
1734 va_list ap;
1735 unsigned int instruction;
1736 va_start(ap,exception);
1737 instruction = va_arg(ap,unsigned int);
1738 va_end(ap);
1739 /* Provide simple monitor support using ReservedInstruction
1740 exceptions. The following code simulates the fixed vector
1741 entry points into the IDT monitor by causing a simulator
1742 trap, performing the monitor operation, and returning to
1743 the address held in the $ra register (standard PCS return
1744 address). This means we only need to pre-load the vector
1745 space with suitable instruction values. For systems were
1746 actual trap instructions are used, we would not need to
1747 perform this magic. */
1748 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1749 {
1750 sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
1751 /* NOTE: This assumes that a branch-and-link style
1752 instruction was used to enter the vector (which is the
1753 case with the current IDT monitor). */
1754 sim_engine_restart (SD, CPU, NULL, RA);
1755 }
1756 /* Look for the mips16 entry and exit instructions, and
1757 simulate a handler for them. */
1758 else if ((cia & 1) != 0
1759 && (instruction & 0xf81f) == 0xe809
1760 && (instruction & 0x0c0) != 0x0c0)
1761 {
1762 mips16_entry (SD, CPU, cia, instruction);
1763 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1764 }
1765 /* else fall through to normal exception processing */
1766 sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
1767 }
1768
1769 default:
1770 /* Store exception code into current exception id variable (used
1771 by exit code): */
1772
1773 /* TODO: If not simulating exceptions then stop the simulator
1774 execution. At the moment we always stop the simulation. */
1775
1776 #ifdef SUBTARGET_R3900
1777 /* update interrupt-related registers */
1778
1779 /* insert exception code in bits 6:2 */
1780 CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
1781 /* shift IE/KU history bits left */
1782 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
1783
1784 if (STATE & simDELAYSLOT)
1785 {
1786 STATE &= ~simDELAYSLOT;
1787 CAUSE |= cause_BD;
1788 EPC = (cia - 4); /* reference the branch instruction */
1789 }
1790 else
1791 EPC = cia;
1792
1793 if (SR & status_BEV)
1794 PC = (signed)0xBFC00000 + 0x180;
1795 else
1796 PC = (signed)0x80000000 + 0x080;
1797 #else
1798 /* See figure 5-17 for an outline of the code below */
1799 if (! (SR & status_EXL))
1800 {
1801 CAUSE = (exception << 2);
1802 if (STATE & simDELAYSLOT)
1803 {
1804 STATE &= ~simDELAYSLOT;
1805 CAUSE |= cause_BD;
1806 EPC = (cia - 4); /* reference the branch instruction */
1807 }
1808 else
1809 EPC = cia;
1810 /* FIXME: TLB et.al. */
1811 /* vector = 0x180; */
1812 }
1813 else
1814 {
1815 CAUSE = (exception << 2);
1816 /* vector = 0x180; */
1817 }
1818 SR |= status_EXL;
1819 /* Store exception code into current exception id variable (used
1820 by exit code): */
1821
1822 if (SR & status_BEV)
1823 PC = (signed)0xBFC00200 + 0x180;
1824 else
1825 PC = (signed)0x80000000 + 0x180;
1826 #endif
1827
1828 switch ((CAUSE >> 2) & 0x1F)
1829 {
1830 case Interrupt:
1831 /* Interrupts arrive during event processing, no need to
1832 restart */
1833 return;
1834
1835 case NMIReset:
1836 /* Ditto */
1837 #ifdef SUBTARGET_3900
1838 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1839 PC = (signed)0xBFC00000;
1840 #endif SUBTARGET_3900
1841 return;
1842
1843 case TLBModification:
1844 case TLBLoad:
1845 case TLBStore:
1846 case AddressLoad:
1847 case AddressStore:
1848 case InstructionFetch:
1849 case DataReference:
1850 /* The following is so that the simulator will continue from the
1851 exception address on breakpoint operations. */
1852 PC = EPC;
1853 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1854 sim_stopped, SIM_SIGBUS);
1855
1856 case ReservedInstruction:
1857 case CoProcessorUnusable:
1858 PC = EPC;
1859 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1860 sim_stopped, SIM_SIGILL);
1861
1862 case IntegerOverflow:
1863 case FPE:
1864 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1865 sim_stopped, SIM_SIGFPE);
1866
1867 case BreakPoint:
1868 case SystemCall:
1869 case Trap:
1870 sim_engine_restart (SD, CPU, NULL, PC);
1871 break;
1872
1873 case Watch:
1874 PC = EPC;
1875 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1876 sim_stopped, SIM_SIGTRAP);
1877
1878 default : /* Unknown internal exception */
1879 PC = EPC;
1880 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1881 sim_stopped, SIM_SIGABRT);
1882
1883 }
1884
1885 case SimulatorFault:
1886 {
1887 va_list ap;
1888 char *msg;
1889 va_start(ap,exception);
1890 msg = va_arg(ap,char *);
1891 va_end(ap);
1892 sim_engine_abort (SD, CPU, NULL_CIA,
1893 "FATAL: Simulator error \"%s\"\n",msg);
1894 }
1895 }
1896
1897 return;
1898 }
1899
1900 #if defined(WARN_RESULT)
1901 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1902 /* This function indicates that the result of the operation is
1903 undefined. However, this should not affect the instruction
1904 stream. All that is meant to happen is that the destination
1905 register is set to an undefined result. To keep the simulator
1906 simple, we just don't bother updating the destination register, so
1907 the overall result will be undefined. If desired we can stop the
1908 simulator by raising a pseudo-exception. */
1909 #define UndefinedResult() undefined_result (sd,cia)
1910 static void
1911 undefined_result(sd,cia)
1912 SIM_DESC sd;
1913 address_word cia;
1914 {
1915 sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
1916 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1917 state |= simSTOP;
1918 #endif
1919 return;
1920 }
1921 #endif /* WARN_RESULT */
1922
1923 /*-- FPU support routines ---------------------------------------------------*/
1924
1925 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1926 formats conform to ANSI/IEEE Std 754-1985. */
1927 /* SINGLE precision floating:
1928 * seeeeeeeefffffffffffffffffffffff
1929 * s = 1bit = sign
1930 * e = 8bits = exponent
1931 * f = 23bits = fraction
1932 */
1933 /* SINGLE precision fixed:
1934 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1935 * s = 1bit = sign
1936 * i = 31bits = integer
1937 */
1938 /* DOUBLE precision floating:
1939 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1940 * s = 1bit = sign
1941 * e = 11bits = exponent
1942 * f = 52bits = fraction
1943 */
1944 /* DOUBLE precision fixed:
1945 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1946 * s = 1bit = sign
1947 * i = 63bits = integer
1948 */
1949
1950 /* Extract sign-bit: */
1951 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
1952 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
1953 /* Extract biased exponent: */
1954 #define FP_S_be(v) (((v) >> 23) & 0xFF)
1955 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
1956 /* Extract unbiased Exponent: */
1957 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
1958 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1959 /* Extract complete fraction field: */
1960 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
1961 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
1962 /* Extract numbered fraction bit: */
1963 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1964 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1965
1966 /* Explicit QNaN values used when value required: */
1967 #define FPQNaN_SINGLE (0x7FBFFFFF)
1968 #define FPQNaN_WORD (0x7FFFFFFF)
1969 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1970 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
1971
1972 /* Explicit Infinity values used when required: */
1973 #define FPINF_SINGLE (0x7F800000)
1974 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
1975
1976 #if 1 /* def DEBUG */
1977 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1978 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
1979 #endif /* DEBUG */
1980
1981 uword64
1982 value_fpr (SIM_DESC sd,
1983 sim_cpu *cpu,
1984 address_word cia,
1985 int fpr,
1986 FP_formats fmt)
1987 {
1988 uword64 value = 0;
1989 int err = 0;
1990
1991 /* Treat unused register values, as fixed-point 64bit values: */
1992 if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
1993 #if 1
1994 /* If request to read data as "uninterpreted", then use the current
1995 encoding: */
1996 fmt = FPR_STATE[fpr];
1997 #else
1998 fmt = fmt_long;
1999 #endif
2000
2001 /* For values not yet accessed, set to the desired format: */
2002 if (FPR_STATE[fpr] == fmt_uninterpreted) {
2003 FPR_STATE[fpr] = fmt;
2004 #ifdef DEBUG
2005 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
2006 #endif /* DEBUG */
2007 }
2008 if (fmt != FPR_STATE[fpr]) {
2009 sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia));
2010 FPR_STATE[fpr] = fmt_unknown;
2011 }
2012
2013 if (FPR_STATE[fpr] == fmt_unknown) {
2014 /* Set QNaN value: */
2015 switch (fmt) {
2016 case fmt_single:
2017 value = FPQNaN_SINGLE;
2018 break;
2019
2020 case fmt_double:
2021 value = FPQNaN_DOUBLE;
2022 break;
2023
2024 case fmt_word:
2025 value = FPQNaN_WORD;
2026 break;
2027
2028 case fmt_long:
2029 value = FPQNaN_LONG;
2030 break;
2031
2032 default:
2033 err = -1;
2034 break;
2035 }
2036 } else if (SizeFGR() == 64) {
2037 switch (fmt) {
2038 case fmt_single:
2039 case fmt_word:
2040 value = (FGR[fpr] & 0xFFFFFFFF);
2041 break;
2042
2043 case fmt_uninterpreted:
2044 case fmt_double:
2045 case fmt_long:
2046 value = FGR[fpr];
2047 break;
2048
2049 default :
2050 err = -1;
2051 break;
2052 }
2053 } else {
2054 switch (fmt) {
2055 case fmt_single:
2056 case fmt_word:
2057 value = (FGR[fpr] & 0xFFFFFFFF);
2058 break;
2059
2060 case fmt_uninterpreted:
2061 case fmt_double:
2062 case fmt_long:
2063 if ((fpr & 1) == 0) { /* even registers only */
2064 value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
2065 } else {
2066 SignalException(ReservedInstruction,0);
2067 }
2068 break;
2069
2070 default :
2071 err = -1;
2072 break;
2073 }
2074 }
2075
2076 if (err)
2077 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2078
2079 #ifdef DEBUG
2080 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2081 #endif /* DEBUG */
2082
2083 return(value);
2084 }
2085
2086 void
2087 store_fpr (SIM_DESC sd,
2088 sim_cpu *cpu,
2089 address_word cia,
2090 int fpr,
2091 FP_formats fmt,
2092 uword64 value)
2093 {
2094 int err = 0;
2095
2096 #ifdef DEBUG
2097 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2098 #endif /* DEBUG */
2099
2100 if (SizeFGR() == 64) {
2101 switch (fmt) {
2102 case fmt_uninterpreted_32:
2103 fmt = fmt_uninterpreted;
2104 case fmt_single :
2105 case fmt_word :
2106 FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
2107 FPR_STATE[fpr] = fmt;
2108 break;
2109
2110 case fmt_uninterpreted_64:
2111 fmt = fmt_uninterpreted;
2112 case fmt_uninterpreted:
2113 case fmt_double :
2114 case fmt_long :
2115 FGR[fpr] = value;
2116 FPR_STATE[fpr] = fmt;
2117 break;
2118
2119 default :
2120 FPR_STATE[fpr] = fmt_unknown;
2121 err = -1;
2122 break;
2123 }
2124 } else {
2125 switch (fmt) {
2126 case fmt_uninterpreted_32:
2127 fmt = fmt_uninterpreted;
2128 case fmt_single :
2129 case fmt_word :
2130 FGR[fpr] = (value & 0xFFFFFFFF);
2131 FPR_STATE[fpr] = fmt;
2132 break;
2133
2134 case fmt_uninterpreted_64:
2135 fmt = fmt_uninterpreted;
2136 case fmt_uninterpreted:
2137 case fmt_double :
2138 case fmt_long :
2139 if ((fpr & 1) == 0) { /* even register number only */
2140 FGR[fpr+1] = (value >> 32);
2141 FGR[fpr] = (value & 0xFFFFFFFF);
2142 FPR_STATE[fpr + 1] = fmt;
2143 FPR_STATE[fpr] = fmt;
2144 } else {
2145 FPR_STATE[fpr] = fmt_unknown;
2146 FPR_STATE[fpr + 1] = fmt_unknown;
2147 SignalException(ReservedInstruction,0);
2148 }
2149 break;
2150
2151 default :
2152 FPR_STATE[fpr] = fmt_unknown;
2153 err = -1;
2154 break;
2155 }
2156 }
2157 #if defined(WARN_RESULT)
2158 else
2159 UndefinedResult();
2160 #endif /* WARN_RESULT */
2161
2162 if (err)
2163 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2164
2165 #ifdef DEBUG
2166 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
2167 #endif /* DEBUG */
2168
2169 return;
2170 }
2171
2172 int
2173 NaN(op,fmt)
2174 uword64 op;
2175 FP_formats fmt;
2176 {
2177 int boolean = 0;
2178 switch (fmt) {
2179 case fmt_single:
2180 case fmt_word:
2181 {
2182 sim_fpu wop;
2183 sim_fpu_32to (&wop, op);
2184 boolean = sim_fpu_is_nan (&wop);
2185 break;
2186 }
2187 case fmt_double:
2188 case fmt_long:
2189 {
2190 sim_fpu wop;
2191 sim_fpu_64to (&wop, op);
2192 boolean = sim_fpu_is_nan (&wop);
2193 break;
2194 }
2195 default:
2196 fprintf (stderr, "Bad switch\n");
2197 abort ();
2198 }
2199
2200 #ifdef DEBUG
2201 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2202 #endif /* DEBUG */
2203
2204 return(boolean);
2205 }
2206
2207 int
2208 Infinity(op,fmt)
2209 uword64 op;
2210 FP_formats fmt;
2211 {
2212 int boolean = 0;
2213
2214 #ifdef DEBUG
2215 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
2216 #endif /* DEBUG */
2217
2218 switch (fmt) {
2219 case fmt_single:
2220 {
2221 sim_fpu wop;
2222 sim_fpu_32to (&wop, op);
2223 boolean = sim_fpu_is_infinity (&wop);
2224 break;
2225 }
2226 case fmt_double:
2227 {
2228 sim_fpu wop;
2229 sim_fpu_64to (&wop, op);
2230 boolean = sim_fpu_is_infinity (&wop);
2231 break;
2232 }
2233 default:
2234 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
2235 break;
2236 }
2237
2238 #ifdef DEBUG
2239 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2240 #endif /* DEBUG */
2241
2242 return(boolean);
2243 }
2244
2245 int
2246 Less(op1,op2,fmt)
2247 uword64 op1;
2248 uword64 op2;
2249 FP_formats fmt;
2250 {
2251 int boolean = 0;
2252
2253 /* Argument checking already performed by the FPCOMPARE code */
2254
2255 #ifdef DEBUG
2256 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2257 #endif /* DEBUG */
2258
2259 /* The format type should already have been checked: */
2260 switch (fmt) {
2261 case fmt_single:
2262 {
2263 sim_fpu wop1;
2264 sim_fpu wop2;
2265 sim_fpu_32to (&wop1, op1);
2266 sim_fpu_32to (&wop2, op2);
2267 boolean = sim_fpu_is_lt (&wop1, &wop2);
2268 break;
2269 }
2270 case fmt_double:
2271 {
2272 sim_fpu wop1;
2273 sim_fpu wop2;
2274 sim_fpu_64to (&wop1, op1);
2275 sim_fpu_64to (&wop2, op2);
2276 boolean = sim_fpu_is_lt (&wop1, &wop2);
2277 break;
2278 }
2279 default:
2280 fprintf (stderr, "Bad switch\n");
2281 abort ();
2282 }
2283
2284 #ifdef DEBUG
2285 printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2286 #endif /* DEBUG */
2287
2288 return(boolean);
2289 }
2290
2291 int
2292 Equal(op1,op2,fmt)
2293 uword64 op1;
2294 uword64 op2;
2295 FP_formats fmt;
2296 {
2297 int boolean = 0;
2298
2299 /* Argument checking already performed by the FPCOMPARE code */
2300
2301 #ifdef DEBUG
2302 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2303 #endif /* DEBUG */
2304
2305 /* The format type should already have been checked: */
2306 switch (fmt) {
2307 case fmt_single:
2308 {
2309 sim_fpu wop1;
2310 sim_fpu wop2;
2311 sim_fpu_32to (&wop1, op1);
2312 sim_fpu_32to (&wop2, op2);
2313 boolean = sim_fpu_is_eq (&wop1, &wop2);
2314 break;
2315 }
2316 case fmt_double:
2317 {
2318 sim_fpu wop1;
2319 sim_fpu wop2;
2320 sim_fpu_64to (&wop1, op1);
2321 sim_fpu_64to (&wop2, op2);
2322 boolean = sim_fpu_is_eq (&wop1, &wop2);
2323 break;
2324 }
2325 default:
2326 fprintf (stderr, "Bad switch\n");
2327 abort ();
2328 }
2329
2330 #ifdef DEBUG
2331 printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2332 #endif /* DEBUG */
2333
2334 return(boolean);
2335 }
2336
2337 uword64
2338 AbsoluteValue(op,fmt)
2339 uword64 op;
2340 FP_formats fmt;
2341 {
2342 uword64 result = 0;
2343
2344 #ifdef DEBUG
2345 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2346 #endif /* DEBUG */
2347
2348 /* The format type should already have been checked: */
2349 switch (fmt) {
2350 case fmt_single:
2351 {
2352 sim_fpu wop;
2353 unsigned32 ans;
2354 sim_fpu_32to (&wop, op);
2355 sim_fpu_abs (&wop, &wop);
2356 sim_fpu_to32 (&ans, &wop);
2357 result = ans;
2358 break;
2359 }
2360 case fmt_double:
2361 {
2362 sim_fpu wop;
2363 unsigned64 ans;
2364 sim_fpu_64to (&wop, op);
2365 sim_fpu_abs (&wop, &wop);
2366 sim_fpu_to64 (&ans, &wop);
2367 result = ans;
2368 break;
2369 }
2370 default:
2371 fprintf (stderr, "Bad switch\n");
2372 abort ();
2373 }
2374
2375 return(result);
2376 }
2377
2378 uword64
2379 Negate(op,fmt)
2380 uword64 op;
2381 FP_formats fmt;
2382 {
2383 uword64 result = 0;
2384
2385 #ifdef DEBUG
2386 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2387 #endif /* DEBUG */
2388
2389 /* The format type should already have been checked: */
2390 switch (fmt) {
2391 case fmt_single:
2392 {
2393 sim_fpu wop;
2394 unsigned32 ans;
2395 sim_fpu_32to (&wop, op);
2396 sim_fpu_neg (&wop, &wop);
2397 sim_fpu_to32 (&ans, &wop);
2398 result = ans;
2399 break;
2400 }
2401 case fmt_double:
2402 {
2403 sim_fpu wop;
2404 unsigned64 ans;
2405 sim_fpu_64to (&wop, op);
2406 sim_fpu_neg (&wop, &wop);
2407 sim_fpu_to64 (&ans, &wop);
2408 result = ans;
2409 break;
2410 }
2411 default:
2412 fprintf (stderr, "Bad switch\n");
2413 abort ();
2414 }
2415
2416 return(result);
2417 }
2418
2419 uword64
2420 Add(op1,op2,fmt)
2421 uword64 op1;
2422 uword64 op2;
2423 FP_formats fmt;
2424 {
2425 uword64 result = 0;
2426
2427 #ifdef DEBUG
2428 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2429 #endif /* DEBUG */
2430
2431 /* The registers must specify FPRs valid for operands of type
2432 "fmt". If they are not valid, the result is undefined. */
2433
2434 /* The format type should already have been checked: */
2435 switch (fmt) {
2436 case fmt_single:
2437 {
2438 sim_fpu wop1;
2439 sim_fpu wop2;
2440 sim_fpu ans;
2441 unsigned32 res;
2442 sim_fpu_32to (&wop1, op1);
2443 sim_fpu_32to (&wop2, op2);
2444 sim_fpu_add (&ans, &wop1, &wop2);
2445 sim_fpu_to32 (&res, &ans);
2446 result = res;
2447 break;
2448 }
2449 case fmt_double:
2450 {
2451 sim_fpu wop1;
2452 sim_fpu wop2;
2453 sim_fpu ans;
2454 unsigned64 res;
2455 sim_fpu_64to (&wop1, op1);
2456 sim_fpu_64to (&wop2, op2);
2457 sim_fpu_add (&ans, &wop1, &wop2);
2458 sim_fpu_to64 (&res, &ans);
2459 result = res;
2460 break;
2461 }
2462 default:
2463 fprintf (stderr, "Bad switch\n");
2464 abort ();
2465 }
2466
2467 #ifdef DEBUG
2468 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2469 #endif /* DEBUG */
2470
2471 return(result);
2472 }
2473
2474 uword64
2475 Sub(op1,op2,fmt)
2476 uword64 op1;
2477 uword64 op2;
2478 FP_formats fmt;
2479 {
2480 uword64 result = 0;
2481
2482 #ifdef DEBUG
2483 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2484 #endif /* DEBUG */
2485
2486 /* The registers must specify FPRs valid for operands of type
2487 "fmt". If they are not valid, the result is undefined. */
2488
2489 /* The format type should already have been checked: */
2490 switch (fmt) {
2491 case fmt_single:
2492 {
2493 sim_fpu wop1;
2494 sim_fpu wop2;
2495 sim_fpu ans;
2496 unsigned32 res;
2497 sim_fpu_32to (&wop1, op1);
2498 sim_fpu_32to (&wop2, op2);
2499 sim_fpu_sub (&ans, &wop1, &wop2);
2500 sim_fpu_to32 (&res, &ans);
2501 result = res;
2502 }
2503 break;
2504 case fmt_double:
2505 {
2506 sim_fpu wop1;
2507 sim_fpu wop2;
2508 sim_fpu ans;
2509 unsigned64 res;
2510 sim_fpu_64to (&wop1, op1);
2511 sim_fpu_64to (&wop2, op2);
2512 sim_fpu_sub (&ans, &wop1, &wop2);
2513 sim_fpu_to64 (&res, &ans);
2514 result = res;
2515 }
2516 break;
2517 default:
2518 fprintf (stderr, "Bad switch\n");
2519 abort ();
2520 }
2521
2522 #ifdef DEBUG
2523 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2524 #endif /* DEBUG */
2525
2526 return(result);
2527 }
2528
2529 uword64
2530 Multiply(op1,op2,fmt)
2531 uword64 op1;
2532 uword64 op2;
2533 FP_formats fmt;
2534 {
2535 uword64 result = 0;
2536
2537 #ifdef DEBUG
2538 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2539 #endif /* DEBUG */
2540
2541 /* The registers must specify FPRs valid for operands of type
2542 "fmt". If they are not valid, the result is undefined. */
2543
2544 /* The format type should already have been checked: */
2545 switch (fmt) {
2546 case fmt_single:
2547 {
2548 sim_fpu wop1;
2549 sim_fpu wop2;
2550 sim_fpu ans;
2551 unsigned32 res;
2552 sim_fpu_32to (&wop1, op1);
2553 sim_fpu_32to (&wop2, op2);
2554 sim_fpu_mul (&ans, &wop1, &wop2);
2555 sim_fpu_to32 (&res, &ans);
2556 result = res;
2557 break;
2558 }
2559 case fmt_double:
2560 {
2561 sim_fpu wop1;
2562 sim_fpu wop2;
2563 sim_fpu ans;
2564 unsigned64 res;
2565 sim_fpu_64to (&wop1, op1);
2566 sim_fpu_64to (&wop2, op2);
2567 sim_fpu_mul (&ans, &wop1, &wop2);
2568 sim_fpu_to64 (&res, &ans);
2569 result = res;
2570 break;
2571 }
2572 default:
2573 fprintf (stderr, "Bad switch\n");
2574 abort ();
2575 }
2576
2577 #ifdef DEBUG
2578 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2579 #endif /* DEBUG */
2580
2581 return(result);
2582 }
2583
2584 uword64
2585 Divide(op1,op2,fmt)
2586 uword64 op1;
2587 uword64 op2;
2588 FP_formats fmt;
2589 {
2590 uword64 result = 0;
2591
2592 #ifdef DEBUG
2593 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2594 #endif /* DEBUG */
2595
2596 /* The registers must specify FPRs valid for operands of type
2597 "fmt". If they are not valid, the result is undefined. */
2598
2599 /* The format type should already have been checked: */
2600 switch (fmt) {
2601 case fmt_single:
2602 {
2603 sim_fpu wop1;
2604 sim_fpu wop2;
2605 sim_fpu ans;
2606 unsigned32 res;
2607 sim_fpu_32to (&wop1, op1);
2608 sim_fpu_32to (&wop2, op2);
2609 sim_fpu_div (&ans, &wop1, &wop2);
2610 sim_fpu_to32 (&res, &ans);
2611 result = res;
2612 break;
2613 }
2614 case fmt_double:
2615 {
2616 sim_fpu wop1;
2617 sim_fpu wop2;
2618 sim_fpu ans;
2619 unsigned64 res;
2620 sim_fpu_64to (&wop1, op1);
2621 sim_fpu_64to (&wop2, op2);
2622 sim_fpu_div (&ans, &wop1, &wop2);
2623 sim_fpu_to64 (&res, &ans);
2624 result = res;
2625 break;
2626 }
2627 default:
2628 fprintf (stderr, "Bad switch\n");
2629 abort ();
2630 }
2631
2632 #ifdef DEBUG
2633 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2634 #endif /* DEBUG */
2635
2636 return(result);
2637 }
2638
2639 uword64 UNUSED
2640 Recip(op,fmt)
2641 uword64 op;
2642 FP_formats fmt;
2643 {
2644 uword64 result = 0;
2645
2646 #ifdef DEBUG
2647 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2648 #endif /* DEBUG */
2649
2650 /* The registers must specify FPRs valid for operands of type
2651 "fmt". If they are not valid, the result is undefined. */
2652
2653 /* The format type should already have been checked: */
2654 switch (fmt) {
2655 case fmt_single:
2656 {
2657 sim_fpu wop;
2658 sim_fpu ans;
2659 unsigned32 res;
2660 sim_fpu_32to (&wop, op);
2661 sim_fpu_inv (&ans, &wop);
2662 sim_fpu_to32 (&res, &ans);
2663 result = res;
2664 break;
2665 }
2666 case fmt_double:
2667 {
2668 sim_fpu wop;
2669 sim_fpu ans;
2670 unsigned64 res;
2671 sim_fpu_64to (&wop, op);
2672 sim_fpu_inv (&ans, &wop);
2673 sim_fpu_to64 (&res, &ans);
2674 result = res;
2675 break;
2676 }
2677 default:
2678 fprintf (stderr, "Bad switch\n");
2679 abort ();
2680 }
2681
2682 #ifdef DEBUG
2683 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2684 #endif /* DEBUG */
2685
2686 return(result);
2687 }
2688
2689 uword64
2690 SquareRoot(op,fmt)
2691 uword64 op;
2692 FP_formats fmt;
2693 {
2694 uword64 result = 0;
2695
2696 #ifdef DEBUG
2697 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2698 #endif /* DEBUG */
2699
2700 /* The registers must specify FPRs valid for operands of type
2701 "fmt". If they are not valid, the result is undefined. */
2702
2703 /* The format type should already have been checked: */
2704 switch (fmt) {
2705 case fmt_single:
2706 {
2707 sim_fpu wop;
2708 sim_fpu ans;
2709 unsigned32 res;
2710 sim_fpu_32to (&wop, op);
2711 sim_fpu_sqrt (&ans, &wop);
2712 sim_fpu_to32 (&res, &ans);
2713 result = res;
2714 break;
2715 }
2716 case fmt_double:
2717 {
2718 sim_fpu wop;
2719 sim_fpu ans;
2720 unsigned64 res;
2721 sim_fpu_64to (&wop, op);
2722 sim_fpu_sqrt (&ans, &wop);
2723 sim_fpu_to64 (&res, &ans);
2724 result = res;
2725 break;
2726 }
2727 default:
2728 fprintf (stderr, "Bad switch\n");
2729 abort ();
2730 }
2731
2732 #ifdef DEBUG
2733 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2734 #endif /* DEBUG */
2735
2736 return(result);
2737 }
2738
2739 #if 0
2740 uword64
2741 Max (uword64 op1,
2742 uword64 op2,
2743 FP_formats fmt)
2744 {
2745 int cmp;
2746 unsigned64 result;
2747
2748 #ifdef DEBUG
2749 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2750 #endif /* DEBUG */
2751
2752 /* The registers must specify FPRs valid for operands of type
2753 "fmt". If they are not valid, the result is undefined. */
2754
2755 /* The format type should already have been checked: */
2756 switch (fmt)
2757 {
2758 case fmt_single:
2759 {
2760 sim_fpu wop1;
2761 sim_fpu wop2;
2762 sim_fpu_32to (&wop1, op1);
2763 sim_fpu_32to (&wop2, op2);
2764 cmp = sim_fpu_cmp (&wop1, &wop2);
2765 break;
2766 }
2767 case fmt_double:
2768 {
2769 sim_fpu wop1;
2770 sim_fpu wop2;
2771 sim_fpu_64to (&wop1, op1);
2772 sim_fpu_64to (&wop2, op2);
2773 cmp = sim_fpu_cmp (&wop1, &wop2);
2774 break;
2775 }
2776 default:
2777 fprintf (stderr, "Bad switch\n");
2778 abort ();
2779 }
2780
2781 switch (cmp)
2782 {
2783 case SIM_FPU_IS_SNAN:
2784 case SIM_FPU_IS_QNAN:
2785 result = op1;
2786 case SIM_FPU_IS_NINF:
2787 case SIM_FPU_IS_NNUMBER:
2788 case SIM_FPU_IS_NDENORM:
2789 case SIM_FPU_IS_NZERO:
2790 result = op2; /* op1 - op2 < 0 */
2791 case SIM_FPU_IS_PINF:
2792 case SIM_FPU_IS_PNUMBER:
2793 case SIM_FPU_IS_PDENORM:
2794 case SIM_FPU_IS_PZERO:
2795 result = op1; /* op1 - op2 > 0 */
2796 default:
2797 fprintf (stderr, "Bad switch\n");
2798 abort ();
2799 }
2800
2801 #ifdef DEBUG
2802 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2803 #endif /* DEBUG */
2804
2805 return(result);
2806 }
2807 #endif
2808
2809 #if 0
2810 uword64
2811 Min (uword64 op1,
2812 uword64 op2,
2813 FP_formats fmt)
2814 {
2815 int cmp;
2816 unsigned64 result;
2817
2818 #ifdef DEBUG
2819 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2820 #endif /* DEBUG */
2821
2822 /* The registers must specify FPRs valid for operands of type
2823 "fmt". If they are not valid, the result is undefined. */
2824
2825 /* The format type should already have been checked: */
2826 switch (fmt)
2827 {
2828 case fmt_single:
2829 {
2830 sim_fpu wop1;
2831 sim_fpu wop2;
2832 sim_fpu_32to (&wop1, op1);
2833 sim_fpu_32to (&wop2, op2);
2834 cmp = sim_fpu_cmp (&wop1, &wop2);
2835 break;
2836 }
2837 case fmt_double:
2838 {
2839 sim_fpu wop1;
2840 sim_fpu wop2;
2841 sim_fpu_64to (&wop1, op1);
2842 sim_fpu_64to (&wop2, op2);
2843 cmp = sim_fpu_cmp (&wop1, &wop2);
2844 break;
2845 }
2846 default:
2847 fprintf (stderr, "Bad switch\n");
2848 abort ();
2849 }
2850
2851 switch (cmp)
2852 {
2853 case SIM_FPU_IS_SNAN:
2854 case SIM_FPU_IS_QNAN:
2855 result = op1;
2856 case SIM_FPU_IS_NINF:
2857 case SIM_FPU_IS_NNUMBER:
2858 case SIM_FPU_IS_NDENORM:
2859 case SIM_FPU_IS_NZERO:
2860 result = op1; /* op1 - op2 < 0 */
2861 case SIM_FPU_IS_PINF:
2862 case SIM_FPU_IS_PNUMBER:
2863 case SIM_FPU_IS_PDENORM:
2864 case SIM_FPU_IS_PZERO:
2865 result = op2; /* op1 - op2 > 0 */
2866 default:
2867 fprintf (stderr, "Bad switch\n");
2868 abort ();
2869 }
2870
2871 #ifdef DEBUG
2872 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2873 #endif /* DEBUG */
2874
2875 return(result);
2876 }
2877 #endif
2878
2879 uword64
2880 convert (SIM_DESC sd,
2881 sim_cpu *cpu,
2882 address_word cia,
2883 int rm,
2884 uword64 op,
2885 FP_formats from,
2886 FP_formats to)
2887 {
2888 sim_fpu wop;
2889 sim_fpu_round round;
2890 unsigned32 result32;
2891 unsigned64 result64;
2892
2893 #ifdef DEBUG
2894 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
2895 #endif /* DEBUG */
2896
2897 switch (rm)
2898 {
2899 case FP_RM_NEAREST:
2900 /* Round result to nearest representable value. When two
2901 representable values are equally near, round to the value
2902 that has a least significant bit of zero (i.e. is even). */
2903 round = sim_fpu_round_near;
2904 break;
2905 case FP_RM_TOZERO:
2906 /* Round result to the value closest to, and not greater in
2907 magnitude than, the result. */
2908 round = sim_fpu_round_zero;
2909 break;
2910 case FP_RM_TOPINF:
2911 /* Round result to the value closest to, and not less than,
2912 the result. */
2913 round = sim_fpu_round_up;
2914 break;
2915
2916 case FP_RM_TOMINF:
2917 /* Round result to the value closest to, and not greater than,
2918 the result. */
2919 round = sim_fpu_round_down;
2920 break;
2921 default:
2922 round = 0;
2923 fprintf (stderr, "Bad switch\n");
2924 abort ();
2925 }
2926
2927 /* Convert the input to sim_fpu internal format */
2928 switch (from)
2929 {
2930 case fmt_double:
2931 sim_fpu_64to (&wop, op);
2932 break;
2933 case fmt_single:
2934 sim_fpu_32to (&wop, op);
2935 break;
2936 case fmt_word:
2937 sim_fpu_i32to (&wop, op, round);
2938 break;
2939 case fmt_long:
2940 sim_fpu_i64to (&wop, op, round);
2941 break;
2942 default:
2943 fprintf (stderr, "Bad switch\n");
2944 abort ();
2945 }
2946
2947 /* Convert sim_fpu format into the output */
2948 /* The value WOP is converted to the destination format, rounding
2949 using mode RM. When the destination is a fixed-point format, then
2950 a source value of Infinity, NaN or one which would round to an
2951 integer outside the fixed point range then an IEEE Invalid
2952 Operation condition is raised. */
2953 switch (to)
2954 {
2955 case fmt_single:
2956 sim_fpu_round_32 (&wop, round, 0);
2957 sim_fpu_to32 (&result32, &wop);
2958 result64 = result32;
2959 break;
2960 case fmt_double:
2961 sim_fpu_round_64 (&wop, round, 0);
2962 sim_fpu_to64 (&result64, &wop);
2963 break;
2964 case fmt_word:
2965 sim_fpu_to32i (&result32, &wop, round);
2966 result64 = result32;
2967 break;
2968 case fmt_long:
2969 sim_fpu_to64i (&result64, &wop, round);
2970 break;
2971 default:
2972 result64 = 0;
2973 fprintf (stderr, "Bad switch\n");
2974 abort ();
2975 }
2976
2977 #ifdef DEBUG
2978 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to));
2979 #endif /* DEBUG */
2980
2981 return(result64);
2982 }
2983
2984
2985 /*-- co-processor support routines ------------------------------------------*/
2986
2987 static int UNUSED
2988 CoProcPresent(coproc_number)
2989 unsigned int coproc_number;
2990 {
2991 /* Return TRUE if simulator provides a model for the given co-processor number */
2992 return(0);
2993 }
2994
2995 void
2996 cop_lw (SIM_DESC sd,
2997 sim_cpu *cpu,
2998 address_word cia,
2999 int coproc_num,
3000 int coproc_reg,
3001 unsigned int memword)
3002 {
3003 switch (coproc_num)
3004 {
3005 case 1:
3006 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3007 {
3008 #ifdef DEBUG
3009 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
3010 #endif
3011 StoreFPR(coproc_reg,fmt_word,(uword64)memword);
3012 FPR_STATE[coproc_reg] = fmt_uninterpreted;
3013 break;
3014 }
3015
3016 default:
3017 #if 0 /* this should be controlled by a configuration option */
3018 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
3019 #endif
3020 break;
3021 }
3022
3023 return;
3024 }
3025
3026 void
3027 cop_ld (SIM_DESC sd,
3028 sim_cpu *cpu,
3029 address_word cia,
3030 int coproc_num,
3031 int coproc_reg,
3032 uword64 memword)
3033 {
3034 switch (coproc_num) {
3035 case 1:
3036 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3037 {
3038 StoreFPR(coproc_reg,fmt_uninterpreted,memword);
3039 break;
3040 }
3041
3042 default:
3043 #if 0 /* this message should be controlled by a configuration option */
3044 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
3045 #endif
3046 break;
3047 }
3048
3049 return;
3050 }
3051
3052
3053 /* start-sanitize-sky */
3054 #ifdef TARGET_SKY
3055 void
3056 cop_lq (SIM_DESC sd,
3057 sim_cpu *cpu,
3058 address_word cia,
3059 int coproc_num,
3060 int coproc_reg,
3061 unsigned128 memword)
3062 {
3063 switch (coproc_num)
3064 {
3065 case 2:
3066 {
3067 int i;
3068
3069 while(vu0_busy())
3070 vu0_issue(sd);
3071
3072 /* one word at a time, argh! */
3073 for(i=0; i<4; i++)
3074 {
3075 unsigned_4 value;
3076 value = H2T_4(*A4_16(& memword, 3-i));
3077 write_vu_vec_reg(&(vu0_device.regs), coproc_reg, i, & value);
3078 }
3079 }
3080 break;
3081
3082 default:
3083 sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
3084 coproc_num,coproc_reg,pr_addr(cia));
3085 break;
3086 }
3087
3088 return;
3089 }
3090 #endif /* TARGET_SKY */
3091 /* end-sanitize-sky */
3092
3093
3094 unsigned int
3095 cop_sw (SIM_DESC sd,
3096 sim_cpu *cpu,
3097 address_word cia,
3098 int coproc_num,
3099 int coproc_reg)
3100 {
3101 unsigned int value = 0;
3102
3103 switch (coproc_num)
3104 {
3105 case 1:
3106 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3107 {
3108 FP_formats hold;
3109 hold = FPR_STATE[coproc_reg];
3110 FPR_STATE[coproc_reg] = fmt_word;
3111 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
3112 FPR_STATE[coproc_reg] = hold;
3113 break;
3114 }
3115
3116 default:
3117 #if 0 /* should be controlled by configuration option */
3118 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
3119 #endif
3120 break;
3121 }
3122
3123 return(value);
3124 }
3125
3126 uword64
3127 cop_sd (SIM_DESC sd,
3128 sim_cpu *cpu,
3129 address_word cia,
3130 int coproc_num,
3131 int coproc_reg)
3132 {
3133 uword64 value = 0;
3134 switch (coproc_num)
3135 {
3136 case 1:
3137 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3138 {
3139 value = ValueFPR(coproc_reg,fmt_uninterpreted);
3140 break;
3141 }
3142
3143 default:
3144 #if 0 /* should be controlled by configuration option */
3145 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
3146 #endif
3147 break;
3148 }
3149
3150 return(value);
3151 }
3152
3153
3154 /* start-sanitize-sky */
3155 #ifdef TARGET_SKY
3156 unsigned128
3157 cop_sq (SIM_DESC sd,
3158 sim_cpu *cpu,
3159 address_word cia,
3160 int coproc_num,
3161 int coproc_reg)
3162 {
3163 unsigned128 value = U16_8(0, 0);
3164 switch (coproc_num)
3165 {
3166 case 2:
3167 {
3168 unsigned_16 xyzw;
3169 int i;
3170
3171 while(vu0_busy())
3172 vu0_issue(sd);
3173
3174 /* one word at a time, argh! */
3175 for(i=0; i<4; i++)
3176 {
3177 unsigned_4 value;
3178 read_vu_vec_reg(&(vu0_device.regs), coproc_reg, i, & value);
3179 *A4_16(& xyzw, 3-i) = T2H_4(value);
3180 }
3181 return xyzw;
3182 }
3183 break;
3184
3185 default:
3186 sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
3187 coproc_num,coproc_reg,pr_addr(cia));
3188 break;
3189 }
3190
3191 return(value);
3192 }
3193 #endif /* TARGET_SKY */
3194 /* end-sanitize-sky */
3195
3196
3197 void
3198 decode_coproc (SIM_DESC sd,
3199 sim_cpu *cpu,
3200 address_word cia,
3201 unsigned int instruction)
3202 {
3203 int coprocnum = ((instruction >> 26) & 3);
3204
3205 switch (coprocnum)
3206 {
3207 case 0: /* standard CPU control and cache registers */
3208 {
3209 int code = ((instruction >> 21) & 0x1F);
3210 /* R4000 Users Manual (second edition) lists the following CP0
3211 instructions:
3212 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3213 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3214 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3215 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3216 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3217 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3218 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3219 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3220 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3221 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3222 */
3223 if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
3224 {
3225 int rt = ((instruction >> 16) & 0x1F);
3226 int rd = ((instruction >> 11) & 0x1F);
3227
3228 switch (rd) /* NOTEs: Standard CP0 registers */
3229 {
3230 /* 0 = Index R4000 VR4100 VR4300 */
3231 /* 1 = Random R4000 VR4100 VR4300 */
3232 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3233 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3234 /* 4 = Context R4000 VR4100 VR4300 */
3235 /* 5 = PageMask R4000 VR4100 VR4300 */
3236 /* 6 = Wired R4000 VR4100 VR4300 */
3237 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3238 /* 9 = Count R4000 VR4100 VR4300 */
3239 /* 10 = EntryHi R4000 VR4100 VR4300 */
3240 /* 11 = Compare R4000 VR4100 VR4300 */
3241 /* 12 = SR R4000 VR4100 VR4300 */
3242 #ifdef SUBTARGET_R3900
3243 case 3:
3244 /* ignore */
3245 break;
3246 /* 3 = Config R3900 */
3247
3248 case 7:
3249 /* ignore */
3250 break;
3251 /* 3 = Cache R3900 */
3252
3253 #endif /* SUBTARGET_R3900 */
3254 case 12:
3255 if (code == 0x00)
3256 GPR[rt] = SR;
3257 else
3258 SR = GPR[rt];
3259 break;
3260 /* 13 = Cause R4000 VR4100 VR4300 */
3261 case 13:
3262 if (code == 0x00)
3263 GPR[rt] = CAUSE;
3264 else
3265 CAUSE = GPR[rt];
3266 break;
3267 /* 14 = EPC R4000 VR4100 VR4300 */
3268 case 14:
3269 if (code == 0x00)
3270 GPR[rt] = (signed_word) (signed_address) EPC;
3271 else
3272 EPC = GPR[rt];
3273 break;
3274 /* 15 = PRId R4000 VR4100 VR4300 */
3275 #ifdef SUBTARGET_R3900
3276 /* 16 = Debug */
3277 case 16:
3278 if (code == 0x00)
3279 GPR[rt] = Debug;
3280 else
3281 Debug = GPR[rt];
3282 break;
3283 #else
3284 /* 16 = Config R4000 VR4100 VR4300 */
3285 case 16:
3286 if (code == 0x00)
3287 GPR[rt] = C0_CONFIG;
3288 else
3289 C0_CONFIG = GPR[rt];
3290 break;
3291 #endif
3292 #ifdef SUBTARGET_R3900
3293 /* 17 = Debug */
3294 case 17:
3295 if (code == 0x00)
3296 GPR[rt] = DEPC;
3297 else
3298 DEPC = GPR[rt];
3299 break;
3300 #else
3301 /* 17 = LLAddr R4000 VR4100 VR4300 */
3302 #endif
3303 /* 18 = WatchLo R4000 VR4100 VR4300 */
3304 /* 19 = WatchHi R4000 VR4100 VR4300 */
3305 /* 20 = XContext R4000 VR4100 VR4300 */
3306 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3307 /* 27 = CacheErr R4000 VR4100 */
3308 /* 28 = TagLo R4000 VR4100 VR4300 */
3309 /* 29 = TagHi R4000 VR4100 VR4300 */
3310 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3311 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
3312 /* CPR[0,rd] = GPR[rt]; */
3313 default:
3314 if (code == 0x00)
3315 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
3316 else
3317 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
3318 }
3319 }
3320 else if (code == 0x10 && (instruction & 0x3f) == 0x18)
3321 {
3322 /* ERET */
3323 if (SR & status_ERL)
3324 {
3325 /* Oops, not yet available */
3326 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
3327 PC = EPC;
3328 SR &= ~status_ERL;
3329 }
3330 else
3331 {
3332 PC = EPC;
3333 SR &= ~status_EXL;
3334 }
3335 }
3336 else if (code == 0x10 && (instruction & 0x3f) == 0x10)
3337 {
3338 /* RFE */
3339 #ifdef SUBTARGET_R3900
3340 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
3341
3342 /* shift IE/KU history bits right */
3343 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
3344
3345 /* TODO: CACHE register */
3346 #endif /* SUBTARGET_R3900 */
3347 }
3348 else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
3349 {
3350 /* DERET */
3351 Debug &= ~Debug_DM;
3352 DELAYSLOT();
3353 DSPC = DEPC;
3354 }
3355 else
3356 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
3357 /* TODO: When executing an ERET or RFE instruction we should
3358 clear LLBIT, to ensure that any out-standing atomic
3359 read/modify/write sequence fails. */
3360 }
3361 break;
3362
3363 case 2: /* co-processor 2 */
3364 {
3365 int handle = 0;
3366
3367 /* start-sanitize-sky */
3368 #ifdef TARGET_SKY
3369 /* On the R5900, this refers to a "VU" vector co-processor. */
3370
3371 int i_25_21 = (instruction >> 21) & 0x1f;
3372 int i_20_16 = (instruction >> 16) & 0x1f;
3373 int i_20_6 = (instruction >> 6) & 0x7fff;
3374 int i_15_11 = (instruction >> 11) & 0x1f;
3375 int i_15_0 = instruction & 0xffff;
3376 int i_10_1 = (instruction >> 1) & 0x3ff;
3377 int i_10_0 = instruction & 0x7ff;
3378 int i_10_6 = (instruction >> 6) & 0x1f;
3379 int i_5_0 = instruction & 0x03f;
3380 int interlock = instruction & 0x01;
3381 /* setup for semantic.c-like actions below */
3382 typedef unsigned_4 instruction_word;
3383 int CIA = cia;
3384 int NIA = cia + 4;
3385
3386 handle = 1;
3387
3388 /* test COP2 usability */
3389 if(! (SR & status_CU2))
3390 {
3391 SignalException(CoProcessorUnusable,instruction);
3392 /* NOTREACHED */
3393 }
3394
3395 #define MY_INDEX itable_COPz_NORMAL
3396 #define MY_PREFIX COPz_NORMAL
3397 #define MY_NAME "COPz_NORMAL"
3398
3399 /* classify & execute basic COP2 instructions */
3400 if(i_25_21 == 0x08 && i_20_16 == 0x00) /* BC2F */
3401 {
3402 address_word offset = EXTEND16(i_15_0) << 2;
3403 if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
3404 }
3405 else if(i_25_21 == 0x08 && i_20_16==0x02) /* BC2FL */
3406 {
3407 address_word offset = EXTEND16(i_15_0) << 2;
3408 if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
3409 else NULLIFY_NEXT_INSTRUCTION();
3410 }
3411 else if(i_25_21 == 0x08 && i_20_16 == 0x01) /* BC2T */
3412 {
3413 address_word offset = EXTEND16(i_15_0) << 2;
3414 if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
3415 }
3416 else if(i_25_21 == 0x08 && i_20_16 == 0x03) /* BC2TL */
3417 {
3418 address_word offset = EXTEND16(i_15_0) << 2;
3419 if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
3420 else NULLIFY_NEXT_INSTRUCTION();
3421 }
3422 else if((i_25_21 == 0x02 && i_10_1 == 0x000) || /* CFC2 */
3423 (i_25_21 == 0x01)) /* QMFC2 */
3424 {
3425 int rt = i_20_16;
3426 int id = i_15_11;
3427
3428 /* interlock checking */
3429 /* POLICY: never busy in macro mode */
3430 while(vu0_busy() && interlock)
3431 vu0_issue(sd);
3432
3433 /* perform VU register address */
3434 if(i_25_21 == 0x01) /* QMFC2 */
3435 {
3436 unsigned_16 xyzw;
3437 /* one word at a time, argh! */
3438 read_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
3439 read_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
3440 read_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
3441 read_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
3442 GPR[rt] = T2H_8(* A8_16(& xyzw, 1));
3443 GPR1[rt] = T2H_8(* A8_16(& xyzw, 0));
3444 }
3445 else /* CFC2 */
3446 {
3447 GPR[rt] = vu0_read_cop2_register(id);
3448 }
3449 }
3450 else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */
3451 (i_25_21 == 0x05)) /* QMTC2 */
3452 {
3453 int rt = i_20_16;
3454 int id = i_15_11;
3455
3456 /* interlock checking: wait until M or E bits set */
3457 /* POLICY: never busy in macro mode */
3458 while(vu0_busy() && interlock)
3459 {
3460 if(vu0_micro_interlock_released())
3461 {
3462 vu0_micro_interlock_clear();
3463 break;
3464 }
3465
3466 vu0_issue(sd);
3467 }
3468
3469 /* perform VU register address */
3470 if(i_25_21 == 0x05) /* QMTC2 */
3471 {
3472 unsigned_16 xyzw = U16_8(GPR1[rt], GPR[rt]);
3473
3474 xyzw = H2T_16(xyzw);
3475 /* one word at a time, argh! */
3476 write_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
3477 write_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
3478 write_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
3479 write_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
3480 }
3481 else /* CTC2 */
3482 {
3483 vu0_write_cop2_register(id, GPR[rt]);
3484 }
3485 }
3486 else if(i_10_0 == 0x3bf) /* VWAITQ */
3487 {
3488 while(vu0_q_busy())
3489 vu0_issue(sd);
3490 }
3491 else if(i_5_0 == 0x38) /* VCALLMS */
3492 {
3493 unsigned_4 data = H2T_2(i_20_6);
3494
3495 while(vu0_busy())
3496 vu0_issue(sd);
3497
3498 /* write to reserved CIA register to get VU0 moving */
3499 write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
3500
3501 ASSERT(vu0_busy());
3502 }
3503 else if(i_5_0 == 0x39) /* VCALLMSR */
3504 {
3505 unsigned_4 data;
3506
3507 while(vu0_busy())
3508 vu0_issue(sd);
3509
3510 read_vu_special_reg(& vu0_device, VU_REG_CMSAR0, & data);
3511 /* write to reserved CIA register to get VU0 moving */
3512 write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
3513
3514 ASSERT(vu0_busy());
3515 }
3516 /* handle all remaining UPPER VU instructions in one block */
3517 else if((i_5_0 < 0x30) || /* VADDx .. VMINI */
3518 (i_5_0 >= 0x3c && i_10_6 < 0x0c)) /* VADDAx .. VNOP */
3519 {
3520 unsigned_4 vu_upper, vu_lower;
3521 vu_upper =
3522 0x00000000 | /* bits 31 .. 25 */
3523 (instruction & 0x01ffffff); /* bits 24 .. 0 */
3524 vu_lower = 0x8000033c; /* NOP */
3525
3526 /* POLICY: never busy in macro mode */
3527 while(vu0_busy())
3528 vu0_issue(sd);
3529
3530 vu0_macro_issue(vu_upper, vu_lower);
3531
3532 /* POLICY: wait for completion of macro-instruction */
3533 while(vu0_busy())
3534 vu0_issue(sd);
3535 }
3536 /* handle all remaining LOWER VU instructions in one block */
3537 else if((i_5_0 >= 0x30 && i_5_0 <= 0x35) || /* VIADD .. VIOR */
3538 (i_5_0 >= 0x3c && i_10_6 >= 0x0c)) /* VMOVE .. VRXOR */
3539 { /* N.B.: VWAITQ already covered by prior case */
3540 unsigned_4 vu_upper, vu_lower;
3541 vu_upper = 0x000002ff; /* NOP/NOP */
3542 vu_lower =
3543 0x80000000 | /* bits 31 .. 25 */
3544 (instruction & 0x01ffffff); /* bits 24 .. 0 */
3545
3546 /* POLICY: never busy in macro mode */
3547 while(vu0_busy())
3548 vu0_issue(sd);
3549
3550 vu0_macro_issue(vu_upper, vu_lower);
3551
3552 /* POLICY: wait for completion of macro-instruction */
3553 while(vu0_busy())
3554 vu0_issue(sd);
3555 }
3556 /* ... no other COP2 instructions ... */
3557 else
3558 {
3559 SignalException(ReservedInstruction, instruction);
3560 /* NOTREACHED */
3561 }
3562
3563 /* cleanup for semantic.c-like actions above */
3564 PC = NIA;
3565
3566 #undef MY_INDEX
3567 #undef MY_PREFIX
3568 #undef MY_NAME
3569
3570 #endif /* TARGET_SKY */
3571 /* end-sanitize-sky */
3572
3573 if(! handle)
3574 {
3575 sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
3576 instruction,pr_addr(cia));
3577 }
3578 }
3579 break;
3580
3581 case 1: /* should not occur (FPU co-processor) */
3582 case 3: /* should not occur (FPU co-processor) */
3583 SignalException(ReservedInstruction,instruction);
3584 break;
3585 }
3586
3587 return;
3588 }
3589
3590
3591 /*-- instruction simulation -------------------------------------------------*/
3592
3593 /* When the IGEN simulator is being built, the function below is be
3594 replaced by a generated version. However, WITH_IGEN == 2 indicates
3595 that the fubction below should be compiled but under a different
3596 name (to allow backward compatibility) */
3597
3598 #if (WITH_IGEN != 1)
3599 #if (WITH_IGEN > 1)
3600 void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
3601 void
3602 old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
3603 #else
3604 void
3605 sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
3606 #endif
3607 SIM_DESC sd;
3608 int next_cpu_nr; /* ignore */
3609 int nr_cpus; /* ignore */
3610 int siggnal; /* ignore */
3611 {
3612 sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
3613 #if !defined(FASTSIM)
3614 unsigned int pipeline_count = 1;
3615 #endif
3616
3617 #ifdef DEBUG
3618 if (STATE_MEMORY (sd) == NULL) {
3619 printf("DBG: simulate() entered with no memory\n");
3620 exit(1);
3621 }
3622 #endif /* DEBUG */
3623
3624 #if 0 /* Disabled to check that everything works OK */
3625 /* The VR4300 seems to sign-extend the PC on its first
3626 access. However, this may just be because it is currently
3627 configured in 32bit mode. However... */
3628 PC = SIGNEXTEND(PC,32);
3629 #endif
3630
3631 /* main controlling loop */
3632 while (1) {
3633 /* vaddr is slowly being replaced with cia - current instruction
3634 address */
3635 address_word cia = (uword64)PC;
3636 address_word vaddr = cia;
3637 address_word paddr;
3638 int cca;
3639 unsigned int instruction; /* uword64? what's this used for? FIXME! */
3640
3641 #ifdef DEBUG
3642 {
3643 printf("DBG: state = 0x%08X :",state);
3644 if (state & simHALTEX) printf(" simHALTEX");
3645 if (state & simHALTIN) printf(" simHALTIN");
3646 printf("\n");
3647 }
3648 #endif /* DEBUG */
3649
3650 DSSTATE = (STATE & simDELAYSLOT);
3651 #ifdef DEBUG
3652 if (dsstate)
3653 sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
3654 #endif /* DEBUG */
3655
3656 /* Fetch the next instruction from the simulator memory: */
3657 if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
3658 if ((vaddr & 1) == 0) {
3659 /* Copy the action of the LW instruction */
3660 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
3661 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
3662 uword64 value;
3663 unsigned int byte;
3664 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
3665 LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
3666 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
3667 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
3668 } else {
3669 /* Copy the action of the LH instruction */
3670 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
3671 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
3672 uword64 value;
3673 unsigned int byte;
3674 paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
3675 | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
3676 LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
3677 paddr & ~ (uword64) 1,
3678 vaddr, isINSTRUCTION, isREAL);
3679 byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
3680 instruction = ((value >> (8 * byte)) & 0xFFFF);
3681 }
3682 } else {
3683 fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
3684 exit(1);
3685 }
3686
3687 #ifdef DEBUG
3688 sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
3689 #endif /* DEBUG */
3690
3691 /* This is required by exception processing, to ensure that we can
3692 cope with exceptions in the delay slots of branches that may
3693 already have changed the PC. */
3694 if ((vaddr & 1) == 0)
3695 PC += 4; /* increment ready for the next fetch */
3696 else
3697 PC += 2;
3698 /* NOTE: If we perform a delay slot change to the PC, this
3699 increment is not requuired. However, it would make the
3700 simulator more complicated to try and avoid this small hit. */
3701
3702 /* Currently this code provides a simple model. For more
3703 complicated models we could perform exception status checks at
3704 this point, and set the simSTOP state as required. This could
3705 also include processing any hardware interrupts raised by any
3706 I/O model attached to the simulator context.
3707
3708 Support for "asynchronous" I/O events within the simulated world
3709 could be providing by managing a counter, and calling a I/O
3710 specific handler when a particular threshold is reached. On most
3711 architectures a decrement and check for zero operation is
3712 usually quicker than an increment and compare. However, the
3713 process of managing a known value decrement to zero, is higher
3714 than the cost of using an explicit value UINT_MAX into the
3715 future. Which system is used will depend on how complicated the
3716 I/O model is, and how much it is likely to affect the simulator
3717 bandwidth.
3718
3719 If events need to be scheduled further in the future than
3720 UINT_MAX event ticks, then the I/O model should just provide its
3721 own counter, triggered from the event system. */
3722
3723 /* MIPS pipeline ticks. To allow for future support where the
3724 pipeline hit of individual instructions is known, this control
3725 loop manages a "pipeline_count" variable. It is initialised to
3726 1 (one), and will only be changed by the simulator engine when
3727 executing an instruction. If the engine does not have access to
3728 pipeline cycle count information then all instructions will be
3729 treated as using a single cycle. NOTE: A standard system is not
3730 provided by the default simulator because different MIPS
3731 architectures have different cycle counts for the same
3732 instructions.
3733
3734 [NOTE: pipeline_count has been replaced the event queue] */
3735
3736 /* shuffle the floating point status pipeline state */
3737 ENGINE_ISSUE_PREFIX_HOOK();
3738
3739 /* NOTE: For multi-context simulation environments the "instruction"
3740 variable should be local to this routine. */
3741
3742 /* Shorthand accesses for engine. Note: If we wanted to use global
3743 variables (and a single-threaded simulator engine), then we can
3744 create the actual variables with these names. */
3745
3746 if (!(STATE & simSKIPNEXT)) {
3747 /* Include the simulator engine */
3748 #include "oengine.c"
3749 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3750 #error "Mismatch between run-time simulator code and simulation engine"
3751 #endif
3752 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3753 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3754 #endif
3755 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3756 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3757 #endif
3758
3759 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3760 should check for it being changed. It is better doing it here,
3761 than within the simulator, since it will help keep the simulator
3762 small. */
3763 if (ZERO != 0) {
3764 #if defined(WARN_ZERO)
3765 sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
3766 #endif /* WARN_ZERO */
3767 ZERO = 0; /* reset back to zero before next instruction */
3768 }
3769 } else /* simSKIPNEXT check */
3770 STATE &= ~simSKIPNEXT;
3771
3772 /* If the delay slot was active before the instruction is
3773 executed, then update the PC to its new value: */
3774 if (DSSTATE) {
3775 #ifdef DEBUG
3776 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
3777 #endif /* DEBUG */
3778 PC = DSPC;
3779 CANCELDELAYSLOT();
3780 }
3781
3782 if (MIPSISA < 4)
3783 PENDING_TICK();
3784
3785 #if !defined(FASTSIM)
3786 if (sim_events_tickn (sd, pipeline_count))
3787 {
3788 /* cpu->cia = cia; */
3789 sim_events_process (sd);
3790 }
3791 #else
3792 if (sim_events_tick (sd))
3793 {
3794 /* cpu->cia = cia; */
3795 sim_events_process (sd);
3796 }
3797 #endif /* FASTSIM */
3798 }
3799 }
3800 #endif
3801
3802
3803 /* This code copied from gdb's utils.c. Would like to share this code,
3804 but don't know of a common place where both could get to it. */
3805
3806 /* Temporary storage using circular buffer */
3807 #define NUMCELLS 16
3808 #define CELLSIZE 32
3809 static char*
3810 get_cell()
3811 {
3812 static char buf[NUMCELLS][CELLSIZE];
3813 static int cell=0;
3814 if (++cell>=NUMCELLS) cell=0;
3815 return buf[cell];
3816 }
3817
3818 /* Print routines to handle variable size regs, etc */
3819
3820 /* Eliminate warning from compiler on 32-bit systems */
3821 static int thirty_two = 32;
3822
3823 char*
3824 pr_addr(addr)
3825 SIM_ADDR addr;
3826 {
3827 char *paddr_str=get_cell();
3828 switch (sizeof(addr))
3829 {
3830 case 8:
3831 sprintf(paddr_str,"%08lx%08lx",
3832 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3833 break;
3834 case 4:
3835 sprintf(paddr_str,"%08lx",(unsigned long)addr);
3836 break;
3837 case 2:
3838 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
3839 break;
3840 default:
3841 sprintf(paddr_str,"%x",addr);
3842 }
3843 return paddr_str;
3844 }
3845
3846 char*
3847 pr_uword64(addr)
3848 uword64 addr;
3849 {
3850 char *paddr_str=get_cell();
3851 sprintf(paddr_str,"%08lx%08lx",
3852 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3853 return paddr_str;
3854 }
3855
3856
3857
3858 /*---------------------------------------------------------------------------*/
3859 /*> EOF interp.c <*/
GDB Binutils - Deliverables
This page took 0.124209 seconds and 5 git commands to generate.