2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22 We only need to take account of the target endianness when moving data
23 between the simulator and the host. We do not need to worry about the
24 endianness of the host, since this sim code and GDB are executing in
27 The IDT monitor (found on the VR4300 board), seems to lie about
28 register contents. It seems to treat the registers as sign-extended
29 32-bit values. This cause *REAL* problems when single-stepping 64-bit
34 /* The TRACE manifests enable the provision of extra features. If they
35 are not defined then a simpler (quicker) simulator is constructed
36 without the required run-time checks, etc. */
37 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
43 #include "sim-utils.h"
44 #include "sim-options.h"
45 #include "sim-assert.h"
67 #include "libiberty.h"
69 #include "callback.h" /* GDB simulator callback interface */
70 #include "remote-sim.h" /* GDB simulator interface */
78 char* pr_addr
PARAMS ((SIM_ADDR addr
));
79 char* pr_uword64
PARAMS ((uword64 addr
));
82 /* Get the simulator engine description, without including the code: */
88 /* The following reserved instruction value is used when a simulator
89 trap is required. NOTE: Care must be taken, since this value may be
90 used in later revisions of the MIPS ISA. */
91 #define RSVD_INSTRUCTION (0x00000005)
92 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
94 #define RSVD_INSTRUCTION_ARG_SHIFT 6
95 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
98 /* Bits in the Debug register */
99 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
100 #define Debug_DM 0x40000000 /* Debug Mode */
101 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
107 /*---------------------------------------------------------------------------*/
108 /*-- GDB simulator interface ------------------------------------------------*/
109 /*---------------------------------------------------------------------------*/
111 static void dotrace
PARAMS((SIM_DESC sd
,FILE *tracefh
,int type
,SIM_ADDR address
,int width
,char *comment
,...));
112 static void ColdReset
PARAMS((SIM_DESC sd
));
113 static long getnum
PARAMS((SIM_DESC sd
, char *value
));
114 static unsigned int power2
PARAMS((unsigned int value
));
115 static void mips_size
PARAMS((SIM_DESC sd
, int n
));
117 /*---------------------------------------------------------------------------*/
121 #define DELAYSLOT() {\
122 if (STATE & simDELAYSLOT)\
123 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
124 STATE |= simDELAYSLOT;\
127 #define JALDELAYSLOT() {\
129 STATE |= simJALDELAYSLOT;\
133 STATE &= ~simDELAYSLOT;\
134 STATE |= simSKIPNEXT;\
137 #define CANCELDELAYSLOT() {\
139 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
142 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
143 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
145 #define K0BASE (0x80000000)
146 #define K0SIZE (0x20000000)
147 #define K1BASE (0xA0000000)
148 #define K1SIZE (0x20000000)
150 /* Simple run-time monitor support */
151 static unsigned char *monitor
= NULL
;
152 static ut_reg monitor_base
= 0xBFC00000;
153 static unsigned monitor_size
= (1 << 11); /* power-of-2 */
155 static char *logfile
= NULL
; /* logging disabled by default */
156 static FILE *logfh
= NULL
;
159 static char *tracefile
= "trace.din"; /* default filename for trace log */
160 static FILE *tracefh
= NULL
;
161 static void open_trace
PARAMS((SIM_DESC sd
));
165 mips_option_handler (sd
, opt
, arg
)
175 tmp
= (char *)malloc(strlen(arg
) + 1);
177 sim_io_printf(sd
,"Failed to allocate buffer for logfile name \"%s\"\n",optarg
);
186 sim_io_printf(sd
,"Explicit model selection not yet available (Ignoring \"%s\")\n",optarg
);
191 /* Eventually the simTRACE flag could be treated as a toggle, to
192 allow external control of the program points being traced
193 (i.e. only from main onwards, excluding the run-time setup,
197 else if (strcmp (arg
, "yes") == 0)
199 else if (strcmp (arg
, "no") == 0)
203 fprintf (stderr
, "Unreconized trace option `%s'\n", arg
);
209 Simulator constructed without tracing support (for performance).\n\
210 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
216 if (optarg
!= NULL
) {
218 tmp
= (char *)malloc(strlen(optarg
) + 1);
221 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
227 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
238 static const OPTION mips_options
[] =
240 { {"log", required_argument
, NULL
,'l'},
241 'l', "FILE", "Log file",
242 mips_option_handler
},
243 { {"name", required_argument
, NULL
,'n'},
244 'n', "MODEL", "Select arch model",
245 mips_option_handler
},
246 { {"trace", optional_argument
, NULL
,'t'},
247 't', "on|off", "Enable tracing",
248 mips_option_handler
},
249 { {"tracefile",required_argument
, NULL
,'z'},
250 'z', "FILE", "Write trace to file",
251 mips_option_handler
},
252 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
256 int interrupt_pending
;
259 interrupt_event (SIM_DESC sd
, void *data
)
263 interrupt_pending
= 0;
264 SignalExceptionInterrupt ();
266 else if (!interrupt_pending
)
267 sim_events_schedule (sd
, 1, interrupt_event
, data
);
272 /*---------------------------------------------------------------------------*/
273 /*-- GDB simulator interface ------------------------------------------------*/
274 /*---------------------------------------------------------------------------*/
277 sim_open (kind
, cb
, abfd
, argv
)
283 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
284 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
286 /* FIXME: watchpoints code shouldn't need this */
287 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
288 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
289 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
291 /* memory defaults (unless sim_size was here first) */
292 if (STATE_MEM_SIZE (sd
) == 0)
293 STATE_MEM_SIZE (sd
) = (2 << 20);
294 STATE_MEM_BASE (sd
) = K1BASE
;
298 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
300 sim_add_option_table (sd
, mips_options
);
302 /* getopt will print the error message so we just have to exit if this fails.
303 FIXME: Hmmm... in the case of gdb we need getopt to call
305 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
307 /* Uninstall the modules to avoid memory leaks,
308 file descriptor leaks, etc. */
309 sim_module_uninstall (sd
);
313 /* check for/establish the a reference program image */
314 if (sim_analyze_program (sd
,
315 (STATE_PROG_ARGV (sd
) != NULL
316 ? *STATE_PROG_ARGV (sd
)
320 sim_module_uninstall (sd
);
324 /* Configure/verify the target byte order and other runtime
325 configuration options */
326 if (sim_config (sd
) != SIM_RC_OK
)
328 sim_module_uninstall (sd
);
332 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
334 /* Uninstall the modules to avoid memory leaks,
335 file descriptor leaks, etc. */
336 sim_module_uninstall (sd
);
340 /* verify assumptions the simulator made about the host type system.
341 This macro does not return if there is a problem */
342 if (sizeof(int) != (4 * sizeof(char)))
343 SignalExceptionSimulatorFault ("sizeof(int) != 4");
344 if (sizeof(word64
) != (8 * sizeof(char)))
345 SignalExceptionSimulatorFault ("sizeof(word64) != 8");
348 /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
349 and DOUBLE binary formats. This is a bit nasty, requiring that we
350 trust the explicit manifests held in the source: */
351 /* TODO: We need to cope with the simulated target and the host not
352 having the same endianness. This will require the high and low
353 words of a (double) to be swapped when converting between the
354 host and the simulated target. */
362 s
.d
= (double)523.2939453125;
364 if ((s
.i
[0] == 0 && (s
.f
[1] != (float)4.01102924346923828125
365 || s
.i
[1] != 0x40805A5A))
366 || (s
.i
[1] == 0 && (s
.f
[0] != (float)4.01102924346923828125
367 || s
.i
[0] != 0x40805A5A)))
369 fprintf(stderr
,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
375 /* This is NASTY, in that we are assuming the size of specific
379 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++) {
381 cpu
->register_widths
[rn
] = GPRLEN
;
382 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ 32)))
383 cpu
->register_widths
[rn
] = GPRLEN
;
384 else if ((rn
>= 33) && (rn
<= 37))
385 cpu
->register_widths
[rn
] = GPRLEN
;
386 else if ((rn
== SRIDX
) || (rn
== FCR0IDX
) || (rn
== FCR31IDX
) || ((rn
>= 72) && (rn
<= 89)))
387 cpu
->register_widths
[rn
] = 32;
389 cpu
->register_widths
[rn
] = 0;
391 /* start-sanitize-r5900 */
393 /* set the 5900 "upper" registers to 64 bits */
394 for( rn
= LAST_EMBED_REGNUM
+1; rn
< NUM_REGS
; rn
++)
395 cpu
->register_widths
[rn
] = 64;
396 /* end-sanitize-r5900 */
400 if (logfile
!= NULL
) {
401 if (strcmp(logfile
,"-") == 0)
404 logfh
= fopen(logfile
,"wb+");
406 sim_io_printf(sd
,"Failed to create file \"%s\", writing log information to stderr.\n",tracefile
);
412 /* FIXME: In the future both of these malloc's can be replaced by
413 calls to sim-core. */
415 /* If the host has "mmap" available we could use it to provide a
416 very large virtual address space for the simulator, since memory
417 would only be allocated within the "mmap" space as it is
418 accessed. This can also be linked to the architecture specific
419 support, required to simulate the MMU. */
420 mips_size(sd
, STATE_MEM_SIZE (sd
));
421 /* NOTE: The above will also have enabled any profiling state! */
423 /* Create the monitor address space as well */
424 monitor
= (unsigned char *)calloc(1,monitor_size
);
426 fprintf(stderr
,"Not enough VM for monitor simulation (%d bytes)\n",
430 if (STATE
& simTRACE
)
434 /* Write the monitor trap address handlers into the monitor (eeprom)
435 address space. This can only be done once the target endianness
436 has been determined. */
439 /* Entry into the IDT monitor is via fixed address vectors, and
440 not using machine instructions. To avoid clashing with use of
441 the MIPS TRAP system, we place our own (simulator specific)
442 "undefined" instructions into the relevant vector slots. */
443 for (loop
= 0; (loop
< monitor_size
); loop
+= 4) {
444 uword64 vaddr
= (monitor_base
+ loop
);
447 if (AddressTranslation(vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isTARGET
, isRAW
))
448 StoreMemory(cca
, AccessLength_WORD
,
449 (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
)),
450 0, paddr
, vaddr
, isRAW
);
452 /* The PMON monitor uses the same address space, but rather than
453 branching into it the address of a routine is loaded. We can
454 cheat for the moment, and direct the PMON routine to IDT style
455 instructions within the monitor space. This relies on the IDT
456 monitor not using the locations from 0xBFC00500 onwards as its
458 for (loop
= 0; (loop
< 24); loop
++)
460 uword64 vaddr
= (monitor_base
+ 0x500 + (loop
* 4));
463 unsigned int value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
483 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
486 case 8: /* cliexit */
490 case 11: /* flush_cache */
494 /* FIXME - should monitor_base be SIM_ADDR?? */
495 value
= ((unsigned int)monitor_base
+ (value
* 8));
496 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
))
497 StoreMemory(cca
,AccessLength_WORD
,value
,0,paddr
,vaddr
,isRAW
);
499 sim_io_error(sd
,"Failed to write to monitor space 0x%s",pr_addr(vaddr
));
501 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
503 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
))
504 StoreMemory(cca
,AccessLength_WORD
,value
,0,paddr
,vaddr
,isRAW
);
506 sim_io_error(sd
,"Failed to write to monitor space 0x%s",pr_addr(vaddr
));
518 tracefh
= fopen(tracefile
,"wb+");
521 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
528 sim_close (sd
, quitting
)
533 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
536 /* "quitting" is non-zero if we cannot hang on errors */
538 /* Ensure that any resources allocated through the callback
539 mechanism are released: */
540 sim_io_shutdown (sd
);
543 if (tracefh
!= NULL
&& tracefh
!= stderr
)
549 if (logfh
!= NULL
&& logfh
!= stdout
&& logfh
!= stderr
)
553 if (STATE_MEMORY (sd
) != NULL
)
554 free(STATE_MEMORY (sd
)); /* cfree not available on all hosts */
555 STATE_MEMORY (sd
) = NULL
;
562 sim_write (sd
,addr
,buffer
,size
)
565 unsigned char *buffer
;
569 uword64 vaddr
= (uword64
)addr
;
571 /* Return the number of bytes written, or zero if error. */
573 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
576 /* We provide raw read and write routines, since we do not want to
577 count the GDB memory accesses in our statistics gathering. */
579 /* There is a lot of code duplication in the individual blocks
580 below, but the variables are declared locally to a block to give
581 the optimiser the best chance of improving the code. We have to
582 perform slow byte reads from the host memory, to ensure that we
583 get the data into the correct endianness for the (simulated)
584 target memory world. */
586 /* Mask count to get odd byte, odd halfword, and odd word out of the
587 way. We can then perform doubleword transfers to and from the
588 simulator memory for optimum performance. */
589 if (index
&& (index
& 1)) {
592 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
593 uword64 value
= ((uword64
)(*buffer
++));
594 StoreMemory(cca
,AccessLength_BYTE
,value
,0,paddr
,vaddr
,isRAW
);
597 index
&= ~1; /* logical operations usually quicker than arithmetic on RISC systems */
599 if (index
&& (index
& 2)) {
602 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
604 /* We need to perform the following magic to ensure that that
605 bytes are written into same byte positions in the target memory
606 world, regardless of the endianness of the host. */
608 value
= ((uword64
)(*buffer
++) << 8);
609 value
|= ((uword64
)(*buffer
++) << 0);
611 value
= ((uword64
)(*buffer
++) << 0);
612 value
|= ((uword64
)(*buffer
++) << 8);
614 StoreMemory(cca
,AccessLength_HALFWORD
,value
,0,paddr
,vaddr
,isRAW
);
619 if (index
&& (index
& 4)) {
622 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
625 value
= ((uword64
)(*buffer
++) << 24);
626 value
|= ((uword64
)(*buffer
++) << 16);
627 value
|= ((uword64
)(*buffer
++) << 8);
628 value
|= ((uword64
)(*buffer
++) << 0);
630 value
= ((uword64
)(*buffer
++) << 0);
631 value
|= ((uword64
)(*buffer
++) << 8);
632 value
|= ((uword64
)(*buffer
++) << 16);
633 value
|= ((uword64
)(*buffer
++) << 24);
635 StoreMemory(cca
,AccessLength_WORD
,value
,0,paddr
,vaddr
,isRAW
);
640 for (;index
; index
-= 8) {
643 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
646 value
= ((uword64
)(*buffer
++) << 56);
647 value
|= ((uword64
)(*buffer
++) << 48);
648 value
|= ((uword64
)(*buffer
++) << 40);
649 value
|= ((uword64
)(*buffer
++) << 32);
650 value
|= ((uword64
)(*buffer
++) << 24);
651 value
|= ((uword64
)(*buffer
++) << 16);
652 value
|= ((uword64
)(*buffer
++) << 8);
653 value
|= ((uword64
)(*buffer
++) << 0);
655 value
= ((uword64
)(*buffer
++) << 0);
656 value
|= ((uword64
)(*buffer
++) << 8);
657 value
|= ((uword64
)(*buffer
++) << 16);
658 value
|= ((uword64
)(*buffer
++) << 24);
659 value
|= ((uword64
)(*buffer
++) << 32);
660 value
|= ((uword64
)(*buffer
++) << 40);
661 value
|= ((uword64
)(*buffer
++) << 48);
662 value
|= ((uword64
)(*buffer
++) << 56);
664 StoreMemory(cca
,AccessLength_DOUBLEWORD
,value
,0,paddr
,vaddr
,isRAW
);
673 sim_read (sd
,addr
,buffer
,size
)
676 unsigned char *buffer
;
681 /* Return the number of bytes read, or zero if error. */
683 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
686 /* TODO: Perform same optimisation as the sim_write() code
687 above. NOTE: This will require a bit more work since we will need
688 to ensure that the source physical address is doubleword aligned
689 before, and then deal with trailing bytes. */
690 for (index
= 0; (index
< size
); index
++) {
691 uword64 vaddr
,paddr
,value
;
693 vaddr
= (uword64
)addr
+ index
;
694 if (AddressTranslation(vaddr
,isDATA
,isLOAD
,&paddr
,&cca
,isTARGET
,isRAW
)) {
695 LoadMemory(&value
,NULL
,cca
,AccessLength_BYTE
,paddr
,vaddr
,isDATA
,isRAW
);
696 buffer
[index
] = (unsigned char)(value
&0xFF);
705 sim_store_register (sd
,rn
,memory
)
708 unsigned char *memory
;
710 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
711 /* NOTE: gdb (the client) stores registers in target byte order
712 while the simulator uses host byte order */
714 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
717 /* Unfortunately this suffers from the same problem as the register
718 numbering one. We need to know what the width of each logical
719 register number is for the architecture being simulated. */
721 if (cpu
->register_widths
[rn
] == 0)
722 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
723 /* start-sanitize-r5900 */
724 else if (rn
== REGISTER_SA
)
725 SA
= T2H_8(*(uword64
*)memory
);
726 else if (rn
> LAST_EMBED_REGNUM
)
727 cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1] = T2H_8(*(uword64
*)memory
);
728 /* end-sanitize-r5900 */
729 else if (cpu
->register_widths
[rn
] == 32)
730 cpu
->registers
[rn
] = T2H_4 (*(unsigned int*)memory
);
732 cpu
->registers
[rn
] = T2H_8 (*(uword64
*)memory
);
738 sim_fetch_register (sd
,rn
,memory
)
741 unsigned char *memory
;
743 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
744 /* NOTE: gdb (the client) stores registers in target byte order
745 while the simulator uses host byte order */
747 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
750 if (cpu
->register_widths
[rn
] == 0)
751 sim_io_eprintf(sd
,"Invalid register width for %d (register fetch ignored)\n",rn
);
752 /* start-sanitize-r5900 */
753 else if (rn
== REGISTER_SA
)
754 *((uword64
*)memory
) = H2T_8(SA
);
755 else if (rn
> LAST_EMBED_REGNUM
)
756 *((uword64
*)memory
) = H2T_8(cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1]);
757 /* end-sanitize-r5900 */
758 else if (cpu
->register_widths
[rn
] == 32)
759 *((unsigned int *)memory
) = H2T_4 ((unsigned int)(cpu
->registers
[rn
] & 0xFFFFFFFF));
760 else /* 64bit register */
761 *((uword64
*)memory
) = H2T_8 (cpu
->registers
[rn
]);
768 sim_info (sd
,verbose
)
772 /* Accessed from the GDB "info files" command: */
773 if (STATE_VERBOSE_P (sd
) || verbose
)
776 sim_io_printf (sd
, "MIPS %d-bit %s endian simulator\n",
777 (PROCESSOR_64BIT
? 64 : 32),
778 (CURRENT_TARGET_BYTE_ORDER
== BIG_ENDIAN
? "Big" : "Little"));
780 sim_io_printf (sd
, "0x%08X bytes of memory at 0x%s\n",
782 pr_addr (STATE_MEM_BASE (sd
)));
784 #if !defined(FASTSIM)
785 /* It would be a useful feature, if when performing multi-cycle
786 simulations (rather than single-stepping) we keep the start and
787 end times of the execution, so that we can give a performance
788 figure for the simulator. */
789 #endif /* !FASTSIM */
790 sim_io_printf (sd
, "Number of execution cycles = %ld\n",
791 (long) sim_events_time (sd
));
793 /* print information pertaining to MIPS ISA and architecture being simulated */
794 /* things that may be interesting */
795 /* instructions executed - if available */
796 /* cycles executed - if available */
797 /* pipeline stalls - if available */
798 /* virtual time taken */
800 /* profiling frequency */
804 profile_print (sd
, STATE_VERBOSE_P (sd
), NULL
, NULL
);
809 sim_create_inferior (sd
, abfd
, argv
,env
)
817 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
822 /* If we were providing a more complete I/O, co-processor or memory
823 simulation, we should perform any "device" initialisation at this
824 point. This can include pre-loading memory areas with particular
825 patterns (e.g. simulating ROM monitors). */
829 PC
= (unsigned64
) bfd_get_start_address(abfd
);
833 /* TODO: Sort this properly. SIM_ADDR may already be a 64bit value: */
834 PC
= SIGNEXTEND(bfd_get_start_address(abfd
),32);
837 /* Prepare to execute the program to be simulated */
838 /* argv and env are NULL terminated lists of pointers */
841 #if 0 /* def DEBUG */
842 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
845 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
846 printf("DBG: arg \"%s\"\n",*cptr
);
849 /* We should really place the argv slot values into the argument
850 registers, and onto the stack as required. However, this
851 assumes that we have a stack defined, which is not necessarily
852 true at the moment. */
858 typedef enum {e_terminate
,e_help
,e_setmemsize
,e_reset
} e_cmds
;
860 static struct t_sim_command
{
865 {e_help
, "help", ": Show MIPS simulator private commands"},
866 {e_setmemsize
,"set-memory-size","<n> : Specify amount of memory simulated"},
867 {e_reset
, "reset-system", ": Reset the simulated processor"},
872 sim_do_command (sd
,cmd
)
876 struct t_sim_command
*cptr
;
878 if (!(cmd
&& *cmd
!= '\0'))
881 /* NOTE: Accessed from the GDB "sim" commmand: */
882 for (cptr
= sim_commands
; cptr
&& cptr
->name
; cptr
++)
883 if (strncmp (cmd
, cptr
->name
, strlen(cptr
->name
)) == 0)
885 cmd
+= strlen(cptr
->name
);
887 case e_help
: /* no arguments */
889 struct t_sim_command
*lptr
;
890 sim_io_printf(sd
,"List of MIPS simulator commands:\n");
891 for (lptr
= sim_commands
; lptr
->name
; lptr
++)
892 sim_io_printf(sd
,"%s %s\n",lptr
->name
,lptr
->help
);
893 sim_args_command (sd
, "help");
897 case e_setmemsize
: /* memory size argument */
899 unsigned int newsize
= (unsigned int)getnum(sd
, cmd
);
900 mips_size(sd
, newsize
);
904 case e_reset
: /* no arguments */
906 /* NOTE: See the comments in sim_open() relating to device
911 sim_io_printf(sd
,"FATAL: Matched \"%s\", but failed to match command id %d.\n",cmd
,cptr
->id
);
919 /* try for a common command when the sim specific lookup fails */
920 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
921 sim_io_printf(sd
,"Error: \"%s\" is not a valid MIPS simulator command.\n",cmd
);
927 /*---------------------------------------------------------------------------*/
928 /* NOTE: The following routines do not seem to be used by GDB at the
929 moment. However, they may be useful to the standalone simulator
934 mips_size(sd
, newsize
)
939 /* Used by "run", and internally, to set the simulated memory size */
941 sim_io_printf(sd
,"Zero not valid: Memory size still 0x%08X bytes\n",STATE_MEM_SIZE (sd
));
944 newsize
= power2(newsize
);
945 if (STATE_MEMORY (sd
) == NULL
)
946 new = (char *)calloc(64,(STATE_MEM_SIZE (sd
) / 64));
948 new = (char *)realloc(STATE_MEMORY (sd
),newsize
);
950 if (STATE_MEMORY (sd
) == NULL
)
951 sim_io_error(sd
,"Not enough VM for simulation memory of 0x%08X bytes",STATE_MEM_SIZE (sd
));
953 sim_io_eprintf(sd
,"Failed to resize memory (still 0x%08X bytes)\n",STATE_MEM_SIZE (sd
));
955 STATE_MEM_SIZE (sd
) = (unsigned)newsize
;
956 STATE_MEMORY (sd
) = new;
962 /*---------------------------------------------------------------------------*/
963 /*-- Private simulator support interface ------------------------------------*/
964 /*---------------------------------------------------------------------------*/
966 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
968 sim_monitor(sd
,reason
)
973 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
976 /* The IDT monitor actually allows two instructions per vector
977 slot. However, the simulator currently causes a trap on each
978 individual instruction. We cheat, and lose the bottom bit. */
981 /* The following callback functions are available, however the
982 monitor we are simulating does not make use of them: get_errno,
983 isatty, lseek, rename, system, time and unlink */
985 case 6: /* int open(char *path,int flags) */
989 if (AddressTranslation(A0
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
))
990 V0
= sim_io_open(sd
,(char *)((int)paddr
),(int)A1
);
992 sim_io_error(sd
,"Attempt to pass pointer that does not reference simulated memory");
996 case 7: /* int read(int file,char *ptr,int len) */
1000 if (AddressTranslation(A1
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
))
1001 V0
= sim_io_read(sd
,(int)A0
,(char *)((int)paddr
),(int)A2
);
1003 sim_io_error(sd
,"Attempt to pass pointer that does not reference simulated memory");
1007 case 8: /* int write(int file,char *ptr,int len) */
1011 if (AddressTranslation(A1
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
))
1012 V0
= sim_io_write(sd
,(int)A0
,(const char *)((int)paddr
),(int)A2
);
1014 sim_io_error(sd
,"Attempt to pass pointer that does not reference simulated memory");
1018 case 10: /* int close(int file) */
1019 V0
= sim_io_close(sd
,(int)A0
);
1022 case 11: /* char inbyte(void) */
1025 if (sim_io_read_stdin(sd
,&tmp
,sizeof(char)) != sizeof(char)) {
1026 sim_io_error(sd
,"Invalid return from character read");
1034 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1036 char tmp
= (char)(A0
& 0xFF);
1037 sim_io_write_stdout(sd
,&tmp
,sizeof(char));
1041 case 17: /* void _exit() */
1042 sim_io_eprintf(sd
,"sim_monitor(17): _exit(int reason) to be coded\n");
1043 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
, sim_exited
,
1044 (unsigned int)(A0
& 0xFFFFFFFF));
1047 case 28 : /* PMON flush_cache */
1050 case 55: /* void get_mem_info(unsigned int *ptr) */
1051 /* in: A0 = pointer to three word memory location */
1052 /* out: [A0 + 0] = size */
1053 /* [A0 + 4] = instruction cache size */
1054 /* [A0 + 8] = data cache size */
1057 uword64 paddr
, value
;
1061 /* NOTE: We use RAW memory writes here, but since we are not
1062 gathering statistics for the monitor calls we are simulating,
1063 it is not an issue. */
1066 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isREAL
)) {
1067 value
= (uword64
)STATE_MEM_SIZE (sd
);
1068 StoreMemory(cca
,AccessLength_WORD
,value
,0,paddr
,vaddr
,isRAW
);
1069 /* We re-do the address translations, in-case the block
1070 overlaps a memory boundary: */
1072 vaddr
+= (AccessLength_WORD
+ 1);
1073 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isREAL
)) {
1074 StoreMemory(cca
,AccessLength_WORD
,0,value
,paddr
,vaddr
,isRAW
);
1075 vaddr
+= (AccessLength_WORD
+ 1);
1076 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isREAL
))
1077 StoreMemory(cca
,AccessLength_WORD
,value
,0,paddr
,vaddr
,isRAW
);
1086 sim_io_error(sd
,"Invalid pointer passed into monitor call");
1090 case 158 : /* PMON printf */
1091 /* in: A0 = pointer to format string */
1092 /* A1 = optional argument 1 */
1093 /* A2 = optional argument 2 */
1094 /* A3 = optional argument 3 */
1096 /* The following is based on the PMON printf source */
1100 /* This isn't the quickest way, since we call the host print
1101 routine for every character almost. But it does avoid
1102 having to allocate and manage a temporary string buffer. */
1103 if (AddressTranslation(A0
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
)) {
1104 char *s
= (char *)((int)paddr
);
1105 signed_word
*ap
= &A1
; /* 1st argument */
1106 /* TODO: Include check that we only use three arguments (A1, A2 and A3) */
1110 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1111 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1114 if (strchr ("dobxXulscefg%", *s
))
1122 else if (*s
== '*') {
1127 } else if (*s
>= '1' && *s
<= '9') {
1130 for (t
= s
; isdigit (*s
); s
++);
1131 strncpy (tmp
, t
, s
- t
);
1133 n
= (unsigned int)strtol(tmp
,NULL
,10);
1139 } else if (*s
== '.')
1143 sim_io_printf(sd
,"%%");
1144 } else if (*s
== 's') {
1145 if ((int)*ap
!= 0) {
1146 if (AddressTranslation(*ap
++,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
)) {
1147 char *p
= (char *)((int)paddr
);;
1148 sim_io_printf(sd
,p
);
1151 sim_io_error(sd
,"Attempt to pass pointer that does not reference simulated memory");
1155 sim_io_printf(sd
,"(null)");
1156 } else if (*s
== 'c') {
1158 sim_io_printf(sd
,"%c",n
);
1166 if (strchr ("dobxXu", *s
)) {
1167 word64 lv
= (word64
) *ap
++;
1169 sim_io_printf(sd
,"<binary not supported>");
1171 sprintf(tmp
,"%%%s%c",longlong
? "ll" : "",*s
);
1173 sim_io_printf(sd
,tmp
,lv
);
1175 sim_io_printf(sd
,tmp
,(int)lv
);
1177 } else if (strchr ("eEfgG", *s
)) {
1178 #ifdef _MSC_VER /* MSVC version 2.x can't convert from uword64 directly */
1179 double dbl
= (double)((word64
)*ap
++);
1181 double dbl
= (double)*ap
++;
1183 sprintf(tmp
,"%%%d.%d%c",width
,trunc
,*s
);
1184 sim_io_printf(sd
,tmp
,dbl
);
1190 sim_io_printf(sd
,"%c",*s
++);
1193 sim_io_error(sd
,"Attempt to pass pointer that does not reference simulated memory");
1198 sim_io_eprintf(sd
,"TODO: sim_monitor(%d) : PC = 0x%s\n",reason
,pr_addr(IPC
));
1199 sim_io_eprintf(sd
,"(Arguments : A0 = 0x%s : A1 = 0x%s : A2 = 0x%s : A3 = 0x%s)\n",pr_addr(A0
),pr_addr(A1
),pr_addr(A2
),pr_addr(A3
));
1205 /* Store a word into memory. */
1208 store_word (sd
, vaddr
, val
)
1216 if ((vaddr
& 3) != 0)
1217 SignalExceptionAddressStore ();
1220 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1223 const uword64 mask
= 7;
1227 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1228 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1229 memval
= ((uword64
) val
) << (8 * byte
);
1230 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1236 /* Load a word from memory. */
1239 load_word (sd
, vaddr
)
1243 if ((vaddr
& 3) != 0)
1244 SignalExceptionAddressLoad ();
1250 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1253 const uword64 mask
= 0x7;
1254 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1255 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1259 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1260 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1262 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1263 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1270 /* Simulate the mips16 entry and exit pseudo-instructions. These
1271 would normally be handled by the reserved instruction exception
1272 code, but for ease of simulation we just handle them directly. */
1275 mips16_entry (sd
,insn
)
1279 int aregs
, sregs
, rreg
;
1282 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1285 aregs
= (insn
& 0x700) >> 8;
1286 sregs
= (insn
& 0x0c0) >> 6;
1287 rreg
= (insn
& 0x020) >> 5;
1289 /* This should be checked by the caller. */
1298 /* This is the entry pseudo-instruction. */
1300 for (i
= 0; i
< aregs
; i
++)
1301 store_word ((uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1309 store_word ((uword64
) tsp
, RA
);
1312 for (i
= 0; i
< sregs
; i
++)
1315 store_word ((uword64
) tsp
, GPR
[16 + i
]);
1323 /* This is the exit pseudo-instruction. */
1330 RA
= load_word ((uword64
) tsp
);
1333 for (i
= 0; i
< sregs
; i
++)
1336 GPR
[i
+ 16] = load_word ((uword64
) tsp
);
1344 FGR
[0] = WORD64LO (GPR
[4]);
1345 FPR_STATE
[0] = fmt_uninterpreted
;
1347 else if (aregs
== 6)
1349 FGR
[0] = WORD64LO (GPR
[5]);
1350 FGR
[1] = WORD64LO (GPR
[4]);
1351 FPR_STATE
[0] = fmt_uninterpreted
;
1352 FPR_STATE
[1] = fmt_uninterpreted
;
1354 #endif /* defined(HASFPU) */
1366 /* Round *UP* to the nearest power-of-2 if not already one */
1367 if (value
!= (value
& ~(value
- 1))) {
1368 for (tmp
= value
, loop
= 0; (tmp
!= 0); loop
++)
1370 value
= (1 << loop
);
1384 num
= strtol(value
,&end
,10);
1386 sim_io_printf(sd
,"Warning: Invalid number \"%s\" ignored, using zero\n",value
);
1388 if (*end
&& ((tolower(*end
) == 'k') || (tolower(*end
) == 'm'))) {
1389 if (tolower(*end
) == 'k')
1396 sim_io_printf(sd
,"Warning: Spurious characters \"%s\" at end of number ignored\n",end
);
1402 /*-- trace support ----------------------------------------------------------*/
1404 /* The TRACE support is provided (if required) in the memory accessing
1405 routines. Since we are also providing the architecture specific
1406 features, the architecture simulation code can also deal with
1407 notifying the TRACE world of cache flushes, etc. Similarly we do
1408 not need to provide profiling support in the simulator engine,
1409 since we can sample in the instruction fetch control loop. By
1410 defining the TRACE manifest, we add tracing as a run-time
1414 /* Tracing by default produces "din" format (as required by
1415 dineroIII). Each line of such a trace file *MUST* have a din label
1416 and address field. The rest of the line is ignored, so comments can
1417 be included if desired. The first field is the label which must be
1418 one of the following values:
1423 3 escape record (treated as unknown access type)
1424 4 escape record (causes cache flush)
1426 The address field is a 32bit (lower-case) hexadecimal address
1427 value. The address should *NOT* be preceded by "0x".
1429 The size of the memory transfer is not important when dealing with
1430 cache lines (as long as no more than a cache line can be
1431 transferred in a single operation :-), however more information
1432 could be given following the dineroIII requirement to allow more
1433 complete memory and cache simulators to provide better
1434 results. i.e. the University of Pisa has a cache simulator that can
1435 also take bus size and speed as (variable) inputs to calculate
1436 complete system performance (a much more useful ability when trying
1437 to construct an end product, rather than a processor). They
1438 currently have an ARM version of their tool called ChARM. */
1442 void dotrace(SIM_DESC sd
,FILE *tracefh
,int type
,SIM_ADDR address
,int width
,char *comment
,...)
1444 if (STATE
& simTRACE
) {
1446 fprintf(tracefh
,"%d %s ; width %d ; ",
1450 va_start(ap
,comment
);
1451 vfprintf(tracefh
,comment
,ap
);
1453 fprintf(tracefh
,"\n");
1455 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1456 we may be generating 64bit ones, we should put the hi-32bits of the
1457 address into the comment field. */
1459 /* TODO: Provide a buffer for the trace lines. We can then avoid
1460 performing writes until the buffer is filled, or the file is
1463 /* NOTE: We could consider adding a comment field to the "din" file
1464 produced using type 3 markers (unknown access). This would then
1465 allow information about the program that the "din" is for, and
1466 the MIPs world that was being simulated, to be placed into the
1473 /*---------------------------------------------------------------------------*/
1474 /*-- simulator engine -------------------------------------------------------*/
1475 /*---------------------------------------------------------------------------*/
1481 /* RESET: Fixed PC address: */
1482 PC
= (((uword64
)0xFFFFFFFF<<32) | 0xBFC00000);
1483 /* The reset vector address is in the unmapped, uncached memory space. */
1485 SR
&= ~(status_SR
| status_TS
| status_RP
);
1486 SR
|= (status_ERL
| status_BEV
);
1488 #if defined(HASFPU) && (GPRLEN == (64))
1489 /* Cheat and allow access to the complete register set immediately: */
1490 SR
|= status_FR
; /* 64bit registers */
1491 #endif /* HASFPU and 64bit FP registers */
1493 /* Ensure that any instructions with pending register updates are
1497 for (loop
= 0; (loop
< PSLOTS
); loop
++)
1498 PENDING_SLOT_REG
[loop
] = (LAST_EMBED_REGNUM
+ 1);
1499 PENDING_IN
= PENDING_OUT
= PENDING_TOTAL
= 0;
1503 /* Initialise the FPU registers to the unknown state */
1506 for (rn
= 0; (rn
< 32); rn
++)
1507 FPR_STATE
[rn
] = fmt_uninterpreted
;
1514 /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1515 /* Translate a virtual address to a physical address and cache
1516 coherence algorithm describing the mechanism used to resolve the
1517 memory reference. Given the virtual address vAddr, and whether the
1518 reference is to Instructions ot Data (IorD), find the corresponding
1519 physical address (pAddr) and the cache coherence algorithm (CCA)
1520 used to resolve the reference. If the virtual address is in one of
1521 the unmapped address spaces the physical address and the CCA are
1522 determined directly by the virtual address. If the virtual address
1523 is in one of the mapped address spaces then the TLB is used to
1524 determine the physical address and access type; if the required
1525 translation is not present in the TLB or the desired access is not
1526 permitted the function fails and an exception is taken.
1528 NOTE: This function is extended to return an exception state. This,
1529 along with the exception generation is used to notify whether a
1530 valid address translation occured */
1533 address_translation(sd
,vAddr
,IorD
,LorS
,pAddr
,CCA
,host
,raw
)
1543 int res
= -1; /* TRUE : Assume good return */
1546 sim_io_printf(sd
,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
1549 /* Check that the address is valid for this memory model */
1551 /* For a simple (flat) memory model, we simply pass virtual
1552 addressess through (mostly) unchanged. */
1553 vAddr
&= 0xFFFFFFFF;
1555 /* Treat the kernel memory spaces identically for the moment: */
1556 if ((STATE_MEM_BASE (sd
) == K1BASE
) && (vAddr
>= K0BASE
) && (vAddr
< (K0BASE
+ K0SIZE
)))
1557 vAddr
+= (K1BASE
- K0BASE
);
1559 /* Also assume that the K1BASE memory wraps. This is required to
1560 allow the PMON run-time __sizemem() routine to function (without
1561 having to provide exception simulation). NOTE: A kludge to work
1562 around the fact that the monitor memory is currently held in the
1564 if (((vAddr
< monitor_base
) || (vAddr
>= (monitor_base
+ monitor_size
))) && (vAddr
>= K1BASE
&& vAddr
< (K1BASE
+ K1SIZE
)))
1565 vAddr
= (K1BASE
| (vAddr
& (STATE_MEM_SIZE (sd
) - 1)));
1567 *pAddr
= vAddr
; /* default for isTARGET */
1568 *CCA
= Uncached
; /* not used for isHOST */
1570 /* NOTE: This is a duplicate of the code that appears in the
1571 LoadMemory and StoreMemory functions. They should be merged into
1572 a single function (that can be in-lined if required). */
1573 if ((vAddr
>= STATE_MEM_BASE (sd
)) && (vAddr
< (STATE_MEM_BASE (sd
) + STATE_MEM_SIZE (sd
)))) {
1575 *pAddr
= (int)&STATE_MEMORY (sd
)[((unsigned int)(vAddr
- STATE_MEM_BASE (sd
)) & (STATE_MEM_SIZE (sd
) - 1))];
1576 } else if ((vAddr
>= monitor_base
) && (vAddr
< (monitor_base
+ monitor_size
))) {
1578 *pAddr
= (int)&monitor
[((unsigned int)(vAddr
- monitor_base
) & (monitor_size
- 1))];
1581 sim_io_eprintf(sd
,"Failed: AddressTranslation(0x%s,%s,%s,...) IPC = 0x%s\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "isSTORE" : "isLOAD"),pr_addr(IPC
));
1583 res
= 0; /* AddressTranslation has failed */
1584 *pAddr
= (SIM_ADDR
)-1;
1585 if (!raw
) /* only generate exceptions on real memory transfers */
1586 if (LorS
== isSTORE
)
1587 SignalExceptionAddressStore ();
1589 SignalExceptionAddressLoad ();
1592 /* This is a normal occurance during gdb operation, for instance trying
1593 to print parameters at function start before they have been setup,
1594 and hence we should not print a warning except when debugging the
1596 sim_io_eprintf(sd
,"AddressTranslation for %s %s from 0x%s failed\n",(IorD
? "data" : "instruction"),(LorS
? "store" : "load"),pr_addr(vAddr
));
1603 /* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1604 /* Prefetch data from memory. Prefetch is an advisory instruction for
1605 which an implementation specific action is taken. The action taken
1606 may increase performance, but must not change the meaning of the
1607 program, or alter architecturally-visible state. */
1610 prefetch(sd
,CCA
,pAddr
,vAddr
,DATA
,hint
)
1619 sim_io_printf(sd
,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA
,pr_addr(pAddr
),pr_addr(vAddr
),DATA
,hint
);
1622 /* For our simple memory model we do nothing */
1626 /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1627 /* Load a value from memory. Use the cache and main memory as
1628 specified in the Cache Coherence Algorithm (CCA) and the sort of
1629 access (IorD) to find the contents of AccessLength memory bytes
1630 starting at physical location pAddr. The data is returned in the
1631 fixed width naturally-aligned memory element (MemElem). The
1632 low-order two (or three) bits of the address and the AccessLength
1633 indicate which of the bytes within MemElem needs to be given to the
1634 processor. If the memory access type of the reference is uncached
1635 then only the referenced bytes are read from memory and valid
1636 within the memory element. If the access type is cached, and the
1637 data is not present in cache, an implementation specific size and
1638 alignment block of memory is read and loaded into the cache to
1639 satisfy a load reference. At a minimum, the block is the entire
1642 load_memory(sd
,memvalp
,memval1p
,CCA
,AccessLength
,pAddr
,vAddr
,IorD
,raw
)
1657 if (STATE_MEMORY (sd
) == NULL
)
1658 sim_io_printf(sd
,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s,%s)\n",memvalp
,memval1p
,CCA
,AccessLength
,pr_addr(pAddr
),pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(raw
? "isRAW" : "isREAL"));
1661 #if defined(WARN_MEM)
1662 if (CCA
!= uncached
)
1663 sim_io_eprintf(sd
,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1665 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
) {
1666 /* In reality this should be a Bus Error */
1667 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
1669 #endif /* WARN_MEM */
1671 /* Decide which physical memory locations are being dealt with. At
1672 this point we should be able to split the pAddr bits into the
1673 relevant address map being simulated. If the "raw" variable is
1674 set, the memory read being performed should *NOT* update any I/O
1675 state or affect the CPU state. This also includes avoiding
1676 affecting statistics gathering. */
1678 /* If instruction fetch then we need to check that the two lo-order
1679 bits are zero, otherwise raise a InstructionFetch exception: */
1680 if ((IorD
== isINSTRUCTION
)
1681 && ((pAddr
& 0x3) != 0)
1682 && (((pAddr
& 0x1) != 0) || ((vAddr
& 0x1) == 0)))
1683 SignalExceptionInstructionFetch ();
1685 unsigned int index
= 0;
1686 unsigned char *mem
= NULL
;
1690 dotrace(sd
,tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
1693 /* NOTE: Quicker methods of decoding the address space can be used
1694 when a real memory map is being simulated (i.e. using hi-order
1695 address bits to select device). */
1696 if ((pAddr
>= STATE_MEM_BASE (sd
)) && (pAddr
< (STATE_MEM_BASE (sd
) + STATE_MEM_SIZE (sd
)))) {
1697 index
= ((unsigned int)(pAddr
- STATE_MEM_BASE (sd
)) & (STATE_MEM_SIZE (sd
) - 1));
1698 mem
= STATE_MEMORY (sd
);
1699 } else if ((pAddr
>= monitor_base
) && (pAddr
< (monitor_base
+ monitor_size
))) {
1700 index
= ((unsigned int)(pAddr
- monitor_base
) & (monitor_size
- 1));
1704 sim_io_error(sd
,"Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr
));
1706 /* If we obtained the endianness of the host, and it is the same
1707 as the target memory system we can optimise the memory
1708 accesses. However, without that information we must perform
1709 slow transfer, and hope that the compiler optimisation will
1710 merge successive loads. */
1712 /* In reality we should always be loading a doubleword value (or
1713 word value in 32bit memory worlds). The external code then
1714 extracts the required bytes. However, to keep performance
1715 high we only load the required bytes into the relevant
1718 switch (AccessLength
) { /* big-endian memory */
1719 case AccessLength_QUADWORD
:
1720 value1
|= ((uword64
)mem
[index
++] << 56);
1721 case 14: /* AccessLength is one less than datalen */
1722 value1
|= ((uword64
)mem
[index
++] << 48);
1724 value1
|= ((uword64
)mem
[index
++] << 40);
1726 value1
|= ((uword64
)mem
[index
++] << 32);
1728 value1
|= ((unsigned int)mem
[index
++] << 24);
1730 value1
|= ((unsigned int)mem
[index
++] << 16);
1732 value1
|= ((unsigned int)mem
[index
++] << 8);
1734 value1
|= mem
[index
];
1736 case AccessLength_DOUBLEWORD
:
1737 value
|= ((uword64
)mem
[index
++] << 56);
1738 case AccessLength_SEPTIBYTE
:
1739 value
|= ((uword64
)mem
[index
++] << 48);
1740 case AccessLength_SEXTIBYTE
:
1741 value
|= ((uword64
)mem
[index
++] << 40);
1742 case AccessLength_QUINTIBYTE
:
1743 value
|= ((uword64
)mem
[index
++] << 32);
1744 case AccessLength_WORD
:
1745 value
|= ((unsigned int)mem
[index
++] << 24);
1746 case AccessLength_TRIPLEBYTE
:
1747 value
|= ((unsigned int)mem
[index
++] << 16);
1748 case AccessLength_HALFWORD
:
1749 value
|= ((unsigned int)mem
[index
++] << 8);
1750 case AccessLength_BYTE
:
1751 value
|= mem
[index
];
1755 index
+= (AccessLength
+ 1);
1756 switch (AccessLength
) { /* little-endian memory */
1757 case AccessLength_QUADWORD
:
1758 value1
|= ((uword64
)mem
[--index
] << 56);
1759 case 14: /* AccessLength is one less than datalen */
1760 value1
|= ((uword64
)mem
[--index
] << 48);
1762 value1
|= ((uword64
)mem
[--index
] << 40);
1764 value1
|= ((uword64
)mem
[--index
] << 32);
1766 value1
|= ((uword64
)mem
[--index
] << 24);
1768 value1
|= ((uword64
)mem
[--index
] << 16);
1770 value1
|= ((uword64
)mem
[--index
] << 8);
1772 value1
|= ((uword64
)mem
[--index
] << 0);
1774 case AccessLength_DOUBLEWORD
:
1775 value
|= ((uword64
)mem
[--index
] << 56);
1776 case AccessLength_SEPTIBYTE
:
1777 value
|= ((uword64
)mem
[--index
] << 48);
1778 case AccessLength_SEXTIBYTE
:
1779 value
|= ((uword64
)mem
[--index
] << 40);
1780 case AccessLength_QUINTIBYTE
:
1781 value
|= ((uword64
)mem
[--index
] << 32);
1782 case AccessLength_WORD
:
1783 value
|= ((uword64
)mem
[--index
] << 24);
1784 case AccessLength_TRIPLEBYTE
:
1785 value
|= ((uword64
)mem
[--index
] << 16);
1786 case AccessLength_HALFWORD
:
1787 value
|= ((uword64
)mem
[--index
] << 8);
1788 case AccessLength_BYTE
:
1789 value
|= ((uword64
)mem
[--index
] << 0);
1795 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1796 (int)(pAddr
& LOADDRMASK
),pr_uword64(value1
),pr_uword64(value
));
1799 /* TODO: We could try and avoid the shifts when dealing with raw
1800 memory accesses. This would mean updating the LoadMemory and
1801 StoreMemory routines to avoid shifting the data before
1802 returning or using it. */
1803 if (AccessLength
<= AccessLength_DOUBLEWORD
) {
1804 if (!raw
) { /* do nothing for raw accessess */
1806 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1807 else /* little-endian only needs to be shifted up to the correct byte offset */
1808 value
<<= ((pAddr
& LOADDRMASK
) * 8);
1813 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1814 pr_uword64(value1
),pr_uword64(value
));
1820 if (memval1p
) *memval1p
= value1
;
1824 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1826 /* Store a value to memory. The specified data is stored into the
1827 physical location pAddr using the memory hierarchy (data caches and
1828 main memory) as specified by the Cache Coherence Algorithm
1829 (CCA). The MemElem contains the data for an aligned, fixed-width
1830 memory element (word for 32-bit processors, doubleword for 64-bit
1831 processors), though only the bytes that will actually be stored to
1832 memory need to be valid. The low-order two (or three) bits of pAddr
1833 and the AccessLength field indicates which of the bytes within the
1834 MemElem data should actually be stored; only these bytes in memory
1838 store_memory(sd
,CCA
,AccessLength
,MemElem
,MemElem1
,pAddr
,vAddr
,raw
)
1843 uword64 MemElem1
; /* High order 64 bits */
1849 sim_io_printf(sd
,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s,%s)\n",CCA
,AccessLength
,pr_uword64(MemElem
),pr_uword64(MemElem1
),pr_addr(pAddr
),pr_addr(vAddr
),(raw
? "isRAW" : "isREAL"));
1852 #if defined(WARN_MEM)
1853 if (CCA
!= uncached
)
1854 sim_io_eprintf(sd
,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1856 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1857 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
1858 #endif /* WARN_MEM */
1862 dotrace(sd
,tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
1865 /* See the comments in the LoadMemory routine about optimising
1866 memory accesses. Also if we wanted to make the simulator smaller,
1867 we could merge a lot of this code with the LoadMemory
1868 routine. However, this would slow the simulator down with
1869 run-time conditionals. */
1871 unsigned int index
= 0;
1872 unsigned char *mem
= NULL
;
1874 if ((pAddr
>= STATE_MEM_BASE (sd
)) && (pAddr
< (STATE_MEM_BASE (sd
) + STATE_MEM_SIZE (sd
)))) {
1875 index
= ((unsigned int)(pAddr
- STATE_MEM_BASE (sd
)) & (STATE_MEM_SIZE (sd
) - 1));
1876 mem
= STATE_MEMORY (sd
);
1877 } else if ((pAddr
>= monitor_base
) && (pAddr
< (monitor_base
+ monitor_size
))) {
1878 index
= ((unsigned int)(pAddr
- monitor_base
) & (monitor_size
- 1));
1883 sim_io_error(sd
,"Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr
));
1888 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr
& LOADDRMASK
),pr_uword64(MemElem1
),pr_uword64(MemElem
));
1891 if (AccessLength
<= AccessLength_DOUBLEWORD
) {
1894 shift
= ((7 - AccessLength
) * 8);
1895 else /* real memory access */
1896 shift
= ((pAddr
& LOADDRMASK
) * 8);
1899 /* no need to shift raw little-endian data */
1901 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
1906 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift
,pr_uword64(MemElem1
),pr_uword64(MemElem
));
1910 switch (AccessLength
) { /* big-endian memory */
1911 case AccessLength_QUADWORD
:
1912 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1915 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1918 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1921 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1924 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1927 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1930 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1933 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1935 case AccessLength_DOUBLEWORD
:
1936 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1938 case AccessLength_SEPTIBYTE
:
1939 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1941 case AccessLength_SEXTIBYTE
:
1942 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1944 case AccessLength_QUINTIBYTE
:
1945 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1947 case AccessLength_WORD
:
1948 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1950 case AccessLength_TRIPLEBYTE
:
1951 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1953 case AccessLength_HALFWORD
:
1954 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1956 case AccessLength_BYTE
:
1957 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1961 index
+= (AccessLength
+ 1);
1962 switch (AccessLength
) { /* little-endian memory */
1963 case AccessLength_QUADWORD
:
1964 mem
[--index
] = (unsigned char)(MemElem1
>> 56);
1966 mem
[--index
] = (unsigned char)(MemElem1
>> 48);
1968 mem
[--index
] = (unsigned char)(MemElem1
>> 40);
1970 mem
[--index
] = (unsigned char)(MemElem1
>> 32);
1972 mem
[--index
] = (unsigned char)(MemElem1
>> 24);
1974 mem
[--index
] = (unsigned char)(MemElem1
>> 16);
1976 mem
[--index
] = (unsigned char)(MemElem1
>> 8);
1978 mem
[--index
] = (unsigned char)(MemElem1
>> 0);
1980 case AccessLength_DOUBLEWORD
:
1981 mem
[--index
] = (unsigned char)(MemElem
>> 56);
1982 case AccessLength_SEPTIBYTE
:
1983 mem
[--index
] = (unsigned char)(MemElem
>> 48);
1984 case AccessLength_SEXTIBYTE
:
1985 mem
[--index
] = (unsigned char)(MemElem
>> 40);
1986 case AccessLength_QUINTIBYTE
:
1987 mem
[--index
] = (unsigned char)(MemElem
>> 32);
1988 case AccessLength_WORD
:
1989 mem
[--index
] = (unsigned char)(MemElem
>> 24);
1990 case AccessLength_TRIPLEBYTE
:
1991 mem
[--index
] = (unsigned char)(MemElem
>> 16);
1992 case AccessLength_HALFWORD
:
1993 mem
[--index
] = (unsigned char)(MemElem
>> 8);
1994 case AccessLength_BYTE
:
1995 mem
[--index
] = (unsigned char)(MemElem
>> 0);
2006 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2007 /* Order loads and stores to synchronise shared memory. Perform the
2008 action necessary to make the effects of groups of synchronizable
2009 loads and stores indicated by stype occur in the same order for all
2012 sync_operation(sd
,stype
)
2017 sim_io_printf(sd
,"SyncOperation(%d) : TODO\n",stype
);
2022 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2023 /* Signal an exception condition. This will result in an exception
2024 that aborts the instruction. The instruction operation pseudocode
2025 will never see a return from this function call. */
2028 signal_exception (SIM_DESC sd
, int exception
,...)
2033 sim_io_printf(sd
,"DBG: SignalException(%d) IPC = 0x%s\n",exception
,pr_addr(IPC
));
2036 /* Ensure that any active atomic read/modify/write operation will fail: */
2039 switch (exception
) {
2040 /* TODO: For testing purposes I have been ignoring TRAPs. In
2041 reality we should either simulate them, or allow the user to
2042 ignore them at run-time.
2045 sim_io_eprintf(sd
,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(IPC
));
2051 unsigned int instruction
;
2054 va_start(ap
,exception
);
2055 instruction
= va_arg(ap
,unsigned int);
2058 code
= (instruction
>> 6) & 0xFFFFF;
2060 sim_io_eprintf(sd
,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
2061 code
, pr_addr(IPC
));
2065 case DebugBreakPoint
:
2066 if (! (Debug
& Debug_DM
))
2072 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
2073 DEPC
= IPC
- 4; /* reference the branch instruction */
2077 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
2081 Debug
|= Debug_DM
; /* in debugging mode */
2082 Debug
|= Debug_DBp
; /* raising a DBp exception */
2084 sim_engine_restart (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
);
2088 case ReservedInstruction
:
2091 unsigned int instruction
;
2092 va_start(ap
,exception
);
2093 instruction
= va_arg(ap
,unsigned int);
2095 /* Provide simple monitor support using ReservedInstruction
2096 exceptions. The following code simulates the fixed vector
2097 entry points into the IDT monitor by causing a simulator
2098 trap, performing the monitor operation, and returning to
2099 the address held in the $ra register (standard PCS return
2100 address). This means we only need to pre-load the vector
2101 space with suitable instruction values. For systems were
2102 actual trap instructions are used, we would not need to
2103 perform this magic. */
2104 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
) {
2105 sim_monitor(sd
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
2106 PC
= RA
; /* simulate the return from the vector entry */
2107 /* NOTE: This assumes that a branch-and-link style
2108 instruction was used to enter the vector (which is the
2109 case with the current IDT monitor). */
2110 sim_engine_restart (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
);
2112 /* Look for the mips16 entry and exit instructions, and
2113 simulate a handler for them. */
2114 else if ((IPC
& 1) != 0
2115 && (instruction
& 0xf81f) == 0xe809
2116 && (instruction
& 0x0c0) != 0x0c0) {
2117 mips16_entry (instruction
);
2118 sim_engine_restart (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
);
2119 } /* else fall through to normal exception processing */
2120 sim_io_eprintf(sd
,"ReservedInstruction 0x%08X at IPC = 0x%s\n",instruction
,pr_addr(IPC
));
2125 sim_io_printf(sd
,"DBG: SignalException(%d) IPC = 0x%s\n",exception
,pr_addr(IPC
));
2127 /* Keep a copy of the current A0 in-case this is the program exit
2131 unsigned int instruction
;
2132 va_start(ap
,exception
);
2133 instruction
= va_arg(ap
,unsigned int);
2135 /* Check for our special terminating BREAK: */
2136 if ((instruction
& 0x03FFFFC0) == 0x03ff0000) {
2137 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2138 sim_exited
, (unsigned int)(A0
& 0xFFFFFFFF));
2141 if (STATE
& simDELAYSLOT
)
2142 PC
= IPC
- 4; /* reference the branch instruction */
2145 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2146 sim_stopped
, SIGTRAP
);
2149 /* Store exception code into current exception id variable (used
2152 /* TODO: If not simulating exceptions then stop the simulator
2153 execution. At the moment we always stop the simulation. */
2155 /* See figure 5-17 for an outline of the code below */
2156 if (! (SR
& status_EXL
))
2158 CAUSE
= (exception
<< 2);
2159 if (STATE
& simDELAYSLOT
)
2161 STATE
&= ~simDELAYSLOT
;
2163 EPC
= (IPC
- 4); /* reference the branch instruction */
2167 /* FIXME: TLB et.al. */
2172 CAUSE
= (exception
<< 2);
2176 /* Store exception code into current exception id variable (used
2178 if (SR
& status_BEV
)
2179 PC
= (signed)0xBFC00200 + 0x180;
2181 PC
= (signed)0x80000000 + 0x180;
2183 switch ((CAUSE
>> 2) & 0x1F)
2186 /* Interrupts arrive during event processing, no need to
2190 case TLBModification
:
2195 case InstructionFetch
:
2197 /* The following is so that the simulator will continue from the
2198 exception address on breakpoint operations. */
2200 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2201 sim_stopped
, SIGBUS
);
2203 case ReservedInstruction
:
2204 case CoProcessorUnusable
:
2206 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2207 sim_stopped
, SIGILL
);
2209 case IntegerOverflow
:
2211 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2212 sim_stopped
, SIGFPE
);
2218 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2219 sim_stopped
, SIGTRAP
);
2223 sim_engine_abort (sd
, STATE_CPU (sd
, 0), NULL_CIA
,
2224 "FATAL: Should not encounter a breakpoint\n");
2226 default : /* Unknown internal exception */
2228 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2229 sim_stopped
, SIGQUIT
);
2233 case SimulatorFault
:
2237 va_start(ap
,exception
);
2238 msg
= va_arg(ap
,char *);
2240 sim_engine_abort (sd
, STATE_CPU (sd
, 0), NULL_CIA
,
2241 "FATAL: Simulator error \"%s\"\n",msg
);
2248 #if defined(WARN_RESULT)
2249 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2250 /* This function indicates that the result of the operation is
2251 undefined. However, this should not affect the instruction
2252 stream. All that is meant to happen is that the destination
2253 register is set to an undefined result. To keep the simulator
2254 simple, we just don't bother updating the destination register, so
2255 the overall result will be undefined. If desired we can stop the
2256 simulator by raising a pseudo-exception. */
2260 sim_io_eprintf(sd
,"UndefinedResult: IPC = 0x%s\n",pr_addr(IPC
));
2261 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
2266 #endif /* WARN_RESULT */
2269 cache_op(sd
,op
,pAddr
,vAddr
,instruction
)
2274 unsigned int instruction
;
2276 #if 1 /* stop warning message being displayed (we should really just remove the code) */
2277 static int icache_warning
= 1;
2278 static int dcache_warning
= 1;
2280 static int icache_warning
= 0;
2281 static int dcache_warning
= 0;
2284 /* If CP0 is not useable (User or Supervisor mode) and the CP0
2285 enable bit in the Status Register is clear - a coprocessor
2286 unusable exception is taken. */
2288 sim_io_printf(sd
,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(IPC
));
2292 case 0: /* instruction cache */
2294 case 0: /* Index Invalidate */
2295 case 1: /* Index Load Tag */
2296 case 2: /* Index Store Tag */
2297 case 4: /* Hit Invalidate */
2299 case 6: /* Hit Writeback */
2300 if (!icache_warning
)
2302 sim_io_eprintf(sd
,"Instruction CACHE operation %d to be coded\n",(op
>> 2));
2308 SignalException(ReservedInstruction
,instruction
);
2313 case 1: /* data cache */
2315 case 0: /* Index Writeback Invalidate */
2316 case 1: /* Index Load Tag */
2317 case 2: /* Index Store Tag */
2318 case 3: /* Create Dirty */
2319 case 4: /* Hit Invalidate */
2320 case 5: /* Hit Writeback Invalidate */
2321 case 6: /* Hit Writeback */
2322 if (!dcache_warning
)
2324 sim_io_eprintf(sd
,"Data CACHE operation %d to be coded\n",(op
>> 2));
2330 SignalException(ReservedInstruction
,instruction
);
2335 default: /* unrecognised cache ID */
2336 SignalException(ReservedInstruction
,instruction
);
2343 /*-- FPU support routines ---------------------------------------------------*/
2345 #if defined(HASFPU) /* Only needed when building FPU aware simulators */
2347 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
2348 formats conform to ANSI/IEEE Std 754-1985. */
2349 /* SINGLE precision floating:
2350 * seeeeeeeefffffffffffffffffffffff
2352 * e = 8bits = exponent
2353 * f = 23bits = fraction
2355 /* SINGLE precision fixed:
2356 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2358 * i = 31bits = integer
2360 /* DOUBLE precision floating:
2361 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2363 * e = 11bits = exponent
2364 * f = 52bits = fraction
2366 /* DOUBLE precision fixed:
2367 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2369 * i = 63bits = integer
2372 /* Extract sign-bit: */
2373 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2374 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2375 /* Extract biased exponent: */
2376 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2377 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2378 /* Extract unbiased Exponent: */
2379 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2380 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2381 /* Extract complete fraction field: */
2382 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2383 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2384 /* Extract numbered fraction bit: */
2385 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2386 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2388 /* Explicit QNaN values used when value required: */
2389 #define FPQNaN_SINGLE (0x7FBFFFFF)
2390 #define FPQNaN_WORD (0x7FFFFFFF)
2391 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2392 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2394 /* Explicit Infinity values used when required: */
2395 #define FPINF_SINGLE (0x7F800000)
2396 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2398 #if 1 /* def DEBUG */
2399 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2400 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2404 value_fpr(sd
,fpr
,fmt
)
2412 /* Treat unused register values, as fixed-point 64bit values: */
2413 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
2415 /* If request to read data as "uninterpreted", then use the current
2417 fmt
= FPR_STATE
[fpr
];
2422 /* For values not yet accessed, set to the desired format: */
2423 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
2424 FPR_STATE
[fpr
] = fmt
;
2426 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
2429 if (fmt
!= FPR_STATE
[fpr
]) {
2430 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(IPC
));
2431 FPR_STATE
[fpr
] = fmt_unknown
;
2434 if (FPR_STATE
[fpr
] == fmt_unknown
) {
2435 /* Set QNaN value: */
2438 value
= FPQNaN_SINGLE
;
2442 value
= FPQNaN_DOUBLE
;
2446 value
= FPQNaN_WORD
;
2450 value
= FPQNaN_LONG
;
2457 } else if (SizeFGR() == 64) {
2461 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2464 case fmt_uninterpreted
:
2478 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2481 case fmt_uninterpreted
:
2484 if ((fpr
& 1) == 0) { /* even registers only */
2485 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2487 SignalException(ReservedInstruction
,0);
2498 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2501 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(IPC
),SizeFGR());
2508 store_fpr(sd
,fpr
,fmt
,value
)
2517 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(IPC
),SizeFGR());
2520 if (SizeFGR() == 64) {
2524 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2525 FPR_STATE
[fpr
] = fmt
;
2528 case fmt_uninterpreted
:
2532 FPR_STATE
[fpr
] = fmt
;
2536 FPR_STATE
[fpr
] = fmt_unknown
;
2544 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2545 FPR_STATE
[fpr
] = fmt
;
2548 case fmt_uninterpreted
:
2551 if ((fpr
& 1) == 0) { /* even register number only */
2552 FGR
[fpr
+1] = (value
>> 32);
2553 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2554 FPR_STATE
[fpr
+ 1] = fmt
;
2555 FPR_STATE
[fpr
] = fmt
;
2557 FPR_STATE
[fpr
] = fmt_unknown
;
2558 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2559 SignalException(ReservedInstruction
,0);
2564 FPR_STATE
[fpr
] = fmt_unknown
;
2569 #if defined(WARN_RESULT)
2572 #endif /* WARN_RESULT */
2575 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2578 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
2591 /* Check if (((E - bias) == (E_max + 1)) && (fraction != 0)). We
2592 know that the exponent field is biased... we we cheat and avoid
2593 removing the bias value. */
2596 boolean
= ((FP_S_be(op
) == 0xFF) && (FP_S_f(op
) != 0));
2597 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
2598 dealing with a SNaN or QNaN */
2601 boolean
= ((FP_D_be(op
) == 0x7FF) && (FP_D_f(op
) != 0));
2602 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
2603 dealing with a SNaN or QNaN */
2606 boolean
= (op
== FPQNaN_WORD
);
2609 boolean
= (op
== FPQNaN_LONG
);
2612 fprintf (stderr
, "Bad switch\n");
2617 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2631 printf("DBG: Infinity: format %s 0x%s (PC = 0x%s)\n",DOFMT(fmt
),pr_addr(op
),pr_addr(IPC
));
2634 /* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We
2635 know that the exponent field is biased... we we cheat and avoid
2636 removing the bias value. */
2639 boolean
= ((FP_S_be(op
) == 0xFF) && (FP_S_f(op
) == 0));
2642 boolean
= ((FP_D_be(op
) == 0x7FF) && (FP_D_f(op
) == 0));
2645 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2650 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2664 /* Argument checking already performed by the FPCOMPARE code */
2667 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2670 /* The format type should already have been checked: */
2674 unsigned int wop1
= (unsigned int)op1
;
2675 unsigned int wop2
= (unsigned int)op2
;
2676 boolean
= (*(float *)&wop1
< *(float *)&wop2
);
2680 boolean
= (*(double *)&op1
< *(double *)&op2
);
2683 fprintf (stderr
, "Bad switch\n");
2688 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2702 /* Argument checking already performed by the FPCOMPARE code */
2705 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2708 /* The format type should already have been checked: */
2711 boolean
= ((op1
& 0xFFFFFFFF) == (op2
& 0xFFFFFFFF));
2714 boolean
= (op1
== op2
);
2717 fprintf (stderr
, "Bad switch\n");
2722 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2729 AbsoluteValue(op
,fmt
)
2736 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2739 /* The format type should already have been checked: */
2743 unsigned int wop
= (unsigned int)op
;
2744 float tmp
= ((float)fabs((double)*(float *)&wop
));
2745 result
= (uword64
)*(unsigned int *)&tmp
;
2750 double tmp
= (fabs(*(double *)&op
));
2751 result
= *(uword64
*)&tmp
;
2754 fprintf (stderr
, "Bad switch\n");
2769 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2772 /* The format type should already have been checked: */
2776 unsigned int wop
= (unsigned int)op
;
2777 float tmp
= ((float)0.0 - *(float *)&wop
);
2778 result
= (uword64
)*(unsigned int *)&tmp
;
2783 double tmp
= ((double)0.0 - *(double *)&op
);
2784 result
= *(uword64
*)&tmp
;
2788 fprintf (stderr
, "Bad switch\n");
2804 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2807 /* The registers must specify FPRs valid for operands of type
2808 "fmt". If they are not valid, the result is undefined. */
2810 /* The format type should already have been checked: */
2814 unsigned int wop1
= (unsigned int)op1
;
2815 unsigned int wop2
= (unsigned int)op2
;
2816 float tmp
= (*(float *)&wop1
+ *(float *)&wop2
);
2817 result
= (uword64
)*(unsigned int *)&tmp
;
2822 double tmp
= (*(double *)&op1
+ *(double *)&op2
);
2823 result
= *(uword64
*)&tmp
;
2827 fprintf (stderr
, "Bad switch\n");
2832 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2847 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2850 /* The registers must specify FPRs valid for operands of type
2851 "fmt". If they are not valid, the result is undefined. */
2853 /* The format type should already have been checked: */
2857 unsigned int wop1
= (unsigned int)op1
;
2858 unsigned int wop2
= (unsigned int)op2
;
2859 float tmp
= (*(float *)&wop1
- *(float *)&wop2
);
2860 result
= (uword64
)*(unsigned int *)&tmp
;
2865 double tmp
= (*(double *)&op1
- *(double *)&op2
);
2866 result
= *(uword64
*)&tmp
;
2870 fprintf (stderr
, "Bad switch\n");
2875 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2882 Multiply(op1
,op2
,fmt
)
2890 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2893 /* The registers must specify FPRs valid for operands of type
2894 "fmt". If they are not valid, the result is undefined. */
2896 /* The format type should already have been checked: */
2900 unsigned int wop1
= (unsigned int)op1
;
2901 unsigned int wop2
= (unsigned int)op2
;
2902 float tmp
= (*(float *)&wop1
* *(float *)&wop2
);
2903 result
= (uword64
)*(unsigned int *)&tmp
;
2908 double tmp
= (*(double *)&op1
* *(double *)&op2
);
2909 result
= *(uword64
*)&tmp
;
2913 fprintf (stderr
, "Bad switch\n");
2918 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2933 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2936 /* The registers must specify FPRs valid for operands of type
2937 "fmt". If they are not valid, the result is undefined. */
2939 /* The format type should already have been checked: */
2943 unsigned int wop1
= (unsigned int)op1
;
2944 unsigned int wop2
= (unsigned int)op2
;
2945 float tmp
= (*(float *)&wop1
/ *(float *)&wop2
);
2946 result
= (uword64
)*(unsigned int *)&tmp
;
2951 double tmp
= (*(double *)&op1
/ *(double *)&op2
);
2952 result
= *(uword64
*)&tmp
;
2956 fprintf (stderr
, "Bad switch\n");
2961 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2975 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2978 /* The registers must specify FPRs valid for operands of type
2979 "fmt". If they are not valid, the result is undefined. */
2981 /* The format type should already have been checked: */
2985 unsigned int wop
= (unsigned int)op
;
2986 float tmp
= ((float)1.0 / *(float *)&wop
);
2987 result
= (uword64
)*(unsigned int *)&tmp
;
2992 double tmp
= ((double)1.0 / *(double *)&op
);
2993 result
= *(uword64
*)&tmp
;
2997 fprintf (stderr
, "Bad switch\n");
3002 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3016 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
3019 /* The registers must specify FPRs valid for operands of type
3020 "fmt". If they are not valid, the result is undefined. */
3022 /* The format type should already have been checked: */
3026 unsigned int wop
= (unsigned int)op
;
3028 float tmp
= ((float)sqrt((double)*(float *)&wop
));
3029 result
= (uword64
)*(unsigned int *)&tmp
;
3031 /* TODO: Provide square-root */
3032 result
= (uword64
)0;
3039 double tmp
= (sqrt(*(double *)&op
));
3040 result
= *(uword64
*)&tmp
;
3042 /* TODO: Provide square-root */
3043 result
= (uword64
)0;
3048 fprintf (stderr
, "Bad switch\n");
3053 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3060 convert(sd
,rm
,op
,from
,to
)
3070 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
3073 /* The value "op" is converted to the destination format, rounding
3074 using mode "rm". When the destination is a fixed-point format,
3075 then a source value of Infinity, NaN or one which would round to
3076 an integer outside the fixed point range then an IEEE Invalid
3077 Operation condition is raised. */
3084 tmp
= (float)(*(double *)&op
);
3088 tmp
= (float)((int)(op
& 0xFFFFFFFF));
3092 tmp
= (float)((word64
)op
);
3095 fprintf (stderr
, "Bad switch\n");
3100 /* FIXME: This code is incorrect. The rounding mode does not
3101 round to integral values; it rounds to the nearest
3102 representable value in the format. */
3106 /* Round result to nearest representable value. When two
3107 representable values are equally near, round to the value
3108 that has a least significant bit of zero (i.e. is even). */
3110 tmp
= (float)anint((double)tmp
);
3112 /* TODO: Provide round-to-nearest */
3117 /* Round result to the value closest to, and not greater in
3118 magnitude than, the result. */
3120 tmp
= (float)aint((double)tmp
);
3122 /* TODO: Provide round-to-zero */
3127 /* Round result to the value closest to, and not less than,
3129 tmp
= (float)ceil((double)tmp
);
3133 /* Round result to the value closest to, and not greater than,
3135 tmp
= (float)floor((double)tmp
);
3140 result
= (uword64
)*(unsigned int *)&tmp
;
3152 unsigned int wop
= (unsigned int)op
;
3153 tmp
= (double)(*(float *)&wop
);
3158 xxx
= SIGNEXTEND((op
& 0xFFFFFFFF),32);
3163 tmp
= (double)((word64
)op
);
3167 fprintf (stderr
, "Bad switch\n");
3172 /* FIXME: This code is incorrect. The rounding mode does not
3173 round to integral values; it rounds to the nearest
3174 representable value in the format. */
3179 tmp
= anint(*(double *)&tmp
);
3181 /* TODO: Provide round-to-nearest */
3187 tmp
= aint(*(double *)&tmp
);
3189 /* TODO: Provide round-to-zero */
3194 tmp
= ceil(*(double *)&tmp
);
3198 tmp
= floor(*(double *)&tmp
);
3203 result
= *(uword64
*)&tmp
;
3209 if (Infinity(op
,from
) || NaN(op
,from
) || (1 == 0/*TODO: check range */)) {
3210 printf("DBG: TODO: update FCSR\n");
3211 SignalExceptionFPE ();
3213 if (to
== fmt_word
) {
3218 unsigned int wop
= (unsigned int)op
;
3219 tmp
= (int)*((float *)&wop
);
3223 tmp
= (int)*((double *)&op
);
3225 printf("DBG: from double %.30f (0x%s) to word: 0x%08X\n",*((double *)&op
),pr_addr(op
),tmp
);
3229 fprintf (stderr
, "Bad switch\n");
3232 result
= (uword64
)tmp
;
3233 } else { /* fmt_long */
3238 unsigned int wop
= (unsigned int)op
;
3239 tmp
= (word64
)*((float *)&wop
);
3243 tmp
= (word64
)*((double *)&op
);
3246 fprintf (stderr
, "Bad switch\n");
3249 result
= (uword64
)tmp
;
3254 fprintf (stderr
, "Bad switch\n");
3259 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result
),DOFMT(to
));
3266 /*-- co-processor support routines ------------------------------------------*/
3269 CoProcPresent(coproc_number
)
3270 unsigned int coproc_number
;
3272 /* Return TRUE if simulator provides a model for the given co-processor number */
3277 cop_lw(sd
,coproc_num
,coproc_reg
,memword
)
3279 int coproc_num
, coproc_reg
;
3280 unsigned int memword
;
3282 switch (coproc_num
) {
3286 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
3288 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
3289 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
3294 #if 0 /* this should be controlled by a configuration option */
3295 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(IPC
));
3304 cop_ld(sd
,coproc_num
,coproc_reg
,memword
)
3306 int coproc_num
, coproc_reg
;
3309 switch (coproc_num
) {
3312 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
3317 #if 0 /* this message should be controlled by a configuration option */
3318 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(IPC
));
3327 cop_sw(sd
,coproc_num
,coproc_reg
)
3329 int coproc_num
, coproc_reg
;
3331 unsigned int value
= 0;
3333 switch (coproc_num
) {
3339 hold
= FPR_STATE
[coproc_reg
];
3340 FPR_STATE
[coproc_reg
] = fmt_word
;
3341 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
3342 FPR_STATE
[coproc_reg
] = hold
;
3346 value
= (unsigned int)ValueFPR(coproc_reg
,FPR_STATE
[coproc_reg
]);
3349 printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE
[coproc_reg
]));
3351 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_single
);
3358 #if 0 /* should be controlled by configuration option */
3359 sim_io_printf(sd
,"COP_SW(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(IPC
));
3368 cop_sd(sd
,coproc_num
,coproc_reg
)
3370 int coproc_num
, coproc_reg
;
3373 switch (coproc_num
) {
3377 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
3380 value
= ValueFPR(coproc_reg
,FPR_STATE
[coproc_reg
]);
3383 printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE
[coproc_reg
]));
3385 value
= ValueFPR(coproc_reg
,fmt_double
);
3392 #if 0 /* should be controlled by configuration option */
3393 sim_io_printf(sd
,"COP_SD(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(IPC
));
3402 decode_coproc(sd
,instruction
)
3404 unsigned int instruction
;
3406 int coprocnum
= ((instruction
>> 26) & 3);
3410 case 0: /* standard CPU control and cache registers */
3412 int code
= ((instruction
>> 21) & 0x1F);
3413 /* R4000 Users Manual (second edition) lists the following CP0
3415 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3416 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3417 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3418 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3419 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3420 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3421 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3422 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3423 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3424 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3426 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0))
3428 int rt
= ((instruction
>> 16) & 0x1F);
3429 int rd
= ((instruction
>> 11) & 0x1F);
3431 switch (rd
) /* NOTEs: Standard CP0 registers */
3433 /* 0 = Index R4000 VR4100 VR4300 */
3434 /* 1 = Random R4000 VR4100 VR4300 */
3435 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3436 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3437 /* 4 = Context R4000 VR4100 VR4300 */
3438 /* 5 = PageMask R4000 VR4100 VR4300 */
3439 /* 6 = Wired R4000 VR4100 VR4300 */
3440 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3441 /* 9 = Count R4000 VR4100 VR4300 */
3442 /* 10 = EntryHi R4000 VR4100 VR4300 */
3443 /* 11 = Compare R4000 VR4100 VR4300 */
3444 /* 12 = SR R4000 VR4100 VR4300 */
3451 /* 13 = Cause R4000 VR4100 VR4300 */
3458 /* 14 = EPC R4000 VR4100 VR4300 */
3459 /* 15 = PRId R4000 VR4100 VR4300 */
3460 #ifdef SUBTARGET_R3900
3469 /* 16 = Config R4000 VR4100 VR4300 */
3471 #ifdef SUBTARGET_R3900
3480 /* 17 = LLAddr R4000 VR4100 VR4300 */
3482 /* 18 = WatchLo R4000 VR4100 VR4300 */
3483 /* 19 = WatchHi R4000 VR4100 VR4300 */
3484 /* 20 = XContext R4000 VR4100 VR4300 */
3485 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3486 /* 27 = CacheErr R4000 VR4100 */
3487 /* 28 = TagLo R4000 VR4100 VR4300 */
3488 /* 29 = TagHi R4000 VR4100 VR4300 */
3489 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3490 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3491 /* CPR[0,rd] = GPR[rt]; */
3494 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3496 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3499 else if (code
== 0x10 && (instruction
& 0x3f) == 0x18)
3502 if (SR
& status_ERL
)
3504 /* Oops, not yet available */
3505 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3515 else if (code
== 0x10 && (instruction
& 0x3f) == 0x10)
3519 else if (code
== 0x10 && (instruction
& 0x3f) == 0x1F)
3527 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at IPC = 0x%s : No handler present\n",instruction
,pr_addr(IPC
));
3528 /* TODO: When executing an ERET or RFE instruction we should
3529 clear LLBIT, to ensure that any out-standing atomic
3530 read/modify/write sequence fails. */
3534 case 2: /* undefined co-processor */
3535 sim_io_eprintf(sd
,"COP2 instruction 0x%08X at IPC = 0x%s : No handler present\n",instruction
,pr_addr(IPC
));
3538 case 1: /* should not occur (FPU co-processor) */
3539 case 3: /* should not occur (FPU co-processor) */
3540 SignalException(ReservedInstruction
,instruction
);
3547 /*-- instruction simulation -------------------------------------------------*/
3550 sim_engine_run (sd
, next_cpu_nr
, siggnal
)
3552 int next_cpu_nr
; /* ignore */
3553 int siggnal
; /* ignore */
3555 #if !defined(FASTSIM)
3556 unsigned int pipeline_count
= 1;
3560 if (STATE_MEMORY (sd
) == NULL
) {
3561 printf("DBG: simulate() entered with no memory\n");
3566 #if 0 /* Disabled to check that everything works OK */
3567 /* The VR4300 seems to sign-extend the PC on its first
3568 access. However, this may just be because it is currently
3569 configured in 32bit mode. However... */
3570 PC
= SIGNEXTEND(PC
,32);
3573 /* main controlling loop */
3575 /* Fetch the next instruction from the simulator memory: */
3576 uword64 vaddr
= (uword64
)PC
;
3579 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
3583 printf("DBG: state = 0x%08X :",state
);
3585 if (state
& simSTOP
) printf(" simSTOP");
3586 if (state
& simSTEP
) printf(" simSTEP");
3588 if (state
& simHALTEX
) printf(" simHALTEX");
3589 if (state
& simHALTIN
) printf(" simHALTIN");
3591 if (state
& simBE
) printf(" simBE");
3597 DSSTATE
= (STATE
& simDELAYSLOT
);
3600 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
3603 if (AddressTranslation(PC
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
3604 if ((vaddr
& 1) == 0) {
3605 /* Copy the action of the LW instruction */
3606 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
3607 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
3610 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
3611 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3612 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
3613 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3615 /* Copy the action of the LH instruction */
3616 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
3617 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
3620 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
3621 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
3622 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
3623 paddr
& ~ (uword64
) 1,
3624 vaddr
, isINSTRUCTION
, isREAL
);
3625 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
3626 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
3629 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
3634 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
3637 IPC
= PC
; /* copy PC for this instruction */
3638 /* This is required by exception processing, to ensure that we can
3639 cope with exceptions in the delay slots of branches that may
3640 already have changed the PC. */
3641 if ((vaddr
& 1) == 0)
3642 PC
+= 4; /* increment ready for the next fetch */
3645 /* NOTE: If we perform a delay slot change to the PC, this
3646 increment is not requuired. However, it would make the
3647 simulator more complicated to try and avoid this small hit. */
3649 /* Currently this code provides a simple model. For more
3650 complicated models we could perform exception status checks at
3651 this point, and set the simSTOP state as required. This could
3652 also include processing any hardware interrupts raised by any
3653 I/O model attached to the simulator context.
3655 Support for "asynchronous" I/O events within the simulated world
3656 could be providing by managing a counter, and calling a I/O
3657 specific handler when a particular threshold is reached. On most
3658 architectures a decrement and check for zero operation is
3659 usually quicker than an increment and compare. However, the
3660 process of managing a known value decrement to zero, is higher
3661 than the cost of using an explicit value UINT_MAX into the
3662 future. Which system is used will depend on how complicated the
3663 I/O model is, and how much it is likely to affect the simulator
3666 If events need to be scheduled further in the future than
3667 UINT_MAX event ticks, then the I/O model should just provide its
3668 own counter, triggered from the event system. */
3670 /* MIPS pipeline ticks. To allow for future support where the
3671 pipeline hit of individual instructions is known, this control
3672 loop manages a "pipeline_count" variable. It is initialised to
3673 1 (one), and will only be changed by the simulator engine when
3674 executing an instruction. If the engine does not have access to
3675 pipeline cycle count information then all instructions will be
3676 treated as using a single cycle. NOTE: A standard system is not
3677 provided by the default simulator because different MIPS
3678 architectures have different cycle counts for the same
3681 [NOTE: pipeline_count has been replaced the event queue] */
3684 /* Set previous flag, depending on current: */
3685 if (STATE
& simPCOC0
)
3689 /* and update the current value: */
3696 /* NOTE: For multi-context simulation environments the "instruction"
3697 variable should be local to this routine. */
3699 /* Shorthand accesses for engine. Note: If we wanted to use global
3700 variables (and a single-threaded simulator engine), then we can
3701 create the actual variables with these names. */
3703 if (!(STATE
& simSKIPNEXT
)) {
3704 /* Include the simulator engine */
3705 #include "oengine.c"
3706 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3707 #error "Mismatch between run-time simulator code and simulation engine"
3709 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3710 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3712 #if (WITH_FLOATING_POINT == HARD_FLOATING_POINT != defined (HASFPU))
3713 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3716 #if defined(WARN_LOHI)
3717 /* Decrement the HI/LO validity ticks */
3726 #endif /* WARN_LOHI */
3728 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3729 should check for it being changed. It is better doing it here,
3730 than within the simulator, since it will help keep the simulator
3733 #if defined(WARN_ZERO)
3734 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(IPC
));
3735 #endif /* WARN_ZERO */
3736 ZERO
= 0; /* reset back to zero before next instruction */
3738 } else /* simSKIPNEXT check */
3739 STATE
&= ~simSKIPNEXT
;
3741 /* If the delay slot was active before the instruction is
3742 executed, then update the PC to its new value: */
3745 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
3751 if (MIPSISA
< 4) { /* The following is only required on pre MIPS IV processors: */
3752 /* Deal with pending register updates: */
3754 printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in
,pending_out
,pending_total
);
3756 if (PENDING_OUT
!= PENDING_IN
) {
3758 int index
= PENDING_OUT
;
3759 int total
= PENDING_TOTAL
;
3760 if (PENDING_TOTAL
== 0) {
3761 fprintf(stderr
,"FATAL: Mis-match on pending update pointers\n");
3764 for (loop
= 0; (loop
< total
); loop
++) {
3766 printf("DBG: BEFORE index = %d, loop = %d\n",index
,loop
);
3768 if (PENDING_SLOT_REG
[index
] != (LAST_EMBED_REGNUM
+ 1)) {
3770 printf("pending_slot_count[%d] = %d\n",index
,PENDING_SLOT_COUNT
[index
]);
3772 if (--(PENDING_SLOT_COUNT
[index
]) == 0) {
3774 printf("pending_slot_reg[%d] = %d\n",index
,PENDING_SLOT_REG
[index
]);
3775 printf("pending_slot_value[%d] = 0x%s\n",index
,pr_addr(PENDING_SLOT_VALUE
[index
]));
3777 if (PENDING_SLOT_REG
[index
] == COCIDX
) {
3779 SETFCC(0,((FCR31
& (1 << 23)) ? 1 : 0));
3784 REGISTERS
[PENDING_SLOT_REG
[index
]] = PENDING_SLOT_VALUE
[index
];
3786 /* The only time we have PENDING updates to FPU
3787 registers, is when performing binary transfers. This
3788 means we should update the register type field. */
3789 if ((PENDING_SLOT_REG
[index
] >= FGRIDX
) && (PENDING_SLOT_REG
[index
] < (FGRIDX
+ 32)))
3790 FPR_STATE
[PENDING_SLOT_REG
[index
] - FGRIDX
] = fmt_uninterpreted
;
3794 printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG
[index
],pr_addr(REGISTERS
[PENDING_SLOT_REG
[index
]]));
3796 PENDING_SLOT_REG
[index
] = (LAST_EMBED_REGNUM
+ 1);
3798 if (PENDING_OUT
== PSLOTS
)
3804 printf("DBG: AFTER index = %d, loop = %d\n",index
,loop
);
3807 if (index
== PSLOTS
)
3812 printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN
,PENDING_OUT
,PENDING_TOTAL
);
3816 #if !defined(FASTSIM)
3817 if (sim_events_tickn (sd
, pipeline_count
))
3819 /* cpu->cia = cia; */
3820 sim_events_process (sd
);
3823 if (sim_events_tick (sd
))
3825 /* cpu->cia = cia; */
3826 sim_events_process (sd
);
3828 #endif /* FASTSIM */
3832 /* This code copied from gdb's utils.c. Would like to share this code,
3833 but don't know of a common place where both could get to it. */
3835 /* Temporary storage using circular buffer */
3841 static char buf
[NUMCELLS
][CELLSIZE
];
3843 if (++cell
>=NUMCELLS
) cell
=0;
3847 /* Print routines to handle variable size regs, etc */
3849 /* Eliminate warning from compiler on 32-bit systems */
3850 static int thirty_two
= 32;
3856 char *paddr_str
=get_cell();
3857 switch (sizeof(addr
))
3860 sprintf(paddr_str
,"%08lx%08lx",
3861 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3864 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3867 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3870 sprintf(paddr_str
,"%x",addr
);
3879 char *paddr_str
=get_cell();
3880 sprintf(paddr_str
,"%08lx%08lx",
3881 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3886 /*---------------------------------------------------------------------------*/
3887 /*> EOF interp.c <*/