2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
21 The IDT monitor (found on the VR4300 board), seems to lie about
22 register contents. It seems to treat the registers as sign-extended
23 32-bit values. This cause *REAL* problems when single-stepping 64-bit
28 /* The TRACE manifests enable the provision of extra features. If they
29 are not defined then a simpler (quicker) simulator is constructed
30 without the required run-time checks, etc. */
31 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
37 #include "sim-utils.h"
38 #include "sim-options.h"
39 #include "sim-assert.h"
65 #include "libiberty.h"
67 #include "callback.h" /* GDB simulator callback interface */
68 #include "remote-sim.h" /* GDB simulator interface */
76 char* pr_addr
PARAMS ((SIM_ADDR addr
));
77 char* pr_uword64
PARAMS ((uword64 addr
));
80 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
85 /* The following reserved instruction value is used when a simulator
86 trap is required. NOTE: Care must be taken, since this value may be
87 used in later revisions of the MIPS ISA. */
89 #define RSVD_INSTRUCTION (0x00000005)
90 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
92 #define RSVD_INSTRUCTION_ARG_SHIFT 6
93 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
96 /* Bits in the Debug register */
97 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
98 #define Debug_DM 0x40000000 /* Debug Mode */
99 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
101 /*---------------------------------------------------------------------------*/
102 /*-- GDB simulator interface ------------------------------------------------*/
103 /*---------------------------------------------------------------------------*/
105 static void ColdReset
PARAMS((SIM_DESC sd
));
107 /*---------------------------------------------------------------------------*/
111 #define DELAYSLOT() {\
112 if (STATE & simDELAYSLOT)\
113 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
114 STATE |= simDELAYSLOT;\
117 #define JALDELAYSLOT() {\
119 STATE |= simJALDELAYSLOT;\
123 STATE &= ~simDELAYSLOT;\
124 STATE |= simSKIPNEXT;\
127 #define CANCELDELAYSLOT() {\
129 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
132 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
133 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
135 /* Note that the monitor code essentially assumes this layout of memory.
136 If you change these, change the monitor code, too. */
137 #define K0BASE (0x80000000)
138 #define K0SIZE (0x20000000)
139 #define K1BASE (0xA0000000)
140 #define K1SIZE (0x20000000)
142 /* Simple run-time monitor support.
144 We emulate the monitor by placing magic reserved instructions at
145 the monitor's entry points; when we hit these instructions, instead
146 of raising an exception (as we would normally), we look at the
147 instruction and perform the appropriate monitory operation.
149 `*_monitor_base' are the physical addresses at which the corresponding
150 monitor vectors are located. `0' means none. By default,
152 The RSVD_INSTRUCTION... macros specify the magic instructions we
153 use at the monitor entry points. */
154 static int firmware_option_p
= 0;
155 static SIM_ADDR idt_monitor_base
= 0xBFC00000;
156 static SIM_ADDR pmon_monitor_base
= 0xBFC00500;
157 static SIM_ADDR lsipmon_monitor_base
= 0xBFC00200;
159 static SIM_RC
sim_firmware_command (SIM_DESC sd
, char* arg
);
162 #define MEM_SIZE (2 << 20)
166 static char *tracefile
= "trace.din"; /* default filename for trace log */
167 FILE *tracefh
= NULL
;
168 static void open_trace
PARAMS((SIM_DESC sd
));
171 static const char * get_insn_name (sim_cpu
*, int);
173 /* simulation target board. NULL=canonical */
174 static char* board
= NULL
;
177 static DECLARE_OPTION_HANDLER (mips_option_handler
);
180 OPTION_DINERO_TRACE
= OPTION_START
,
188 mips_option_handler (sd
, cpu
, opt
, arg
, is_command
)
198 case OPTION_DINERO_TRACE
: /* ??? */
200 /* Eventually the simTRACE flag could be treated as a toggle, to
201 allow external control of the program points being traced
202 (i.e. only from main onwards, excluding the run-time setup,
204 for (cpu_nr
= 0; cpu_nr
< MAX_NR_PROCESSORS
; cpu_nr
++)
206 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
209 else if (strcmp (arg
, "yes") == 0)
211 else if (strcmp (arg
, "no") == 0)
213 else if (strcmp (arg
, "on") == 0)
215 else if (strcmp (arg
, "off") == 0)
219 fprintf (stderr
, "Unrecognized dinero-trace option `%s'\n", arg
);
226 Simulator constructed without dinero tracing support (for performance).\n\
227 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
231 case OPTION_DINERO_FILE
:
233 if (optarg
!= NULL
) {
235 tmp
= (char *)malloc(strlen(optarg
) + 1);
238 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
244 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
250 case OPTION_FIRMWARE
:
251 return sim_firmware_command (sd
, arg
);
257 board
= zalloc(strlen(arg
) + 1);
268 static const OPTION mips_options
[] =
270 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
271 '\0', "on|off", "Enable dinero tracing",
272 mips_option_handler
},
273 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
274 '\0', "FILE", "Write dinero trace to FILE",
275 mips_option_handler
},
276 { {"firmware", required_argument
, NULL
, OPTION_FIRMWARE
},
277 '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
278 mips_option_handler
},
279 { {"board", required_argument
, NULL
, OPTION_BOARD
},
280 '\0', "none" /* rely on compile-time string concatenation for other options */
282 #define BOARD_JMR3904 "jmr3904"
284 #define BOARD_JMR3904_PAL "jmr3904pal"
285 "|" BOARD_JMR3904_PAL
286 #define BOARD_JMR3904_DEBUG "jmr3904debug"
287 "|" BOARD_JMR3904_DEBUG
288 #define BOARD_BSP "bsp"
291 , "Customize simulation for a particular board.", mips_option_handler
},
293 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
297 int interrupt_pending
;
300 interrupt_event (SIM_DESC sd
, void *data
)
302 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
303 address_word cia
= CIA_GET (cpu
);
306 interrupt_pending
= 0;
307 SignalExceptionInterrupt (1); /* interrupt "1" */
309 else if (!interrupt_pending
)
310 sim_events_schedule (sd
, 1, interrupt_event
, data
);
314 /*---------------------------------------------------------------------------*/
315 /*-- Device registration hook -----------------------------------------------*/
316 /*---------------------------------------------------------------------------*/
317 static void device_init(SIM_DESC sd
) {
319 extern void register_devices(SIM_DESC
);
320 register_devices(sd
);
324 /*---------------------------------------------------------------------------*/
325 /*-- GDB simulator interface ------------------------------------------------*/
326 /*---------------------------------------------------------------------------*/
329 sim_open (kind
, cb
, abfd
, argv
)
335 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
336 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
338 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
340 /* FIXME: watchpoints code shouldn't need this */
341 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
342 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
343 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
345 /* Initialize the mechanism for doing insn profiling. */
346 CPU_INSN_NAME (cpu
) = get_insn_name
;
347 CPU_MAX_INSNS (cpu
) = nr_itable_entries
;
351 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
353 sim_add_option_table (sd
, NULL
, mips_options
);
356 /* getopt will print the error message so we just have to exit if this fails.
357 FIXME: Hmmm... in the case of gdb we need getopt to call
359 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
361 /* Uninstall the modules to avoid memory leaks,
362 file descriptor leaks, etc. */
363 sim_module_uninstall (sd
);
367 /* handle board-specific memory maps */
370 /* Allocate core managed memory */
373 /* For compatibility with the old code - under this (at level one)
374 are the kernel spaces K0 & K1. Both of these map to a single
375 smaller sub region */
376 sim_do_command(sd
," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
377 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
379 MEM_SIZE
, /* actual size */
384 else if (board
!= NULL
385 && (strcmp(board
, BOARD_BSP
) == 0))
389 STATE_ENVIRONMENT (sd
) = OPERATING_ENVIRONMENT
;
391 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
392 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
394 4 * 1024 * 1024, /* 4 MB */
397 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
398 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
400 4 * 1024 * 1024, /* 4 MB */
403 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
404 for (i
=0; i
<8; i
++) /* 32 MB total */
406 unsigned size
= 4 * 1024 * 1024; /* 4 MB */
407 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
408 0x88000000 + (i
* size
),
410 0xA8000000 + (i
* size
));
414 else if (board
!= NULL
415 && (strcmp(board
, BOARD_JMR3904
) == 0 ||
416 strcmp(board
, BOARD_JMR3904_PAL
) == 0 ||
417 strcmp(board
, BOARD_JMR3904_DEBUG
) == 0))
419 /* match VIRTUAL memory layout of JMR-TX3904 board */
422 /* --- disable monitor unless forced on by user --- */
424 if (! firmware_option_p
)
426 idt_monitor_base
= 0;
427 pmon_monitor_base
= 0;
428 lsipmon_monitor_base
= 0;
431 /* --- environment --- */
433 STATE_ENVIRONMENT (sd
) = OPERATING_ENVIRONMENT
;
437 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
438 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
440 4 * 1024 * 1024, /* 4 MB */
443 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
444 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
446 4 * 1024 * 1024, /* 4 MB */
449 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
450 for (i
=0; i
<8; i
++) /* 32 MB total */
452 unsigned size
= 4 * 1024 * 1024; /* 4 MB */
453 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
454 0x88000000 + (i
* size
),
456 0xA8000000 + (i
* size
));
459 /* Dummy memory regions for unsimulated devices */
461 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
462 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
463 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
464 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x804); /* DRAMC */
465 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
466 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
467 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
468 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
470 /* --- simulated devices --- */
471 sim_hw_parse (sd
, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
472 sim_hw_parse (sd
, "/tx3904cpu");
473 sim_hw_parse (sd
, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
474 sim_hw_parse (sd
, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
475 sim_hw_parse (sd
, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
476 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
478 /* FIXME: poking at dv-sockser internals, use tcp backend if
479 --sockser_addr option was given.*/
480 extern char* sockser_addr
;
481 if(sockser_addr
== NULL
)
482 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/backend stdio");
484 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/backend tcp");
486 sim_hw_parse (sd
, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
487 sim_hw_parse (sd
, "/tx3904sio@0xfffff400/backend stdio");
489 /* -- device connections --- */
490 sim_hw_parse (sd
, "/tx3904irc > ip level /tx3904cpu");
491 sim_hw_parse (sd
, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
492 sim_hw_parse (sd
, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
493 sim_hw_parse (sd
, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
494 sim_hw_parse (sd
, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
495 sim_hw_parse (sd
, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
497 /* add PAL timer & I/O module */
498 if(! strcmp(board
, BOARD_JMR3904_PAL
))
501 sim_hw_parse (sd
, "/pal@0xffff0000");
502 sim_hw_parse (sd
, "/pal@0xffff0000/reg 0xffff0000 64");
504 /* wire up interrupt ports to irc */
505 sim_hw_parse (sd
, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
506 sim_hw_parse (sd
, "/pal@0x31000000 > timer tmr1 /tx3904irc");
507 sim_hw_parse (sd
, "/pal@0x31000000 > int int0 /tx3904irc");
510 if(! strcmp(board
, BOARD_JMR3904_DEBUG
))
512 /* -- DEBUG: glue interrupt generators --- */
513 sim_hw_parse (sd
, "/glue@0xffff0000/reg 0xffff0000 0x50");
514 sim_hw_parse (sd
, "/glue@0xffff0000 > int0 int0 /tx3904irc");
515 sim_hw_parse (sd
, "/glue@0xffff0000 > int1 int1 /tx3904irc");
516 sim_hw_parse (sd
, "/glue@0xffff0000 > int2 int2 /tx3904irc");
517 sim_hw_parse (sd
, "/glue@0xffff0000 > int3 int3 /tx3904irc");
518 sim_hw_parse (sd
, "/glue@0xffff0000 > int4 int4 /tx3904irc");
519 sim_hw_parse (sd
, "/glue@0xffff0000 > int5 int5 /tx3904irc");
520 sim_hw_parse (sd
, "/glue@0xffff0000 > int6 int6 /tx3904irc");
521 sim_hw_parse (sd
, "/glue@0xffff0000 > int7 int7 /tx3904irc");
522 sim_hw_parse (sd
, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
523 sim_hw_parse (sd
, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
524 sim_hw_parse (sd
, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
525 sim_hw_parse (sd
, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
526 sim_hw_parse (sd
, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
527 sim_hw_parse (sd
, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
528 sim_hw_parse (sd
, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
529 sim_hw_parse (sd
, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
530 sim_hw_parse (sd
, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
531 sim_hw_parse (sd
, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
539 /* check for/establish the a reference program image */
540 if (sim_analyze_program (sd
,
541 (STATE_PROG_ARGV (sd
) != NULL
542 ? *STATE_PROG_ARGV (sd
)
546 sim_module_uninstall (sd
);
550 /* Configure/verify the target byte order and other runtime
551 configuration options */
552 if (sim_config (sd
) != SIM_RC_OK
)
554 sim_module_uninstall (sd
);
558 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
560 /* Uninstall the modules to avoid memory leaks,
561 file descriptor leaks, etc. */
562 sim_module_uninstall (sd
);
566 /* verify assumptions the simulator made about the host type system.
567 This macro does not return if there is a problem */
568 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
569 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
571 /* This is NASTY, in that we are assuming the size of specific
575 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++)
578 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
579 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ NR_FGR
)))
580 cpu
->register_widths
[rn
] = WITH_TARGET_FLOATING_POINT_BITSIZE
;
581 else if ((rn
>= 33) && (rn
<= 37))
582 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
583 else if ((rn
== SRIDX
)
586 || ((rn
>= 72) && (rn
<= 89)))
587 cpu
->register_widths
[rn
] = 32;
589 cpu
->register_widths
[rn
] = 0;
596 if (STATE
& simTRACE
)
601 sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
604 lsipmon_monitor_base);
607 /* Write the monitor trap address handlers into the monitor (eeprom)
608 address space. This can only be done once the target endianness
609 has been determined. */
610 if (idt_monitor_base
!= 0)
613 unsigned idt_monitor_size
= 1 << 11;
615 /* the default monitor region */
616 sim_do_commandf (sd
, "memory region 0x%x,0x%x",
617 idt_monitor_base
, idt_monitor_size
);
619 /* Entry into the IDT monitor is via fixed address vectors, and
620 not using machine instructions. To avoid clashing with use of
621 the MIPS TRAP system, we place our own (simulator specific)
622 "undefined" instructions into the relevant vector slots. */
623 for (loop
= 0; (loop
< idt_monitor_size
); loop
+= 4)
625 address_word vaddr
= (idt_monitor_base
+ loop
);
626 unsigned32 insn
= (RSVD_INSTRUCTION
|
627 (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
)
628 << RSVD_INSTRUCTION_ARG_SHIFT
));
630 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
634 if ((pmon_monitor_base
!= 0) || (lsipmon_monitor_base
!= 0))
636 /* The PMON monitor uses the same address space, but rather than
637 branching into it the address of a routine is loaded. We can
638 cheat for the moment, and direct the PMON routine to IDT style
639 instructions within the monitor space. This relies on the IDT
640 monitor not using the locations from 0xBFC00500 onwards as its
643 for (loop
= 0; (loop
< 24); loop
++)
645 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
661 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
663 case 8: /* cliexit */
666 case 11: /* flush_cache */
671 SIM_ASSERT (idt_monitor_base
!= 0);
672 value
= ((unsigned int) idt_monitor_base
+ (value
* 8));
675 if (pmon_monitor_base
!= 0)
677 address_word vaddr
= (pmon_monitor_base
+ (loop
* 4));
678 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
681 if (lsipmon_monitor_base
!= 0)
683 address_word vaddr
= (lsipmon_monitor_base
+ (loop
* 4));
684 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
688 /* Write an abort sequence into the TRAP (common) exception vector
689 addresses. This is to catch code executing a TRAP (et.al.)
690 instruction without installing a trap handler. */
691 if ((idt_monitor_base
!= 0) ||
692 (pmon_monitor_base
!= 0) ||
693 (lsipmon_monitor_base
!= 0))
695 unsigned32 halt
[2] = { 0x2404002f /* addiu r4, r0, 47 */,
696 HALT_INSTRUCTION
/* BREAK */ };
699 sim_write (sd
, 0x80000000, (char *) halt
, sizeof (halt
));
700 sim_write (sd
, 0x80000180, (char *) halt
, sizeof (halt
));
701 sim_write (sd
, 0x80000200, (char *) halt
, sizeof (halt
));
702 /* XXX: Write here unconditionally? */
703 sim_write (sd
, 0xBFC00200, (char *) halt
, sizeof (halt
));
704 sim_write (sd
, 0xBFC00380, (char *) halt
, sizeof (halt
));
705 sim_write (sd
, 0xBFC00400, (char *) halt
, sizeof (halt
));
719 tracefh
= fopen(tracefile
,"wb+");
722 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
728 /* Return name of an insn, used by insn profiling. */
730 get_insn_name (sim_cpu
*cpu
, int i
)
732 return itable
[i
].name
;
736 sim_close (sd
, quitting
)
741 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
745 /* "quitting" is non-zero if we cannot hang on errors */
747 /* shut down modules */
748 sim_module_uninstall (sd
);
750 /* Ensure that any resources allocated through the callback
751 mechanism are released: */
752 sim_io_shutdown (sd
);
755 if (tracefh
!= NULL
&& tracefh
!= stderr
)
760 /* FIXME - free SD */
767 sim_write (sd
,addr
,buffer
,size
)
770 unsigned char *buffer
;
774 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
776 /* Return the number of bytes written, or zero if error. */
778 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
781 /* We use raw read and write routines, since we do not want to count
782 the GDB memory accesses in our statistics gathering. */
784 for (index
= 0; index
< size
; index
++)
786 address_word vaddr
= (address_word
)addr
+ index
;
789 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
791 if (sim_core_write_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
799 sim_read (sd
,addr
,buffer
,size
)
802 unsigned char *buffer
;
806 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
808 /* Return the number of bytes read, or zero if error. */
810 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
813 for (index
= 0; (index
< size
); index
++)
815 address_word vaddr
= (address_word
)addr
+ index
;
818 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
820 if (sim_core_read_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
828 sim_store_register (sd
,rn
,memory
,length
)
831 unsigned char *memory
;
834 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
835 /* NOTE: gdb (the client) stores registers in target byte order
836 while the simulator uses host byte order */
838 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
841 /* Unfortunately this suffers from the same problem as the register
842 numbering one. We need to know what the width of each logical
843 register number is for the architecture being simulated. */
845 if (cpu
->register_widths
[rn
] == 0)
847 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
853 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
855 cpu
->fpr_state
[rn
- FGRIDX
] = fmt_uninterpreted
;
856 if (cpu
->register_widths
[rn
] == 32)
860 cpu
->fgr
[rn
- FGRIDX
] =
861 (unsigned32
) T2H_8 (*(unsigned64
*)memory
);
866 cpu
->fgr
[rn
- FGRIDX
] = T2H_4 (*(unsigned32
*)memory
);
872 cpu
->fgr
[rn
- FGRIDX
] = T2H_8 (*(unsigned64
*)memory
);
877 if (cpu
->register_widths
[rn
] == 32)
882 (unsigned32
) T2H_8 (*(unsigned64
*)memory
);
887 cpu
->registers
[rn
] = T2H_4 (*(unsigned32
*)memory
);
893 cpu
->registers
[rn
] = T2H_8 (*(unsigned64
*)memory
);
901 sim_fetch_register (sd
,rn
,memory
,length
)
904 unsigned char *memory
;
907 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
908 /* NOTE: gdb (the client) stores registers in target byte order
909 while the simulator uses host byte order */
911 #if 0 /* FIXME: doesn't compile */
912 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
916 if (cpu
->register_widths
[rn
] == 0)
918 sim_io_eprintf (sd
, "Invalid register width for %d (register fetch ignored)\n",rn
);
924 /* Any floating point register */
925 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
927 if (cpu
->register_widths
[rn
] == 32)
931 *(unsigned64
*)memory
=
932 H2T_8 ((unsigned32
) (cpu
->fgr
[rn
- FGRIDX
]));
937 *(unsigned32
*)memory
= H2T_4 (cpu
->fgr
[rn
- FGRIDX
]);
943 *(unsigned64
*)memory
= H2T_8 (cpu
->fgr
[rn
- FGRIDX
]);
948 if (cpu
->register_widths
[rn
] == 32)
952 *(unsigned64
*)memory
=
953 H2T_8 ((unsigned32
) (cpu
->registers
[rn
]));
958 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
964 *(unsigned64
*)memory
= H2T_8 ((unsigned64
)(cpu
->registers
[rn
]));
973 sim_create_inferior (sd
, abfd
, argv
,env
)
981 #if 0 /* FIXME: doesn't compile */
982 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
991 /* override PC value set by ColdReset () */
993 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
995 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
996 CIA_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
1000 #if 0 /* def DEBUG */
1003 /* We should really place the argv slot values into the argument
1004 registers, and onto the stack as required. However, this
1005 assumes that we have a stack defined, which is not
1006 necessarily true at the moment. */
1008 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
1009 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
1010 printf("DBG: arg \"%s\"\n",*cptr
);
1018 sim_do_command (sd
,cmd
)
1022 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
1023 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
1027 /*---------------------------------------------------------------------------*/
1028 /*-- Private simulator support interface ------------------------------------*/
1029 /*---------------------------------------------------------------------------*/
1031 /* Read a null terminated string from memory, return in a buffer */
1033 fetch_str (SIM_DESC sd
,
1039 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
1041 buf
= NZALLOC (char, nr
+ 1);
1042 sim_read (sd
, addr
, buf
, nr
);
1047 /* Implements the "sim firmware" command:
1048 sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
1049 NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
1050 defaults to the normal address for that monitor.
1051 sim firmware none --- don't emulate any ROM monitor. Useful
1052 if you need a clean address space. */
1054 sim_firmware_command (SIM_DESC sd
, char *arg
)
1056 int address_present
= 0;
1059 /* Signal occurrence of this option. */
1060 firmware_option_p
= 1;
1062 /* Parse out the address, if present. */
1064 char *p
= strchr (arg
, '@');
1068 address_present
= 1;
1069 p
++; /* skip over @ */
1071 address
= strtoul (p
, &q
, 0);
1074 sim_io_printf (sd
, "Invalid address given to the"
1075 "`sim firmware NAME@ADDRESS' command: %s\n",
1081 address_present
= 0;
1084 if (! strncmp (arg
, "idt", 3))
1086 idt_monitor_base
= address_present
? address
: 0xBFC00000;
1087 pmon_monitor_base
= 0;
1088 lsipmon_monitor_base
= 0;
1090 else if (! strncmp (arg
, "pmon", 4))
1092 /* pmon uses indirect calls. Hook into implied idt. */
1093 pmon_monitor_base
= address_present
? address
: 0xBFC00500;
1094 idt_monitor_base
= pmon_monitor_base
- 0x500;
1095 lsipmon_monitor_base
= 0;
1097 else if (! strncmp (arg
, "lsipmon", 7))
1099 /* lsipmon uses indirect calls. Hook into implied idt. */
1100 pmon_monitor_base
= 0;
1101 lsipmon_monitor_base
= address_present
? address
: 0xBFC00200;
1102 idt_monitor_base
= lsipmon_monitor_base
- 0x200;
1104 else if (! strncmp (arg
, "none", 4))
1106 if (address_present
)
1109 "The `sim firmware none' command does "
1110 "not take an `ADDRESS' argument.\n");
1113 idt_monitor_base
= 0;
1114 pmon_monitor_base
= 0;
1115 lsipmon_monitor_base
= 0;
1119 sim_io_printf (sd
, "\
1120 Unrecognized name given to the `sim firmware NAME' command: %s\n\
1121 Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
1131 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1133 sim_monitor (SIM_DESC sd
,
1136 unsigned int reason
)
1139 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
1142 /* The IDT monitor actually allows two instructions per vector
1143 slot. However, the simulator currently causes a trap on each
1144 individual instruction. We cheat, and lose the bottom bit. */
1147 /* The following callback functions are available, however the
1148 monitor we are simulating does not make use of them: get_errno,
1149 isatty, lseek, rename, system, time and unlink */
1153 case 6: /* int open(char *path,int flags) */
1155 char *path
= fetch_str (sd
, A0
);
1156 V0
= sim_io_open (sd
, path
, (int)A1
);
1161 case 7: /* int read(int file,char *ptr,int len) */
1165 char *buf
= zalloc (nr
);
1166 V0
= sim_io_read (sd
, fd
, buf
, nr
);
1167 sim_write (sd
, A1
, buf
, nr
);
1172 case 8: /* int write(int file,char *ptr,int len) */
1176 char *buf
= zalloc (nr
);
1177 sim_read (sd
, A1
, buf
, nr
);
1178 V0
= sim_io_write (sd
, fd
, buf
, nr
);
1183 case 10: /* int close(int file) */
1185 V0
= sim_io_close (sd
, (int)A0
);
1189 case 2: /* Densan monitor: char inbyte(int waitflag) */
1191 if (A0
== 0) /* waitflag == NOWAIT */
1192 V0
= (unsigned_word
)-1;
1194 /* Drop through to case 11 */
1196 case 11: /* char inbyte(void) */
1199 /* ensure that all output has gone... */
1200 sim_io_flush_stdout (sd
);
1201 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
1203 sim_io_error(sd
,"Invalid return from character read");
1204 V0
= (unsigned_word
)-1;
1207 V0
= (unsigned_word
)tmp
;
1211 case 3: /* Densan monitor: void co(char chr) */
1212 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1214 char tmp
= (char)(A0
& 0xFF);
1215 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
1219 case 17: /* void _exit() */
1221 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
1222 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
1223 (unsigned int)(A0
& 0xFFFFFFFF));
1227 case 28 : /* PMON flush_cache */
1230 case 55: /* void get_mem_info(unsigned int *ptr) */
1231 /* in: A0 = pointer to three word memory location */
1232 /* out: [A0 + 0] = size */
1233 /* [A0 + 4] = instruction cache size */
1234 /* [A0 + 8] = data cache size */
1236 unsigned_4 value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
1237 unsigned_4 zero
= 0;
1239 sim_write (sd
, A0
+ 0, (char *)&value
, 4);
1240 sim_write (sd
, A0
+ 4, (char *)&zero
, 4);
1241 sim_write (sd
, A0
+ 8, (char *)&zero
, 4);
1242 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1246 case 158 : /* PMON printf */
1247 /* in: A0 = pointer to format string */
1248 /* A1 = optional argument 1 */
1249 /* A2 = optional argument 2 */
1250 /* A3 = optional argument 3 */
1252 /* The following is based on the PMON printf source */
1254 address_word s
= A0
;
1256 signed_word
*ap
= &A1
; /* 1st argument */
1257 /* This isn't the quickest way, since we call the host print
1258 routine for every character almost. But it does avoid
1259 having to allocate and manage a temporary string buffer. */
1260 /* TODO: Include check that we only use three arguments (A1,
1262 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1267 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1268 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1269 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1271 if (strchr ("dobxXulscefg%", c
))
1286 else if (c
>= '1' && c
<= '9')
1290 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
1293 n
= (unsigned int)strtol(tmp
,NULL
,10);
1306 sim_io_printf (sd
, "%%");
1311 address_word p
= *ap
++;
1313 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
1314 sim_io_printf(sd
, "%c", ch
);
1317 sim_io_printf(sd
,"(null)");
1320 sim_io_printf (sd
, "%c", (int)*ap
++);
1325 sim_read (sd
, s
++, &c
, 1);
1329 sim_read (sd
, s
++, &c
, 1);
1332 if (strchr ("dobxXu", c
))
1334 word64 lv
= (word64
) *ap
++;
1336 sim_io_printf(sd
,"<binary not supported>");
1339 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
1341 sim_io_printf(sd
, tmp
, lv
);
1343 sim_io_printf(sd
, tmp
, (int)lv
);
1346 else if (strchr ("eEfgG", c
))
1348 double dbl
= *(double*)(ap
++);
1349 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
1350 sim_io_printf (sd
, tmp
, dbl
);
1356 sim_io_printf(sd
, "%c", c
);
1362 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1363 reason
, pr_addr(cia
));
1369 /* Store a word into memory. */
1372 store_word (SIM_DESC sd
,
1381 if ((vaddr
& 3) != 0)
1382 SignalExceptionAddressStore ();
1385 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1388 const uword64 mask
= 7;
1392 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1393 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1394 memval
= ((uword64
) val
) << (8 * byte
);
1395 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1401 /* Load a word from memory. */
1404 load_word (SIM_DESC sd
,
1409 if ((vaddr
& 3) != 0)
1411 SIM_CORE_SIGNAL (SD
, cpu
, cia
, read_map
, AccessLength_WORD
+1, vaddr
, read_transfer
, sim_core_unaligned_signal
);
1418 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1421 const uword64 mask
= 0x7;
1422 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1423 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1427 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1428 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1430 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1431 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1438 /* Simulate the mips16 entry and exit pseudo-instructions. These
1439 would normally be handled by the reserved instruction exception
1440 code, but for ease of simulation we just handle them directly. */
1443 mips16_entry (SIM_DESC sd
,
1448 int aregs
, sregs
, rreg
;
1451 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1454 aregs
= (insn
& 0x700) >> 8;
1455 sregs
= (insn
& 0x0c0) >> 6;
1456 rreg
= (insn
& 0x020) >> 5;
1458 /* This should be checked by the caller. */
1467 /* This is the entry pseudo-instruction. */
1469 for (i
= 0; i
< aregs
; i
++)
1470 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1478 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1481 for (i
= 0; i
< sregs
; i
++)
1484 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1492 /* This is the exit pseudo-instruction. */
1499 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1502 for (i
= 0; i
< sregs
; i
++)
1505 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1510 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1514 FGR
[0] = WORD64LO (GPR
[4]);
1515 FPR_STATE
[0] = fmt_uninterpreted
;
1517 else if (aregs
== 6)
1519 FGR
[0] = WORD64LO (GPR
[5]);
1520 FGR
[1] = WORD64LO (GPR
[4]);
1521 FPR_STATE
[0] = fmt_uninterpreted
;
1522 FPR_STATE
[1] = fmt_uninterpreted
;
1531 /*-- trace support ----------------------------------------------------------*/
1533 /* The TRACE support is provided (if required) in the memory accessing
1534 routines. Since we are also providing the architecture specific
1535 features, the architecture simulation code can also deal with
1536 notifying the TRACE world of cache flushes, etc. Similarly we do
1537 not need to provide profiling support in the simulator engine,
1538 since we can sample in the instruction fetch control loop. By
1539 defining the TRACE manifest, we add tracing as a run-time
1543 /* Tracing by default produces "din" format (as required by
1544 dineroIII). Each line of such a trace file *MUST* have a din label
1545 and address field. The rest of the line is ignored, so comments can
1546 be included if desired. The first field is the label which must be
1547 one of the following values:
1552 3 escape record (treated as unknown access type)
1553 4 escape record (causes cache flush)
1555 The address field is a 32bit (lower-case) hexadecimal address
1556 value. The address should *NOT* be preceded by "0x".
1558 The size of the memory transfer is not important when dealing with
1559 cache lines (as long as no more than a cache line can be
1560 transferred in a single operation :-), however more information
1561 could be given following the dineroIII requirement to allow more
1562 complete memory and cache simulators to provide better
1563 results. i.e. the University of Pisa has a cache simulator that can
1564 also take bus size and speed as (variable) inputs to calculate
1565 complete system performance (a much more useful ability when trying
1566 to construct an end product, rather than a processor). They
1567 currently have an ARM version of their tool called ChARM. */
1571 dotrace (SIM_DESC sd
,
1579 if (STATE
& simTRACE
) {
1581 fprintf(tracefh
,"%d %s ; width %d ; ",
1585 va_start(ap
,comment
);
1586 vfprintf(tracefh
,comment
,ap
);
1588 fprintf(tracefh
,"\n");
1590 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1591 we may be generating 64bit ones, we should put the hi-32bits of the
1592 address into the comment field. */
1594 /* TODO: Provide a buffer for the trace lines. We can then avoid
1595 performing writes until the buffer is filled, or the file is
1598 /* NOTE: We could consider adding a comment field to the "din" file
1599 produced using type 3 markers (unknown access). This would then
1600 allow information about the program that the "din" is for, and
1601 the MIPs world that was being simulated, to be placed into the
1608 /*---------------------------------------------------------------------------*/
1609 /*-- simulator engine -------------------------------------------------------*/
1610 /*---------------------------------------------------------------------------*/
1613 ColdReset (SIM_DESC sd
)
1616 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1618 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1619 /* RESET: Fixed PC address: */
1620 PC
= (unsigned_word
) UNSIGNED64 (0xFFFFFFFFBFC00000);
1621 /* The reset vector address is in the unmapped, uncached memory space. */
1623 SR
&= ~(status_SR
| status_TS
| status_RP
);
1624 SR
|= (status_ERL
| status_BEV
);
1626 /* Cheat and allow access to the complete register set immediately */
1627 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1628 && WITH_TARGET_WORD_BITSIZE
== 64)
1629 SR
|= status_FR
; /* 64bit registers */
1631 /* Ensure that any instructions with pending register updates are
1633 PENDING_INVALIDATE();
1635 /* Initialise the FPU registers to the unknown state */
1636 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1639 for (rn
= 0; (rn
< 32); rn
++)
1640 FPR_STATE
[rn
] = fmt_uninterpreted
;
1649 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1650 /* Signal an exception condition. This will result in an exception
1651 that aborts the instruction. The instruction operation pseudocode
1652 will never see a return from this function call. */
1655 signal_exception (SIM_DESC sd
,
1663 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1666 /* Ensure that any active atomic read/modify/write operation will fail: */
1669 /* Save registers before interrupt dispatching */
1670 #ifdef SIM_CPU_EXCEPTION_TRIGGER
1671 SIM_CPU_EXCEPTION_TRIGGER(sd
, cpu
, cia
);
1674 switch (exception
) {
1676 case DebugBreakPoint
:
1677 if (! (Debug
& Debug_DM
))
1683 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1684 DEPC
= cia
- 4; /* reference the branch instruction */
1688 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1692 Debug
|= Debug_DM
; /* in debugging mode */
1693 Debug
|= Debug_DBp
; /* raising a DBp exception */
1695 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1699 case ReservedInstruction
:
1702 unsigned int instruction
;
1703 va_start(ap
,exception
);
1704 instruction
= va_arg(ap
,unsigned int);
1706 /* Provide simple monitor support using ReservedInstruction
1707 exceptions. The following code simulates the fixed vector
1708 entry points into the IDT monitor by causing a simulator
1709 trap, performing the monitor operation, and returning to
1710 the address held in the $ra register (standard PCS return
1711 address). This means we only need to pre-load the vector
1712 space with suitable instruction values. For systems were
1713 actual trap instructions are used, we would not need to
1714 perform this magic. */
1715 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1717 sim_monitor (SD
, CPU
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1718 /* NOTE: This assumes that a branch-and-link style
1719 instruction was used to enter the vector (which is the
1720 case with the current IDT monitor). */
1721 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1723 /* Look for the mips16 entry and exit instructions, and
1724 simulate a handler for them. */
1725 else if ((cia
& 1) != 0
1726 && (instruction
& 0xf81f) == 0xe809
1727 && (instruction
& 0x0c0) != 0x0c0)
1729 mips16_entry (SD
, CPU
, cia
, instruction
);
1730 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1732 /* else fall through to normal exception processing */
1733 sim_io_eprintf(sd
,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia
));
1737 /* Store exception code into current exception id variable (used
1740 /* TODO: If not simulating exceptions then stop the simulator
1741 execution. At the moment we always stop the simulation. */
1743 #ifdef SUBTARGET_R3900
1744 /* update interrupt-related registers */
1746 /* insert exception code in bits 6:2 */
1747 CAUSE
= LSMASKED32(CAUSE
, 31, 7) | LSINSERTED32(exception
, 6, 2);
1748 /* shift IE/KU history bits left */
1749 SR
= LSMASKED32(SR
, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR
, 3, 0), 5, 2);
1751 if (STATE
& simDELAYSLOT
)
1753 STATE
&= ~simDELAYSLOT
;
1755 EPC
= (cia
- 4); /* reference the branch instruction */
1760 if (SR
& status_BEV
)
1761 PC
= (signed)0xBFC00000 + 0x180;
1763 PC
= (signed)0x80000000 + 0x080;
1765 /* See figure 5-17 for an outline of the code below */
1766 if (! (SR
& status_EXL
))
1768 CAUSE
= (exception
<< 2);
1769 if (STATE
& simDELAYSLOT
)
1771 STATE
&= ~simDELAYSLOT
;
1773 EPC
= (cia
- 4); /* reference the branch instruction */
1777 /* FIXME: TLB et.al. */
1778 /* vector = 0x180; */
1782 CAUSE
= (exception
<< 2);
1783 /* vector = 0x180; */
1786 /* Store exception code into current exception id variable (used
1789 if (SR
& status_BEV
)
1790 PC
= (signed)0xBFC00200 + 0x180;
1792 PC
= (signed)0x80000000 + 0x180;
1795 switch ((CAUSE
>> 2) & 0x1F)
1798 /* Interrupts arrive during event processing, no need to
1804 #ifdef SUBTARGET_3900
1805 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1806 PC
= (signed)0xBFC00000;
1807 #endif SUBTARGET_3900
1810 case TLBModification
:
1815 case InstructionFetch
:
1817 /* The following is so that the simulator will continue from the
1818 exception handler address. */
1819 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1820 sim_stopped
, SIM_SIGBUS
);
1822 case ReservedInstruction
:
1823 case CoProcessorUnusable
:
1825 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1826 sim_stopped
, SIM_SIGILL
);
1828 case IntegerOverflow
:
1830 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1831 sim_stopped
, SIM_SIGFPE
);
1834 sim_engine_halt (SD
, CPU
, NULL
, PC
, sim_stopped
, SIM_SIGTRAP
);
1839 sim_engine_restart (SD
, CPU
, NULL
, PC
);
1844 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1845 sim_stopped
, SIM_SIGTRAP
);
1847 default : /* Unknown internal exception */
1849 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1850 sim_stopped
, SIM_SIGABRT
);
1854 case SimulatorFault
:
1858 va_start(ap
,exception
);
1859 msg
= va_arg(ap
,char *);
1861 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1862 "FATAL: Simulator error \"%s\"\n",msg
);
1871 #if defined(WARN_RESULT)
1872 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1873 /* This function indicates that the result of the operation is
1874 undefined. However, this should not affect the instruction
1875 stream. All that is meant to happen is that the destination
1876 register is set to an undefined result. To keep the simulator
1877 simple, we just don't bother updating the destination register, so
1878 the overall result will be undefined. If desired we can stop the
1879 simulator by raising a pseudo-exception. */
1880 #define UndefinedResult() undefined_result (sd,cia)
1882 undefined_result(sd
,cia
)
1886 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
1887 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1892 #endif /* WARN_RESULT */
1894 /*-- FPU support routines ---------------------------------------------------*/
1896 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1897 formats conform to ANSI/IEEE Std 754-1985. */
1898 /* SINGLE precision floating:
1899 * seeeeeeeefffffffffffffffffffffff
1901 * e = 8bits = exponent
1902 * f = 23bits = fraction
1904 /* SINGLE precision fixed:
1905 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1907 * i = 31bits = integer
1909 /* DOUBLE precision floating:
1910 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1912 * e = 11bits = exponent
1913 * f = 52bits = fraction
1915 /* DOUBLE precision fixed:
1916 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1918 * i = 63bits = integer
1921 /* Extract sign-bit: */
1922 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
1923 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
1924 /* Extract biased exponent: */
1925 #define FP_S_be(v) (((v) >> 23) & 0xFF)
1926 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
1927 /* Extract unbiased Exponent: */
1928 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
1929 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1930 /* Extract complete fraction field: */
1931 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
1932 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
1933 /* Extract numbered fraction bit: */
1934 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1935 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1937 /* Explicit QNaN values used when value required: */
1938 #define FPQNaN_SINGLE (0x7FBFFFFF)
1939 #define FPQNaN_WORD (0x7FFFFFFF)
1940 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1941 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
1943 /* Explicit Infinity values used when required: */
1944 #define FPINF_SINGLE (0x7F800000)
1945 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
1947 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1948 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : (((v) == fmt_uninterpreted_32) ? "<uninterpreted_32>" : (((v) == fmt_uninterpreted_64) ? "<uninterpreted_64>" : "<format error>"))))))))
1951 value_fpr (SIM_DESC sd
,
1960 /* Treat unused register values, as fixed-point 64bit values: */
1961 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
1963 /* If request to read data as "uninterpreted", then use the current
1965 fmt
= FPR_STATE
[fpr
];
1970 /* For values not yet accessed, set to the desired format: */
1971 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
1972 FPR_STATE
[fpr
] = fmt
;
1974 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
1977 if (fmt
!= FPR_STATE
[fpr
]) {
1978 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
1979 FPR_STATE
[fpr
] = fmt_unknown
;
1982 if (FPR_STATE
[fpr
] == fmt_unknown
) {
1983 /* Set QNaN value: */
1986 value
= FPQNaN_SINGLE
;
1990 value
= FPQNaN_DOUBLE
;
1994 value
= FPQNaN_WORD
;
1998 value
= FPQNaN_LONG
;
2005 } else if (SizeFGR() == 64) {
2009 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2012 case fmt_uninterpreted
:
2026 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2029 case fmt_uninterpreted
:
2032 if ((fpr
& 1) == 0) { /* even registers only */
2034 printf("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n",
2035 fpr
+1, pr_uword64( (uword64
) FGR
[fpr
+1] ),
2036 fpr
, pr_uword64( (uword64
) FGR
[fpr
] ));
2038 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2040 SignalException(ReservedInstruction
,0);
2051 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2054 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_uword64(value
),pr_addr(cia
),SizeFGR());
2061 store_fpr (SIM_DESC sd
,
2071 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d,\n",fpr
,DOFMT(fmt
),pr_uword64(value
),pr_addr(cia
),SizeFGR());
2074 if (SizeFGR() == 64) {
2076 case fmt_uninterpreted_32
:
2077 fmt
= fmt_uninterpreted
;
2080 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2081 FPR_STATE
[fpr
] = fmt
;
2084 case fmt_uninterpreted_64
:
2085 fmt
= fmt_uninterpreted
;
2086 case fmt_uninterpreted
:
2090 FPR_STATE
[fpr
] = fmt
;
2094 FPR_STATE
[fpr
] = fmt_unknown
;
2100 case fmt_uninterpreted_32
:
2101 fmt
= fmt_uninterpreted
;
2104 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2105 FPR_STATE
[fpr
] = fmt
;
2108 case fmt_uninterpreted_64
:
2109 fmt
= fmt_uninterpreted
;
2110 case fmt_uninterpreted
:
2113 if ((fpr
& 1) == 0) { /* even register number only */
2114 FGR
[fpr
+1] = (value
>> 32);
2115 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2116 FPR_STATE
[fpr
+ 1] = fmt
;
2117 FPR_STATE
[fpr
] = fmt
;
2119 FPR_STATE
[fpr
] = fmt_unknown
;
2120 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2121 SignalException(ReservedInstruction
,0);
2126 FPR_STATE
[fpr
] = fmt_unknown
;
2131 #if defined(WARN_RESULT)
2134 #endif /* WARN_RESULT */
2137 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2140 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_uword64(FGR
[fpr
]),DOFMT(fmt
));
2157 sim_fpu_32to (&wop
, op
);
2158 boolean
= sim_fpu_is_nan (&wop
);
2165 sim_fpu_64to (&wop
, op
);
2166 boolean
= sim_fpu_is_nan (&wop
);
2170 fprintf (stderr
, "Bad switch\n");
2175 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2189 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2196 sim_fpu_32to (&wop
, op
);
2197 boolean
= sim_fpu_is_infinity (&wop
);
2203 sim_fpu_64to (&wop
, op
);
2204 boolean
= sim_fpu_is_infinity (&wop
);
2208 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2213 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2227 /* Argument checking already performed by the FPCOMPARE code */
2230 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2233 /* The format type should already have been checked: */
2239 sim_fpu_32to (&wop1
, op1
);
2240 sim_fpu_32to (&wop2
, op2
);
2241 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2248 sim_fpu_64to (&wop1
, op1
);
2249 sim_fpu_64to (&wop2
, op2
);
2250 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2254 fprintf (stderr
, "Bad switch\n");
2259 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2273 /* Argument checking already performed by the FPCOMPARE code */
2276 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2279 /* The format type should already have been checked: */
2285 sim_fpu_32to (&wop1
, op1
);
2286 sim_fpu_32to (&wop2
, op2
);
2287 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2294 sim_fpu_64to (&wop1
, op1
);
2295 sim_fpu_64to (&wop2
, op2
);
2296 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2300 fprintf (stderr
, "Bad switch\n");
2305 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2312 AbsoluteValue(op
,fmt
)
2319 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2322 /* The format type should already have been checked: */
2328 sim_fpu_32to (&wop
, op
);
2329 sim_fpu_abs (&wop
, &wop
);
2330 sim_fpu_to32 (&ans
, &wop
);
2338 sim_fpu_64to (&wop
, op
);
2339 sim_fpu_abs (&wop
, &wop
);
2340 sim_fpu_to64 (&ans
, &wop
);
2345 fprintf (stderr
, "Bad switch\n");
2360 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2363 /* The format type should already have been checked: */
2369 sim_fpu_32to (&wop
, op
);
2370 sim_fpu_neg (&wop
, &wop
);
2371 sim_fpu_to32 (&ans
, &wop
);
2379 sim_fpu_64to (&wop
, op
);
2380 sim_fpu_neg (&wop
, &wop
);
2381 sim_fpu_to64 (&ans
, &wop
);
2386 fprintf (stderr
, "Bad switch\n");
2402 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2405 /* The registers must specify FPRs valid for operands of type
2406 "fmt". If they are not valid, the result is undefined. */
2408 /* The format type should already have been checked: */
2416 sim_fpu_32to (&wop1
, op1
);
2417 sim_fpu_32to (&wop2
, op2
);
2418 sim_fpu_add (&ans
, &wop1
, &wop2
);
2419 sim_fpu_to32 (&res
, &ans
);
2429 sim_fpu_64to (&wop1
, op1
);
2430 sim_fpu_64to (&wop2
, op2
);
2431 sim_fpu_add (&ans
, &wop1
, &wop2
);
2432 sim_fpu_to64 (&res
, &ans
);
2437 fprintf (stderr
, "Bad switch\n");
2442 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2457 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2460 /* The registers must specify FPRs valid for operands of type
2461 "fmt". If they are not valid, the result is undefined. */
2463 /* The format type should already have been checked: */
2471 sim_fpu_32to (&wop1
, op1
);
2472 sim_fpu_32to (&wop2
, op2
);
2473 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2474 sim_fpu_to32 (&res
, &ans
);
2484 sim_fpu_64to (&wop1
, op1
);
2485 sim_fpu_64to (&wop2
, op2
);
2486 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2487 sim_fpu_to64 (&res
, &ans
);
2492 fprintf (stderr
, "Bad switch\n");
2497 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2504 Multiply(op1
,op2
,fmt
)
2512 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2515 /* The registers must specify FPRs valid for operands of type
2516 "fmt". If they are not valid, the result is undefined. */
2518 /* The format type should already have been checked: */
2526 sim_fpu_32to (&wop1
, op1
);
2527 sim_fpu_32to (&wop2
, op2
);
2528 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2529 sim_fpu_to32 (&res
, &ans
);
2539 sim_fpu_64to (&wop1
, op1
);
2540 sim_fpu_64to (&wop2
, op2
);
2541 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2542 sim_fpu_to64 (&res
, &ans
);
2547 fprintf (stderr
, "Bad switch\n");
2552 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2567 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2570 /* The registers must specify FPRs valid for operands of type
2571 "fmt". If they are not valid, the result is undefined. */
2573 /* The format type should already have been checked: */
2581 sim_fpu_32to (&wop1
, op1
);
2582 sim_fpu_32to (&wop2
, op2
);
2583 sim_fpu_div (&ans
, &wop1
, &wop2
);
2584 sim_fpu_to32 (&res
, &ans
);
2594 sim_fpu_64to (&wop1
, op1
);
2595 sim_fpu_64to (&wop2
, op2
);
2596 sim_fpu_div (&ans
, &wop1
, &wop2
);
2597 sim_fpu_to64 (&res
, &ans
);
2602 fprintf (stderr
, "Bad switch\n");
2607 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2621 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2624 /* The registers must specify FPRs valid for operands of type
2625 "fmt". If they are not valid, the result is undefined. */
2627 /* The format type should already have been checked: */
2634 sim_fpu_32to (&wop
, op
);
2635 sim_fpu_inv (&ans
, &wop
);
2636 sim_fpu_to32 (&res
, &ans
);
2645 sim_fpu_64to (&wop
, op
);
2646 sim_fpu_inv (&ans
, &wop
);
2647 sim_fpu_to64 (&res
, &ans
);
2652 fprintf (stderr
, "Bad switch\n");
2657 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2671 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2674 /* The registers must specify FPRs valid for operands of type
2675 "fmt". If they are not valid, the result is undefined. */
2677 /* The format type should already have been checked: */
2684 sim_fpu_32to (&wop
, op
);
2685 sim_fpu_sqrt (&ans
, &wop
);
2686 sim_fpu_to32 (&res
, &ans
);
2695 sim_fpu_64to (&wop
, op
);
2696 sim_fpu_sqrt (&ans
, &wop
);
2697 sim_fpu_to64 (&res
, &ans
);
2702 fprintf (stderr
, "Bad switch\n");
2707 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2723 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2726 /* The registers must specify FPRs valid for operands of type
2727 "fmt". If they are not valid, the result is undefined. */
2729 /* The format type should already have been checked: */
2736 sim_fpu_32to (&wop1
, op1
);
2737 sim_fpu_32to (&wop2
, op2
);
2738 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2745 sim_fpu_64to (&wop1
, op1
);
2746 sim_fpu_64to (&wop2
, op2
);
2747 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2751 fprintf (stderr
, "Bad switch\n");
2757 case SIM_FPU_IS_SNAN
:
2758 case SIM_FPU_IS_QNAN
:
2760 case SIM_FPU_IS_NINF
:
2761 case SIM_FPU_IS_NNUMBER
:
2762 case SIM_FPU_IS_NDENORM
:
2763 case SIM_FPU_IS_NZERO
:
2764 result
= op2
; /* op1 - op2 < 0 */
2765 case SIM_FPU_IS_PINF
:
2766 case SIM_FPU_IS_PNUMBER
:
2767 case SIM_FPU_IS_PDENORM
:
2768 case SIM_FPU_IS_PZERO
:
2769 result
= op1
; /* op1 - op2 > 0 */
2771 fprintf (stderr
, "Bad switch\n");
2776 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2793 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2796 /* The registers must specify FPRs valid for operands of type
2797 "fmt". If they are not valid, the result is undefined. */
2799 /* The format type should already have been checked: */
2806 sim_fpu_32to (&wop1
, op1
);
2807 sim_fpu_32to (&wop2
, op2
);
2808 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2815 sim_fpu_64to (&wop1
, op1
);
2816 sim_fpu_64to (&wop2
, op2
);
2817 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2821 fprintf (stderr
, "Bad switch\n");
2827 case SIM_FPU_IS_SNAN
:
2828 case SIM_FPU_IS_QNAN
:
2830 case SIM_FPU_IS_NINF
:
2831 case SIM_FPU_IS_NNUMBER
:
2832 case SIM_FPU_IS_NDENORM
:
2833 case SIM_FPU_IS_NZERO
:
2834 result
= op1
; /* op1 - op2 < 0 */
2835 case SIM_FPU_IS_PINF
:
2836 case SIM_FPU_IS_PNUMBER
:
2837 case SIM_FPU_IS_PDENORM
:
2838 case SIM_FPU_IS_PZERO
:
2839 result
= op2
; /* op1 - op2 > 0 */
2841 fprintf (stderr
, "Bad switch\n");
2846 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2854 convert (SIM_DESC sd
,
2863 sim_fpu_round round
;
2864 unsigned32 result32
;
2865 unsigned64 result64
;
2868 #if 0 /* FIXME: doesn't compile */
2869 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
2876 /* Round result to nearest representable value. When two
2877 representable values are equally near, round to the value
2878 that has a least significant bit of zero (i.e. is even). */
2879 round
= sim_fpu_round_near
;
2882 /* Round result to the value closest to, and not greater in
2883 magnitude than, the result. */
2884 round
= sim_fpu_round_zero
;
2887 /* Round result to the value closest to, and not less than,
2889 round
= sim_fpu_round_up
;
2893 /* Round result to the value closest to, and not greater than,
2895 round
= sim_fpu_round_down
;
2899 fprintf (stderr
, "Bad switch\n");
2903 /* Convert the input to sim_fpu internal format */
2907 sim_fpu_64to (&wop
, op
);
2910 sim_fpu_32to (&wop
, op
);
2913 sim_fpu_i32to (&wop
, op
, round
);
2916 sim_fpu_i64to (&wop
, op
, round
);
2919 fprintf (stderr
, "Bad switch\n");
2923 /* Convert sim_fpu format into the output */
2924 /* The value WOP is converted to the destination format, rounding
2925 using mode RM. When the destination is a fixed-point format, then
2926 a source value of Infinity, NaN or one which would round to an
2927 integer outside the fixed point range then an IEEE Invalid
2928 Operation condition is raised. */
2932 sim_fpu_round_32 (&wop
, round
, 0);
2933 sim_fpu_to32 (&result32
, &wop
);
2934 result64
= result32
;
2937 sim_fpu_round_64 (&wop
, round
, 0);
2938 sim_fpu_to64 (&result64
, &wop
);
2941 sim_fpu_to32i (&result32
, &wop
, round
);
2942 result64
= result32
;
2945 sim_fpu_to64i (&result64
, &wop
, round
);
2949 fprintf (stderr
, "Bad switch\n");
2954 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
2961 /*-- co-processor support routines ------------------------------------------*/
2964 CoProcPresent(unsigned int coproc_number
)
2966 /* Return TRUE if simulator provides a model for the given co-processor number */
2971 cop_lw (SIM_DESC sd
,
2976 unsigned int memword
)
2981 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2984 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
2986 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
2987 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
2992 #if 0 /* this should be controlled by a configuration option */
2993 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
3002 cop_ld (SIM_DESC sd
,
3011 printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num
, coproc_reg
, pr_uword64(memword
), pr_addr(cia
) );
3014 switch (coproc_num
) {
3016 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3018 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
3023 #if 0 /* this message should be controlled by a configuration option */
3024 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
3036 cop_sw (SIM_DESC sd
,
3042 unsigned int value
= 0;
3047 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3050 hold
= FPR_STATE
[coproc_reg
];
3051 FPR_STATE
[coproc_reg
] = fmt_word
;
3052 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
3053 FPR_STATE
[coproc_reg
] = hold
;
3058 #if 0 /* should be controlled by configuration option */
3059 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3068 cop_sd (SIM_DESC sd
,
3078 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3080 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
3085 #if 0 /* should be controlled by configuration option */
3086 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3098 decode_coproc (SIM_DESC sd
,
3101 unsigned int instruction
)
3103 int coprocnum
= ((instruction
>> 26) & 3);
3107 case 0: /* standard CPU control and cache registers */
3109 int code
= ((instruction
>> 21) & 0x1F);
3110 int rt
= ((instruction
>> 16) & 0x1F);
3111 int rd
= ((instruction
>> 11) & 0x1F);
3112 int tail
= instruction
& 0x3ff;
3113 /* R4000 Users Manual (second edition) lists the following CP0
3115 CODE><-RT><RD-><--TAIL--->
3116 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3117 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3118 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3119 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3120 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3121 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3122 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3123 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3124 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3125 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3127 if (((code
== 0x00) || (code
== 0x04)) && tail
== 0)
3129 /* M[TF]C0 - 32 bit word */
3131 switch (rd
) /* NOTEs: Standard CP0 registers */
3133 /* 0 = Index R4000 VR4100 VR4300 */
3134 /* 1 = Random R4000 VR4100 VR4300 */
3135 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3136 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3137 /* 4 = Context R4000 VR4100 VR4300 */
3138 /* 5 = PageMask R4000 VR4100 VR4300 */
3139 /* 6 = Wired R4000 VR4100 VR4300 */
3140 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3141 /* 9 = Count R4000 VR4100 VR4300 */
3142 /* 10 = EntryHi R4000 VR4100 VR4300 */
3143 /* 11 = Compare R4000 VR4100 VR4300 */
3144 /* 12 = SR R4000 VR4100 VR4300 */
3145 #ifdef SUBTARGET_R3900
3147 /* 3 = Config R3900 */
3149 /* 7 = Cache R3900 */
3151 /* 15 = PRID R3900 */
3157 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3159 GPR
[rt
] = COP0_BADVADDR
;
3161 COP0_BADVADDR
= GPR
[rt
];
3164 #endif /* SUBTARGET_R3900 */
3171 /* 13 = Cause R4000 VR4100 VR4300 */
3178 /* 14 = EPC R4000 VR4100 VR4300 */
3181 GPR
[rt
] = (signed_word
) (signed_address
) EPC
;
3185 /* 15 = PRId R4000 VR4100 VR4300 */
3186 #ifdef SUBTARGET_R3900
3195 /* 16 = Config R4000 VR4100 VR4300 */
3198 GPR
[rt
] = C0_CONFIG
;
3200 C0_CONFIG
= GPR
[rt
];
3203 #ifdef SUBTARGET_R3900
3212 /* 17 = LLAddr R4000 VR4100 VR4300 */
3214 /* 18 = WatchLo R4000 VR4100 VR4300 */
3215 /* 19 = WatchHi R4000 VR4100 VR4300 */
3216 /* 20 = XContext R4000 VR4100 VR4300 */
3217 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3218 /* 27 = CacheErr R4000 VR4100 */
3219 /* 28 = TagLo R4000 VR4100 VR4300 */
3220 /* 29 = TagHi R4000 VR4100 VR4300 */
3221 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3222 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3223 /* CPR[0,rd] = GPR[rt]; */
3226 GPR
[rt
] = (signed_word
) (signed32
) COP0_GPR
[rd
];
3228 COP0_GPR
[rd
] = GPR
[rt
];
3231 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt
,rd
, (unsigned)cia
);
3233 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt
,rd
, (unsigned)cia
);
3237 else if (code
== 0x10 && (tail
& 0x3f) == 0x18)
3240 if (SR
& status_ERL
)
3242 /* Oops, not yet available */
3243 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3253 else if (code
== 0x10 && (tail
& 0x3f) == 0x10)
3256 #ifdef SUBTARGET_R3900
3257 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
3259 /* shift IE/KU history bits right */
3260 SR
= LSMASKED32(SR
, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR
, 5, 2), 3, 0);
3262 /* TODO: CACHE register */
3263 #endif /* SUBTARGET_R3900 */
3265 else if (code
== 0x10 && (tail
& 0x3f) == 0x1F)
3273 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3274 /* TODO: When executing an ERET or RFE instruction we should
3275 clear LLBIT, to ensure that any out-standing atomic
3276 read/modify/write sequence fails. */
3280 case 2: /* co-processor 2 */
3287 sim_io_eprintf(sd
, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
3288 instruction
,pr_addr(cia
));
3293 case 1: /* should not occur (FPU co-processor) */
3294 case 3: /* should not occur (FPU co-processor) */
3295 SignalException(ReservedInstruction
,instruction
);
3303 /* This code copied from gdb's utils.c. Would like to share this code,
3304 but don't know of a common place where both could get to it. */
3306 /* Temporary storage using circular buffer */
3312 static char buf
[NUMCELLS
][CELLSIZE
];
3314 if (++cell
>=NUMCELLS
) cell
=0;
3318 /* Print routines to handle variable size regs, etc */
3320 /* Eliminate warning from compiler on 32-bit systems */
3321 static int thirty_two
= 32;
3327 char *paddr_str
=get_cell();
3328 switch (sizeof(addr
))
3331 sprintf(paddr_str
,"%08lx%08lx",
3332 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3335 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3338 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3341 sprintf(paddr_str
,"%x",addr
);
3350 char *paddr_str
=get_cell();
3351 sprintf(paddr_str
,"%08lx%08lx",
3352 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3358 mips_core_signal (SIM_DESC sd
,
3364 transfer_type transfer
,
3365 sim_core_signals sig
)
3367 const char *copy
= (transfer
== read_transfer
? "read" : "write");
3368 address_word ip
= CIA_ADDR (cia
);
3372 case sim_core_unmapped_signal
:
3373 sim_io_eprintf (sd
, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
3375 (unsigned long) addr
, (unsigned long) ip
);
3376 COP0_BADVADDR
= addr
;
3377 SignalExceptionDataReference();
3380 case sim_core_unaligned_signal
:
3381 sim_io_eprintf (sd
, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
3383 (unsigned long) addr
, (unsigned long) ip
);
3384 COP0_BADVADDR
= addr
;
3385 if(transfer
== read_transfer
)
3386 SignalExceptionAddressLoad();
3388 SignalExceptionAddressStore();
3392 sim_engine_abort (sd
, cpu
, cia
,
3393 "mips_core_signal - internal error - bad switch");
3399 mips_cpu_exception_trigger(SIM_DESC sd
, sim_cpu
* cpu
, address_word cia
)
3401 ASSERT(cpu
!= NULL
);
3403 if(cpu
->exc_suspended
> 0)
3404 sim_io_eprintf(sd
, "Warning, nested exception triggered (%d)\n", cpu
->exc_suspended
);
3407 memcpy(cpu
->exc_trigger_registers
, cpu
->registers
, sizeof(cpu
->exc_trigger_registers
));
3408 cpu
->exc_suspended
= 0;
3412 mips_cpu_exception_suspend(SIM_DESC sd
, sim_cpu
* cpu
, int exception
)
3414 ASSERT(cpu
!= NULL
);
3416 if(cpu
->exc_suspended
> 0)
3417 sim_io_eprintf(sd
, "Warning, nested exception signal (%d then %d)\n",
3418 cpu
->exc_suspended
, exception
);
3420 memcpy(cpu
->exc_suspend_registers
, cpu
->registers
, sizeof(cpu
->exc_suspend_registers
));
3421 memcpy(cpu
->registers
, cpu
->exc_trigger_registers
, sizeof(cpu
->registers
));
3422 cpu
->exc_suspended
= exception
;
3426 mips_cpu_exception_resume(SIM_DESC sd
, sim_cpu
* cpu
, int exception
)
3428 ASSERT(cpu
!= NULL
);
3430 if(exception
== 0 && cpu
->exc_suspended
> 0)
3432 /* warn not for breakpoints */
3433 if(cpu
->exc_suspended
!= sim_signal_to_host(sd
, SIM_SIGTRAP
))
3434 sim_io_eprintf(sd
, "Warning, resuming but ignoring pending exception signal (%d)\n",
3435 cpu
->exc_suspended
);
3437 else if(exception
!= 0 && cpu
->exc_suspended
> 0)
3439 if(exception
!= cpu
->exc_suspended
)
3440 sim_io_eprintf(sd
, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
3441 cpu
->exc_suspended
, exception
);
3443 memcpy(cpu
->registers
, cpu
->exc_suspend_registers
, sizeof(cpu
->registers
));
3445 else if(exception
!= 0 && cpu
->exc_suspended
== 0)
3447 sim_io_eprintf(sd
, "Warning, ignoring spontanous exception signal (%d)\n", exception
);
3449 cpu
->exc_suspended
= 0;
3453 /*---------------------------------------------------------------------------*/
3454 /*> EOF interp.c <*/