sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator are defined below.
  34 //
  35 // When placing models in the instruction descriptions, please place
  36 // them one per line, in the order given here.
  37
  38 //  MIPS ISAs:
  39 //
  40 //  Instructions and related functions for these models are included in
  41 //  this file.
  42 :model:::mipsI:mips3000:
  43 :model:::mipsII:mips6000:
  44 :model:::mipsIII:mips4000:
  45 :model:::mipsIV:mips8000:
  46 :model:::mipsV:mipsisaV:
  47 :model:::mips32:mipsisa32:
  48 :model:::mips64:mipsisa64:
  49
  50 //  Vendor ISAs:
  51 //
  52 //  Standard MIPS ISA instructions used for these models are listed here,
  53 //  as are functions needed by those standard instructions.  Instructions
  54 //  which are model-dependent and which are not in the standard MIPS ISAs
  55 //  (or which pre-date or use different encodings than the standard
  56 //  instructions) are (for the most part) in separate .igen files.
  57 :model:::vr4100:mips4100:               // vr.igen
  58 :model:::vr5000:mips5000:
  59 :model:::r3900:mips3900:                // tx.igen
  60
  61 //  MIPS Application Specific Extensions (ASEs)
  62 //
  63 //  Instructions for the ASEs are in separate .igen files.
  64 //  ASEs add instructions on to a base ISA.
  65 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  66 :model:::mdmx:mdmx:                     // mdmx.igen
  67
  68 //  Vendor Extensions
  69 //
  70 //  Instructions specific to these extensions are in separate .igen files.
  71 //  Extensions add instructions on to a base ISA.
  72 :model:::sb1:sb1:                       // sb1.igen
  73
  74
  75 // Pseudo instructions known by IGEN
  76 :internal::::illegal:
  77 {
  78   SignalException (ReservedInstruction, 0);
  79 }
  80
  81
  82 // Pseudo instructions known by interp.c
  83 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  84 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  85 "rsvd <OP>"
  86 {
  87   SignalException (ReservedInstruction, instruction_0);
  88 }
  89
  90
  91
  92 // Helper:
  93 //
  94 // Simulate a 32 bit delayslot instruction
  95 //
  96
  97 :function:::address_word:delayslot32:address_word target
  98 {
  99   instruction_word delay_insn;
 100   sim_events_slip (SD, 1);
 101   DSPC = CIA;
 102   CIA = CIA + 4; /* NOTE not mips16 */
 103   STATE |= simDELAYSLOT;
 104   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
 105   ENGINE_ISSUE_PREFIX_HOOK();
 106   idecode_issue (CPU_, delay_insn, (CIA));
 107   STATE &= ~simDELAYSLOT;
 108   return target;
 109 }
 110
 111 :function:::address_word:nullify_next_insn32:
 112 {
 113   sim_events_slip (SD, 1);
 114   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 115   return CIA + 8;
 116 }
 117
 118
 119 // Helper:
 120 //
 121 // Calculate an effective address given a base and an offset.
 122 //
 123
 124 :function:::address_word:loadstore_ea:address_word base, address_word offset
 125 *mipsI:
 126 *mipsII:
 127 *mipsIII:
 128 *mipsIV:
 129 *mipsV:
 130 *mips32:
 131 *vr4100:
 132 *vr5000:
 133 *r3900:
 134 {
 135   return base + offset;
 136 }
 137
 138 :function:::address_word:loadstore_ea:address_word base, address_word offset
 139 *mips64:
 140 {
 141 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 142   /* If in user mode and UX is not set, use 32-bit compatibility effective
 143      address computations as defined in the MIPS64 Architecture for
 144      Programmers Volume III, Revision 0.95, section 4.9.  */
 145   if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
 146       == (ksu_user << status_KSU_shift))
 147     return (address_word)((signed32)base + (signed32)offset);
 148 #endif
 149   return base + offset;
 150 }
 151
 152
 153 // Helper:
 154 //
 155 // Check that a 32-bit register value is properly sign-extended.
 156 // (See NotWordValue in ISA spec.)
 157 //
 158
 159 :function:::int:not_word_value:unsigned_word value
 160 *mipsI:
 161 *mipsII:
 162 *mipsIII:
 163 *mipsIV:
 164 *mipsV:
 165 *vr4100:
 166 *vr5000:
 167 *r3900:
 168 {
 169   /* For historical simulator compatibility (until documentation is
 170      found that makes these operations unpredictable on some of these
 171      architectures), this check never returns true.  */
 172   return 0;
 173 }
 174
 175 :function:::int:not_word_value:unsigned_word value
 176 *mips32:
 177 {
 178   /* On MIPS32, since registers are 32-bits, there's no check to be done.  */
 179   return 0;
 180 }
 181
 182 :function:::int:not_word_value:unsigned_word value
 183 *mips64:
 184 {
 185   return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
 186 }
 187
 188
 189 // Helper:
 190 //
 191 // Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
 192 // theoretically portable code which invokes non-portable behaviour from
 193 // running with no indication of the portability issue.
 194 // (See definition of UNPREDICTABLE in ISA spec.)
 195 //
 196
 197 :function:::void:unpredictable:
 198 *mipsI:
 199 *mipsII:
 200 *mipsIII:
 201 *mipsIV:
 202 *mipsV:
 203 *vr4100:
 204 *vr5000:
 205 *r3900:
 206 {
 207 }
 208
 209 :function:::void:unpredictable:
 210 *mips32:
 211 *mips64:
 212 {
 213   unpredictable_action (CPU, CIA);
 214 }
 215
 216
 217 // Helper:
 218 //
 219 // Check that an access to a HI/LO register meets timing requirements
 220 //
 221 // The following requirements exist:
 222 //
 223 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 224 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 225 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 226 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 227 //
 228
 229 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 230 {
 231   if (history->mf.timestamp + 3 > time)
 232     {
 233       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 234                         itable[MY_INDEX].name,
 235                         new, (long) CIA,
 236                         (long) history->mf.cia);
 237       return 0;
 238     }
 239   return 1;
 240 }
 241
 242 :function:::int:check_mt_hilo:hilo_history *history
 243 *mipsI:
 244 *mipsII:
 245 *mipsIII:
 246 *mipsIV:
 247 *mipsV:
 248 *vr4100:
 249 *vr5000:
 250 {
 251   signed64 time = sim_events_time (SD);
 252   int ok = check_mf_cycles (SD_, history, time, "MT");
 253   history->mt.timestamp = time;
 254   history->mt.cia = CIA;
 255   return ok;
 256 }
 257
 258 :function:::int:check_mt_hilo:hilo_history *history
 259 *mips32:
 260 *mips64:
 261 *r3900:
 262 {
 263   signed64 time = sim_events_time (SD);
 264   history->mt.timestamp = time;
 265   history->mt.cia = CIA;
 266   return 1;
 267 }
 268
 269
 270 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 271 *mipsI:
 272 *mipsII:
 273 *mipsIII:
 274 *mipsIV:
 275 *mipsV:
 276 *mips32:
 277 *mips64:
 278 *vr4100:
 279 *vr5000:
 280 *r3900:
 281 {
 282   signed64 time = sim_events_time (SD);
 283   int ok = 1;
 284   if (peer != NULL
 285       && peer->mt.timestamp > history->op.timestamp
 286       && history->mt.timestamp < history->op.timestamp
 287       && ! (history->mf.timestamp > history->op.timestamp
 288             && history->mf.timestamp < peer->mt.timestamp)
 289       && ! (peer->mf.timestamp > history->op.timestamp
 290             && peer->mf.timestamp < peer->mt.timestamp))
 291     {
 292       /* The peer has been written to since the last OP yet we have
 293          not */
 294       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 295                         itable[MY_INDEX].name,
 296                         (long) CIA,
 297                         (long) history->op.cia,
 298                         (long) peer->mt.cia);
 299       ok = 0;
 300     }
 301   history->mf.timestamp = time;
 302   history->mf.cia = CIA;
 303   return ok;
 304 }
 305
 306
 307
 308 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 309 *mipsI:
 310 *mipsII:
 311 *mipsIII:
 312 *mipsIV:
 313 *mipsV:
 314 *vr4100:
 315 *vr5000:
 316 {
 317   signed64 time = sim_events_time (SD);
 318   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 319             && check_mf_cycles (SD_, lo, time, "OP"));
 320   hi->op.timestamp = time;
 321   lo->op.timestamp = time;
 322   hi->op.cia = CIA;
 323   lo->op.cia = CIA;
 324   return ok;
 325 }
 326
 327 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 328 // a mf{hi,lo}
 329 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 330 *mips32:
 331 *mips64:
 332 *r3900:
 333 {
 334   /* FIXME: could record the fact that a stall occured if we want */
 335   signed64 time = sim_events_time (SD);
 336   hi->op.timestamp = time;
 337   lo->op.timestamp = time;
 338   hi->op.cia = CIA;
 339   lo->op.cia = CIA;
 340   return 1;
 341 }
 342
 343
 344 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 345 *mipsI:
 346 *mipsII:
 347 *mipsIII:
 348 *mipsIV:
 349 *mipsV:
 350 *mips32:
 351 *mips64:
 352 *vr4100:
 353 *vr5000:
 354 *r3900:
 355 {
 356   signed64 time = sim_events_time (SD);
 357   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 358             && check_mf_cycles (SD_, lo, time, "OP"));
 359   hi->op.timestamp = time;
 360   lo->op.timestamp = time;
 361   hi->op.cia = CIA;
 362   lo->op.cia = CIA;
 363   return ok;
 364 }
 365
 366
 367 // Helper:
 368 //
 369 // Check that the 64-bit instruction can currently be used, and signal
 370 // a ReservedInstruction exception if not.
 371 //
 372
 373 :function:::void:check_u64:instruction_word insn
 374 *mipsIII:
 375 *mipsIV:
 376 *mipsV:
 377 *vr4100:
 378 *vr5000:
 379 {
 380   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 381 }
 382
 383 :function:::void:check_u64:instruction_word insn
 384 *mips64:
 385 {
 386 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 387   if (UserMode && (SR & (status_UX|status_PX)) == 0)
 388     SignalException (ReservedInstruction, insn);
 389 #endif
 390 }
 391
 392
 393
 394 //
 395 // MIPS Architecture:
 396 //
 397 //        CPU Instruction Set (mipsI - mipsV, mips32, mips64)
 398 //
 399
 400
 401
 402 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 403 "add r<RD>, r<RS>, r<RT>"
 404 *mipsI:
 405 *mipsII:
 406 *mipsIII:
 407 *mipsIV:
 408 *mipsV:
 409 *mips32:
 410 *mips64:
 411 *vr4100:
 412 *vr5000:
 413 *r3900:
 414 {
 415   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
 416     Unpredictable ();
 417   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 418   {
 419     ALU32_BEGIN (GPR[RS]);
 420     ALU32_ADD (GPR[RT]);
 421     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
 422   }
 423   TRACE_ALU_RESULT (GPR[RD]);
 424 }
 425
 426
 427
 428 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 429 "addi r<RT>, r<RS>, <IMMEDIATE>"
 430 *mipsI:
 431 *mipsII:
 432 *mipsIII:
 433 *mipsIV:
 434 *mipsV:
 435 *mips32:
 436 *mips64:
 437 *vr4100:
 438 *vr5000:
 439 *r3900:
 440 {
 441   if (NotWordValue (GPR[RS]))
 442     Unpredictable ();
 443   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 444   {
 445     ALU32_BEGIN (GPR[RS]);
 446     ALU32_ADD (EXTEND16 (IMMEDIATE));
 447     ALU32_END (GPR[RT]);   /* This checks for overflow.  */
 448   }
 449   TRACE_ALU_RESULT (GPR[RT]);
 450 }
 451
 452
 453
 454 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 455 {
 456   if (NotWordValue (GPR[rs]))
 457     Unpredictable ();
 458   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 459   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 460   TRACE_ALU_RESULT (GPR[rt]);
 461 }
 462
 463 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 464 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 465 *mipsI:
 466 *mipsII:
 467 *mipsIII:
 468 *mipsIV:
 469 *mipsV:
 470 *mips32:
 471 *mips64:
 472 *vr4100:
 473 *vr5000:
 474 *r3900:
 475 {
 476   do_addiu (SD_, RS, RT, IMMEDIATE);
 477 }
 478
 479
 480
 481 :function:::void:do_addu:int rs, int rt, int rd
 482 {
 483   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 484     Unpredictable ();
 485   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 486   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 487   TRACE_ALU_RESULT (GPR[rd]);
 488 }
 489
 490 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 491 "addu r<RD>, r<RS>, r<RT>"
 492 *mipsI:
 493 *mipsII:
 494 *mipsIII:
 495 *mipsIV:
 496 *mipsV:
 497 *mips32:
 498 *mips64:
 499 *vr4100:
 500 *vr5000:
 501 *r3900:
 502 {
 503   do_addu (SD_, RS, RT, RD);
 504 }
 505
 506
 507
 508 :function:::void:do_and:int rs, int rt, int rd
 509 {
 510   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 511   GPR[rd] = GPR[rs] & GPR[rt];
 512   TRACE_ALU_RESULT (GPR[rd]);
 513 }
 514
 515 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 516 "and r<RD>, r<RS>, r<RT>"
 517 *mipsI:
 518 *mipsII:
 519 *mipsIII:
 520 *mipsIV:
 521 *mipsV:
 522 *mips32:
 523 *mips64:
 524 *vr4100:
 525 *vr5000:
 526 *r3900:
 527 {
 528   do_and (SD_, RS, RT, RD);
 529 }
 530
 531
 532
 533 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 534 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
 535 *mipsI:
 536 *mipsII:
 537 *mipsIII:
 538 *mipsIV:
 539 *mipsV:
 540 *mips32:
 541 *mips64:
 542 *vr4100:
 543 *vr5000:
 544 *r3900:
 545 {
 546   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 547   GPR[RT] = GPR[RS] & IMMEDIATE;
 548   TRACE_ALU_RESULT (GPR[RT]);
 549 }
 550
 551
 552
 553 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 554 "beq r<RS>, r<RT>, <OFFSET>"
 555 *mipsI:
 556 *mipsII:
 557 *mipsIII:
 558 *mipsIV:
 559 *mipsV:
 560 *mips32:
 561 *mips64:
 562 *vr4100:
 563 *vr5000:
 564 *r3900:
 565 {
 566   address_word offset = EXTEND16 (OFFSET) << 2;
 567   check_branch_bug ();
 568   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 569     {
 570       mark_branch_bug (NIA+offset);
 571       DELAY_SLOT (NIA + offset);
 572     }
 573 }
 574
 575
 576
 577 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 578 "beql r<RS>, r<RT>, <OFFSET>"
 579 *mipsII:
 580 *mipsIII:
 581 *mipsIV:
 582 *mipsV:
 583 *mips32:
 584 *mips64:
 585 *vr4100:
 586 *vr5000:
 587 *r3900:
 588 {
 589   address_word offset = EXTEND16 (OFFSET) << 2;
 590   check_branch_bug ();
 591   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 592     {
 593       mark_branch_bug (NIA+offset);
 594       DELAY_SLOT (NIA + offset);
 595     }
 596   else
 597     NULLIFY_NEXT_INSTRUCTION ();
 598 }
 599
 600
 601
 602 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 603 "bgez r<RS>, <OFFSET>"
 604 *mipsI:
 605 *mipsII:
 606 *mipsIII:
 607 *mipsIV:
 608 *mipsV:
 609 *mips32:
 610 *mips64:
 611 *vr4100:
 612 *vr5000:
 613 *r3900:
 614 {
 615   address_word offset = EXTEND16 (OFFSET) << 2;
 616   check_branch_bug ();
 617   if ((signed_word) GPR[RS] >= 0)
 618     {
 619       mark_branch_bug (NIA+offset);
 620       DELAY_SLOT (NIA + offset);
 621     }
 622 }
 623
 624
 625
 626 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 627 "bgezal r<RS>, <OFFSET>"
 628 *mipsI:
 629 *mipsII:
 630 *mipsIII:
 631 *mipsIV:
 632 *mipsV:
 633 *mips32:
 634 *mips64:
 635 *vr4100:
 636 *vr5000:
 637 *r3900:
 638 {
 639   address_word offset = EXTEND16 (OFFSET) << 2;
 640   check_branch_bug ();
 641   if (RS == 31)
 642     Unpredictable ();
 643   RA = (CIA + 8);
 644   if ((signed_word) GPR[RS] >= 0)
 645     {
 646       mark_branch_bug (NIA+offset);
 647       DELAY_SLOT (NIA + offset);
 648     }
 649 }
 650
 651
 652
 653 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 654 "bgezall r<RS>, <OFFSET>"
 655 *mipsII:
 656 *mipsIII:
 657 *mipsIV:
 658 *mipsV:
 659 *mips32:
 660 *mips64:
 661 *vr4100:
 662 *vr5000:
 663 *r3900:
 664 {
 665   address_word offset = EXTEND16 (OFFSET) << 2;
 666   check_branch_bug ();
 667   if (RS == 31)
 668     Unpredictable ();
 669   RA = (CIA + 8);
 670   /* NOTE: The branch occurs AFTER the next instruction has been
 671      executed */
 672   if ((signed_word) GPR[RS] >= 0)
 673     {
 674       mark_branch_bug (NIA+offset);
 675       DELAY_SLOT (NIA + offset);
 676     }
 677   else
 678     NULLIFY_NEXT_INSTRUCTION ();
 679 }
 680
 681
 682
 683 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 684 "bgezl r<RS>, <OFFSET>"
 685 *mipsII:
 686 *mipsIII:
 687 *mipsIV:
 688 *mipsV:
 689 *mips32:
 690 *mips64:
 691 *vr4100:
 692 *vr5000:
 693 *r3900:
 694 {
 695   address_word offset = EXTEND16 (OFFSET) << 2;
 696   check_branch_bug ();
 697   if ((signed_word) GPR[RS] >= 0)
 698     {
 699       mark_branch_bug (NIA+offset);
 700       DELAY_SLOT (NIA + offset);
 701     }
 702   else
 703     NULLIFY_NEXT_INSTRUCTION ();
 704 }
 705
 706
 707
 708 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 709 "bgtz r<RS>, <OFFSET>"
 710 *mipsI:
 711 *mipsII:
 712 *mipsIII:
 713 *mipsIV:
 714 *mipsV:
 715 *mips32:
 716 *mips64:
 717 *vr4100:
 718 *vr5000:
 719 *r3900:
 720 {
 721   address_word offset = EXTEND16 (OFFSET) << 2;
 722   check_branch_bug ();
 723   if ((signed_word) GPR[RS] > 0)
 724     {
 725       mark_branch_bug (NIA+offset);
 726       DELAY_SLOT (NIA + offset);
 727     }
 728 }
 729
 730
 731
 732 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 733 "bgtzl r<RS>, <OFFSET>"
 734 *mipsII:
 735 *mipsIII:
 736 *mipsIV:
 737 *mipsV:
 738 *mips32:
 739 *mips64:
 740 *vr4100:
 741 *vr5000:
 742 *r3900:
 743 {
 744   address_word offset = EXTEND16 (OFFSET) << 2;
 745   check_branch_bug ();
 746   /* NOTE: The branch occurs AFTER the next instruction has been
 747      executed */
 748   if ((signed_word) GPR[RS] > 0)
 749     {
 750       mark_branch_bug (NIA+offset);
 751       DELAY_SLOT (NIA + offset);
 752     }
 753   else
 754     NULLIFY_NEXT_INSTRUCTION ();
 755 }
 756
 757
 758
 759 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 760 "blez r<RS>, <OFFSET>"
 761 *mipsI:
 762 *mipsII:
 763 *mipsIII:
 764 *mipsIV:
 765 *mipsV:
 766 *mips32:
 767 *mips64:
 768 *vr4100:
 769 *vr5000:
 770 *r3900:
 771 {
 772   address_word offset = EXTEND16 (OFFSET) << 2;
 773   check_branch_bug ();
 774   /* NOTE: The branch occurs AFTER the next instruction has been
 775      executed */
 776   if ((signed_word) GPR[RS] <= 0)
 777     {
 778       mark_branch_bug (NIA+offset);
 779       DELAY_SLOT (NIA + offset);
 780     }
 781 }
 782
 783
 784
 785 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 786 "bgezl r<RS>, <OFFSET>"
 787 *mipsII:
 788 *mipsIII:
 789 *mipsIV:
 790 *mipsV:
 791 *mips32:
 792 *mips64:
 793 *vr4100:
 794 *vr5000:
 795 *r3900:
 796 {
 797   address_word offset = EXTEND16 (OFFSET) << 2;
 798   check_branch_bug ();
 799   if ((signed_word) GPR[RS] <= 0)
 800     {
 801       mark_branch_bug (NIA+offset);
 802       DELAY_SLOT (NIA + offset);
 803     }
 804   else
 805     NULLIFY_NEXT_INSTRUCTION ();
 806 }
 807
 808
 809
 810 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 811 "bltz r<RS>, <OFFSET>"
 812 *mipsI:
 813 *mipsII:
 814 *mipsIII:
 815 *mipsIV:
 816 *mipsV:
 817 *mips32:
 818 *mips64:
 819 *vr4100:
 820 *vr5000:
 821 *r3900:
 822 {
 823   address_word offset = EXTEND16 (OFFSET) << 2;
 824   check_branch_bug ();
 825   if ((signed_word) GPR[RS] < 0)
 826     {
 827       mark_branch_bug (NIA+offset);
 828       DELAY_SLOT (NIA + offset);
 829     }
 830 }
 831
 832
 833
 834 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 835 "bltzal r<RS>, <OFFSET>"
 836 *mipsI:
 837 *mipsII:
 838 *mipsIII:
 839 *mipsIV:
 840 *mipsV:
 841 *mips32:
 842 *mips64:
 843 *vr4100:
 844 *vr5000:
 845 *r3900:
 846 {
 847   address_word offset = EXTEND16 (OFFSET) << 2;
 848   check_branch_bug ();
 849   if (RS == 31)
 850     Unpredictable ();
 851   RA = (CIA + 8);
 852   /* NOTE: The branch occurs AFTER the next instruction has been
 853      executed */
 854   if ((signed_word) GPR[RS] < 0)
 855     {
 856       mark_branch_bug (NIA+offset);
 857       DELAY_SLOT (NIA + offset);
 858     }
 859 }
 860
 861
 862
 863 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 864 "bltzall r<RS>, <OFFSET>"
 865 *mipsII:
 866 *mipsIII:
 867 *mipsIV:
 868 *mipsV:
 869 *mips32:
 870 *mips64:
 871 *vr4100:
 872 *vr5000:
 873 *r3900:
 874 {
 875   address_word offset = EXTEND16 (OFFSET) << 2;
 876   check_branch_bug ();
 877   if (RS == 31)
 878     Unpredictable ();
 879   RA = (CIA + 8);
 880   if ((signed_word) GPR[RS] < 0)
 881     {
 882       mark_branch_bug (NIA+offset);
 883       DELAY_SLOT (NIA + offset);
 884     }
 885   else
 886     NULLIFY_NEXT_INSTRUCTION ();
 887 }
 888
 889
 890
 891 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 892 "bltzl r<RS>, <OFFSET>"
 893 *mipsII:
 894 *mipsIII:
 895 *mipsIV:
 896 *mipsV:
 897 *mips32:
 898 *mips64:
 899 *vr4100:
 900 *vr5000:
 901 *r3900:
 902 {
 903   address_word offset = EXTEND16 (OFFSET) << 2;
 904   check_branch_bug ();
 905   /* NOTE: The branch occurs AFTER the next instruction has been
 906      executed */
 907   if ((signed_word) GPR[RS] < 0)
 908     {
 909       mark_branch_bug (NIA+offset);
 910       DELAY_SLOT (NIA + offset);
 911     }
 912   else
 913     NULLIFY_NEXT_INSTRUCTION ();
 914 }
 915
 916
 917
 918 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 919 "bne r<RS>, r<RT>, <OFFSET>"
 920 *mipsI:
 921 *mipsII:
 922 *mipsIII:
 923 *mipsIV:
 924 *mipsV:
 925 *mips32:
 926 *mips64:
 927 *vr4100:
 928 *vr5000:
 929 *r3900:
 930 {
 931   address_word offset = EXTEND16 (OFFSET) << 2;
 932   check_branch_bug ();
 933   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 934     {
 935       mark_branch_bug (NIA+offset);
 936       DELAY_SLOT (NIA + offset);
 937     }
 938 }
 939
 940
 941
 942 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 943 "bnel r<RS>, r<RT>, <OFFSET>"
 944 *mipsII:
 945 *mipsIII:
 946 *mipsIV:
 947 *mipsV:
 948 *mips32:
 949 *mips64:
 950 *vr4100:
 951 *vr5000:
 952 *r3900:
 953 {
 954   address_word offset = EXTEND16 (OFFSET) << 2;
 955   check_branch_bug ();
 956   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 957     {
 958       mark_branch_bug (NIA+offset);
 959       DELAY_SLOT (NIA + offset);
 960     }
 961   else
 962     NULLIFY_NEXT_INSTRUCTION ();
 963 }
 964
 965
 966
 967 000000,20.CODE,001101:SPECIAL:32::BREAK
 968 "break %#lx<CODE>"
 969 *mipsI:
 970 *mipsII:
 971 *mipsIII:
 972 *mipsIV:
 973 *mipsV:
 974 *mips32:
 975 *mips64:
 976 *vr4100:
 977 *vr5000:
 978 *r3900:
 979 {
 980   /* Check for some break instruction which are reserved for use by the simulator.  */
 981   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
 982   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 983       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 984     {
 985       sim_engine_halt (SD, CPU, NULL, cia,
 986                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
 987     }
 988   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 989            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 990     {
 991       if (STATE & simDELAYSLOT)
 992         PC = cia - 4; /* reference the branch instruction */
 993       else
 994         PC = cia;
 995       SignalException (BreakPoint, instruction_0);
 996     }
 997
 998   else
 999     {
1000       /* If we get this far, we're not an instruction reserved by the sim.  Raise
1001          the exception. */
1002       SignalException (BreakPoint, instruction_0);
1003     }
1004 }
1005
1006
1007
1008 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1009 "clo r<RD>, r<RS>"
1010 *mips32:
1011 *mips64:
1012 {
1013   unsigned32 temp = GPR[RS];
1014   unsigned32 i, mask;
1015   if (RT != RD)
1016     Unpredictable ();
1017   if (NotWordValue (GPR[RS]))
1018     Unpredictable ();
1019   TRACE_ALU_INPUT1 (GPR[RS]);
1020   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1021     {
1022       if ((temp & mask) == 0)
1023         break;
1024       mask >>= 1;
1025     }
1026   GPR[RD] = EXTEND32 (i);
1027   TRACE_ALU_RESULT (GPR[RD]);
1028 }
1029
1030
1031
1032 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1033 "clz r<RD>, r<RS>"
1034 *mips32:
1035 *mips64:
1036 {
1037   unsigned32 temp = GPR[RS];
1038   unsigned32 i, mask;
1039   if (RT != RD)
1040     Unpredictable ();
1041   if (NotWordValue (GPR[RS]))
1042     Unpredictable ();
1043   TRACE_ALU_INPUT1 (GPR[RS]);
1044   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1045     {
1046       if ((temp & mask) != 0)
1047         break;
1048       mask >>= 1;
1049     }
1050   GPR[RD] = EXTEND32 (i);
1051   TRACE_ALU_RESULT (GPR[RD]);
1052 }
1053
1054
1055
1056 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1057 "dadd r<RD>, r<RS>, r<RT>"
1058 *mipsIII:
1059 *mipsIV:
1060 *mipsV:
1061 *mips64:
1062 *vr4100:
1063 *vr5000:
1064 {
1065   check_u64 (SD_, instruction_0);
1066   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1067   {
1068     ALU64_BEGIN (GPR[RS]);
1069     ALU64_ADD (GPR[RT]);
1070     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1071   }
1072   TRACE_ALU_RESULT (GPR[RD]);
1073 }
1074
1075
1076
1077 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1078 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1079 *mipsIII:
1080 *mipsIV:
1081 *mipsV:
1082 *mips64:
1083 *vr4100:
1084 *vr5000:
1085 {
1086   check_u64 (SD_, instruction_0);
1087   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1088   {
1089     ALU64_BEGIN (GPR[RS]);
1090     ALU64_ADD (EXTEND16 (IMMEDIATE));
1091     ALU64_END (GPR[RT]);   /* This checks for overflow.  */
1092   }
1093   TRACE_ALU_RESULT (GPR[RT]);
1094 }
1095
1096
1097
1098 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1099 {
1100   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1101   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1102   TRACE_ALU_RESULT (GPR[rt]);
1103 }
1104
1105 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1106 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1107 *mipsIII:
1108 *mipsIV:
1109 *mipsV:
1110 *mips64:
1111 *vr4100:
1112 *vr5000:
1113 {
1114   check_u64 (SD_, instruction_0);
1115   do_daddiu (SD_, RS, RT, IMMEDIATE);
1116 }
1117
1118
1119
1120 :function:::void:do_daddu:int rs, int rt, int rd
1121 {
1122   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1123   GPR[rd] = GPR[rs] + GPR[rt];
1124   TRACE_ALU_RESULT (GPR[rd]);
1125 }
1126
1127 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1128 "daddu r<RD>, r<RS>, r<RT>"
1129 *mipsIII:
1130 *mipsIV:
1131 *mipsV:
1132 *mips64:
1133 *vr4100:
1134 *vr5000:
1135 {
1136   check_u64 (SD_, instruction_0);
1137   do_daddu (SD_, RS, RT, RD);
1138 }
1139
1140
1141
1142 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1143 "dclo r<RD>, r<RS>"
1144 *mips64:
1145 {
1146   unsigned64 temp = GPR[RS];
1147   unsigned32 i;
1148   unsigned64 mask;
1149   check_u64 (SD_, instruction_0);
1150   if (RT != RD)
1151     Unpredictable ();
1152   TRACE_ALU_INPUT1 (GPR[RS]);
1153   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1154     {
1155       if ((temp & mask) == 0)
1156         break;
1157       mask >>= 1;
1158     }
1159   GPR[RD] = EXTEND32 (i);
1160   TRACE_ALU_RESULT (GPR[RD]);
1161 }
1162
1163
1164
1165 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1166 "dclz r<RD>, r<RS>"
1167 *mips64:
1168 {
1169   unsigned64 temp = GPR[RS];
1170   unsigned32 i;
1171   unsigned64 mask;
1172   check_u64 (SD_, instruction_0);
1173   if (RT != RD)
1174     Unpredictable ();
1175   TRACE_ALU_INPUT1 (GPR[RS]);
1176   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1177     {
1178       if ((temp & mask) != 0)
1179         break;
1180       mask >>= 1;
1181     }
1182   GPR[RD] = EXTEND32 (i);
1183   TRACE_ALU_RESULT (GPR[RD]);
1184 }
1185
1186
1187
1188 :function:::void:do_ddiv:int rs, int rt
1189 {
1190   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1191   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1192   {
1193     signed64 n = GPR[rs];
1194     signed64 d = GPR[rt];
1195     signed64 hi;
1196     signed64 lo;
1197     if (d == 0)
1198       {
1199         lo = SIGNED64 (0x8000000000000000);
1200         hi = 0;
1201       }
1202     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1203       {
1204         lo = SIGNED64 (0x8000000000000000);
1205         hi = 0;
1206       }
1207     else
1208       {
1209         lo = (n / d);
1210         hi = (n % d);
1211       }
1212     HI = hi;
1213     LO = lo;
1214   }
1215   TRACE_ALU_RESULT2 (HI, LO);
1216 }
1217
1218 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1219 "ddiv r<RS>, r<RT>"
1220 *mipsIII:
1221 *mipsIV:
1222 *mipsV:
1223 *mips64:
1224 *vr4100:
1225 *vr5000:
1226 {
1227   check_u64 (SD_, instruction_0);
1228   do_ddiv (SD_, RS, RT);
1229 }
1230
1231
1232
1233 :function:::void:do_ddivu:int rs, int rt
1234 {
1235   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1236   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1237   {
1238     unsigned64 n = GPR[rs];
1239     unsigned64 d = GPR[rt];
1240     unsigned64 hi;
1241     unsigned64 lo;
1242     if (d == 0)
1243       {
1244         lo = SIGNED64 (0x8000000000000000);
1245         hi = 0;
1246       }
1247     else
1248       {
1249         lo = (n / d);
1250         hi = (n % d);
1251       }
1252     HI = hi;
1253     LO = lo;
1254   }
1255   TRACE_ALU_RESULT2 (HI, LO);
1256 }
1257
1258 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1259 "ddivu r<RS>, r<RT>"
1260 *mipsIII:
1261 *mipsIV:
1262 *mipsV:
1263 *mips64:
1264 *vr4100:
1265 *vr5000:
1266 {
1267   check_u64 (SD_, instruction_0);
1268   do_ddivu (SD_, RS, RT);
1269 }
1270
1271
1272
1273 :function:::void:do_div:int rs, int rt
1274 {
1275   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1276   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1277   {
1278     signed32 n = GPR[rs];
1279     signed32 d = GPR[rt];
1280     if (d == 0)
1281       {
1282         LO = EXTEND32 (0x80000000);
1283         HI = EXTEND32 (0);
1284       }
1285     else if (n == SIGNED32 (0x80000000) && d == -1)
1286       {
1287         LO = EXTEND32 (0x80000000);
1288         HI = EXTEND32 (0);
1289       }
1290     else
1291       {
1292         LO = EXTEND32 (n / d);
1293         HI = EXTEND32 (n % d);
1294       }
1295   }
1296   TRACE_ALU_RESULT2 (HI, LO);
1297 }
1298
1299 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1300 "div r<RS>, r<RT>"
1301 *mipsI:
1302 *mipsII:
1303 *mipsIII:
1304 *mipsIV:
1305 *mipsV:
1306 *mips32:
1307 *mips64:
1308 *vr4100:
1309 *vr5000:
1310 *r3900:
1311 {
1312   do_div (SD_, RS, RT);
1313 }
1314
1315
1316
1317 :function:::void:do_divu:int rs, int rt
1318 {
1319   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1320   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1321   {
1322     unsigned32 n = GPR[rs];
1323     unsigned32 d = GPR[rt];
1324     if (d == 0)
1325       {
1326         LO = EXTEND32 (0x80000000);
1327         HI = EXTEND32 (0);
1328       }
1329     else
1330       {
1331         LO = EXTEND32 (n / d);
1332         HI = EXTEND32 (n % d);
1333       }
1334   }
1335   TRACE_ALU_RESULT2 (HI, LO);
1336 }
1337
1338 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1339 "divu r<RS>, r<RT>"
1340 *mipsI:
1341 *mipsII:
1342 *mipsIII:
1343 *mipsIV:
1344 *mipsV:
1345 *mips32:
1346 *mips64:
1347 *vr4100:
1348 *vr5000:
1349 *r3900:
1350 {
1351   do_divu (SD_, RS, RT);
1352 }
1353
1354
1355
1356 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1357 {
1358   unsigned64 lo;
1359   unsigned64 hi;
1360   unsigned64 m00;
1361   unsigned64 m01;
1362   unsigned64 m10;
1363   unsigned64 m11;
1364   unsigned64 mid;
1365   int sign;
1366   unsigned64 op1 = GPR[rs];
1367   unsigned64 op2 = GPR[rt];
1368   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1369   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1370   /* make signed multiply unsigned */
1371   sign = 0;
1372   if (signed_p)
1373     {
1374       if (op1 < 0)
1375         {
1376           op1 = - op1;
1377           ++sign;
1378         }
1379       if (op2 < 0)
1380         {
1381           op2 = - op2;
1382           ++sign;
1383         }
1384     }
1385   /* multiply out the 4 sub products */
1386   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1387   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1388   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1389   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1390   /* add the products */
1391   mid = ((unsigned64) VH4_8 (m00)
1392          + (unsigned64) VL4_8 (m10)
1393          + (unsigned64) VL4_8 (m01));
1394   lo = U8_4 (mid, m00);
1395   hi = (m11
1396         + (unsigned64) VH4_8 (mid)
1397         + (unsigned64) VH4_8 (m01)
1398         + (unsigned64) VH4_8 (m10));
1399   /* fix the sign */
1400   if (sign & 1)
1401     {
1402       lo = -lo;
1403       if (lo == 0)
1404         hi = -hi;
1405       else
1406         hi = -hi - 1;
1407     }
1408   /* save the result HI/LO (and a gpr) */
1409   LO = lo;
1410   HI = hi;
1411   if (rd != 0)
1412     GPR[rd] = lo;
1413   TRACE_ALU_RESULT2 (HI, LO);
1414 }
1415
1416 :function:::void:do_dmult:int rs, int rt, int rd
1417 {
1418   do_dmultx (SD_, rs, rt, rd, 1);
1419 }
1420
1421 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1422 "dmult r<RS>, r<RT>"
1423 *mipsIII:
1424 *mipsIV:
1425 *mipsV:
1426 *mips64:
1427 *vr4100:
1428 {
1429   check_u64 (SD_, instruction_0);
1430   do_dmult (SD_, RS, RT, 0);
1431 }
1432
1433 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1434 "dmult r<RS>, r<RT>":RD == 0
1435 "dmult r<RD>, r<RS>, r<RT>"
1436 *vr5000:
1437 {
1438   check_u64 (SD_, instruction_0);
1439   do_dmult (SD_, RS, RT, RD);
1440 }
1441
1442
1443
1444 :function:::void:do_dmultu:int rs, int rt, int rd
1445 {
1446   do_dmultx (SD_, rs, rt, rd, 0);
1447 }
1448
1449 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1450 "dmultu r<RS>, r<RT>"
1451 *mipsIII:
1452 *mipsIV:
1453 *mipsV:
1454 *mips64:
1455 *vr4100:
1456 {
1457   check_u64 (SD_, instruction_0);
1458   do_dmultu (SD_, RS, RT, 0);
1459 }
1460
1461 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1462 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1463 "dmultu r<RS>, r<RT>"
1464 *vr5000:
1465 {
1466   check_u64 (SD_, instruction_0);
1467   do_dmultu (SD_, RS, RT, RD);
1468 }
1469
1470 :function:::void:do_dsll:int rt, int rd, int shift
1471 {
1472   TRACE_ALU_INPUT2 (GPR[rt], shift);
1473   GPR[rd] = GPR[rt] << shift;
1474   TRACE_ALU_RESULT (GPR[rd]);
1475 }
1476
1477 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1478 "dsll r<RD>, r<RT>, <SHIFT>"
1479 *mipsIII:
1480 *mipsIV:
1481 *mipsV:
1482 *mips64:
1483 *vr4100:
1484 *vr5000:
1485 {
1486   check_u64 (SD_, instruction_0);
1487   do_dsll (SD_, RT, RD, SHIFT);
1488 }
1489
1490
1491 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1492 "dsll32 r<RD>, r<RT>, <SHIFT>"
1493 *mipsIII:
1494 *mipsIV:
1495 *mipsV:
1496 *mips64:
1497 *vr4100:
1498 *vr5000:
1499 {
1500   int s = 32 + SHIFT;
1501   check_u64 (SD_, instruction_0);
1502   TRACE_ALU_INPUT2 (GPR[RT], s);
1503   GPR[RD] = GPR[RT] << s;
1504   TRACE_ALU_RESULT (GPR[RD]);
1505 }
1506
1507 :function:::void:do_dsllv:int rs, int rt, int rd
1508 {
1509   int s = MASKED64 (GPR[rs], 5, 0);
1510   TRACE_ALU_INPUT2 (GPR[rt], s);
1511   GPR[rd] = GPR[rt] << s;
1512   TRACE_ALU_RESULT (GPR[rd]);
1513 }
1514
1515 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1516 "dsllv r<RD>, r<RT>, r<RS>"
1517 *mipsIII:
1518 *mipsIV:
1519 *mipsV:
1520 *mips64:
1521 *vr4100:
1522 *vr5000:
1523 {
1524   check_u64 (SD_, instruction_0);
1525   do_dsllv (SD_, RS, RT, RD);
1526 }
1527
1528 :function:::void:do_dsra:int rt, int rd, int shift
1529 {
1530   TRACE_ALU_INPUT2 (GPR[rt], shift);
1531   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1532   TRACE_ALU_RESULT (GPR[rd]);
1533 }
1534
1535
1536 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1537 "dsra r<RD>, r<RT>, <SHIFT>"
1538 *mipsIII:
1539 *mipsIV:
1540 *mipsV:
1541 *mips64:
1542 *vr4100:
1543 *vr5000:
1544 {
1545   check_u64 (SD_, instruction_0);
1546   do_dsra (SD_, RT, RD, SHIFT);
1547 }
1548
1549
1550 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1551 "dsra32 r<RD>, r<RT>, <SHIFT>"
1552 *mipsIII:
1553 *mipsIV:
1554 *mipsV:
1555 *mips64:
1556 *vr4100:
1557 *vr5000:
1558 {
1559   int s = 32 + SHIFT;
1560   check_u64 (SD_, instruction_0);
1561   TRACE_ALU_INPUT2 (GPR[RT], s);
1562   GPR[RD] = ((signed64) GPR[RT]) >> s;
1563   TRACE_ALU_RESULT (GPR[RD]);
1564 }
1565
1566
1567 :function:::void:do_dsrav:int rs, int rt, int rd
1568 {
1569   int s = MASKED64 (GPR[rs], 5, 0);
1570   TRACE_ALU_INPUT2 (GPR[rt], s);
1571   GPR[rd] = ((signed64) GPR[rt]) >> s;
1572   TRACE_ALU_RESULT (GPR[rd]);
1573 }
1574
1575 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1576 "dsrav r<RD>, r<RT>, r<RS>"
1577 *mipsIII:
1578 *mipsIV:
1579 *mipsV:
1580 *mips64:
1581 *vr4100:
1582 *vr5000:
1583 {
1584   check_u64 (SD_, instruction_0);
1585   do_dsrav (SD_, RS, RT, RD);
1586 }
1587
1588 :function:::void:do_dsrl:int rt, int rd, int shift
1589 {
1590   TRACE_ALU_INPUT2 (GPR[rt], shift);
1591   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1592   TRACE_ALU_RESULT (GPR[rd]);
1593 }
1594
1595
1596 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1597 "dsrl r<RD>, r<RT>, <SHIFT>"
1598 *mipsIII:
1599 *mipsIV:
1600 *mipsV:
1601 *mips64:
1602 *vr4100:
1603 *vr5000:
1604 {
1605   check_u64 (SD_, instruction_0);
1606   do_dsrl (SD_, RT, RD, SHIFT);
1607 }
1608
1609
1610 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1611 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1612 *mipsIII:
1613 *mipsIV:
1614 *mipsV:
1615 *mips64:
1616 *vr4100:
1617 *vr5000:
1618 {
1619   int s = 32 + SHIFT;
1620   check_u64 (SD_, instruction_0);
1621   TRACE_ALU_INPUT2 (GPR[RT], s);
1622   GPR[RD] = (unsigned64) GPR[RT] >> s;
1623   TRACE_ALU_RESULT (GPR[RD]);
1624 }
1625
1626
1627 :function:::void:do_dsrlv:int rs, int rt, int rd
1628 {
1629   int s = MASKED64 (GPR[rs], 5, 0);
1630   TRACE_ALU_INPUT2 (GPR[rt], s);
1631   GPR[rd] = (unsigned64) GPR[rt] >> s;
1632   TRACE_ALU_RESULT (GPR[rd]);
1633 }
1634
1635
1636
1637 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1638 "dsrlv r<RD>, r<RT>, r<RS>"
1639 *mipsIII:
1640 *mipsIV:
1641 *mipsV:
1642 *mips64:
1643 *vr4100:
1644 *vr5000:
1645 {
1646   check_u64 (SD_, instruction_0);
1647   do_dsrlv (SD_, RS, RT, RD);
1648 }
1649
1650
1651 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1652 "dsub r<RD>, r<RS>, r<RT>"
1653 *mipsIII:
1654 *mipsIV:
1655 *mipsV:
1656 *mips64:
1657 *vr4100:
1658 *vr5000:
1659 {
1660   check_u64 (SD_, instruction_0);
1661   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1662   {
1663     ALU64_BEGIN (GPR[RS]);
1664     ALU64_SUB (GPR[RT]);
1665     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1666   }
1667   TRACE_ALU_RESULT (GPR[RD]);
1668 }
1669
1670
1671 :function:::void:do_dsubu:int rs, int rt, int rd
1672 {
1673   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1674   GPR[rd] = GPR[rs] - GPR[rt];
1675   TRACE_ALU_RESULT (GPR[rd]);
1676 }
1677
1678 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1679 "dsubu r<RD>, r<RS>, r<RT>"
1680 *mipsIII:
1681 *mipsIV:
1682 *mipsV:
1683 *mips64:
1684 *vr4100:
1685 *vr5000:
1686 {
1687   check_u64 (SD_, instruction_0);
1688   do_dsubu (SD_, RS, RT, RD);
1689 }
1690
1691
1692 000010,26.INSTR_INDEX:NORMAL:32::J
1693 "j <INSTR_INDEX>"
1694 *mipsI:
1695 *mipsII:
1696 *mipsIII:
1697 *mipsIV:
1698 *mipsV:
1699 *mips32:
1700 *mips64:
1701 *vr4100:
1702 *vr5000:
1703 *r3900:
1704 {
1705   /* NOTE: The region used is that of the delay slot NIA and NOT the
1706      current instruction */
1707   address_word region = (NIA & MASK (63, 28));
1708   DELAY_SLOT (region | (INSTR_INDEX << 2));
1709 }
1710
1711
1712 000011,26.INSTR_INDEX:NORMAL:32::JAL
1713 "jal <INSTR_INDEX>"
1714 *mipsI:
1715 *mipsII:
1716 *mipsIII:
1717 *mipsIV:
1718 *mipsV:
1719 *mips32:
1720 *mips64:
1721 *vr4100:
1722 *vr5000:
1723 *r3900:
1724 {
1725   /* NOTE: The region used is that of the delay slot and NOT the
1726      current instruction */
1727   address_word region = (NIA & MASK (63, 28));
1728   GPR[31] = CIA + 8;
1729   DELAY_SLOT (region | (INSTR_INDEX << 2));
1730 }
1731
1732 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1733 "jalr r<RS>":RD == 31
1734 "jalr r<RD>, r<RS>"
1735 *mipsI:
1736 *mipsII:
1737 *mipsIII:
1738 *mipsIV:
1739 *mipsV:
1740 *mips32:
1741 *mips64:
1742 *vr4100:
1743 *vr5000:
1744 *r3900:
1745 {
1746   address_word temp = GPR[RS];
1747   GPR[RD] = CIA + 8;
1748   DELAY_SLOT (temp);
1749 }
1750
1751
1752 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1753 "jr r<RS>"
1754 *mipsI:
1755 *mipsII:
1756 *mipsIII:
1757 *mipsIV:
1758 *mipsV:
1759 *mips32:
1760 *mips64:
1761 *vr4100:
1762 *vr5000:
1763 *r3900:
1764 {
1765   DELAY_SLOT (GPR[RS]);
1766 }
1767
1768
1769 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1770 {
1771   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1772   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1773   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1774   unsigned int byte;
1775   address_word paddr;
1776   int uncached;
1777   unsigned64 memval;
1778   address_word vaddr;
1779
1780   vaddr = loadstore_ea (SD_, base, offset);
1781   if ((vaddr & access) != 0)
1782     {
1783       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1784     }
1785   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1786   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1787   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1788   byte = ((vaddr & mask) ^ bigendiancpu);
1789   return (memval >> (8 * byte));
1790 }
1791
1792 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1793 {
1794   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1795   address_word reverseendian = (ReverseEndian ? -1 : 0);
1796   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1797   unsigned int byte;
1798   unsigned int word;
1799   address_word paddr;
1800   int uncached;
1801   unsigned64 memval;
1802   address_word vaddr;
1803   int nr_lhs_bits;
1804   int nr_rhs_bits;
1805   unsigned_word lhs_mask;
1806   unsigned_word temp;
1807
1808   vaddr = loadstore_ea (SD_, base, offset);
1809   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1810   paddr = (paddr ^ (reverseendian & mask));
1811   if (BigEndianMem == 0)
1812     paddr = paddr & ~access;
1813
1814   /* compute where within the word/mem we are */
1815   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1816   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1817   nr_lhs_bits = 8 * byte + 8;
1818   nr_rhs_bits = 8 * access - 8 * byte;
1819   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1820
1821   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1822            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1823            (long) ((unsigned64) paddr >> 32), (long) paddr,
1824            word, byte, nr_lhs_bits, nr_rhs_bits); */
1825
1826   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1827   if (word == 0)
1828     {
1829       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1830       temp = (memval << nr_rhs_bits);
1831     }
1832   else
1833     {
1834       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1835       temp = (memval >> nr_lhs_bits);
1836     }
1837   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1838   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1839
1840   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1841            (long) ((unsigned64) memval >> 32), (long) memval,
1842            (long) ((unsigned64) temp >> 32), (long) temp,
1843            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1844            (long) (rt >> 32), (long) rt); */
1845   return rt;
1846 }
1847
1848 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1849 {
1850   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1851   address_word reverseendian = (ReverseEndian ? -1 : 0);
1852   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1853   unsigned int byte;
1854   address_word paddr;
1855   int uncached;
1856   unsigned64 memval;
1857   address_word vaddr;
1858
1859   vaddr = loadstore_ea (SD_, base, offset);
1860   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1861   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1862   paddr = (paddr ^ (reverseendian & mask));
1863   if (BigEndianMem != 0)
1864     paddr = paddr & ~access;
1865   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1866   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
1867   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1868   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1869      (long) paddr, byte, (long) paddr, (long) memval); */
1870   {
1871     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1872     rt &= ~screen;
1873     rt |= (memval >> (8 * byte)) & screen;
1874   }
1875   return rt;
1876 }
1877
1878
1879 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1880 "lb r<RT>, <OFFSET>(r<BASE>)"
1881 *mipsI:
1882 *mipsII:
1883 *mipsIII:
1884 *mipsIV:
1885 *mipsV:
1886 *mips32:
1887 *mips64:
1888 *vr4100:
1889 *vr5000:
1890 *r3900:
1891 {
1892   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1893 }
1894
1895
1896 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1897 "lbu r<RT>, <OFFSET>(r<BASE>)"
1898 *mipsI:
1899 *mipsII:
1900 *mipsIII:
1901 *mipsIV:
1902 *mipsV:
1903 *mips32:
1904 *mips64:
1905 *vr4100:
1906 *vr5000:
1907 *r3900:
1908 {
1909   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1910 }
1911
1912
1913 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1914 "ld r<RT>, <OFFSET>(r<BASE>)"
1915 *mipsIII:
1916 *mipsIV:
1917 *mipsV:
1918 *mips64:
1919 *vr4100:
1920 *vr5000:
1921 {
1922   check_u64 (SD_, instruction_0);
1923   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1924 }
1925
1926
1927 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1928 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1929 *mipsII:
1930 *mipsIII:
1931 *mipsIV:
1932 *mipsV:
1933 *mips32:
1934 *mips64:
1935 *vr4100:
1936 *vr5000:
1937 *r3900:
1938 {
1939   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1940 }
1941
1942
1943
1944
1945 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1946 "ldl r<RT>, <OFFSET>(r<BASE>)"
1947 *mipsIII:
1948 *mipsIV:
1949 *mipsV:
1950 *mips64:
1951 *vr4100:
1952 *vr5000:
1953 {
1954   check_u64 (SD_, instruction_0);
1955   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1956 }
1957
1958
1959 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1960 "ldr r<RT>, <OFFSET>(r<BASE>)"
1961 *mipsIII:
1962 *mipsIV:
1963 *mipsV:
1964 *mips64:
1965 *vr4100:
1966 *vr5000:
1967 {
1968   check_u64 (SD_, instruction_0);
1969   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1970 }
1971
1972
1973 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1974 "lh r<RT>, <OFFSET>(r<BASE>)"
1975 *mipsI:
1976 *mipsII:
1977 *mipsIII:
1978 *mipsIV:
1979 *mipsV:
1980 *mips32:
1981 *mips64:
1982 *vr4100:
1983 *vr5000:
1984 *r3900:
1985 {
1986   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1987 }
1988
1989
1990 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1991 "lhu r<RT>, <OFFSET>(r<BASE>)"
1992 *mipsI:
1993 *mipsII:
1994 *mipsIII:
1995 *mipsIV:
1996 *mipsV:
1997 *mips32:
1998 *mips64:
1999 *vr4100:
2000 *vr5000:
2001 *r3900:
2002 {
2003   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2004 }
2005
2006
2007 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2008 "ll r<RT>, <OFFSET>(r<BASE>)"
2009 *mipsII:
2010 *mipsIII:
2011 *mipsIV:
2012 *mipsV:
2013 *mips32:
2014 *mips64:
2015 *vr4100:
2016 *vr5000:
2017 {
2018   address_word base = GPR[BASE];
2019   address_word offset = EXTEND16 (OFFSET);
2020   {
2021     address_word vaddr = loadstore_ea (SD_, base, offset);
2022     address_word paddr;
2023     int uncached;
2024     if ((vaddr & 3) != 0)
2025       {
2026         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2027       }
2028     else
2029       {
2030         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2031           {
2032             unsigned64 memval = 0;
2033             unsigned64 memval1 = 0;
2034             unsigned64 mask = 0x7;
2035             unsigned int shift = 2;
2036             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2037             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2038             unsigned int byte;
2039             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2040             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2041             byte = ((vaddr & mask) ^ (bigend << shift));
2042             GPR[RT] = EXTEND32 (memval >> (8 * byte));
2043             LLBIT = 1;
2044           }
2045       }
2046   }
2047 }
2048
2049
2050 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2051 "lld r<RT>, <OFFSET>(r<BASE>)"
2052 *mipsIII:
2053 *mipsIV:
2054 *mipsV:
2055 *mips64:
2056 *vr4100:
2057 *vr5000:
2058 {
2059   address_word base = GPR[BASE];
2060   address_word offset = EXTEND16 (OFFSET);
2061   check_u64 (SD_, instruction_0);
2062   {
2063     address_word vaddr = loadstore_ea (SD_, base, offset);
2064     address_word paddr;
2065     int uncached;
2066     if ((vaddr & 7) != 0)
2067       {
2068         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2069       }
2070     else
2071       {
2072         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2073           {
2074             unsigned64 memval = 0;
2075             unsigned64 memval1 = 0;
2076             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2077             GPR[RT] = memval;
2078             LLBIT = 1;
2079           }
2080       }
2081   }
2082 }
2083
2084
2085 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2086 "lui r<RT>, %#lx<IMMEDIATE>"
2087 *mipsI:
2088 *mipsII:
2089 *mipsIII:
2090 *mipsIV:
2091 *mipsV:
2092 *mips32:
2093 *mips64:
2094 *vr4100:
2095 *vr5000:
2096 *r3900:
2097 {
2098   TRACE_ALU_INPUT1 (IMMEDIATE);
2099   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2100   TRACE_ALU_RESULT (GPR[RT]);
2101 }
2102
2103
2104 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2105 "lw r<RT>, <OFFSET>(r<BASE>)"
2106 *mipsI:
2107 *mipsII:
2108 *mipsIII:
2109 *mipsIV:
2110 *mipsV:
2111 *mips32:
2112 *mips64:
2113 *vr4100:
2114 *vr5000:
2115 *r3900:
2116 {
2117   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2118 }
2119
2120
2121 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2122 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2123 *mipsI:
2124 *mipsII:
2125 *mipsIII:
2126 *mipsIV:
2127 *mipsV:
2128 *mips32:
2129 *mips64:
2130 *vr4100:
2131 *vr5000:
2132 *r3900:
2133 {
2134   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2135 }
2136
2137
2138 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2139 "lwl r<RT>, <OFFSET>(r<BASE>)"
2140 *mipsI:
2141 *mipsII:
2142 *mipsIII:
2143 *mipsIV:
2144 *mipsV:
2145 *mips32:
2146 *mips64:
2147 *vr4100:
2148 *vr5000:
2149 *r3900:
2150 {
2151   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2152 }
2153
2154
2155 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2156 "lwr r<RT>, <OFFSET>(r<BASE>)"
2157 *mipsI:
2158 *mipsII:
2159 *mipsIII:
2160 *mipsIV:
2161 *mipsV:
2162 *mips32:
2163 *mips64:
2164 *vr4100:
2165 *vr5000:
2166 *r3900:
2167 {
2168   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2169 }
2170
2171
2172 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2173 "lwu r<RT>, <OFFSET>(r<BASE>)"
2174 *mipsIII:
2175 *mipsIV:
2176 *mipsV:
2177 *mips64:
2178 *vr4100:
2179 *vr5000:
2180 {
2181   check_u64 (SD_, instruction_0);
2182   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2183 }
2184
2185
2186
2187 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2188 "madd r<RS>, r<RT>"
2189 *mips32:
2190 *mips64:
2191 {
2192   signed64 temp;
2193   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2194   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2195     Unpredictable ();
2196   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2197   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2198           + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2199   LO = EXTEND32 (temp);
2200   HI = EXTEND32 (VH4_8 (temp));
2201   TRACE_ALU_RESULT2 (HI, LO);
2202 }
2203
2204
2205
2206 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2207 "maddu r<RS>, r<RT>"
2208 *mips32:
2209 *mips64:
2210 {
2211   unsigned64 temp;
2212   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2213   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2214     Unpredictable ();
2215   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2216   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2217           + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2218   LO = EXTEND32 (temp);
2219   HI = EXTEND32 (VH4_8 (temp));
2220   TRACE_ALU_RESULT2 (HI, LO);
2221 }
2222
2223
2224 :function:::void:do_mfhi:int rd
2225 {
2226   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2227   TRACE_ALU_INPUT1 (HI);
2228   GPR[rd] = HI;
2229   TRACE_ALU_RESULT (GPR[rd]);
2230 }
2231
2232 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2233 "mfhi r<RD>"
2234 *mipsI:
2235 *mipsII:
2236 *mipsIII:
2237 *mipsIV:
2238 *mipsV:
2239 *mips32:
2240 *mips64:
2241 *vr4100:
2242 *vr5000:
2243 *r3900:
2244 {
2245   do_mfhi (SD_, RD);
2246 }
2247
2248
2249
2250 :function:::void:do_mflo:int rd
2251 {
2252   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2253   TRACE_ALU_INPUT1 (LO);
2254   GPR[rd] = LO;
2255   TRACE_ALU_RESULT (GPR[rd]);
2256 }
2257
2258 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2259 "mflo r<RD>"
2260 *mipsI:
2261 *mipsII:
2262 *mipsIII:
2263 *mipsIV:
2264 *mipsV:
2265 *mips32:
2266 *mips64:
2267 *vr4100:
2268 *vr5000:
2269 *r3900:
2270 {
2271   do_mflo (SD_, RD);
2272 }
2273
2274
2275
2276 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2277 "movn r<RD>, r<RS>, r<RT>"
2278 *mipsIV:
2279 *mipsV:
2280 *mips32:
2281 *mips64:
2282 *vr5000:
2283 {
2284   if (GPR[RT] != 0)
2285     GPR[RD] = GPR[RS];
2286 }
2287
2288
2289
2290 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2291 "movz r<RD>, r<RS>, r<RT>"
2292 *mipsIV:
2293 *mipsV:
2294 *mips32:
2295 *mips64:
2296 *vr5000:
2297 {
2298   if (GPR[RT] == 0)
2299     GPR[RD] = GPR[RS];
2300 }
2301
2302
2303
2304 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2305 "msub r<RS>, r<RT>"
2306 *mips32:
2307 *mips64:
2308 {
2309   signed64 temp;
2310   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2311   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2312     Unpredictable ();
2313   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2314   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2315           - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2316   LO = EXTEND32 (temp);
2317   HI = EXTEND32 (VH4_8 (temp));
2318   TRACE_ALU_RESULT2 (HI, LO);
2319 }
2320
2321
2322
2323 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2324 "msubu r<RS>, r<RT>"
2325 *mips32:
2326 *mips64:
2327 {
2328   unsigned64 temp;
2329   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2330   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2331     Unpredictable ();
2332   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2333   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2334           - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2335   LO = EXTEND32 (temp);
2336   HI = EXTEND32 (VH4_8 (temp));
2337   TRACE_ALU_RESULT2 (HI, LO);
2338 }
2339
2340
2341
2342 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2343 "mthi r<RS>"
2344 *mipsI:
2345 *mipsII:
2346 *mipsIII:
2347 *mipsIV:
2348 *mipsV:
2349 *mips32:
2350 *mips64:
2351 *vr4100:
2352 *vr5000:
2353 *r3900:
2354 {
2355   check_mt_hilo (SD_, HIHISTORY);
2356   HI = GPR[RS];
2357 }
2358
2359
2360
2361 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2362 "mtlo r<RS>"
2363 *mipsI:
2364 *mipsII:
2365 *mipsIII:
2366 *mipsIV:
2367 *mipsV:
2368 *mips32:
2369 *mips64:
2370 *vr4100:
2371 *vr5000:
2372 *r3900:
2373 {
2374   check_mt_hilo (SD_, LOHISTORY);
2375   LO = GPR[RS];
2376 }
2377
2378
2379
2380 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2381 "mul r<RD>, r<RS>, r<RT>"
2382 *mips32:
2383 *mips64:
2384 {
2385   signed64 prod;
2386   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2387     Unpredictable ();
2388   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2389   prod = (((signed64)(signed32) GPR[RS])
2390           * ((signed64)(signed32) GPR[RT]));
2391   GPR[RD] = EXTEND32 (VL4_8 (prod));
2392   TRACE_ALU_RESULT (GPR[RD]);
2393 }
2394
2395
2396
2397 :function:::void:do_mult:int rs, int rt, int rd
2398 {
2399   signed64 prod;
2400   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2401   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2402     Unpredictable ();
2403   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2404   prod = (((signed64)(signed32) GPR[rs])
2405           * ((signed64)(signed32) GPR[rt]));
2406   LO = EXTEND32 (VL4_8 (prod));
2407   HI = EXTEND32 (VH4_8 (prod));
2408   if (rd != 0)
2409     GPR[rd] = LO;
2410   TRACE_ALU_RESULT2 (HI, LO);
2411 }
2412
2413 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2414 "mult r<RS>, r<RT>"
2415 *mipsI:
2416 *mipsII:
2417 *mipsIII:
2418 *mipsIV:
2419 *mipsV:
2420 *mips32:
2421 *mips64:
2422 *vr4100:
2423 {
2424   do_mult (SD_, RS, RT, 0);
2425 }
2426
2427
2428 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2429 "mult r<RS>, r<RT>":RD == 0
2430 "mult r<RD>, r<RS>, r<RT>"
2431 *vr5000:
2432 *r3900:
2433 {
2434   do_mult (SD_, RS, RT, RD);
2435 }
2436
2437
2438 :function:::void:do_multu:int rs, int rt, int rd
2439 {
2440   unsigned64 prod;
2441   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2442   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2443     Unpredictable ();
2444   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2445   prod = (((unsigned64)(unsigned32) GPR[rs])
2446           * ((unsigned64)(unsigned32) GPR[rt]));
2447   LO = EXTEND32 (VL4_8 (prod));
2448   HI = EXTEND32 (VH4_8 (prod));
2449   if (rd != 0)
2450     GPR[rd] = LO;
2451   TRACE_ALU_RESULT2 (HI, LO);
2452 }
2453
2454 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2455 "multu r<RS>, r<RT>"
2456 *mipsI:
2457 *mipsII:
2458 *mipsIII:
2459 *mipsIV:
2460 *mipsV:
2461 *mips32:
2462 *mips64:
2463 *vr4100:
2464 {
2465   do_multu (SD_, RS, RT, 0);
2466 }
2467
2468 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2469 "multu r<RS>, r<RT>":RD == 0
2470 "multu r<RD>, r<RS>, r<RT>"
2471 *vr5000:
2472 *r3900:
2473 {
2474   do_multu (SD_, RS, RT, RD);
2475 }
2476
2477
2478 :function:::void:do_nor:int rs, int rt, int rd
2479 {
2480   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2481   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2482   TRACE_ALU_RESULT (GPR[rd]);
2483 }
2484
2485 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2486 "nor r<RD>, r<RS>, r<RT>"
2487 *mipsI:
2488 *mipsII:
2489 *mipsIII:
2490 *mipsIV:
2491 *mipsV:
2492 *mips32:
2493 *mips64:
2494 *vr4100:
2495 *vr5000:
2496 *r3900:
2497 {
2498   do_nor (SD_, RS, RT, RD);
2499 }
2500
2501
2502 :function:::void:do_or:int rs, int rt, int rd
2503 {
2504   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2505   GPR[rd] = (GPR[rs] | GPR[rt]);
2506   TRACE_ALU_RESULT (GPR[rd]);
2507 }
2508
2509 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2510 "or r<RD>, r<RS>, r<RT>"
2511 *mipsI:
2512 *mipsII:
2513 *mipsIII:
2514 *mipsIV:
2515 *mipsV:
2516 *mips32:
2517 *mips64:
2518 *vr4100:
2519 *vr5000:
2520 *r3900:
2521 {
2522   do_or (SD_, RS, RT, RD);
2523 }
2524
2525
2526
2527 :function:::void:do_ori:int rs, int rt, unsigned immediate
2528 {
2529   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2530   GPR[rt] = (GPR[rs] | immediate);
2531   TRACE_ALU_RESULT (GPR[rt]);
2532 }
2533
2534 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2535 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2536 *mipsI:
2537 *mipsII:
2538 *mipsIII:
2539 *mipsIV:
2540 *mipsV:
2541 *mips32:
2542 *mips64:
2543 *vr4100:
2544 *vr5000:
2545 *r3900:
2546 {
2547   do_ori (SD_, RS, RT, IMMEDIATE);
2548 }
2549
2550
2551 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2552 "pref <HINT>, <OFFSET>(r<BASE>)"
2553 *mipsIV:
2554 *mipsV:
2555 *mips32:
2556 *mips64:
2557 *vr5000:
2558 {
2559   address_word base = GPR[BASE];
2560   address_word offset = EXTEND16 (OFFSET);
2561   {
2562     address_word vaddr = loadstore_ea (SD_, base, offset);
2563     address_word paddr;
2564     int uncached;
2565     {
2566       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2567         Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2568     }
2569   }
2570 }
2571
2572
2573 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2574 {
2575   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2576   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2577   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2578   unsigned int byte;
2579   address_word paddr;
2580   int uncached;
2581   unsigned64 memval;
2582   address_word vaddr;
2583
2584   vaddr = loadstore_ea (SD_, base, offset);
2585   if ((vaddr & access) != 0)
2586     {
2587       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2588     }
2589   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2590   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2591   byte = ((vaddr & mask) ^ bigendiancpu);
2592   memval = (word << (8 * byte));
2593   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2594 }
2595
2596 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2597 {
2598   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2599   address_word reverseendian = (ReverseEndian ? -1 : 0);
2600   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2601   unsigned int byte;
2602   unsigned int word;
2603   address_word paddr;
2604   int uncached;
2605   unsigned64 memval;
2606   address_word vaddr;
2607   int nr_lhs_bits;
2608   int nr_rhs_bits;
2609
2610   vaddr = loadstore_ea (SD_, base, offset);
2611   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2612   paddr = (paddr ^ (reverseendian & mask));
2613   if (BigEndianMem == 0)
2614     paddr = paddr & ~access;
2615
2616   /* compute where within the word/mem we are */
2617   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2618   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2619   nr_lhs_bits = 8 * byte + 8;
2620   nr_rhs_bits = 8 * access - 8 * byte;
2621   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2622   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2623            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2624            (long) ((unsigned64) paddr >> 32), (long) paddr,
2625            word, byte, nr_lhs_bits, nr_rhs_bits); */
2626
2627   if (word == 0)
2628     {
2629       memval = (rt >> nr_rhs_bits);
2630     }
2631   else
2632     {
2633       memval = (rt << nr_lhs_bits);
2634     }
2635   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2636            (long) ((unsigned64) rt >> 32), (long) rt,
2637            (long) ((unsigned64) memval >> 32), (long) memval); */
2638   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2639 }
2640
2641 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2642 {
2643   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2644   address_word reverseendian = (ReverseEndian ? -1 : 0);
2645   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2646   unsigned int byte;
2647   address_word paddr;
2648   int uncached;
2649   unsigned64 memval;
2650   address_word vaddr;
2651
2652   vaddr = loadstore_ea (SD_, base, offset);
2653   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2654   paddr = (paddr ^ (reverseendian & mask));
2655   if (BigEndianMem != 0)
2656     paddr &= ~access;
2657   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2658   memval = (rt << (byte * 8));
2659   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2660 }
2661
2662
2663 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2664 "sb r<RT>, <OFFSET>(r<BASE>)"
2665 *mipsI:
2666 *mipsII:
2667 *mipsIII:
2668 *mipsIV:
2669 *mipsV:
2670 *mips32:
2671 *mips64:
2672 *vr4100:
2673 *vr5000:
2674 *r3900:
2675 {
2676   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2677 }
2678
2679
2680 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2681 "sc r<RT>, <OFFSET>(r<BASE>)"
2682 *mipsII:
2683 *mipsIII:
2684 *mipsIV:
2685 *mipsV:
2686 *mips32:
2687 *mips64:
2688 *vr4100:
2689 *vr5000:
2690 {
2691   unsigned32 instruction = instruction_0;
2692   address_word base = GPR[BASE];
2693   address_word offset = EXTEND16 (OFFSET);
2694   {
2695     address_word vaddr = loadstore_ea (SD_, base, offset);
2696     address_word paddr;
2697     int uncached;
2698     if ((vaddr & 3) != 0)
2699       {
2700         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2701       }
2702     else
2703       {
2704         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2705           {
2706             unsigned64 memval = 0;
2707             unsigned64 memval1 = 0;
2708             unsigned64 mask = 0x7;
2709             unsigned int byte;
2710             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2711             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2712             memval = ((unsigned64) GPR[RT] << (8 * byte));
2713             if (LLBIT)
2714               {
2715                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2716               }
2717             GPR[RT] = LLBIT;
2718           }
2719       }
2720   }
2721 }
2722
2723
2724 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2725 "scd r<RT>, <OFFSET>(r<BASE>)"
2726 *mipsIII:
2727 *mipsIV:
2728 *mipsV:
2729 *mips64:
2730 *vr4100:
2731 *vr5000:
2732 {
2733   address_word base = GPR[BASE];
2734   address_word offset = EXTEND16 (OFFSET);
2735   check_u64 (SD_, instruction_0);
2736   {
2737     address_word vaddr = loadstore_ea (SD_, base, offset);
2738     address_word paddr;
2739     int uncached;
2740     if ((vaddr & 7) != 0)
2741       {
2742         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2743       }
2744     else
2745       {
2746         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2747           {
2748             unsigned64 memval = 0;
2749             unsigned64 memval1 = 0;
2750             memval = GPR[RT];
2751             if (LLBIT)
2752               {
2753                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2754               }
2755             GPR[RT] = LLBIT;
2756           }
2757       }
2758   }
2759 }
2760
2761
2762 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2763 "sd r<RT>, <OFFSET>(r<BASE>)"
2764 *mipsIII:
2765 *mipsIV:
2766 *mipsV:
2767 *mips64:
2768 *vr4100:
2769 *vr5000:
2770 {
2771   check_u64 (SD_, instruction_0);
2772   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2773 }
2774
2775
2776 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2777 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2778 *mipsII:
2779 *mipsIII:
2780 *mipsIV:
2781 *mipsV:
2782 *mips32:
2783 *mips64:
2784 *vr4100:
2785 *vr5000:
2786 {
2787   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2788 }
2789
2790
2791 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2792 "sdl r<RT>, <OFFSET>(r<BASE>)"
2793 *mipsIII:
2794 *mipsIV:
2795 *mipsV:
2796 *mips64:
2797 *vr4100:
2798 *vr5000:
2799 {
2800   check_u64 (SD_, instruction_0);
2801   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2802 }
2803
2804
2805 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2806 "sdr r<RT>, <OFFSET>(r<BASE>)"
2807 *mipsIII:
2808 *mipsIV:
2809 *mipsV:
2810 *mips64:
2811 *vr4100:
2812 *vr5000:
2813 {
2814   check_u64 (SD_, instruction_0);
2815   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2816 }
2817
2818
2819 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2820 "sh r<RT>, <OFFSET>(r<BASE>)"
2821 *mipsI:
2822 *mipsII:
2823 *mipsIII:
2824 *mipsIV:
2825 *mipsV:
2826 *mips32:
2827 *mips64:
2828 *vr4100:
2829 *vr5000:
2830 *r3900:
2831 {
2832   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2833 }
2834
2835
2836 :function:::void:do_sll:int rt, int rd, int shift
2837 {
2838   unsigned32 temp = (GPR[rt] << shift);
2839   TRACE_ALU_INPUT2 (GPR[rt], shift);
2840   GPR[rd] = EXTEND32 (temp);
2841   TRACE_ALU_RESULT (GPR[rd]);
2842 }
2843
2844 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
2845 "nop":RD == 0 && RT == 0 && SHIFT == 0
2846 "sll r<RD>, r<RT>, <SHIFT>"
2847 *mipsI:
2848 *mipsII:
2849 *mipsIII:
2850 *mipsIV:
2851 *mipsV:
2852 *vr4100:
2853 *vr5000:
2854 *r3900:
2855 {
2856   /* Skip shift for NOP, so that there won't be lots of extraneous
2857      trace output.  */
2858   if (RD != 0 || RT != 0 || SHIFT != 0)
2859     do_sll (SD_, RT, RD, SHIFT);
2860 }
2861
2862 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
2863 "nop":RD == 0 && RT == 0 && SHIFT == 0
2864 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
2865 "sll r<RD>, r<RT>, <SHIFT>"
2866 *mips32:
2867 *mips64:
2868 {
2869   /* Skip shift for NOP and SSNOP, so that there won't be lots of
2870      extraneous trace output.  */
2871   if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
2872     do_sll (SD_, RT, RD, SHIFT);
2873 }
2874
2875
2876 :function:::void:do_sllv:int rs, int rt, int rd
2877 {
2878   int s = MASKED (GPR[rs], 4, 0);
2879   unsigned32 temp = (GPR[rt] << s);
2880   TRACE_ALU_INPUT2 (GPR[rt], s);
2881   GPR[rd] = EXTEND32 (temp);
2882   TRACE_ALU_RESULT (GPR[rd]);
2883 }
2884
2885 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
2886 "sllv r<RD>, r<RT>, r<RS>"
2887 *mipsI:
2888 *mipsII:
2889 *mipsIII:
2890 *mipsIV:
2891 *mipsV:
2892 *mips32:
2893 *mips64:
2894 *vr4100:
2895 *vr5000:
2896 *r3900:
2897 {
2898   do_sllv (SD_, RS, RT, RD);
2899 }
2900
2901
2902 :function:::void:do_slt:int rs, int rt, int rd
2903 {
2904   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2905   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2906   TRACE_ALU_RESULT (GPR[rd]);
2907 }
2908
2909 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
2910 "slt r<RD>, r<RS>, r<RT>"
2911 *mipsI:
2912 *mipsII:
2913 *mipsIII:
2914 *mipsIV:
2915 *mipsV:
2916 *mips32:
2917 *mips64:
2918 *vr4100:
2919 *vr5000:
2920 *r3900:
2921 {
2922   do_slt (SD_, RS, RT, RD);
2923 }
2924
2925
2926 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2927 {
2928   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2929   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2930   TRACE_ALU_RESULT (GPR[rt]);
2931 }
2932
2933 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2934 "slti r<RT>, r<RS>, <IMMEDIATE>"
2935 *mipsI:
2936 *mipsII:
2937 *mipsIII:
2938 *mipsIV:
2939 *mipsV:
2940 *mips32:
2941 *mips64:
2942 *vr4100:
2943 *vr5000:
2944 *r3900:
2945 {
2946   do_slti (SD_, RS, RT, IMMEDIATE);
2947 }
2948
2949
2950 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2951 {
2952   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2953   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2954   TRACE_ALU_RESULT (GPR[rt]);
2955 }
2956
2957 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2958 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2959 *mipsI:
2960 *mipsII:
2961 *mipsIII:
2962 *mipsIV:
2963 *mipsV:
2964 *mips32:
2965 *mips64:
2966 *vr4100:
2967 *vr5000:
2968 *r3900:
2969 {
2970   do_sltiu (SD_, RS, RT, IMMEDIATE);
2971 }
2972
2973
2974
2975 :function:::void:do_sltu:int rs, int rt, int rd
2976 {
2977   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2978   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2979   TRACE_ALU_RESULT (GPR[rd]);
2980 }
2981
2982 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
2983 "sltu r<RD>, r<RS>, r<RT>"
2984 *mipsI:
2985 *mipsII:
2986 *mipsIII:
2987 *mipsIV:
2988 *mipsV:
2989 *mips32:
2990 *mips64:
2991 *vr4100:
2992 *vr5000:
2993 *r3900:
2994 {
2995   do_sltu (SD_, RS, RT, RD);
2996 }
2997
2998
2999 :function:::void:do_sra:int rt, int rd, int shift
3000 {
3001   signed32 temp = (signed32) GPR[rt] >> shift;
3002   if (NotWordValue (GPR[rt]))
3003     Unpredictable ();
3004   TRACE_ALU_INPUT2 (GPR[rt], shift);
3005   GPR[rd] = EXTEND32 (temp);
3006   TRACE_ALU_RESULT (GPR[rd]);
3007 }
3008
3009 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3010 "sra r<RD>, r<RT>, <SHIFT>"
3011 *mipsI:
3012 *mipsII:
3013 *mipsIII:
3014 *mipsIV:
3015 *mipsV:
3016 *mips32:
3017 *mips64:
3018 *vr4100:
3019 *vr5000:
3020 *r3900:
3021 {
3022   do_sra (SD_, RT, RD, SHIFT);
3023 }
3024
3025
3026
3027 :function:::void:do_srav:int rs, int rt, int rd
3028 {
3029   int s = MASKED (GPR[rs], 4, 0);
3030   signed32 temp = (signed32) GPR[rt] >> s;
3031   if (NotWordValue (GPR[rt]))
3032     Unpredictable ();
3033   TRACE_ALU_INPUT2 (GPR[rt], s);
3034   GPR[rd] = EXTEND32 (temp);
3035   TRACE_ALU_RESULT (GPR[rd]);
3036 }
3037
3038 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3039 "srav r<RD>, r<RT>, r<RS>"
3040 *mipsI:
3041 *mipsII:
3042 *mipsIII:
3043 *mipsIV:
3044 *mipsV:
3045 *mips32:
3046 *mips64:
3047 *vr4100:
3048 *vr5000:
3049 *r3900:
3050 {
3051   do_srav (SD_, RS, RT, RD);
3052 }
3053
3054
3055
3056 :function:::void:do_srl:int rt, int rd, int shift
3057 {
3058   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3059   if (NotWordValue (GPR[rt]))
3060     Unpredictable ();
3061   TRACE_ALU_INPUT2 (GPR[rt], shift);
3062   GPR[rd] = EXTEND32 (temp);
3063   TRACE_ALU_RESULT (GPR[rd]);
3064 }
3065
3066 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3067 "srl r<RD>, r<RT>, <SHIFT>"
3068 *mipsI:
3069 *mipsII:
3070 *mipsIII:
3071 *mipsIV:
3072 *mipsV:
3073 *mips32:
3074 *mips64:
3075 *vr4100:
3076 *vr5000:
3077 *r3900:
3078 {
3079   do_srl (SD_, RT, RD, SHIFT);
3080 }
3081
3082
3083 :function:::void:do_srlv:int rs, int rt, int rd
3084 {
3085   int s = MASKED (GPR[rs], 4, 0);
3086   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3087   if (NotWordValue (GPR[rt]))
3088     Unpredictable ();
3089   TRACE_ALU_INPUT2 (GPR[rt], s);
3090   GPR[rd] = EXTEND32 (temp);
3091   TRACE_ALU_RESULT (GPR[rd]);
3092 }
3093
3094 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3095 "srlv r<RD>, r<RT>, r<RS>"
3096 *mipsI:
3097 *mipsII:
3098 *mipsIII:
3099 *mipsIV:
3100 *mipsV:
3101 *mips32:
3102 *mips64:
3103 *vr4100:
3104 *vr5000:
3105 *r3900:
3106 {
3107   do_srlv (SD_, RS, RT, RD);
3108 }
3109
3110
3111 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3112 "sub r<RD>, r<RS>, r<RT>"
3113 *mipsI:
3114 *mipsII:
3115 *mipsIII:
3116 *mipsIV:
3117 *mipsV:
3118 *mips32:
3119 *mips64:
3120 *vr4100:
3121 *vr5000:
3122 *r3900:
3123 {
3124   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3125     Unpredictable ();
3126   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3127   {
3128     ALU32_BEGIN (GPR[RS]);
3129     ALU32_SUB (GPR[RT]);
3130     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
3131   }
3132   TRACE_ALU_RESULT (GPR[RD]);
3133 }
3134
3135
3136 :function:::void:do_subu:int rs, int rt, int rd
3137 {
3138   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3139     Unpredictable ();
3140   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3141   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3142   TRACE_ALU_RESULT (GPR[rd]);
3143 }
3144
3145 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3146 "subu r<RD>, r<RS>, r<RT>"
3147 *mipsI:
3148 *mipsII:
3149 *mipsIII:
3150 *mipsIV:
3151 *mipsV:
3152 *mips32:
3153 *mips64:
3154 *vr4100:
3155 *vr5000:
3156 *r3900:
3157 {
3158   do_subu (SD_, RS, RT, RD);
3159 }
3160
3161
3162 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3163 "sw r<RT>, <OFFSET>(r<BASE>)"
3164 *mipsI:
3165 *mipsII:
3166 *mipsIII:
3167 *mipsIV:
3168 *mipsV:
3169 *mips32:
3170 *mips64:
3171 *vr4100:
3172 *r3900:
3173 *vr5000:
3174 {
3175   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3176 }
3177
3178
3179 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3180 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3181 *mipsI:
3182 *mipsII:
3183 *mipsIII:
3184 *mipsIV:
3185 *mipsV:
3186 *mips32:
3187 *mips64:
3188 *vr4100:
3189 *vr5000:
3190 *r3900:
3191 {
3192   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3193 }
3194
3195
3196 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3197 "swl r<RT>, <OFFSET>(r<BASE>)"
3198 *mipsI:
3199 *mipsII:
3200 *mipsIII:
3201 *mipsIV:
3202 *mipsV:
3203 *mips32:
3204 *mips64:
3205 *vr4100:
3206 *vr5000:
3207 *r3900:
3208 {
3209   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3210 }
3211
3212
3213 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3214 "swr r<RT>, <OFFSET>(r<BASE>)"
3215 *mipsI:
3216 *mipsII:
3217 *mipsIII:
3218 *mipsIV:
3219 *mipsV:
3220 *mips32:
3221 *mips64:
3222 *vr4100:
3223 *vr5000:
3224 *r3900:
3225 {
3226   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3227 }
3228
3229
3230 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3231 "sync":STYPE == 0
3232 "sync <STYPE>"
3233 *mipsII:
3234 *mipsIII:
3235 *mipsIV:
3236 *mipsV:
3237 *mips32:
3238 *mips64:
3239 *vr4100:
3240 *vr5000:
3241 *r3900:
3242 {
3243   SyncOperation (STYPE);
3244 }
3245
3246
3247 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3248 "syscall %#lx<CODE>"
3249 *mipsI:
3250 *mipsII:
3251 *mipsIII:
3252 *mipsIV:
3253 *mipsV:
3254 *mips32:
3255 *mips64:
3256 *vr4100:
3257 *vr5000:
3258 *r3900:
3259 {
3260   SignalException (SystemCall, instruction_0);
3261 }
3262
3263
3264 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3265 "teq r<RS>, r<RT>"
3266 *mipsII:
3267 *mipsIII:
3268 *mipsIV:
3269 *mipsV:
3270 *mips32:
3271 *mips64:
3272 *vr4100:
3273 *vr5000:
3274 {
3275   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3276     SignalException (Trap, instruction_0);
3277 }
3278
3279
3280 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3281 "teqi r<RS>, <IMMEDIATE>"
3282 *mipsII:
3283 *mipsIII:
3284 *mipsIV:
3285 *mipsV:
3286 *mips32:
3287 *mips64:
3288 *vr4100:
3289 *vr5000:
3290 {
3291   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3292     SignalException (Trap, instruction_0);
3293 }
3294
3295
3296 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3297 "tge r<RS>, r<RT>"
3298 *mipsII:
3299 *mipsIII:
3300 *mipsIV:
3301 *mipsV:
3302 *mips32:
3303 *mips64:
3304 *vr4100:
3305 *vr5000:
3306 {
3307   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3308     SignalException (Trap, instruction_0);
3309 }
3310
3311
3312 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3313 "tgei r<RS>, <IMMEDIATE>"
3314 *mipsII:
3315 *mipsIII:
3316 *mipsIV:
3317 *mipsV:
3318 *mips32:
3319 *mips64:
3320 *vr4100:
3321 *vr5000:
3322 {
3323   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3324     SignalException (Trap, instruction_0);
3325 }
3326
3327
3328 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3329 "tgeiu r<RS>, <IMMEDIATE>"
3330 *mipsII:
3331 *mipsIII:
3332 *mipsIV:
3333 *mipsV:
3334 *mips32:
3335 *mips64:
3336 *vr4100:
3337 *vr5000:
3338 {
3339   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3340     SignalException (Trap, instruction_0);
3341 }
3342
3343
3344 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3345 "tgeu r<RS>, r<RT>"
3346 *mipsII:
3347 *mipsIII:
3348 *mipsIV:
3349 *mipsV:
3350 *mips32:
3351 *mips64:
3352 *vr4100:
3353 *vr5000:
3354 {
3355   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3356     SignalException (Trap, instruction_0);
3357 }
3358
3359
3360 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3361 "tlt r<RS>, r<RT>"
3362 *mipsII:
3363 *mipsIII:
3364 *mipsIV:
3365 *mipsV:
3366 *mips32:
3367 *mips64:
3368 *vr4100:
3369 *vr5000:
3370 {
3371   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3372     SignalException (Trap, instruction_0);
3373 }
3374
3375
3376 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3377 "tlti r<RS>, <IMMEDIATE>"
3378 *mipsII:
3379 *mipsIII:
3380 *mipsIV:
3381 *mipsV:
3382 *mips32:
3383 *mips64:
3384 *vr4100:
3385 *vr5000:
3386 {
3387   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3388     SignalException (Trap, instruction_0);
3389 }
3390
3391
3392 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3393 "tltiu r<RS>, <IMMEDIATE>"
3394 *mipsII:
3395 *mipsIII:
3396 *mipsIV:
3397 *mipsV:
3398 *mips32:
3399 *mips64:
3400 *vr4100:
3401 *vr5000:
3402 {
3403   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3404     SignalException (Trap, instruction_0);
3405 }
3406
3407
3408 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3409 "tltu r<RS>, r<RT>"
3410 *mipsII:
3411 *mipsIII:
3412 *mipsIV:
3413 *mipsV:
3414 *mips32:
3415 *mips64:
3416 *vr4100:
3417 *vr5000:
3418 {
3419   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3420     SignalException (Trap, instruction_0);
3421 }
3422
3423
3424 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3425 "tne r<RS>, r<RT>"
3426 *mipsII:
3427 *mipsIII:
3428 *mipsIV:
3429 *mipsV:
3430 *mips32:
3431 *mips64:
3432 *vr4100:
3433 *vr5000:
3434 {
3435   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3436     SignalException (Trap, instruction_0);
3437 }
3438
3439
3440 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3441 "tne r<RS>, <IMMEDIATE>"
3442 *mipsII:
3443 *mipsIII:
3444 *mipsIV:
3445 *mipsV:
3446 *mips32:
3447 *mips64:
3448 *vr4100:
3449 *vr5000:
3450 {
3451   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3452     SignalException (Trap, instruction_0);
3453 }
3454
3455
3456 :function:::void:do_xor:int rs, int rt, int rd
3457 {
3458   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3459   GPR[rd] = GPR[rs] ^ GPR[rt];
3460   TRACE_ALU_RESULT (GPR[rd]);
3461 }
3462
3463 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3464 "xor r<RD>, r<RS>, r<RT>"
3465 *mipsI:
3466 *mipsII:
3467 *mipsIII:
3468 *mipsIV:
3469 *mipsV:
3470 *mips32:
3471 *mips64:
3472 *vr4100:
3473 *vr5000:
3474 *r3900:
3475 {
3476   do_xor (SD_, RS, RT, RD);
3477 }
3478
3479
3480 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3481 {
3482   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3483   GPR[rt] = GPR[rs] ^ immediate;
3484   TRACE_ALU_RESULT (GPR[rt]);
3485 }
3486
3487 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3488 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3489 *mipsI:
3490 *mipsII:
3491 *mipsIII:
3492 *mipsIV:
3493 *mipsV:
3494 *mips32:
3495 *mips64:
3496 *vr4100:
3497 *vr5000:
3498 *r3900:
3499 {
3500   do_xori (SD_, RS, RT, IMMEDIATE);
3501 }
3502
3503 \f
3504 //
3505 // MIPS Architecture:
3506 //
3507 //        FPU Instruction Set (COP1 & COP1X)
3508 //
3509
3510
3511 :%s::::FMT:int fmt
3512 {
3513   switch (fmt)
3514     {
3515     case fmt_single: return "s";
3516     case fmt_double: return "d";
3517     case fmt_word: return "w";
3518     case fmt_long: return "l";
3519     default: return "?";
3520     }
3521 }
3522
3523 :%s::::X:int x
3524 {
3525   switch (x)
3526     {
3527     case 0: return "f";
3528     case 1: return "t";
3529     default: return "?";
3530     }
3531 }
3532
3533 :%s::::TF:int tf
3534 {
3535   if (tf)
3536     return "t";
3537   else
3538     return "f";
3539 }
3540
3541 :%s::::ND:int nd
3542 {
3543   if (nd)
3544     return "l";
3545   else
3546     return "";
3547 }
3548
3549 :%s::::COND:int cond
3550 {
3551   switch (cond)
3552     {
3553     case 00: return "f";
3554     case 01: return "un";
3555     case 02: return "eq";
3556     case 03: return "ueq";
3557     case 04: return "olt";
3558     case 05: return "ult";
3559     case 06: return "ole";
3560     case 07: return "ule";
3561     case 010: return "sf";
3562     case 011: return "ngle";
3563     case 012: return "seq";
3564     case 013: return "ngl";
3565     case 014: return "lt";
3566     case 015: return "nge";
3567     case 016: return "le";
3568     case 017: return "ngt";
3569     default: return "?";
3570     }
3571 }
3572
3573
3574 // Helpers:
3575 //
3576 // Check that the given FPU format is usable, and signal a
3577 // ReservedInstruction exception if not.
3578 //
3579
3580 // check_fmt checks that the format is single or double.
3581 :function:::void:check_fmt:int fmt, instruction_word insn
3582 *mipsI:
3583 *mipsII:
3584 *mipsIII:
3585 *mipsIV:
3586 *mipsV:
3587 *mips32:
3588 *mips64:
3589 *vr4100:
3590 *vr5000:
3591 *r3900:
3592 {
3593   if ((fmt != fmt_single) && (fmt != fmt_double))
3594     SignalException (ReservedInstruction, insn);
3595 }
3596
3597 // check_fmt_p checks that the format is single, double, or paired single.
3598 :function:::void:check_fmt_p:int fmt, instruction_word insn
3599 *mipsI:
3600 *mipsII:
3601 *mipsIII:
3602 *mipsIV:
3603 *mips32:
3604 *vr4100:
3605 *vr5000:
3606 *r3900:
3607 {
3608   /* None of these ISAs support Paired Single, so just fall back to
3609      the single/double check.  */
3610   check_fmt (SD_, fmt, insn);
3611 }
3612
3613 :function:::void:check_fmt_p:int fmt, instruction_word insn
3614 *mipsV:
3615 *mips64:
3616 {
3617 #if 0 /* XXX FIXME: FP code doesn't yet support paired single ops.  */
3618   if ((fmt != fmt_single) && (fmt != fmt_double)
3619       && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3620     SignalException (ReservedInstruction, insn);
3621 #else
3622   check_fmt (SD_, fmt, insn);
3623 #endif
3624 }
3625
3626
3627 // Helper:
3628 //
3629 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3630 // exception if not.
3631 //
3632
3633 :function:::void:check_fpu:
3634 *mipsI:
3635 *mipsII:
3636 *mipsIII:
3637 *mipsIV:
3638 *mipsV:
3639 *mips32:
3640 *mips64:
3641 *vr4100:
3642 *vr5000:
3643 *r3900:
3644 {
3645   if (! COP_Usable (1))
3646     SignalExceptionCoProcessorUnusable (1);
3647 }
3648
3649
3650 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3651 "abs.%s<FMT> f<FD>, f<FS>"
3652 *mipsI:
3653 *mipsII:
3654 *mipsIII:
3655 *mipsIV:
3656 *mipsV:
3657 *mips32:
3658 *mips64:
3659 *vr4100:
3660 *vr5000:
3661 *r3900:
3662 {
3663   int fmt = FMT;
3664   check_fpu (SD_);
3665   check_fmt_p (SD_, fmt, instruction_0);
3666   StoreFPR(FD,fmt,AbsoluteValue(ValueFPR(FS,fmt),fmt));
3667 }
3668
3669
3670
3671 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3672 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3673 *mipsI:
3674 *mipsII:
3675 *mipsIII:
3676 *mipsIV:
3677 *mipsV:
3678 *mips32:
3679 *mips64:
3680 *vr4100:
3681 *vr5000:
3682 *r3900:
3683 {
3684   int fmt = FMT;
3685   check_fpu (SD_);
3686   check_fmt_p (SD_, fmt, instruction_0);
3687   StoreFPR(FD,fmt,Add(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
3688 }
3689
3690
3691
3692 // BC1F
3693 // BC1FL
3694 // BC1T
3695 // BC1TL
3696
3697 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3698 "bc1%s<TF>%s<ND> <OFFSET>"
3699 *mipsI:
3700 *mipsII:
3701 *mipsIII:
3702 {
3703   check_fpu (SD_);
3704   check_branch_bug ();
3705   TRACE_BRANCH_INPUT (PREVCOC1());
3706   if (PREVCOC1() == TF)
3707     {
3708       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3709       TRACE_BRANCH_RESULT (dest);
3710       mark_branch_bug (dest);
3711       DELAY_SLOT (dest);
3712     }
3713   else if (ND)
3714     {
3715       TRACE_BRANCH_RESULT (0);
3716       NULLIFY_NEXT_INSTRUCTION ();
3717     }
3718   else
3719     {
3720       TRACE_BRANCH_RESULT (NIA);
3721     }
3722 }
3723
3724 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3725 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3726 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3727 *mipsIV:
3728 *mipsV:
3729 *mips32:
3730 *mips64:
3731 #*vr4100:
3732 *vr5000:
3733 *r3900:
3734 {
3735   check_fpu (SD_);
3736   check_branch_bug ();
3737   if (GETFCC(CC) == TF)
3738     {
3739       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3740       mark_branch_bug (dest);
3741       DELAY_SLOT (dest);
3742     }
3743   else if (ND)
3744     {
3745       NULLIFY_NEXT_INSTRUCTION ();
3746     }
3747 }
3748
3749
3750
3751
3752
3753
3754 // C.EQ.S
3755 // C.EQ.D
3756 // ...
3757
3758 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3759 {
3760   int less;
3761   int equal;
3762   int unordered;
3763   int condition;
3764   unsigned64 ofs = ValueFPR (fs, fmt);
3765   unsigned64 oft = ValueFPR (ft, fmt);
3766   if (NaN (ofs, fmt) || NaN (oft, fmt))
3767     {
3768       if (FCSR & FP_ENABLE (IO))
3769         {
3770           FCSR |= FP_CAUSE (IO);
3771           SignalExceptionFPE ();
3772         }
3773       less = 0;
3774       equal = 0;
3775       unordered = 1;
3776     }
3777   else
3778     {
3779       less = Less (ofs, oft, fmt);
3780       equal = Equal (ofs, oft, fmt);
3781       unordered = 0;
3782     }
3783   condition = (((cond & (1 << 2)) && less)
3784                || ((cond & (1 << 1)) && equal)
3785                || ((cond & (1 << 0)) && unordered));
3786   SETFCC (cc, condition);
3787 }
3788
3789 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
3790 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
3791 *mipsI:
3792 *mipsII:
3793 *mipsIII:
3794 {
3795   int fmt = FMT;
3796   check_fpu (SD_);
3797   check_fmt_p (SD_, fmt, instruction_0);
3798   do_c_cond_fmt (SD_, fmt, FT, FS, 0, COND, instruction_0);
3799 }
3800
3801 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
3802 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3803 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3804 *mipsIV:
3805 *mipsV:
3806 *mips32:
3807 *mips64:
3808 *vr4100:
3809 *vr5000:
3810 *r3900:
3811 {
3812   int fmt = FMT;
3813   check_fpu (SD_);
3814   check_fmt_p (SD_, fmt, instruction_0);
3815   do_c_cond_fmt (SD_, fmt, FT, FS, CC, COND, instruction_0);
3816 }
3817
3818
3819 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
3820 "ceil.l.%s<FMT> f<FD>, f<FS>"
3821 *mipsIII:
3822 *mipsIV:
3823 *mipsV:
3824 *mips64:
3825 *vr4100:
3826 *vr5000:
3827 *r3900:
3828 {
3829   int fmt = FMT;
3830   check_fpu (SD_);
3831   check_fmt (SD_, fmt, instruction_0);
3832   StoreFPR(FD,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_long));
3833 }
3834
3835
3836 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
3837 *mipsII:
3838 *mipsIII:
3839 *mipsIV:
3840 *mipsV:
3841 *mips32:
3842 *mips64:
3843 *vr4100:
3844 *vr5000:
3845 *r3900:
3846 {
3847   int fmt = FMT;
3848   check_fpu (SD_);
3849   check_fmt (SD_, fmt, instruction_0);
3850   StoreFPR(FD,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_word));
3851 }
3852
3853
3854 // CFC1
3855 // CTC1
3856 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32,f::CxC1
3857 "c%s<X>c1 r<RT>, f<FS>"
3858 *mipsI:
3859 *mipsII:
3860 *mipsIII:
3861 {
3862   check_fpu (SD_);
3863   if (X)
3864     {
3865       if (FS == 0)
3866         PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
3867       else if (FS == 31)
3868         PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
3869       /* else NOP */
3870       PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
3871     }
3872   else
3873     { /* control from */
3874       if (FS == 0)
3875         PENDING_FILL(RT, EXTEND32 (FCR0));
3876       else if (FS == 31)
3877         PENDING_FILL(RT, EXTEND32 (FCR31));
3878       /* else NOP */
3879     }
3880 }
3881 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32,f::CxC1
3882 "c%s<X>c1 r<RT>, f<FS>"
3883 *mipsIV:
3884 *mipsV:
3885 *mips32:
3886 *mips64:
3887 *vr4100:
3888 *vr5000:
3889 *r3900:
3890 {
3891   check_fpu (SD_);
3892   if (X)
3893     {
3894       /* control to */
3895       TRACE_ALU_INPUT1 (GPR[RT]);
3896       if (FS == 0)
3897         {
3898           FCR0 = VL4_8(GPR[RT]);
3899           TRACE_ALU_RESULT (FCR0);
3900         }
3901       else if (FS == 31)
3902         {
3903           FCR31 = VL4_8(GPR[RT]);
3904           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3905           TRACE_ALU_RESULT (FCR31);
3906         }
3907       else
3908         {
3909           TRACE_ALU_RESULT0 ();
3910         }
3911       /* else NOP */
3912     }
3913   else
3914     { /* control from */
3915       if (FS == 0)
3916         {
3917           TRACE_ALU_INPUT1 (FCR0);
3918           GPR[RT] = EXTEND32 (FCR0);
3919         }
3920       else if (FS == 31)
3921         {
3922           TRACE_ALU_INPUT1 (FCR31);
3923           GPR[RT] = EXTEND32 (FCR31);
3924         }
3925       TRACE_ALU_RESULT (GPR[RT]);
3926       /* else NOP */
3927     }
3928 }
3929
3930
3931 //
3932 // FIXME: Does not correctly differentiate between mips*
3933 //
3934 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
3935 "cvt.d.%s<FMT> f<FD>, f<FS>"
3936 *mipsI:
3937 *mipsII:
3938 *mipsIII:
3939 *mipsIV:
3940 *mipsV:
3941 *mips32:
3942 *mips64:
3943 *vr4100:
3944 *vr5000:
3945 *r3900:
3946 {
3947   int fmt = FMT;
3948   check_fpu (SD_);
3949   {
3950     if ((fmt == fmt_double) | 0)
3951       SignalException (ReservedInstruction, instruction_0);
3952     else
3953       StoreFPR(FD,fmt_double,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_double));
3954   }
3955 }
3956
3957
3958 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
3959 "cvt.l.%s<FMT> f<FD>, f<FS>"
3960 *mipsIII:
3961 *mipsIV:
3962 *mipsV:
3963 *mips64:
3964 *vr4100:
3965 *vr5000:
3966 *r3900:
3967 {
3968   int fmt = FMT;
3969   check_fpu (SD_);
3970   {
3971     if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
3972       SignalException (ReservedInstruction, instruction_0);
3973     else
3974       StoreFPR(FD,fmt_long,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_long));
3975   }
3976 }
3977
3978
3979 //
3980 // FIXME: Does not correctly differentiate between mips*
3981 //
3982 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
3983 "cvt.s.%s<FMT> f<FD>, f<FS>"
3984 *mipsI:
3985 *mipsII:
3986 *mipsIII:
3987 *mipsIV:
3988 *mipsV:
3989 *mips32:
3990 *mips64:
3991 *vr4100:
3992 *vr5000:
3993 *r3900:
3994 {
3995   int fmt = FMT;
3996   check_fpu (SD_);
3997   {
3998     if ((fmt == fmt_single) | 0)
3999       SignalException (ReservedInstruction, instruction_0);
4000     else
4001       StoreFPR(FD,fmt_single,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_single));
4002   }
4003 }
4004
4005
4006 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4007 "cvt.w.%s<FMT> f<FD>, f<FS>"
4008 *mipsI:
4009 *mipsII:
4010 *mipsIII:
4011 *mipsIV:
4012 *mipsV:
4013 *mips32:
4014 *mips64:
4015 *vr4100:
4016 *vr5000:
4017 *r3900:
4018 {
4019   int fmt = FMT;
4020   check_fpu (SD_);
4021   {
4022     if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4023       SignalException (ReservedInstruction, instruction_0);
4024     else
4025       StoreFPR(FD,fmt_word,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_word));
4026   }
4027 }
4028
4029
4030 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4031 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4032 *mipsI:
4033 *mipsII:
4034 *mipsIII:
4035 *mipsIV:
4036 *mipsV:
4037 *mips32:
4038 *mips64:
4039 *vr4100:
4040 *vr5000:
4041 *r3900:
4042 {
4043   int fmt = FMT;
4044   check_fpu (SD_);
4045   check_fmt (SD_, fmt, instruction_0);
4046   StoreFPR(FD,fmt,Divide(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
4047 }
4048
4049
4050 // DMFC1
4051 // DMTC1
4052 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64,f::DMxC1
4053 "dm%s<X>c1 r<RT>, f<FS>"
4054 *mipsIII:
4055 {
4056   check_fpu (SD_);
4057   check_u64 (SD_, instruction_0);
4058   if (X)
4059     {
4060       if (SizeFGR() == 64)
4061         PENDING_FILL((FS + FGR_BASE),GPR[RT]);
4062       else if ((FS & 0x1) == 0)
4063         {
4064           PENDING_FILL(((FS + 1) + FGR_BASE),VH4_8(GPR[RT]));
4065           PENDING_FILL((FS + FGR_BASE),VL4_8(GPR[RT]));
4066         }
4067     }
4068   else
4069     {
4070       if (SizeFGR() == 64)
4071         PENDING_FILL(RT,FGR[FS]);
4072       else if ((FS & 0x1) == 0)
4073         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4074       else
4075         {
4076           if (STATE_VERBOSE_P(SD))
4077             sim_io_eprintf (SD,
4078               "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
4079               (long) CIA);
4080           PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4081         }
4082     }
4083 }
4084 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64,f::DMxC1
4085 "dm%s<X>c1 r<RT>, f<FS>"
4086 *mipsIV:
4087 *mipsV:
4088 *mips64:
4089 *vr4100:
4090 *vr5000:
4091 *r3900:
4092 {
4093   check_fpu (SD_);
4094   check_u64 (SD_, instruction_0);
4095   if (X)
4096     {
4097       if (SizeFGR() == 64)
4098         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4099       else if ((FS & 0x1) == 0)
4100         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4101     }
4102   else
4103     {
4104       if (SizeFGR() == 64)
4105         GPR[RT] = FGR[FS];
4106       else if ((FS & 0x1) == 0)
4107         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4108       else
4109         {
4110           if (STATE_VERBOSE_P(SD))
4111             sim_io_eprintf (SD,
4112               "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
4113                             (long) CIA);
4114           GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4115         }
4116     }
4117 }
4118
4119
4120 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4121 "floor.l.%s<FMT> f<FD>, f<FS>"
4122 *mipsIII:
4123 *mipsIV:
4124 *mipsV:
4125 *mips64:
4126 *vr4100:
4127 *vr5000:
4128 *r3900:
4129 {
4130   int fmt = FMT;
4131   check_fpu (SD_);
4132   check_fmt (SD_, fmt, instruction_0);
4133   StoreFPR(FD,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_long));
4134 }
4135
4136
4137 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4138 "floor.w.%s<FMT> f<FD>, f<FS>"
4139 *mipsII:
4140 *mipsIII:
4141 *mipsIV:
4142 *mipsV:
4143 *mips32:
4144 *mips64:
4145 *vr4100:
4146 *vr5000:
4147 *r3900:
4148 {
4149   int fmt = FMT;
4150   check_fpu (SD_);
4151   check_fmt (SD_, fmt, instruction_0);
4152   StoreFPR(FD,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_word));
4153 }
4154
4155
4156 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
4157 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4158 *mipsII:
4159 *mipsIII:
4160 *mipsIV:
4161 *mipsV:
4162 *mips32:
4163 *mips64:
4164 *vr4100:
4165 *vr5000:
4166 *r3900:
4167 {
4168   check_fpu (SD_);
4169   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4170 }
4171
4172
4173 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4174 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4175 *mipsIV:
4176 *mipsV:
4177 *mips64:
4178 *vr5000:
4179 {
4180   check_fpu (SD_);
4181   check_u64 (SD_, instruction_0);
4182   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4183 }
4184
4185
4186
4187 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4188 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4189 *mipsI:
4190 *mipsII:
4191 *mipsIII:
4192 *mipsIV:
4193 *mipsV:
4194 *mips32:
4195 *mips64:
4196 *vr4100:
4197 *vr5000:
4198 *r3900:
4199 {
4200   check_fpu (SD_);
4201   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4202 }
4203
4204
4205 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4206 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4207 *mipsIV:
4208 *mipsV:
4209 *mips64:
4210 *vr5000:
4211 {
4212   check_fpu (SD_);
4213   check_u64 (SD_, instruction_0);
4214   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4215 }
4216
4217
4218
4219 //
4220 // FIXME: Not correct for mips*
4221 //
4222 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4223 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4224 *mipsIV:
4225 *mipsV:
4226 *mips64:
4227 *vr5000:
4228 {
4229   check_fpu (SD_);
4230   {
4231     StoreFPR(FD,fmt_double,Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
4232   }
4233 }
4234
4235
4236 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4237 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4238 *mipsIV:
4239 *mipsV:
4240 *mips64:
4241 *vr5000:
4242 {
4243   check_fpu (SD_);
4244   {
4245     StoreFPR(FD,fmt_single,Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
4246   }
4247 }
4248
4249
4250 // MFC1
4251 // MTC1
4252 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32,f::MxC1
4253 "m%s<X>c1 r<RT>, f<FS>"
4254 *mipsI:
4255 *mipsII:
4256 *mipsIII:
4257 {
4258   check_fpu (SD_);
4259   if (X)
4260     { /*MTC1*/
4261       if (SizeFGR() == 64)
4262         {
4263           if (STATE_VERBOSE_P(SD))
4264             sim_io_eprintf (SD,
4265                             "Warning:  PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
4266                             (long) CIA);
4267           PENDING_FILL ((FS + FGR_BASE), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4268         }
4269       else
4270         PENDING_FILL ((FS + FGR_BASE), VL4_8(GPR[RT]));
4271     }
4272   else /*MFC1*/
4273     PENDING_FILL (RT, EXTEND32 (FGR[FS]));
4274 }
4275 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1
4276 "m%s<X>c1 r<RT>, f<FS>"
4277 *mipsIV:
4278 *mipsV:
4279 *mips32:
4280 *mips64:
4281 *vr4100:
4282 *vr5000:
4283 *r3900:
4284 {
4285   int fs = FS;
4286   check_fpu (SD_);
4287   if (X)
4288     /*MTC1*/
4289     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4290   else /*MFC1*/
4291     GPR[RT] = EXTEND32 (FGR[FS]);
4292 }
4293
4294
4295 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4296 "mov.%s<FMT> f<FD>, f<FS>"
4297 *mipsI:
4298 *mipsII:
4299 *mipsIII:
4300 *mipsIV:
4301 *mipsV:
4302 *mips32:
4303 *mips64:
4304 *vr4100:
4305 *vr5000:
4306 *r3900:
4307 {
4308   int fmt = FMT;
4309   check_fpu (SD_);
4310   check_fmt_p (SD_, fmt, instruction_0);
4311   StoreFPR(FD,fmt,ValueFPR(FS,fmt));
4312 }
4313
4314
4315 // MOVF
4316 // MOVT
4317 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4318 "mov%s<TF> r<RD>, r<RS>, <CC>"
4319 *mipsIV:
4320 *mipsV:
4321 *mips32:
4322 *mips64:
4323 *vr5000:
4324 {
4325   check_fpu (SD_);
4326   if (GETFCC(CC) == TF)
4327     GPR[RD] = GPR[RS];
4328 }
4329
4330
4331 // MOVF.fmt
4332 // MOVT.fmt
4333 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4334 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4335 *mipsIV:
4336 *mipsV:
4337 *mips32:
4338 *mips64:
4339 *vr5000:
4340 {
4341   int fmt = FMT;
4342   check_fpu (SD_);
4343   {
4344    if (GETFCC(CC) == TF)
4345      StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4346    else
4347      StoreFPR (FD, fmt, ValueFPR (FD, fmt));
4348   }
4349 }
4350
4351
4352 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4353 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4354 *mipsIV:
4355 *mipsV:
4356 *mips32:
4357 *mips64:
4358 *vr5000:
4359 {
4360   check_fpu (SD_);
4361   if (GPR[RT] != 0)
4362     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4363   else
4364     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4365 }
4366
4367
4368 // MOVT see MOVtf
4369
4370
4371 // MOVT.fmt see MOVtf.fmt
4372
4373
4374
4375 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4376 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4377 *mipsIV:
4378 *mipsV:
4379 *mips32:
4380 *mips64:
4381 *vr5000:
4382 {
4383   check_fpu (SD_);
4384   if (GPR[RT] == 0)
4385     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4386   else
4387     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4388 }
4389
4390
4391 // MSUB.fmt
4392 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32,f::MSUB.D
4393 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4394 *mipsIV:
4395 *mipsV:
4396 *mips64:
4397 *vr5000:
4398 {
4399   check_fpu (SD_);
4400   StoreFPR(FD,fmt_double,Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
4401 }
4402
4403
4404 // MSUB.fmt
4405 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32,f::MSUB.S
4406 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4407 *mipsIV:
4408 *mipsV:
4409 *mips64:
4410 *vr5000:
4411 {
4412   check_fpu (SD_);
4413   StoreFPR(FD,fmt_single,Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
4414 }
4415
4416
4417 // MTC1 see MxC1
4418
4419
4420 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4421 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4422 *mipsI:
4423 *mipsII:
4424 *mipsIII:
4425 *mipsIV:
4426 *mipsV:
4427 *mips32:
4428 *mips64:
4429 *vr4100:
4430 *vr5000:
4431 *r3900:
4432 {
4433   int fmt = FMT;
4434   check_fpu (SD_);
4435   check_fmt_p (SD_, fmt, instruction_0);
4436   StoreFPR(FD,fmt,Multiply(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
4437 }
4438
4439
4440 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4441 "neg.%s<FMT> f<FD>, f<FS>"
4442 *mipsI:
4443 *mipsII:
4444 *mipsIII:
4445 *mipsIV:
4446 *mipsV:
4447 *mips32:
4448 *mips64:
4449 *vr4100:
4450 *vr5000:
4451 *r3900:
4452 {
4453   int fmt = FMT;
4454   check_fpu (SD_);
4455   check_fmt_p (SD_, fmt, instruction_0);
4456   StoreFPR(FD,fmt,Negate(ValueFPR(FS,fmt),fmt));
4457 }
4458
4459
4460 // NMADD.fmt
4461 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32,f::NMADD.D
4462 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4463 *mipsIV:
4464 *mipsV:
4465 *mips64:
4466 *vr5000:
4467 {
4468   check_fpu (SD_);
4469   StoreFPR(FD,fmt_double,Negate(Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
4470 }
4471
4472
4473 // NMADD.fmt
4474 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32,f::NMADD.S
4475 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4476 *mipsIV:
4477 *mipsV:
4478 *mips64:
4479 *vr5000:
4480 {
4481   check_fpu (SD_);
4482   StoreFPR(FD,fmt_single,Negate(Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
4483 }
4484
4485
4486 // NMSUB.fmt
4487 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32,f::NMSUB.D
4488 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4489 *mipsIV:
4490 *mipsV:
4491 *mips64:
4492 *vr5000:
4493 {
4494   check_fpu (SD_);
4495   StoreFPR(FD,fmt_double,Negate(Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
4496 }
4497
4498
4499 // NMSUB.fmt
4500 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32,f::NMSUB.S
4501 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4502 *mipsIV:
4503 *mipsV:
4504 *mips64:
4505 *vr5000:
4506 {
4507   check_fpu (SD_);
4508   StoreFPR(FD,fmt_single,Negate(Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
4509 }
4510
4511
4512 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
4513 "prefx <HINT>, r<INDEX>(r<BASE>)"
4514 *mipsIV:
4515 *mipsV:
4516 *mips64:
4517 *vr5000:
4518 {
4519   address_word base = GPR[BASE];
4520   address_word index = GPR[INDEX];
4521   {
4522     address_word vaddr = loadstore_ea (SD_, base, index);
4523     address_word paddr;
4524     int uncached;
4525     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4526       Prefetch(uncached,paddr,vaddr,isDATA,HINT);
4527   }
4528 }
4529
4530 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
4531 "recip.%s<FMT> f<FD>, f<FS>"
4532 *mipsIV:
4533 *mipsV:
4534 *mips64:
4535 *vr5000:
4536 {
4537   int fmt = FMT;
4538   check_fpu (SD_);
4539   check_fmt (SD_, fmt, instruction_0);
4540   StoreFPR(FD,fmt,Recip(ValueFPR(FS,fmt),fmt));
4541 }
4542
4543
4544 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
4545 "round.l.%s<FMT> f<FD>, f<FS>"
4546 *mipsIII:
4547 *mipsIV:
4548 *mipsV:
4549 *mips64:
4550 *vr4100:
4551 *vr5000:
4552 *r3900:
4553 {
4554   int fmt = FMT;
4555   check_fpu (SD_);
4556   check_fmt (SD_, fmt, instruction_0);
4557   StoreFPR(FD,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_long));
4558 }
4559
4560
4561 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
4562 "round.w.%s<FMT> f<FD>, f<FS>"
4563 *mipsII:
4564 *mipsIII:
4565 *mipsIV:
4566 *mipsV:
4567 *mips32:
4568 *mips64:
4569 *vr4100:
4570 *vr5000:
4571 *r3900:
4572 {
4573   int fmt = FMT;
4574   check_fpu (SD_);
4575   check_fmt (SD_, fmt, instruction_0);
4576   StoreFPR(FD,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_word));
4577 }
4578
4579
4580 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
4581 *mipsIV:
4582 *mipsV:
4583 *mips64:
4584 "rsqrt.%s<FMT> f<FD>, f<FS>"
4585 *vr5000:
4586 {
4587   int fmt = FMT;
4588   check_fpu (SD_);
4589   check_fmt (SD_, fmt, instruction_0);
4590   StoreFPR(FD,fmt,Recip(SquareRoot(ValueFPR(FS,fmt),fmt),fmt));
4591 }
4592
4593
4594 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
4595 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4596 *mipsII:
4597 *mipsIII:
4598 *mipsIV:
4599 *mipsV:
4600 *mips32:
4601 *mips64:
4602 *vr4100:
4603 *vr5000:
4604 *r3900:
4605 {
4606   check_fpu (SD_);
4607   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4608 }
4609
4610
4611 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
4612 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
4613 *mipsIV:
4614 *mipsV:
4615 *mips64:
4616 *vr5000:
4617 {
4618   check_fpu (SD_);
4619   check_u64 (SD_, instruction_0);
4620   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4621 }
4622
4623
4624 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
4625 "sqrt.%s<FMT> f<FD>, f<FS>"
4626 *mipsII:
4627 *mipsIII:
4628 *mipsIV:
4629 *mipsV:
4630 *mips32:
4631 *mips64:
4632 *vr4100:
4633 *vr5000:
4634 *r3900:
4635 {
4636   int fmt = FMT;
4637   check_fpu (SD_);
4638   check_fmt (SD_, fmt, instruction_0);
4639   StoreFPR(FD,fmt,(SquareRoot(ValueFPR(FS,fmt),fmt)));
4640 }
4641
4642
4643 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
4644 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4645 *mipsI:
4646 *mipsII:
4647 *mipsIII:
4648 *mipsIV:
4649 *mipsV:
4650 *mips32:
4651 *mips64:
4652 *vr4100:
4653 *vr5000:
4654 *r3900:
4655 {
4656   int fmt = FMT;
4657   check_fpu (SD_);
4658   check_fmt_p (SD_, fmt, instruction_0);
4659   StoreFPR(FD,fmt,Sub(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
4660 }
4661
4662
4663
4664 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
4665 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4666 *mipsI:
4667 *mipsII:
4668 *mipsIII:
4669 *mipsIV:
4670 *mipsV:
4671 *mips32:
4672 *mips64:
4673 *vr4100:
4674 *vr5000:
4675 *r3900:
4676 {
4677   address_word base = GPR[BASE];
4678   address_word offset = EXTEND16 (OFFSET);
4679   check_fpu (SD_);
4680   {
4681     address_word vaddr = loadstore_ea (SD_, base, offset);
4682     address_word paddr;
4683     int uncached;
4684     if ((vaddr & 3) != 0)
4685       {
4686         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4687       }
4688     else
4689       {
4690         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4691           {
4692             uword64 memval = 0;
4693             uword64 memval1 = 0;
4694             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4695             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4696             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4697             unsigned int byte;
4698             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4699             byte = ((vaddr & mask) ^ bigendiancpu);
4700             memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
4701             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4702           }
4703       }
4704   }
4705 }
4706
4707
4708 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
4709 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4710 *mipsIV:
4711 *mipsV:
4712 *mips64:
4713 *vr5000:
4714 {
4715
4716   address_word base = GPR[BASE];
4717   address_word index = GPR[INDEX];
4718   check_fpu (SD_);
4719   check_u64 (SD_, instruction_0);
4720   {
4721    address_word vaddr = loadstore_ea (SD_, base, index);
4722    address_word paddr;
4723    int uncached;
4724    if ((vaddr & 3) != 0)
4725      {
4726        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4727      }
4728    else
4729    {
4730     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4731     {
4732      unsigned64 memval = 0;
4733      unsigned64 memval1 = 0;
4734      unsigned64 mask = 0x7;
4735      unsigned int byte;
4736      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4737      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4738      memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
4739       {
4740        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4741       }
4742     }
4743    }
4744   }
4745 }
4746
4747
4748 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
4749 "trunc.l.%s<FMT> f<FD>, f<FS>"
4750 *mipsIII:
4751 *mipsIV:
4752 *mipsV:
4753 *mips64:
4754 *vr4100:
4755 *vr5000:
4756 *r3900:
4757 {
4758   int fmt = FMT;
4759   check_fpu (SD_);
4760   check_fmt (SD_, fmt, instruction_0);
4761   StoreFPR(FD,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_long));
4762 }
4763
4764
4765 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
4766 "trunc.w.%s<FMT> f<FD>, f<FS>"
4767 *mipsII:
4768 *mipsIII:
4769 *mipsIV:
4770 *mipsV:
4771 *mips32:
4772 *mips64:
4773 *vr4100:
4774 *vr5000:
4775 *r3900:
4776 {
4777   int fmt = FMT;
4778   check_fpu (SD_);
4779   check_fmt (SD_, fmt, instruction_0);
4780   StoreFPR(FD,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_word));
4781 }
4782
4783 \f
4784 //
4785 // MIPS Architecture:
4786 //
4787 //        System Control Instruction Set (COP0)
4788 //
4789
4790
4791 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4792 "bc0f <OFFSET>"
4793 *mipsI:
4794 *mipsII:
4795 *mipsIII:
4796 *mipsIV:
4797 *mipsV:
4798 *mips32:
4799 *mips64:
4800 *vr4100:
4801 *vr5000:
4802
4803 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4804 "bc0f <OFFSET>"
4805 // stub needed for eCos as tx39 hardware bug workaround
4806 *r3900:
4807 {
4808   /* do nothing */
4809 }
4810
4811
4812 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4813 "bc0fl <OFFSET>"
4814 *mipsI:
4815 *mipsII:
4816 *mipsIII:
4817 *mipsIV:
4818 *mipsV:
4819 *mips32:
4820 *mips64:
4821 *vr4100:
4822 *vr5000:
4823
4824
4825 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4826 "bc0t <OFFSET>"
4827 *mipsI:
4828 *mipsII:
4829 *mipsIII:
4830 *mipsIV:
4831 *mipsV:
4832 *mips32:
4833 *mips64:
4834 *vr4100:
4835
4836
4837 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4838 "bc0tl <OFFSET>"
4839 *mipsI:
4840 *mipsII:
4841 *mipsIII:
4842 *mipsIV:
4843 *mipsV:
4844 *mips32:
4845 *mips64:
4846 *vr4100:
4847 *vr5000:
4848
4849
4850 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4851 "cache <OP>, <OFFSET>(r<BASE>)"
4852 *mipsIII:
4853 *mipsIV:
4854 *mipsV:
4855 *mips32:
4856 *mips64:
4857 *vr4100:
4858 *vr5000:
4859 *r3900:
4860 {
4861   address_word base = GPR[BASE];
4862   address_word offset = EXTEND16 (OFFSET);
4863   {
4864     address_word vaddr = loadstore_ea (SD_, base, offset);
4865     address_word paddr;
4866     int uncached;
4867     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4868       CacheOp(OP,vaddr,paddr,instruction_0);
4869   }
4870 }
4871
4872
4873 010000,1,0000000000000000000,111001:COP0:32::DI
4874 "di"
4875 *mipsI:
4876 *mipsII:
4877 *mipsIII:
4878 *mipsIV:
4879 *mipsV:
4880 *vr4100:
4881 *vr5000:
4882
4883
4884 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
4885 "dmfc0 r<RT>, r<RD>"
4886 *mipsIII:
4887 *mipsIV:
4888 *mipsV:
4889 *mips64:
4890 {
4891   check_u64 (SD_, instruction_0);
4892   DecodeCoproc (instruction_0);
4893 }
4894
4895
4896 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
4897 "dmtc0 r<RT>, r<RD>"
4898 *mipsIII:
4899 *mipsIV:
4900 *mipsV:
4901 *mips64:
4902 {
4903   check_u64 (SD_, instruction_0);
4904   DecodeCoproc (instruction_0);
4905 }
4906
4907
4908 010000,1,0000000000000000000,111000:COP0:32::EI
4909 "ei"
4910 *mipsI:
4911 *mipsII:
4912 *mipsIII:
4913 *mipsIV:
4914 *mipsV:
4915 *mips64:
4916 *vr4100:
4917 *vr5000:
4918
4919
4920 010000,1,0000000000000000000,011000:COP0:32::ERET
4921 "eret"
4922 *mipsIII:
4923 *mipsIV:
4924 *mipsV:
4925 *mips32:
4926 *mips64:
4927 *vr4100:
4928 *vr5000:
4929 {
4930   if (SR & status_ERL)
4931     {
4932       /* Oops, not yet available */
4933       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
4934       NIA = EPC;
4935       SR &= ~status_ERL;
4936     }
4937   else
4938     {
4939       NIA = EPC;
4940       SR &= ~status_EXL;
4941     }
4942 }
4943
4944
4945 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4946 "mfc0 r<RT>, r<RD> # <REGX>"
4947 *mipsI:
4948 *mipsII:
4949 *mipsIII:
4950 *mipsIV:
4951 *mipsV:
4952 *mips32:
4953 *mips64:
4954 *vr4100:
4955 *vr5000:
4956 *r3900:
4957 {
4958   TRACE_ALU_INPUT0 ();
4959   DecodeCoproc (instruction_0);
4960   TRACE_ALU_RESULT (GPR[RT]);
4961 }
4962
4963 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4964 "mtc0 r<RT>, r<RD> # <REGX>"
4965 *mipsI:
4966 *mipsII:
4967 *mipsIII:
4968 *mipsIV:
4969 *mipsV:
4970 *mips32:
4971 *mips64:
4972 *vr4100:
4973 *vr5000:
4974 *r3900:
4975 {
4976   DecodeCoproc (instruction_0);
4977 }
4978
4979
4980 010000,1,0000000000000000000,010000:COP0:32::RFE
4981 "rfe"
4982 *mipsI:
4983 *mipsII:
4984 *mipsIII:
4985 *mipsIV:
4986 *mipsV:
4987 *vr4100:
4988 *vr5000:
4989 *r3900:
4990 {
4991   DecodeCoproc (instruction_0);
4992 }
4993
4994
4995 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
4996 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
4997 *mipsI:
4998 *mipsII:
4999 *mipsIII:
5000 *mipsIV:
5001 *mipsV:
5002 *mips32:
5003 *mips64:
5004 *vr4100:
5005 *r3900:
5006 {
5007   DecodeCoproc (instruction_0);
5008 }
5009
5010
5011
5012 010000,1,0000000000000000000,001000:COP0:32::TLBP
5013 "tlbp"
5014 *mipsI:
5015 *mipsII:
5016 *mipsIII:
5017 *mipsIV:
5018 *mipsV:
5019 *mips32:
5020 *mips64:
5021 *vr4100:
5022 *vr5000:
5023
5024
5025 010000,1,0000000000000000000,000001:COP0:32::TLBR
5026 "tlbr"
5027 *mipsI:
5028 *mipsII:
5029 *mipsIII:
5030 *mipsIV:
5031 *mipsV:
5032 *mips32:
5033 *mips64:
5034 *vr4100:
5035 *vr5000:
5036
5037
5038 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5039 "tlbwi"
5040 *mipsI:
5041 *mipsII:
5042 *mipsIII:
5043 *mipsIV:
5044 *mipsV:
5045 *mips32:
5046 *mips64:
5047 *vr4100:
5048 *vr5000:
5049
5050
5051 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5052 "tlbwr"
5053 *mipsI:
5054 *mipsII:
5055 *mipsIII:
5056 *mipsIV:
5057 *mipsV:
5058 *mips32:
5059 *mips64:
5060 *vr4100:
5061 *vr5000:
5062
5063 \f
5064 :include:::m16.igen
5065 :include:::mdmx.igen
5066 :include:::sb1.igen
5067 :include:::tx.igen
5068 :include:::vr.igen
5069 \f