3 // In mips.igen, the semantics for many of the instructions were created
4 // using code generated by gencode. Those semantic segments could be
8 // <insn-word> { "+" <insn-word> }
15 // { <insn-mnemonic> }
20 // IGEN config - mips16
21 // :option:16::insn-bit-size:16
22 // :option:16::hi-bit-nr:15
23 :option:16::insn-specifying-widths:true
24 :option:16::gen-delayed-branch:false
26 // IGEN config - mips32/64..
27 // :option:32::insn-bit-size:32
28 // :option:32::hi-bit-nr:31
29 :option:32::insn-specifying-widths:true
30 :option:32::gen-delayed-branch:false
33 // Generate separate simulators for each target
34 // :option:::multi-sim:true
37 // Models known by this simulator
38 :model:::mipsI:mips3000:
39 :model:::mipsII:mips6000:
40 :model:::mipsIII:mips4000:
41 :model:::mipsIV:mips8000:
42 :model:::mips16:mips16:
43 // start-sanitize-r5900
44 :model:::r5900:mips5900:
46 :model:::r3900:mips3900:
47 // start-sanitize-tx19
50 :model:::vr4100:mips4100:
51 // start-sanitize-vr4320
52 :model:::vr4320:mips4320:
53 // end-sanitize-vr4320
54 // start-sanitize-cygnus
55 :model:::vr5400:mips5400:
57 // end-sanitize-cygnus
58 :model:::vr5000:mips5000:
62 // Pseudo instructions known by IGEN
65 SignalException (ReservedInstruction, 0);
69 // Pseudo instructions known by interp.c
70 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
71 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
74 SignalException (ReservedInstruction, instruction_0);
81 // Simulate a 32 bit delayslot instruction
84 :function:::address_word:delayslot32:address_word target
86 instruction_word delay_insn;
87 sim_events_slip (SD, 1);
89 CIA = CIA + 4; /* NOTE not mips16 */
90 STATE |= simDELAYSLOT;
91 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
92 idecode_issue (CPU_, delay_insn, (CIA));
93 STATE &= ~simDELAYSLOT;
97 :function:::address_word:nullify_next_insn32:
99 sim_events_slip (SD, 1);
100 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
104 // start-sanitize-branchbug4011
105 :function:::void:check_4011_branch_bug:
107 if (BRANCHBUG4011_OPTION == 2 && BRANCHBUG4011_LAST_TARGET == CIA)
108 sim_engine_abort (SD, CPU, CIA, "4011 BRANCH BUG: %s at 0x%08lx was target of branch at 0x%08lx\n",
109 itable[MY_INDEX].name,
111 (long) BRANCHBUG4011_LAST_CIA);
114 :function:::void:mark_4011_branch_bug:address_word target
116 if (BRANCHBUG4011_OPTION)
118 BRANCHBUG4011_OPTION = 2;
119 BRANCHBUG4011_LAST_TARGET = target;
120 BRANCHBUG4011_LAST_CIA = CIA;
124 // end-sanitize-branchbug4011
127 // Check that an access to a HI/LO register meets timing requirements
129 // The following requirements exist:
131 // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
132 // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
133 // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
134 // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
137 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
139 if (history->mf.timestamp + 3 > time)
141 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
142 itable[MY_INDEX].name,
144 (long) history->mf.cia);
150 :function:::int:check_mt_hilo:hilo_history *history
151 *mipsI,mipsII,mipsIII,mipsIV:
154 // start-sanitize-vr4320
156 // end-sanitize-vr4320
157 // start-sanitize-cygnus
159 // end-sanitize-cygnus
161 signed64 time = sim_events_time (SD);
162 int ok = check_mf_cycles (SD_, history, time, "MT");
163 history->mt.timestamp = time;
164 history->mt.cia = CIA;
168 :function:::int:check_mt_hilo:hilo_history *history
170 // start-sanitize-tx19
173 // start-sanitize-r5900
175 // end-sanitize-r5900
177 signed64 time = sim_events_time (SD);
178 history->mt.timestamp = time;
179 history->mt.cia = CIA;
184 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
185 *mipsI,mipsII,mipsIII,mipsIV:
188 // start-sanitize-vr4320
190 // end-sanitize-vr4320
191 // start-sanitize-cygnus
193 // end-sanitize-cygnus
195 // start-sanitize-tx19
199 signed64 time = sim_events_time (SD);
202 && peer->mt.timestamp > history->op.timestamp
203 && history->mt.timestamp < history->op.timestamp
204 && ! (history->mf.timestamp > history->op.timestamp
205 && history->mf.timestamp < peer->mt.timestamp)
206 && ! (peer->mf.timestamp > history->op.timestamp
207 && peer->mf.timestamp < peer->mt.timestamp))
209 /* The peer has been written to since the last OP yet we have
211 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
212 itable[MY_INDEX].name,
214 (long) history->op.cia,
215 (long) peer->mt.cia);
218 history->mf.timestamp = time;
219 history->mf.cia = CIA;
223 // start-sanitize-r5900
224 // The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
225 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
226 // end-sanitize-r5900
227 // start-sanitize-r5900
229 // end-sanitize-r5900
230 // start-sanitize-r5900
232 /* FIXME: could record the fact that a stall occured if we want */
233 signed64 time = sim_events_time (SD);
234 history->mf.timestamp = time;
235 history->mf.cia = CIA;
238 // end-sanitize-r5900
241 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
242 *mipsI,mipsII,mipsIII,mipsIV:
245 // start-sanitize-vr4320
247 // end-sanitize-vr4320
248 // start-sanitize-cygnus
250 // end-sanitize-cygnus
252 signed64 time = sim_events_time (SD);
253 int ok = (check_mf_cycles (SD_, hi, time, "OP")
254 && check_mf_cycles (SD_, lo, time, "OP"));
255 hi->op.timestamp = time;
256 lo->op.timestamp = time;
262 // The r3900 mult and multu insns _can_ be exectuted immediatly after
264 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
266 // start-sanitize-tx19
269 // start-sanitize-r5900
271 // end-sanitize-r5900
273 /* FIXME: could record the fact that a stall occured if we want */
274 signed64 time = sim_events_time (SD);
275 hi->op.timestamp = time;
276 lo->op.timestamp = time;
283 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
284 *mipsI,mipsII,mipsIII,mipsIV:
287 // start-sanitize-vr4320
289 // end-sanitize-vr4320
290 // start-sanitize-cygnus
292 // end-sanitize-cygnus
294 // start-sanitize-tx19
298 signed64 time = sim_events_time (SD);
299 int ok = (check_mf_cycles (SD_, hi, time, "OP")
300 && check_mf_cycles (SD_, lo, time, "OP"));
301 hi->op.timestamp = time;
302 lo->op.timestamp = time;
309 // start-sanitize-r5900
310 // The r5900 div et.al insns _can_ be exectuted immediatly after
312 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
313 // end-sanitize-r5900
314 // start-sanitize-r5900
316 // end-sanitize-r5900
317 // start-sanitize-r5900
319 /* FIXME: could record the fact that a stall occured if we want */
320 signed64 time = sim_events_time (SD);
321 hi->op.timestamp = time;
322 lo->op.timestamp = time;
327 // end-sanitize-r5900
332 // Mips Architecture:
334 // CPU Instruction Set (mipsI - mipsIV)
339 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
340 "add r<RD>, r<RS>, r<RT>"
341 *mipsI,mipsII,mipsIII,mipsIV:
344 // start-sanitize-vr4320
346 // end-sanitize-vr4320
347 // start-sanitize-cygnus
349 // end-sanitize-cygnus
350 // start-sanitize-r5900
352 // end-sanitize-r5900
354 // start-sanitize-tx19
358 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
360 ALU32_BEGIN (GPR[RS]);
364 TRACE_ALU_RESULT (GPR[RD]);
369 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
370 "addi r<RT>, r<RS>, IMMEDIATE"
371 *mipsI,mipsII,mipsIII,mipsIV:
374 // start-sanitize-vr4320
376 // end-sanitize-vr4320
377 // start-sanitize-cygnus
379 // end-sanitize-cygnus
380 // start-sanitize-r5900
382 // end-sanitize-r5900
384 // start-sanitize-tx19
388 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
390 ALU32_BEGIN (GPR[RS]);
391 ALU32_ADD (EXTEND16 (IMMEDIATE));
394 TRACE_ALU_RESULT (GPR[RT]);
399 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
401 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
402 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
403 TRACE_ALU_RESULT (GPR[rt]);
406 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
407 "addiu r<RT>, r<RS>, <IMMEDIATE>"
408 *mipsI,mipsII,mipsIII,mipsIV:
411 // start-sanitize-vr4320
413 // end-sanitize-vr4320
414 // start-sanitize-cygnus
416 // end-sanitize-cygnus
417 // start-sanitize-r5900
419 // end-sanitize-r5900
421 // start-sanitize-tx19
425 do_addiu (SD_, RS, RT, IMMEDIATE);
430 :function:::void:do_addu:int rs, int rt, int rd
432 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
433 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
434 TRACE_ALU_RESULT (GPR[rd]);
437 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
438 "addu r<RD>, r<RS>, r<RT>"
439 *mipsI,mipsII,mipsIII,mipsIV:
442 // start-sanitize-vr4320
444 // end-sanitize-vr4320
445 // start-sanitize-cygnus
447 // end-sanitize-cygnus
448 // start-sanitize-r5900
450 // end-sanitize-r5900
452 // start-sanitize-tx19
456 do_addu (SD_, RS, RT, RD);
461 :function:::void:do_and:int rs, int rt, int rd
463 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
464 GPR[rd] = GPR[rs] & GPR[rt];
465 TRACE_ALU_RESULT (GPR[rd]);
468 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
469 "and r<RD>, r<RS>, r<RT>"
470 *mipsI,mipsII,mipsIII,mipsIV:
473 // start-sanitize-vr4320
475 // end-sanitize-vr4320
476 // start-sanitize-cygnus
478 // end-sanitize-cygnus
479 // start-sanitize-r5900
481 // end-sanitize-r5900
483 // start-sanitize-tx19
487 do_and (SD_, RS, RT, RD);
492 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
493 "and r<RT>, r<RS>, <IMMEDIATE>"
494 *mipsI,mipsII,mipsIII,mipsIV:
497 // start-sanitize-vr4320
499 // end-sanitize-vr4320
500 // start-sanitize-cygnus
502 // end-sanitize-cygnus
503 // start-sanitize-r5900
505 // end-sanitize-r5900
507 // start-sanitize-tx19
511 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
512 GPR[RT] = GPR[RS] & IMMEDIATE;
513 TRACE_ALU_RESULT (GPR[RT]);
518 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
519 "beq r<RS>, r<RT>, <OFFSET>"
520 *mipsI,mipsII,mipsIII,mipsIV:
523 // start-sanitize-vr4320
525 // end-sanitize-vr4320
526 // start-sanitize-cygnus
528 // end-sanitize-cygnus
529 // start-sanitize-r5900
531 // end-sanitize-r5900
533 // start-sanitize-tx19
537 address_word offset = EXTEND16 (OFFSET) << 2;
539 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
541 mark_branch_bug (NIA+offset);
542 DELAY_SLOT (NIA + offset);
548 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
549 "beql r<RS>, r<RT>, <OFFSET>"
555 // start-sanitize-vr4320
557 // end-sanitize-vr4320
558 // start-sanitize-cygnus
560 // end-sanitize-cygnus
561 // start-sanitize-r5900
563 // end-sanitize-r5900
565 // start-sanitize-tx19
569 address_word offset = EXTEND16 (OFFSET) << 2;
571 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
573 mark_branch_bug (NIA+offset);
574 DELAY_SLOT (NIA + offset);
577 NULLIFY_NEXT_INSTRUCTION ();
582 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
583 "bgez r<RS>, <OFFSET>"
584 *mipsI,mipsII,mipsIII,mipsIV:
587 // start-sanitize-vr4320
589 // end-sanitize-vr4320
590 // start-sanitize-cygnus
592 // end-sanitize-cygnus
593 // start-sanitize-r5900
595 // end-sanitize-r5900
597 // start-sanitize-tx19
601 address_word offset = EXTEND16 (OFFSET) << 2;
603 if ((signed_word) GPR[RS] >= 0)
605 mark_branch_bug (NIA+offset);
606 DELAY_SLOT (NIA + offset);
612 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
613 "bgezal r<RS>, <OFFSET>"
614 *mipsI,mipsII,mipsIII,mipsIV:
617 // start-sanitize-vr4320
619 // end-sanitize-vr4320
620 // start-sanitize-cygnus
622 // end-sanitize-cygnus
623 // start-sanitize-r5900
625 // end-sanitize-r5900
627 // start-sanitize-tx19
631 address_word offset = EXTEND16 (OFFSET) << 2;
634 if ((signed_word) GPR[RS] >= 0)
636 mark_branch_bug (NIA+offset);
637 DELAY_SLOT (NIA + offset);
643 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
644 "bgezall r<RS>, <OFFSET>"
650 // start-sanitize-vr4320
652 // end-sanitize-vr4320
653 // start-sanitize-cygnus
655 // end-sanitize-cygnus
656 // start-sanitize-r5900
658 // end-sanitize-r5900
660 // start-sanitize-tx19
664 address_word offset = EXTEND16 (OFFSET) << 2;
667 /* NOTE: The branch occurs AFTER the next instruction has been
669 if ((signed_word) GPR[RS] >= 0)
671 mark_branch_bug (NIA+offset);
672 DELAY_SLOT (NIA + offset);
675 NULLIFY_NEXT_INSTRUCTION ();
680 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
681 "bgezl r<RS>, <OFFSET>"
687 // start-sanitize-vr4320
689 // end-sanitize-vr4320
690 // start-sanitize-cygnus
692 // end-sanitize-cygnus
693 // start-sanitize-r5900
695 // end-sanitize-r5900
697 // start-sanitize-tx19
701 address_word offset = EXTEND16 (OFFSET) << 2;
703 if ((signed_word) GPR[RS] >= 0)
705 mark_branch_bug (NIA+offset);
706 DELAY_SLOT (NIA + offset);
709 NULLIFY_NEXT_INSTRUCTION ();
714 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
715 "bgtz r<RS>, <OFFSET>"
716 *mipsI,mipsII,mipsIII,mipsIV:
719 // start-sanitize-vr4320
721 // end-sanitize-vr4320
722 // start-sanitize-cygnus
724 // end-sanitize-cygnus
725 // start-sanitize-r5900
727 // end-sanitize-r5900
729 // start-sanitize-tx19
733 address_word offset = EXTEND16 (OFFSET) << 2;
735 if ((signed_word) GPR[RS] > 0)
737 mark_branch_bug (NIA+offset);
738 DELAY_SLOT (NIA + offset);
744 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
745 "bgtzl r<RS>, <OFFSET>"
751 // start-sanitize-vr4320
753 // end-sanitize-vr4320
754 // start-sanitize-cygnus
756 // end-sanitize-cygnus
757 // start-sanitize-r5900
759 // end-sanitize-r5900
761 // start-sanitize-tx19
765 address_word offset = EXTEND16 (OFFSET) << 2;
767 /* NOTE: The branch occurs AFTER the next instruction has been
769 if ((signed_word) GPR[RS] > 0)
771 mark_branch_bug (NIA+offset);
772 DELAY_SLOT (NIA + offset);
775 NULLIFY_NEXT_INSTRUCTION ();
780 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
781 "blez r<RS>, <OFFSET>"
782 *mipsI,mipsII,mipsIII,mipsIV:
785 // start-sanitize-vr4320
787 // end-sanitize-vr4320
788 // start-sanitize-cygnus
790 // end-sanitize-cygnus
791 // start-sanitize-r5900
793 // end-sanitize-r5900
795 // start-sanitize-tx19
799 address_word offset = EXTEND16 (OFFSET) << 2;
801 /* NOTE: The branch occurs AFTER the next instruction has been
803 if ((signed_word) GPR[RS] <= 0)
805 mark_branch_bug (NIA+offset);
806 DELAY_SLOT (NIA + offset);
812 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
813 "bgezl r<RS>, <OFFSET>"
819 // start-sanitize-vr4320
821 // end-sanitize-vr4320
822 // start-sanitize-cygnus
824 // end-sanitize-cygnus
825 // start-sanitize-r5900
827 // end-sanitize-r5900
829 // start-sanitize-tx19
833 address_word offset = EXTEND16 (OFFSET) << 2;
835 if ((signed_word) GPR[RS] <= 0)
837 mark_branch_bug (NIA+offset);
838 DELAY_SLOT (NIA + offset);
841 NULLIFY_NEXT_INSTRUCTION ();
846 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
847 "bltz r<RS>, <OFFSET>"
848 *mipsI,mipsII,mipsIII,mipsIV:
851 // start-sanitize-vr4320
853 // end-sanitize-vr4320
854 // start-sanitize-cygnus
856 // end-sanitize-cygnus
857 // start-sanitize-r5900
859 // end-sanitize-r5900
861 // start-sanitize-tx19
865 address_word offset = EXTEND16 (OFFSET) << 2;
867 if ((signed_word) GPR[RS] < 0)
869 mark_branch_bug (NIA+offset);
870 DELAY_SLOT (NIA + offset);
876 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
877 "bltzal r<RS>, <OFFSET>"
878 *mipsI,mipsII,mipsIII,mipsIV:
881 // start-sanitize-vr4320
883 // end-sanitize-vr4320
884 // start-sanitize-cygnus
886 // end-sanitize-cygnus
887 // start-sanitize-r5900
889 // end-sanitize-r5900
891 // start-sanitize-tx19
895 address_word offset = EXTEND16 (OFFSET) << 2;
898 /* NOTE: The branch occurs AFTER the next instruction has been
900 if ((signed_word) GPR[RS] < 0)
902 mark_branch_bug (NIA+offset);
903 DELAY_SLOT (NIA + offset);
909 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
910 "bltzall r<RS>, <OFFSET>"
916 // start-sanitize-vr4320
918 // end-sanitize-vr4320
919 // start-sanitize-cygnus
921 // end-sanitize-cygnus
922 // start-sanitize-r5900
924 // end-sanitize-r5900
926 // start-sanitize-tx19
930 address_word offset = EXTEND16 (OFFSET) << 2;
933 if ((signed_word) GPR[RS] < 0)
935 mark_branch_bug (NIA+offset);
936 DELAY_SLOT (NIA + offset);
939 NULLIFY_NEXT_INSTRUCTION ();
944 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
945 "bltzl r<RS>, <OFFSET>"
951 // start-sanitize-vr4320
953 // end-sanitize-vr4320
954 // start-sanitize-cygnus
956 // end-sanitize-cygnus
957 // start-sanitize-r5900
959 // end-sanitize-r5900
961 // start-sanitize-tx19
965 address_word offset = EXTEND16 (OFFSET) << 2;
967 /* NOTE: The branch occurs AFTER the next instruction has been
969 if ((signed_word) GPR[RS] < 0)
971 mark_branch_bug (NIA+offset);
972 DELAY_SLOT (NIA + offset);
975 NULLIFY_NEXT_INSTRUCTION ();
980 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
981 "bne r<RS>, r<RT>, <OFFSET>"
982 *mipsI,mipsII,mipsIII,mipsIV:
985 // start-sanitize-vr4320
987 // end-sanitize-vr4320
988 // start-sanitize-cygnus
990 // end-sanitize-cygnus
991 // start-sanitize-r5900
993 // end-sanitize-r5900
995 // start-sanitize-tx19
999 address_word offset = EXTEND16 (OFFSET) << 2;
1000 check_branch_bug ();
1001 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1003 mark_branch_bug (NIA+offset);
1004 DELAY_SLOT (NIA + offset);
1010 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1011 "bnel r<RS>, r<RT>, <OFFSET>"
1017 // start-sanitize-vr4320
1019 // end-sanitize-vr4320
1020 // start-sanitize-cygnus
1022 // end-sanitize-cygnus
1023 // start-sanitize-r5900
1025 // end-sanitize-r5900
1027 // start-sanitize-tx19
1029 // end-sanitize-tx19
1031 address_word offset = EXTEND16 (OFFSET) << 2;
1032 check_branch_bug ();
1033 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1035 mark_branch_bug (NIA+offset);
1036 DELAY_SLOT (NIA + offset);
1039 NULLIFY_NEXT_INSTRUCTION ();
1044 000000,20.CODE,001101:SPECIAL:32::BREAK
1046 *mipsI,mipsII,mipsIII,mipsIV:
1049 // start-sanitize-vr4320
1051 // end-sanitize-vr4320
1052 // start-sanitize-cygnus
1054 // end-sanitize-cygnus
1055 // start-sanitize-r5900
1057 // end-sanitize-r5900
1059 // start-sanitize-tx19
1061 // end-sanitize-tx19
1063 /* Check for some break instruction which are reserved for use by the simulator. */
1064 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1065 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1066 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1068 sim_engine_halt (SD, CPU, NULL, cia,
1069 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1071 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1072 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1074 if (STATE & simDELAYSLOT)
1075 PC = cia - 4; /* reference the branch instruction */
1078 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1080 // start-sanitize-sky
1082 else if (break_code == (HALT_INSTRUCTION_PASS & HALT_INSTRUCTION_MASK))
1084 sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
1086 else if (break_code == (HALT_INSTRUCTION_FAIL & HALT_INSTRUCTION_MASK))
1088 sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 15);
1090 else if (break_code == (PRINTF_INSTRUCTION & HALT_INSTRUCTION_MASK))
1092 sim_monitor(SD, CPU, cia, 316); /* Magic number for idt printf routine. */
1094 else if (break_code == (LOAD_INSTRUCTION & HALT_INSTRUCTION_MASK))
1096 /* This is a multi-phase load instruction. Load next configured
1097 executable and return its starting PC in A0 ($4). */
1099 if (STATE_MLOAD_INDEX (SD) == STATE_MLOAD_COUNT (SD))
1101 sim_io_eprintf (SD, "Cannot load program %d. Not enough load-next options.\n",
1102 STATE_MLOAD_COUNT (SD));
1107 char* next = STATE_MLOAD_NAME (SD) [STATE_MLOAD_INDEX (SD)];
1110 STATE_MLOAD_INDEX (SD) ++;
1112 /* call sim_load_file, preserving most previous state */
1113 rc = sim_load (SD, next, NULL, 0);
1116 sim_io_eprintf (SD, "Error during multi-phase load #%d.\n",
1117 STATE_MLOAD_INDEX (SD));
1121 A0 = STATE_START_ADDR (SD);
1129 /* If we get this far, we're not an instruction reserved by the sim. Raise
1131 SignalException(BreakPoint, instruction_0);
1140 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1141 "dadd r<RD>, r<RS>, r<RT>"
1146 // start-sanitize-vr4320
1148 // end-sanitize-vr4320
1149 // start-sanitize-cygnus
1151 // end-sanitize-cygnus
1152 // start-sanitize-r5900
1154 // end-sanitize-r5900
1155 // start-sanitize-tx19
1157 // end-sanitize-tx19
1159 /* this check's for overflow */
1160 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1162 ALU64_BEGIN (GPR[RS]);
1163 ALU64_ADD (GPR[RT]);
1164 ALU64_END (GPR[RD]);
1166 TRACE_ALU_RESULT (GPR[RD]);
1171 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1172 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1177 // start-sanitize-vr4320
1179 // end-sanitize-vr4320
1180 // start-sanitize-cygnus
1182 // end-sanitize-cygnus
1183 // start-sanitize-r5900
1185 // end-sanitize-r5900
1186 // start-sanitize-tx19
1188 // end-sanitize-tx19
1190 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1192 ALU64_BEGIN (GPR[RS]);
1193 ALU64_ADD (EXTEND16 (IMMEDIATE));
1194 ALU64_END (GPR[RT]);
1196 TRACE_ALU_RESULT (GPR[RT]);
1201 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
1203 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1204 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1205 TRACE_ALU_RESULT (GPR[rt]);
1208 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1209 "daddu r<RT>, r<RS>, <IMMEDIATE>"
1214 // start-sanitize-vr4320
1216 // end-sanitize-vr4320
1217 // start-sanitize-cygnus
1219 // end-sanitize-cygnus
1220 // start-sanitize-r5900
1222 // end-sanitize-r5900
1223 // start-sanitize-tx19
1225 // end-sanitize-tx19
1227 do_daddiu (SD_, RS, RT, IMMEDIATE);
1232 :function:::void:do_daddu:int rs, int rt, int rd
1234 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1235 GPR[rd] = GPR[rs] + GPR[rt];
1236 TRACE_ALU_RESULT (GPR[rd]);
1239 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1240 "daddu r<RD>, r<RS>, r<RT>"
1245 // start-sanitize-vr4320
1247 // end-sanitize-vr4320
1248 // start-sanitize-cygnus
1250 // end-sanitize-cygnus
1251 // start-sanitize-r5900
1253 // end-sanitize-r5900
1254 // start-sanitize-tx19
1256 // end-sanitize-tx19
1258 do_daddu (SD_, RS, RT, RD);
1263 :function:64::void:do_ddiv:int rs, int rt
1265 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1266 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1268 signed64 n = GPR[rs];
1269 signed64 d = GPR[rt];
1272 LO = SIGNED64 (0x8000000000000000);
1275 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1277 LO = SIGNED64 (0x8000000000000000);
1286 TRACE_ALU_RESULT2 (HI, LO);
1289 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1295 // start-sanitize-vr4320
1297 // end-sanitize-vr4320
1298 // start-sanitize-cygnus
1300 // end-sanitize-cygnus
1301 // start-sanitize-r5900
1303 // end-sanitize-r5900
1304 // start-sanitize-tx19
1306 // end-sanitize-tx19
1308 do_ddiv (SD_, RS, RT);
1313 :function:64::void:do_ddivu:int rs, int rt
1315 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1316 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1318 unsigned64 n = GPR[rs];
1319 unsigned64 d = GPR[rt];
1322 LO = SIGNED64 (0x8000000000000000);
1331 TRACE_ALU_RESULT2 (HI, LO);
1334 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1335 "ddivu r<RS>, r<RT>"
1340 // start-sanitize-vr4320
1342 // end-sanitize-vr4320
1343 // start-sanitize-cygnus
1345 // end-sanitize-cygnus
1346 // start-sanitize-tx19
1348 // end-sanitize-tx19
1350 do_ddivu (SD_, RS, RT);
1355 :function:::void:do_div:int rs, int rt
1357 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1358 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1360 signed32 n = GPR[rs];
1361 signed32 d = GPR[rt];
1364 LO = EXTEND32 (0x80000000);
1367 else if (n == SIGNED32 (0x80000000) && d == -1)
1369 LO = EXTEND32 (0x80000000);
1374 LO = EXTEND32 (n / d);
1375 HI = EXTEND32 (n % d);
1378 TRACE_ALU_RESULT2 (HI, LO);
1381 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1383 *mipsI,mipsII,mipsIII,mipsIV:
1386 // start-sanitize-vr4320
1388 // end-sanitize-vr4320
1389 // start-sanitize-cygnus
1391 // end-sanitize-cygnus
1392 // start-sanitize-r5900
1394 // end-sanitize-r5900
1396 // start-sanitize-tx19
1398 // end-sanitize-tx19
1400 do_div (SD_, RS, RT);
1405 :function:::void:do_divu:int rs, int rt
1407 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1408 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1410 unsigned32 n = GPR[rs];
1411 unsigned32 d = GPR[rt];
1414 LO = EXTEND32 (0x80000000);
1419 LO = EXTEND32 (n / d);
1420 HI = EXTEND32 (n % d);
1423 TRACE_ALU_RESULT2 (HI, LO);
1426 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1428 *mipsI,mipsII,mipsIII,mipsIV:
1431 // start-sanitize-vr4320
1433 // end-sanitize-vr4320
1434 // start-sanitize-cygnus
1436 // end-sanitize-cygnus
1437 // start-sanitize-r5900
1439 // end-sanitize-r5900
1441 // start-sanitize-tx19
1443 // end-sanitize-tx19
1445 do_divu (SD_, RS, RT);
1450 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1460 unsigned64 op1 = GPR[rs];
1461 unsigned64 op2 = GPR[rt];
1462 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1463 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1464 /* make signed multiply unsigned */
1479 /* multuply out the 4 sub products */
1480 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1481 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1482 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1483 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1484 /* add the products */
1485 mid = ((unsigned64) VH4_8 (m00)
1486 + (unsigned64) VL4_8 (m10)
1487 + (unsigned64) VL4_8 (m01));
1488 lo = U8_4 (mid, m00);
1490 + (unsigned64) VH4_8 (mid)
1491 + (unsigned64) VH4_8 (m01)
1492 + (unsigned64) VH4_8 (m10));
1502 /* save the result HI/LO (and a gpr) */
1507 TRACE_ALU_RESULT2 (HI, LO);
1510 :function:::void:do_dmult:int rs, int rt, int rd
1512 do_dmultx (SD_, rs, rt, rd, 1);
1515 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1516 "dmult r<RS>, r<RT>"
1519 // start-sanitize-tx19
1521 // end-sanitize-tx19
1522 // start-sanitize-vr4320
1524 // end-sanitize-vr4320
1526 do_dmult (SD_, RS, RT, 0);
1529 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1530 "dmult r<RS>, r<RT>":RD == 0
1531 "dmult r<RD>, r<RS>, r<RT>"
1533 // start-sanitize-cygnus
1535 // end-sanitize-cygnus
1537 do_dmult (SD_, RS, RT, RD);
1542 :function:::void:do_dmultu:int rs, int rt, int rd
1544 do_dmultx (SD_, rs, rt, rd, 0);
1547 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1548 "dmultu r<RS>, r<RT>"
1551 // start-sanitize-tx19
1553 // end-sanitize-tx19
1554 // start-sanitize-vr4320
1556 // end-sanitize-vr4320
1558 do_dmultu (SD_, RS, RT, 0);
1561 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1562 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1563 "dmultu r<RS>, r<RT>"
1565 // start-sanitize-cygnus
1567 // end-sanitize-cygnus
1569 do_dmultu (SD_, RS, RT, RD);
1574 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1575 "dsll r<RD>, r<RT>, <SHIFT>"
1580 // start-sanitize-vr4320
1582 // end-sanitize-vr4320
1583 // start-sanitize-cygnus
1585 // end-sanitize-cygnus
1586 // start-sanitize-r5900
1588 // end-sanitize-r5900
1589 // start-sanitize-tx19
1591 // end-sanitize-tx19
1594 GPR[RD] = GPR[RT] << s;
1598 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1599 "dsll32 r<RD>, r<RT>, <SHIFT>"
1604 // start-sanitize-vr4320
1606 // end-sanitize-vr4320
1607 // start-sanitize-cygnus
1609 // end-sanitize-cygnus
1610 // start-sanitize-r5900
1612 // end-sanitize-r5900
1613 // start-sanitize-tx19
1615 // end-sanitize-tx19
1618 GPR[RD] = GPR[RT] << s;
1623 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1624 "dsllv r<RD>, r<RT>, r<RS>"
1629 // start-sanitize-vr4320
1631 // end-sanitize-vr4320
1632 // start-sanitize-cygnus
1634 // end-sanitize-cygnus
1635 // start-sanitize-r5900
1637 // end-sanitize-r5900
1638 // start-sanitize-tx19
1640 // end-sanitize-tx19
1642 int s = MASKED64 (GPR[RS], 5, 0);
1643 GPR[RD] = GPR[RT] << s;
1648 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1649 "dsra r<RD>, r<RT>, <SHIFT>"
1654 // start-sanitize-vr4320
1656 // end-sanitize-vr4320
1657 // start-sanitize-cygnus
1659 // end-sanitize-cygnus
1660 // start-sanitize-r5900
1662 // end-sanitize-r5900
1663 // start-sanitize-tx19
1665 // end-sanitize-tx19
1668 GPR[RD] = ((signed64) GPR[RT]) >> s;
1672 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1673 "dsra32 r<RT>, r<RD>, <SHIFT>"
1678 // start-sanitize-vr4320
1680 // end-sanitize-vr4320
1681 // start-sanitize-cygnus
1683 // end-sanitize-cygnus
1684 // start-sanitize-r5900
1686 // end-sanitize-r5900
1687 // start-sanitize-tx19
1689 // end-sanitize-tx19
1692 GPR[RD] = ((signed64) GPR[RT]) >> s;
1696 :function:::void:do_dsrav:int rs, int rt, int rd
1698 int s = MASKED64 (GPR[rs], 5, 0);
1699 TRACE_ALU_INPUT2 (GPR[rt], s);
1700 GPR[rd] = ((signed64) GPR[rt]) >> s;
1701 TRACE_ALU_RESULT (GPR[rd]);
1704 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1705 "dsra32 r<RT>, r<RD>, r<RS>"
1710 // start-sanitize-vr4320
1712 // end-sanitize-vr4320
1713 // start-sanitize-cygnus
1715 // end-sanitize-cygnus
1716 // start-sanitize-r5900
1718 // end-sanitize-r5900
1719 // start-sanitize-tx19
1721 // end-sanitize-tx19
1723 do_dsrav (SD_, RS, RT, RD);
1727 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1728 "dsrl r<RD>, r<RT>, <SHIFT>"
1733 // start-sanitize-vr4320
1735 // end-sanitize-vr4320
1736 // start-sanitize-cygnus
1738 // end-sanitize-cygnus
1739 // start-sanitize-r5900
1741 // end-sanitize-r5900
1742 // start-sanitize-tx19
1744 // end-sanitize-tx19
1747 GPR[RD] = (unsigned64) GPR[RT] >> s;
1751 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1752 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1757 // start-sanitize-vr4320
1759 // end-sanitize-vr4320
1760 // start-sanitize-cygnus
1762 // end-sanitize-cygnus
1763 // start-sanitize-r5900
1765 // end-sanitize-r5900
1766 // start-sanitize-tx19
1768 // end-sanitize-tx19
1771 GPR[RD] = (unsigned64) GPR[RT] >> s;
1775 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1776 "dsrl32 r<RD>, r<RT>, r<RS>"
1781 // start-sanitize-vr4320
1783 // end-sanitize-vr4320
1784 // start-sanitize-cygnus
1786 // end-sanitize-cygnus
1787 // start-sanitize-r5900
1789 // end-sanitize-r5900
1790 // start-sanitize-tx19
1792 // end-sanitize-tx19
1794 int s = MASKED64 (GPR[RS], 5, 0);
1795 GPR[RD] = (unsigned64) GPR[RT] >> s;
1799 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1800 "dsub r<RD>, r<RS>, r<RT>"
1805 // start-sanitize-vr4320
1807 // end-sanitize-vr4320
1808 // start-sanitize-cygnus
1810 // end-sanitize-cygnus
1811 // start-sanitize-r5900
1813 // end-sanitize-r5900
1814 // start-sanitize-tx19
1816 // end-sanitize-tx19
1818 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1820 ALU64_BEGIN (GPR[RS]);
1821 ALU64_SUB (GPR[RT]);
1822 ALU64_END (GPR[RD]);
1824 TRACE_ALU_RESULT (GPR[RD]);
1828 :function:::void:do_dsubu:int rs, int rt, int rd
1830 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1831 GPR[rd] = GPR[rs] - GPR[rt];
1832 TRACE_ALU_RESULT (GPR[rd]);
1835 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1836 "dsubu r<RD>, r<RS>, r<RT>"
1841 // start-sanitize-vr4320
1843 // end-sanitize-vr4320
1844 // start-sanitize-cygnus
1846 // end-sanitize-cygnus
1847 // start-sanitize-r5900
1849 // end-sanitize-r5900
1850 // start-sanitize-tx19
1852 // end-sanitize-tx19
1854 do_dsubu (SD_, RS, RT, RD);
1858 000010,26.INSTR_INDEX:NORMAL:32::J
1860 *mipsI,mipsII,mipsIII,mipsIV:
1863 // start-sanitize-vr4320
1865 // end-sanitize-vr4320
1866 // start-sanitize-cygnus
1868 // end-sanitize-cygnus
1869 // start-sanitize-r5900
1871 // end-sanitize-r5900
1873 // start-sanitize-tx19
1875 // end-sanitize-tx19
1877 /* NOTE: The region used is that of the delay slot NIA and NOT the
1878 current instruction */
1879 address_word region = (NIA & MASK (63, 28));
1880 DELAY_SLOT (region | (INSTR_INDEX << 2));
1884 000011,26.INSTR_INDEX:NORMAL:32::JAL
1886 *mipsI,mipsII,mipsIII,mipsIV:
1889 // start-sanitize-vr4320
1891 // end-sanitize-vr4320
1892 // start-sanitize-cygnus
1894 // end-sanitize-cygnus
1895 // start-sanitize-r5900
1897 // end-sanitize-r5900
1899 // start-sanitize-tx19
1901 // end-sanitize-tx19
1903 /* NOTE: The region used is that of the delay slot and NOT the
1904 current instruction */
1905 address_word region = (NIA & MASK (63, 28));
1907 DELAY_SLOT (region | (INSTR_INDEX << 2));
1911 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1912 "jalr r<RS>":RD == 31
1914 *mipsI,mipsII,mipsIII,mipsIV:
1917 // start-sanitize-vr4320
1919 // end-sanitize-vr4320
1920 // start-sanitize-cygnus
1922 // end-sanitize-cygnus
1923 // start-sanitize-r5900
1925 // end-sanitize-r5900
1927 // start-sanitize-tx19
1929 // end-sanitize-tx19
1931 address_word temp = GPR[RS];
1937 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1939 *mipsI,mipsII,mipsIII,mipsIV:
1942 // start-sanitize-vr4320
1944 // end-sanitize-vr4320
1945 // start-sanitize-cygnus
1947 // end-sanitize-cygnus
1948 // start-sanitize-r5900
1950 // end-sanitize-r5900
1952 // start-sanitize-tx19
1954 // end-sanitize-tx19
1956 DELAY_SLOT (GPR[RS]);
1960 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1962 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1963 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1964 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1971 vaddr = base + offset;
1972 if ((vaddr & access) != 0)
1973 SignalExceptionAddressLoad ();
1974 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1975 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1976 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1977 byte = ((vaddr & mask) ^ bigendiancpu);
1978 return (memval >> (8 * byte));
1982 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1983 "lb r<RT>, <OFFSET>(r<BASE>)"
1984 *mipsI,mipsII,mipsIII,mipsIV:
1987 // start-sanitize-vr4320
1989 // end-sanitize-vr4320
1990 // start-sanitize-cygnus
1992 // end-sanitize-cygnus
1993 // start-sanitize-r5900
1995 // end-sanitize-r5900
1997 // start-sanitize-tx19
1999 // end-sanitize-tx19
2001 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
2005 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2006 "lbu r<RT>, <OFFSET>(r<BASE>)"
2007 *mipsI,mipsII,mipsIII,mipsIV:
2010 // start-sanitize-vr4320
2012 // end-sanitize-vr4320
2013 // start-sanitize-cygnus
2015 // end-sanitize-cygnus
2016 // start-sanitize-r5900
2018 // end-sanitize-r5900
2020 // start-sanitize-tx19
2022 // end-sanitize-tx19
2024 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
2028 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2029 "ld r<RT>, <OFFSET>(r<BASE>)"
2034 // start-sanitize-vr4320
2036 // end-sanitize-vr4320
2037 // start-sanitize-cygnus
2039 // end-sanitize-cygnus
2040 // start-sanitize-r5900
2042 // end-sanitize-r5900
2043 // start-sanitize-tx19
2045 // end-sanitize-tx19
2047 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2051 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
2052 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2058 // start-sanitize-vr4320
2060 // end-sanitize-vr4320
2061 // start-sanitize-cygnus
2063 // end-sanitize-cygnus
2065 // start-sanitize-tx19
2067 // end-sanitize-tx19
2069 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2075 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2076 "ldl r<RT>, <OFFSET>(r<BASE>)"
2081 // start-sanitize-vr4320
2083 // end-sanitize-vr4320
2084 // start-sanitize-cygnus
2086 // end-sanitize-cygnus
2087 // start-sanitize-r5900
2089 // end-sanitize-r5900
2090 // start-sanitize-tx19
2092 // end-sanitize-tx19
2094 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2098 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2099 "ldr r<RT>, <OFFSET>(r<BASE>)"
2104 // start-sanitize-vr4320
2106 // end-sanitize-vr4320
2107 // start-sanitize-cygnus
2109 // end-sanitize-cygnus
2110 // start-sanitize-r5900
2112 // end-sanitize-r5900
2113 // start-sanitize-tx19
2115 // end-sanitize-tx19
2117 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2121 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2122 "lh r<RT>, <OFFSET>(r<BASE>)"
2123 *mipsI,mipsII,mipsIII,mipsIV:
2126 // start-sanitize-vr4320
2128 // end-sanitize-vr4320
2129 // start-sanitize-cygnus
2131 // end-sanitize-cygnus
2132 // start-sanitize-r5900
2134 // end-sanitize-r5900
2136 // start-sanitize-tx19
2138 // end-sanitize-tx19
2140 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2144 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2145 "lhu r<RT>, <OFFSET>(r<BASE>)"
2146 *mipsI,mipsII,mipsIII,mipsIV:
2149 // start-sanitize-vr4320
2151 // end-sanitize-vr4320
2152 // start-sanitize-cygnus
2154 // end-sanitize-cygnus
2155 // start-sanitize-r5900
2157 // end-sanitize-r5900
2159 // start-sanitize-tx19
2161 // end-sanitize-tx19
2163 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2167 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2168 "ll r<RT>, <OFFSET>(r<BASE>)"
2174 // start-sanitize-vr4320
2176 // end-sanitize-vr4320
2177 // start-sanitize-cygnus
2179 // end-sanitize-cygnus
2180 // start-sanitize-r5900
2182 // end-sanitize-r5900
2183 // start-sanitize-tx19
2185 // end-sanitize-tx19
2187 unsigned32 instruction = instruction_0;
2188 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2189 int destreg = ((instruction >> 16) & 0x0000001F);
2190 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2192 address_word vaddr = ((unsigned64)op1 + offset);
2195 if ((vaddr & 3) != 0)
2196 SignalExceptionAddressLoad();
2199 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2201 unsigned64 memval = 0;
2202 unsigned64 memval1 = 0;
2203 unsigned64 mask = 0x7;
2204 unsigned int shift = 2;
2205 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2206 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2208 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2209 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2210 byte = ((vaddr & mask) ^ (bigend << shift));
2211 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2219 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2220 "lld r<RT>, <OFFSET>(r<BASE>)"
2225 // start-sanitize-vr4320
2227 // end-sanitize-vr4320
2228 // start-sanitize-cygnus
2230 // end-sanitize-cygnus
2231 // start-sanitize-r5900
2233 // end-sanitize-r5900
2234 // start-sanitize-tx19
2236 // end-sanitize-tx19
2238 unsigned32 instruction = instruction_0;
2239 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2240 int destreg = ((instruction >> 16) & 0x0000001F);
2241 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2243 address_word vaddr = ((unsigned64)op1 + offset);
2246 if ((vaddr & 7) != 0)
2247 SignalExceptionAddressLoad();
2250 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2252 unsigned64 memval = 0;
2253 unsigned64 memval1 = 0;
2254 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2255 GPR[destreg] = memval;
2263 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2264 "lui r<RT>, <IMMEDIATE>"
2265 *mipsI,mipsII,mipsIII,mipsIV:
2268 // start-sanitize-vr4320
2270 // end-sanitize-vr4320
2271 // start-sanitize-cygnus
2273 // end-sanitize-cygnus
2274 // start-sanitize-r5900
2276 // end-sanitize-r5900
2278 // start-sanitize-tx19
2280 // end-sanitize-tx19
2282 TRACE_ALU_INPUT1 (IMMEDIATE);
2283 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2284 TRACE_ALU_RESULT (GPR[RT]);
2288 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2289 "lw r<RT>, <OFFSET>(r<BASE>)"
2290 *mipsI,mipsII,mipsIII,mipsIV:
2293 // start-sanitize-vr4320
2295 // end-sanitize-vr4320
2296 // start-sanitize-cygnus
2298 // end-sanitize-cygnus
2299 // start-sanitize-r5900
2301 // end-sanitize-r5900
2303 // start-sanitize-tx19
2305 // end-sanitize-tx19
2307 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2311 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2312 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2313 *mipsI,mipsII,mipsIII,mipsIV:
2316 // start-sanitize-vr4320
2318 // end-sanitize-vr4320
2319 // start-sanitize-cygnus
2321 // end-sanitize-cygnus
2322 // start-sanitize-r5900
2324 // end-sanitize-r5900
2326 // start-sanitize-tx19
2328 // end-sanitize-tx19
2330 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2334 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2336 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2337 address_word reverseendian = (ReverseEndian ? -1 : 0);
2338 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2347 unsigned_word lhs_mask;
2350 vaddr = base + offset;
2351 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2352 paddr = (paddr ^ (reverseendian & mask));
2353 if (BigEndianMem == 0)
2354 paddr = paddr & ~access;
2356 /* compute where within the word/mem we are */
2357 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2358 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2359 nr_lhs_bits = 8 * byte + 8;
2360 nr_rhs_bits = 8 * access - 8 * byte;
2361 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2363 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2364 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2365 (long) ((unsigned64) paddr >> 32), (long) paddr,
2366 word, byte, nr_lhs_bits, nr_rhs_bits); */
2368 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2371 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2372 temp = (memval << nr_rhs_bits);
2376 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2377 temp = (memval >> nr_lhs_bits);
2379 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2380 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2382 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2383 (long) ((unsigned64) memval >> 32), (long) memval,
2384 (long) ((unsigned64) temp >> 32), (long) temp,
2385 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2386 (long) (rt >> 32), (long) rt); */
2391 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2392 "lwl r<RT>, <OFFSET>(r<BASE>)"
2393 *mipsI,mipsII,mipsIII,mipsIV:
2396 // start-sanitize-vr4320
2398 // end-sanitize-vr4320
2399 // start-sanitize-cygnus
2401 // end-sanitize-cygnus
2402 // start-sanitize-r5900
2404 // end-sanitize-r5900
2406 // start-sanitize-tx19
2408 // end-sanitize-tx19
2410 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2414 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2416 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2417 address_word reverseendian = (ReverseEndian ? -1 : 0);
2418 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2425 vaddr = base + offset;
2426 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2427 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2428 paddr = (paddr ^ (reverseendian & mask));
2429 if (BigEndianMem != 0)
2430 paddr = paddr & ~access;
2431 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2432 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
2433 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2434 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2435 (long) paddr, byte, (long) paddr, (long) memval); */
2437 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2439 rt |= (memval >> (8 * byte)) & screen;
2445 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2446 "lwr r<RT>, <OFFSET>(r<BASE>)"
2447 *mipsI,mipsII,mipsIII,mipsIV:
2450 // start-sanitize-vr4320
2452 // end-sanitize-vr4320
2453 // start-sanitize-cygnus
2455 // end-sanitize-cygnus
2456 // start-sanitize-r5900
2458 // end-sanitize-r5900
2460 // start-sanitize-tx19
2462 // end-sanitize-tx19
2464 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2468 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2469 "lwu r<RT>, <OFFSET>(r<BASE>)"
2474 // start-sanitize-vr4320
2476 // end-sanitize-vr4320
2477 // start-sanitize-cygnus
2479 // end-sanitize-cygnus
2480 // start-sanitize-r5900
2482 // end-sanitize-r5900
2483 // start-sanitize-tx19
2485 // end-sanitize-tx19
2487 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2491 :function:::void:do_mfhi:int rd
2493 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2494 TRACE_ALU_INPUT1 (HI);
2496 TRACE_ALU_RESULT (GPR[rd]);
2499 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2501 *mipsI,mipsII,mipsIII,mipsIV:
2504 // start-sanitize-vr4320
2506 // end-sanitize-vr4320
2507 // start-sanitize-cygnus
2509 // end-sanitize-cygnus
2510 // start-sanitize-r5900
2512 // end-sanitize-r5900
2514 // start-sanitize-tx19
2516 // end-sanitize-tx19
2523 :function:::void:do_mflo:int rd
2525 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2526 TRACE_ALU_INPUT1 (LO);
2528 TRACE_ALU_RESULT (GPR[rd]);
2531 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2533 *mipsI,mipsII,mipsIII,mipsIV:
2536 // start-sanitize-vr4320
2538 // end-sanitize-vr4320
2539 // start-sanitize-cygnus
2541 // end-sanitize-cygnus
2542 // start-sanitize-r5900
2544 // end-sanitize-r5900
2546 // start-sanitize-tx19
2548 // end-sanitize-tx19
2555 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2556 "movn r<RD>, r<RS>, r<RT>"
2559 // start-sanitize-vr4320
2561 // end-sanitize-vr4320
2562 // start-sanitize-cygnus
2564 // end-sanitize-cygnus
2565 // start-sanitize-r5900
2567 // end-sanitize-r5900
2575 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2576 "movz r<RD>, r<RS>, r<RT>"
2579 // start-sanitize-vr4320
2581 // end-sanitize-vr4320
2582 // start-sanitize-cygnus
2584 // end-sanitize-cygnus
2585 // start-sanitize-r5900
2587 // end-sanitize-r5900
2595 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2597 *mipsI,mipsII,mipsIII,mipsIV:
2600 // start-sanitize-vr4320
2602 // end-sanitize-vr4320
2603 // start-sanitize-cygnus
2605 // end-sanitize-cygnus
2606 // start-sanitize-r5900
2608 // end-sanitize-r5900
2610 // start-sanitize-tx19
2612 // end-sanitize-tx19
2614 check_mt_hilo (SD_, HIHISTORY);
2620 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2622 *mipsI,mipsII,mipsIII,mipsIV:
2625 // start-sanitize-vr4320
2627 // end-sanitize-vr4320
2628 // start-sanitize-cygnus
2630 // end-sanitize-cygnus
2631 // start-sanitize-r5900
2633 // end-sanitize-r5900
2635 // start-sanitize-tx19
2637 // end-sanitize-tx19
2639 check_mt_hilo (SD_, LOHISTORY);
2645 :function:::void:do_mult:int rs, int rt, int rd
2648 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2649 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2650 prod = (((signed64)(signed32) GPR[rs])
2651 * ((signed64)(signed32) GPR[rt]));
2652 LO = EXTEND32 (VL4_8 (prod));
2653 HI = EXTEND32 (VH4_8 (prod));
2656 TRACE_ALU_RESULT2 (HI, LO);
2659 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2661 *mipsI,mipsII,mipsIII,mipsIV:
2663 // start-sanitize-vr4320
2665 // end-sanitize-vr4320
2667 do_mult (SD_, RS, RT, 0);
2671 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2672 "mult r<RD>, r<RS>, r<RT>"
2674 // start-sanitize-cygnus
2676 // end-sanitize-cygnus
2677 // start-sanitize-r5900
2679 // end-sanitize-r5900
2681 // start-sanitize-tx19
2683 // end-sanitize-tx19
2685 do_mult (SD_, RS, RT, RD);
2689 :function:::void:do_multu:int rs, int rt, int rd
2692 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2693 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2694 prod = (((unsigned64)(unsigned32) GPR[rs])
2695 * ((unsigned64)(unsigned32) GPR[rt]));
2696 LO = EXTEND32 (VL4_8 (prod));
2697 HI = EXTEND32 (VH4_8 (prod));
2700 TRACE_ALU_RESULT2 (HI, LO);
2703 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2704 "multu r<RS>, r<RT>"
2705 *mipsI,mipsII,mipsIII,mipsIV:
2707 // start-sanitize-vr4320
2709 // end-sanitize-vr4320
2711 do_multu (SD_, RS, RT, 0);
2714 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2715 "multu r<RD>, r<RS>, r<RT>"
2717 // start-sanitize-cygnus
2719 // end-sanitize-cygnus
2720 // start-sanitize-r5900
2722 // end-sanitize-r5900
2724 // start-sanitize-tx19
2726 // end-sanitize-tx19
2728 do_multu (SD_, RS, RT, 0);
2732 :function:::void:do_nor:int rs, int rt, int rd
2734 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2735 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2736 TRACE_ALU_RESULT (GPR[rd]);
2739 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2740 "nor r<RD>, r<RS>, r<RT>"
2741 *mipsI,mipsII,mipsIII,mipsIV:
2744 // start-sanitize-vr4320
2746 // end-sanitize-vr4320
2747 // start-sanitize-cygnus
2749 // end-sanitize-cygnus
2750 // start-sanitize-r5900
2752 // end-sanitize-r5900
2754 // start-sanitize-tx19
2756 // end-sanitize-tx19
2758 do_nor (SD_, RS, RT, RD);
2762 :function:::void:do_or:int rs, int rt, int rd
2764 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2765 GPR[rd] = (GPR[rs] | GPR[rt]);
2766 TRACE_ALU_RESULT (GPR[rd]);
2769 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2770 "or r<RD>, r<RS>, r<RT>"
2771 *mipsI,mipsII,mipsIII,mipsIV:
2774 // start-sanitize-vr4320
2776 // end-sanitize-vr4320
2777 // start-sanitize-cygnus
2779 // end-sanitize-cygnus
2780 // start-sanitize-r5900
2782 // end-sanitize-r5900
2784 // start-sanitize-tx19
2786 // end-sanitize-tx19
2788 do_or (SD_, RS, RT, RD);
2793 :function:::void:do_ori:int rs, int rt, unsigned immediate
2795 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2796 GPR[rt] = (GPR[rs] | immediate);
2797 TRACE_ALU_RESULT (GPR[rt]);
2800 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2801 "ori r<RT>, r<RS>, <IMMEDIATE>"
2802 *mipsI,mipsII,mipsIII,mipsIV:
2805 // start-sanitize-vr4320
2807 // end-sanitize-vr4320
2808 // start-sanitize-cygnus
2810 // end-sanitize-cygnus
2811 // start-sanitize-r5900
2813 // end-sanitize-r5900
2815 // start-sanitize-tx19
2817 // end-sanitize-tx19
2819 do_ori (SD_, RS, RT, IMMEDIATE);
2823 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2826 // start-sanitize-vr4320
2828 // end-sanitize-vr4320
2829 // start-sanitize-cygnus
2831 // end-sanitize-cygnus
2832 // start-sanitize-r5900
2834 // end-sanitize-r5900
2836 unsigned32 instruction = instruction_0;
2837 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2838 int hint = ((instruction >> 16) & 0x0000001F);
2839 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2841 address_word vaddr = ((unsigned64)op1 + offset);
2845 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2846 Prefetch(uncached,paddr,vaddr,isDATA,hint);
2851 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2853 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2854 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2855 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2862 vaddr = base + offset;
2863 if ((vaddr & access) != 0)
2864 SignalExceptionAddressStore ();
2865 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2866 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2867 byte = ((vaddr & mask) ^ bigendiancpu);
2868 memval = (word << (8 * byte));
2869 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2873 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2874 "sb r<RT>, <OFFSET>(r<BASE>)"
2875 *mipsI,mipsII,mipsIII,mipsIV:
2878 // start-sanitize-vr4320
2880 // end-sanitize-vr4320
2881 // start-sanitize-cygnus
2883 // end-sanitize-cygnus
2884 // start-sanitize-r5900
2886 // end-sanitize-r5900
2888 // start-sanitize-tx19
2890 // end-sanitize-tx19
2892 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2896 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2897 "sc r<RT>, <OFFSET>(r<BASE>)"
2903 // start-sanitize-vr4320
2905 // end-sanitize-vr4320
2906 // start-sanitize-cygnus
2908 // end-sanitize-cygnus
2909 // start-sanitize-r5900
2911 // end-sanitize-r5900
2912 // start-sanitize-tx19
2914 // end-sanitize-tx19
2916 unsigned32 instruction = instruction_0;
2917 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2918 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2919 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2921 address_word vaddr = ((unsigned64)op1 + offset);
2924 if ((vaddr & 3) != 0)
2925 SignalExceptionAddressStore();
2928 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2930 unsigned64 memval = 0;
2931 unsigned64 memval1 = 0;
2932 unsigned64 mask = 0x7;
2934 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2935 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2936 memval = ((unsigned64) op2 << (8 * byte));
2939 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2941 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2948 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2949 "scd r<RT>, <OFFSET>(r<BASE>)"
2954 // start-sanitize-vr4320
2956 // end-sanitize-vr4320
2957 // start-sanitize-cygnus
2959 // end-sanitize-cygnus
2960 // start-sanitize-r5900
2962 // end-sanitize-r5900
2963 // start-sanitize-tx19
2965 // end-sanitize-tx19
2967 unsigned32 instruction = instruction_0;
2968 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2969 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2970 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2972 address_word vaddr = ((unsigned64)op1 + offset);
2975 if ((vaddr & 7) != 0)
2976 SignalExceptionAddressStore();
2979 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2981 unsigned64 memval = 0;
2982 unsigned64 memval1 = 0;
2986 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2988 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2995 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2996 "sd r<RT>, <OFFSET>(r<BASE>)"
3001 // start-sanitize-vr4320
3003 // end-sanitize-vr4320
3004 // start-sanitize-cygnus
3006 // end-sanitize-cygnus
3007 // start-sanitize-r5900
3009 // end-sanitize-r5900
3010 // start-sanitize-tx19
3012 // end-sanitize-tx19
3014 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3018 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3019 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3025 // start-sanitize-vr4320
3027 // end-sanitize-vr4320
3028 // start-sanitize-cygnus
3030 // end-sanitize-cygnus
3031 // start-sanitize-tx19
3033 // end-sanitize-tx19
3035 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3039 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3040 "sdl r<RT>, <OFFSET>(r<BASE>)"
3045 // start-sanitize-vr4320
3047 // end-sanitize-vr4320
3048 // start-sanitize-cygnus
3050 // end-sanitize-cygnus
3051 // start-sanitize-r5900
3053 // end-sanitize-r5900
3054 // start-sanitize-tx19
3056 // end-sanitize-tx19
3058 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3062 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3063 "sdr r<RT>, <OFFSET>(r<BASE>)"
3068 // start-sanitize-vr4320
3070 // end-sanitize-vr4320
3071 // start-sanitize-cygnus
3073 // end-sanitize-cygnus
3074 // start-sanitize-r5900
3076 // end-sanitize-r5900
3077 // start-sanitize-tx19
3079 // end-sanitize-tx19
3081 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3085 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3086 "sh r<RT>, <OFFSET>(r<BASE>)"
3087 *mipsI,mipsII,mipsIII,mipsIV:
3090 // start-sanitize-vr4320
3092 // end-sanitize-vr4320
3093 // start-sanitize-cygnus
3095 // end-sanitize-cygnus
3096 // start-sanitize-r5900
3098 // end-sanitize-r5900
3100 // start-sanitize-tx19
3102 // end-sanitize-tx19
3104 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3108 :function:::void:do_sll:int rt, int rd, int shift
3110 unsigned32 temp = (GPR[rt] << shift);
3111 TRACE_ALU_INPUT2 (GPR[rt], shift);
3112 GPR[rd] = EXTEND32 (temp);
3113 TRACE_ALU_RESULT (GPR[rd]);
3116 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
3117 "sll r<RD>, r<RT>, <SHIFT>"
3118 *mipsI,mipsII,mipsIII,mipsIV:
3121 // start-sanitize-vr4320
3123 // end-sanitize-vr4320
3124 // start-sanitize-cygnus
3126 // end-sanitize-cygnus
3127 // start-sanitize-r5900
3129 // end-sanitize-r5900
3131 // start-sanitize-tx19
3133 // end-sanitize-tx19
3135 do_sll (SD_, RT, RD, SHIFT);
3139 :function:::void:do_sllv:int rs, int rt, int rd
3141 int s = MASKED (GPR[rs], 4, 0);
3142 unsigned32 temp = (GPR[rt] << s);
3143 TRACE_ALU_INPUT2 (GPR[rt], s);
3144 GPR[rd] = EXTEND32 (temp);
3145 TRACE_ALU_RESULT (GPR[rd]);
3148 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
3149 "sllv r<RD>, r<RT>, r<RS>"
3150 *mipsI,mipsII,mipsIII,mipsIV:
3153 // start-sanitize-vr4320
3155 // end-sanitize-vr4320
3156 // start-sanitize-cygnus
3158 // end-sanitize-cygnus
3159 // start-sanitize-r5900
3161 // end-sanitize-r5900
3163 // start-sanitize-tx19
3165 // end-sanitize-tx19
3167 do_sllv (SD_, RS, RT, RD);
3171 :function:::void:do_slt:int rs, int rt, int rd
3173 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3174 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3175 TRACE_ALU_RESULT (GPR[rd]);
3178 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
3179 "slt r<RD>, r<RS>, r<RT>"
3180 *mipsI,mipsII,mipsIII,mipsIV:
3183 // start-sanitize-vr4320
3185 // end-sanitize-vr4320
3186 // start-sanitize-cygnus
3188 // end-sanitize-cygnus
3189 // start-sanitize-r5900
3191 // end-sanitize-r5900
3193 // start-sanitize-tx19
3195 // end-sanitize-tx19
3197 do_slt (SD_, RS, RT, RD);
3201 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3203 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3204 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3205 TRACE_ALU_RESULT (GPR[rt]);
3208 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3209 "slti r<RT>, r<RS>, <IMMEDIATE>"
3210 *mipsI,mipsII,mipsIII,mipsIV:
3213 // start-sanitize-vr4320
3215 // end-sanitize-vr4320
3216 // start-sanitize-cygnus
3218 // end-sanitize-cygnus
3219 // start-sanitize-r5900
3221 // end-sanitize-r5900
3223 // start-sanitize-tx19
3225 // end-sanitize-tx19
3227 do_slti (SD_, RS, RT, IMMEDIATE);
3231 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3233 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3234 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3235 TRACE_ALU_RESULT (GPR[rt]);
3238 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3239 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3240 *mipsI,mipsII,mipsIII,mipsIV:
3243 // start-sanitize-vr4320
3245 // end-sanitize-vr4320
3246 // start-sanitize-cygnus
3248 // end-sanitize-cygnus
3249 // start-sanitize-r5900
3251 // end-sanitize-r5900
3253 // start-sanitize-tx19
3255 // end-sanitize-tx19
3257 do_sltiu (SD_, RS, RT, IMMEDIATE);
3262 :function:::void:do_sltu:int rs, int rt, int rd
3264 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3265 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3266 TRACE_ALU_RESULT (GPR[rd]);
3269 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3270 "sltu r<RD>, r<RS>, r<RT>"
3271 *mipsI,mipsII,mipsIII,mipsIV:
3274 // start-sanitize-vr4320
3276 // end-sanitize-vr4320
3277 // start-sanitize-cygnus
3279 // end-sanitize-cygnus
3280 // start-sanitize-r5900
3282 // end-sanitize-r5900
3284 // start-sanitize-tx19
3286 // end-sanitize-tx19
3288 do_sltu (SD_, RS, RT, RD);
3292 :function:::void:do_sra:int rt, int rd, int shift
3294 signed32 temp = (signed32) GPR[rt] >> shift;
3295 TRACE_ALU_INPUT2 (GPR[rt], shift);
3296 GPR[rd] = EXTEND32 (temp);
3297 TRACE_ALU_RESULT (GPR[rd]);
3300 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3301 "sra r<RD>, r<RT>, <SHIFT>"
3302 *mipsI,mipsII,mipsIII,mipsIV:
3305 // start-sanitize-vr4320
3307 // end-sanitize-vr4320
3308 // start-sanitize-cygnus
3310 // end-sanitize-cygnus
3311 // start-sanitize-r5900
3313 // end-sanitize-r5900
3315 // start-sanitize-tx19
3317 // end-sanitize-tx19
3319 do_sra (SD_, RT, RD, SHIFT);
3324 :function:::void:do_srav:int rs, int rt, int rd
3326 int s = MASKED (GPR[rs], 4, 0);
3327 signed32 temp = (signed32) GPR[rt] >> s;
3328 TRACE_ALU_INPUT2 (GPR[rt], s);
3329 GPR[rd] = EXTEND32 (temp);
3330 TRACE_ALU_RESULT (GPR[rd]);
3333 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3334 "srav r<RD>, r<RT>, r<RS>"
3335 *mipsI,mipsII,mipsIII,mipsIV:
3338 // start-sanitize-vr4320
3340 // end-sanitize-vr4320
3341 // start-sanitize-cygnus
3343 // end-sanitize-cygnus
3344 // start-sanitize-r5900
3346 // end-sanitize-r5900
3348 // start-sanitize-tx19
3350 // end-sanitize-tx19
3352 do_srav (SD_, RS, RT, RD);
3357 :function:::void:do_srl:int rt, int rd, int shift
3359 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3360 TRACE_ALU_INPUT2 (GPR[rt], shift);
3361 GPR[rd] = EXTEND32 (temp);
3362 TRACE_ALU_RESULT (GPR[rd]);
3365 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3366 "srl r<RD>, r<RT>, <SHIFT>"
3367 *mipsI,mipsII,mipsIII,mipsIV:
3370 // start-sanitize-vr4320
3372 // end-sanitize-vr4320
3373 // start-sanitize-cygnus
3375 // end-sanitize-cygnus
3376 // start-sanitize-r5900
3378 // end-sanitize-r5900
3380 // start-sanitize-tx19
3382 // end-sanitize-tx19
3384 do_srl (SD_, RT, RD, SHIFT);
3388 :function:::void:do_srlv:int rs, int rt, int rd
3390 int s = MASKED (GPR[rs], 4, 0);
3391 unsigned32 temp = (unsigned32) GPR[rt] >> s;
3392 TRACE_ALU_INPUT2 (GPR[rt], s);
3393 GPR[rd] = EXTEND32 (temp);
3394 TRACE_ALU_RESULT (GPR[rd]);
3397 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3398 "srlv r<RD>, r<RT>, r<RS>"
3399 *mipsI,mipsII,mipsIII,mipsIV:
3402 // start-sanitize-vr4320
3404 // end-sanitize-vr4320
3405 // start-sanitize-cygnus
3407 // end-sanitize-cygnus
3408 // start-sanitize-r5900
3410 // end-sanitize-r5900
3412 // start-sanitize-tx19
3414 // end-sanitize-tx19
3416 do_srlv (SD_, RS, RT, RD);
3420 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3421 "sub r<RD>, r<RS>, r<RT>"
3422 *mipsI,mipsII,mipsIII,mipsIV:
3425 // start-sanitize-vr4320
3427 // end-sanitize-vr4320
3428 // start-sanitize-cygnus
3430 // end-sanitize-cygnus
3431 // start-sanitize-r5900
3433 // end-sanitize-r5900
3435 // start-sanitize-tx19
3437 // end-sanitize-tx19
3439 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3441 ALU32_BEGIN (GPR[RS]);
3442 ALU32_SUB (GPR[RT]);
3443 ALU32_END (GPR[RD]);
3445 TRACE_ALU_RESULT (GPR[RD]);
3449 :function:::void:do_subu:int rs, int rt, int rd
3451 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3452 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3453 TRACE_ALU_RESULT (GPR[rd]);
3456 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3457 "subu r<RD>, r<RS>, r<RT>"
3458 *mipsI,mipsII,mipsIII,mipsIV:
3461 // start-sanitize-vr4320
3463 // end-sanitize-vr4320
3464 // start-sanitize-cygnus
3466 // end-sanitize-cygnus
3467 // start-sanitize-r5900
3469 // end-sanitize-r5900
3471 // start-sanitize-tx19
3473 // end-sanitize-tx19
3475 do_subu (SD_, RS, RT, RD);
3479 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3480 "sw r<RT>, <OFFSET>(r<BASE>)"
3481 *mipsI,mipsII,mipsIII,mipsIV:
3483 // start-sanitize-tx19
3485 // end-sanitize-tx19
3487 // start-sanitize-vr4320
3489 // end-sanitize-vr4320
3491 // start-sanitize-cygnus
3493 // end-sanitize-cygnus
3494 // start-sanitize-r5900
3496 // end-sanitize-r5900
3498 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3502 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3503 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3504 *mipsI,mipsII,mipsIII,mipsIV:
3507 // start-sanitize-vr4320
3509 // end-sanitize-vr4320
3510 // start-sanitize-cygnus
3512 // end-sanitize-cygnus
3514 // start-sanitize-tx19
3516 // end-sanitize-tx19
3518 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3523 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3525 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3526 address_word reverseendian = (ReverseEndian ? -1 : 0);
3527 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3537 vaddr = base + offset;
3538 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3539 paddr = (paddr ^ (reverseendian & mask));
3540 if (BigEndianMem == 0)
3541 paddr = paddr & ~access;
3543 /* compute where within the word/mem we are */
3544 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3545 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3546 nr_lhs_bits = 8 * byte + 8;
3547 nr_rhs_bits = 8 * access - 8 * byte;
3548 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3549 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3550 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3551 (long) ((unsigned64) paddr >> 32), (long) paddr,
3552 word, byte, nr_lhs_bits, nr_rhs_bits); */
3556 memval = (rt >> nr_rhs_bits);
3560 memval = (rt << nr_lhs_bits);
3562 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3563 (long) ((unsigned64) rt >> 32), (long) rt,
3564 (long) ((unsigned64) memval >> 32), (long) memval); */
3565 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3569 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3570 "swl r<RT>, <OFFSET>(r<BASE>)"
3571 *mipsI,mipsII,mipsIII,mipsIV:
3574 // start-sanitize-vr4320
3576 // end-sanitize-vr4320
3577 // start-sanitize-cygnus
3579 // end-sanitize-cygnus
3580 // start-sanitize-r5900
3582 // end-sanitize-r5900
3584 // start-sanitize-tx19
3586 // end-sanitize-tx19
3588 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3592 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3594 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3595 address_word reverseendian = (ReverseEndian ? -1 : 0);
3596 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3603 vaddr = base + offset;
3604 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3605 paddr = (paddr ^ (reverseendian & mask));
3606 if (BigEndianMem != 0)
3608 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3609 memval = (rt << (byte * 8));
3610 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3613 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3614 "swr r<RT>, <OFFSET>(r<BASE>)"
3615 *mipsI,mipsII,mipsIII,mipsIV:
3618 // start-sanitize-vr4320
3620 // end-sanitize-vr4320
3621 // start-sanitize-cygnus
3623 // end-sanitize-cygnus
3624 // start-sanitize-r5900
3626 // end-sanitize-r5900
3628 // start-sanitize-tx19
3630 // end-sanitize-tx19
3632 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3636 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3644 // start-sanitize-vr4320
3646 // end-sanitize-vr4320
3647 // start-sanitize-cygnus
3649 // end-sanitize-cygnus
3650 // start-sanitize-r5900
3652 // end-sanitize-r5900
3654 // start-sanitize-tx19
3656 // end-sanitize-tx19
3658 SyncOperation (STYPE);
3662 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3664 *mipsI,mipsII,mipsIII,mipsIV:
3667 // start-sanitize-vr4320
3669 // end-sanitize-vr4320
3670 // start-sanitize-cygnus
3672 // end-sanitize-cygnus
3673 // start-sanitize-r5900
3675 // end-sanitize-r5900
3677 // start-sanitize-tx19
3679 // end-sanitize-tx19
3681 SignalException(SystemCall, instruction_0);
3685 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3692 // start-sanitize-vr4320
3694 // end-sanitize-vr4320
3695 // start-sanitize-cygnus
3697 // end-sanitize-cygnus
3698 // start-sanitize-r5900
3700 // end-sanitize-r5900
3701 // start-sanitize-tx19
3703 // end-sanitize-tx19
3705 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3706 SignalException(Trap, instruction_0);
3710 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3711 "teqi r<RS>, <IMMEDIATE>"
3717 // start-sanitize-vr4320
3719 // end-sanitize-vr4320
3720 // start-sanitize-cygnus
3722 // end-sanitize-cygnus
3723 // start-sanitize-r5900
3725 // end-sanitize-r5900
3726 // start-sanitize-tx19
3728 // end-sanitize-tx19
3730 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3731 SignalException(Trap, instruction_0);
3735 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3742 // start-sanitize-vr4320
3744 // end-sanitize-vr4320
3745 // start-sanitize-cygnus
3747 // end-sanitize-cygnus
3748 // start-sanitize-r5900
3750 // end-sanitize-r5900
3751 // start-sanitize-tx19
3753 // end-sanitize-tx19
3755 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3756 SignalException(Trap, instruction_0);
3760 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3761 "tgei r<RS>, <IMMEDIATE>"
3767 // start-sanitize-vr4320
3769 // end-sanitize-vr4320
3770 // start-sanitize-cygnus
3772 // end-sanitize-cygnus
3773 // start-sanitize-r5900
3775 // end-sanitize-r5900
3776 // start-sanitize-tx19
3778 // end-sanitize-tx19
3780 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3781 SignalException(Trap, instruction_0);
3785 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3786 "tgeiu r<RS>, <IMMEDIATE>"
3792 // start-sanitize-vr4320
3794 // end-sanitize-vr4320
3795 // start-sanitize-cygnus
3797 // end-sanitize-cygnus
3798 // start-sanitize-r5900
3800 // end-sanitize-r5900
3801 // start-sanitize-tx19
3803 // end-sanitize-tx19
3805 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3806 SignalException(Trap, instruction_0);
3810 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3817 // start-sanitize-vr4320
3819 // end-sanitize-vr4320
3820 // start-sanitize-cygnus
3822 // end-sanitize-cygnus
3823 // start-sanitize-r5900
3825 // end-sanitize-r5900
3826 // start-sanitize-tx19
3828 // end-sanitize-tx19
3830 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3831 SignalException(Trap, instruction_0);
3835 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3842 // start-sanitize-vr4320
3844 // end-sanitize-vr4320
3845 // start-sanitize-cygnus
3847 // end-sanitize-cygnus
3848 // start-sanitize-r5900
3850 // end-sanitize-r5900
3851 // start-sanitize-tx19
3853 // end-sanitize-tx19
3855 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3856 SignalException(Trap, instruction_0);
3860 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3861 "tlti r<RS>, <IMMEDIATE>"
3867 // start-sanitize-vr4320
3869 // end-sanitize-vr4320
3870 // start-sanitize-cygnus
3872 // end-sanitize-cygnus
3873 // start-sanitize-r5900
3875 // end-sanitize-r5900
3876 // start-sanitize-tx19
3878 // end-sanitize-tx19
3880 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3881 SignalException(Trap, instruction_0);
3885 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3886 "tltiu r<RS>, <IMMEDIATE>"
3892 // start-sanitize-vr4320
3894 // end-sanitize-vr4320
3895 // start-sanitize-cygnus
3897 // end-sanitize-cygnus
3898 // start-sanitize-r5900
3900 // end-sanitize-r5900
3901 // start-sanitize-tx19
3903 // end-sanitize-tx19
3905 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3906 SignalException(Trap, instruction_0);
3910 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3917 // start-sanitize-vr4320
3919 // end-sanitize-vr4320
3920 // start-sanitize-cygnus
3922 // end-sanitize-cygnus
3923 // start-sanitize-r5900
3925 // end-sanitize-r5900
3926 // start-sanitize-tx19
3928 // end-sanitize-tx19
3930 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3931 SignalException(Trap, instruction_0);
3935 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3942 // start-sanitize-vr4320
3944 // end-sanitize-vr4320
3945 // start-sanitize-cygnus
3947 // end-sanitize-cygnus
3948 // start-sanitize-r5900
3950 // end-sanitize-r5900
3951 // start-sanitize-tx19
3953 // end-sanitize-tx19
3955 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3956 SignalException(Trap, instruction_0);
3960 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3961 "tne r<RS>, <IMMEDIATE>"
3967 // start-sanitize-vr4320
3969 // end-sanitize-vr4320
3970 // start-sanitize-cygnus
3972 // end-sanitize-cygnus
3973 // start-sanitize-r5900
3975 // end-sanitize-r5900
3976 // start-sanitize-tx19
3978 // end-sanitize-tx19
3980 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3981 SignalException(Trap, instruction_0);
3985 :function:::void:do_xor:int rs, int rt, int rd
3987 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3988 GPR[rd] = GPR[rs] ^ GPR[rt];
3989 TRACE_ALU_RESULT (GPR[rd]);
3992 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3993 "xor r<RD>, r<RS>, r<RT>"
3994 *mipsI,mipsII,mipsIII,mipsIV:
3997 // start-sanitize-vr4320
3999 // end-sanitize-vr4320
4000 // start-sanitize-cygnus
4002 // end-sanitize-cygnus
4003 // start-sanitize-r5900
4005 // end-sanitize-r5900
4007 // start-sanitize-tx19
4009 // end-sanitize-tx19
4011 do_xor (SD_, RS, RT, RD);
4015 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
4017 TRACE_ALU_INPUT2 (GPR[rs], immediate);
4018 GPR[rt] = GPR[rs] ^ immediate;
4019 TRACE_ALU_RESULT (GPR[rt]);
4022 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
4023 "xori r<RT>, r<RS>, <IMMEDIATE>"
4024 *mipsI,mipsII,mipsIII,mipsIV:
4027 // start-sanitize-vr4320
4029 // end-sanitize-vr4320
4030 // start-sanitize-cygnus
4032 // end-sanitize-cygnus
4033 // start-sanitize-r5900
4035 // end-sanitize-r5900
4037 // start-sanitize-tx19
4039 // end-sanitize-tx19
4041 do_xori (SD_, RS, RT, IMMEDIATE);
4046 // MIPS Architecture:
4048 // FPU Instruction Set (COP1 & COP1X)
4056 case fmt_single: return "s";
4057 case fmt_double: return "d";
4058 case fmt_word: return "w";
4059 case fmt_long: return "l";
4060 default: return "?";
4070 default: return "?";
4090 :%s::::COND:int cond
4094 case 00: return "f";
4095 case 01: return "un";
4096 case 02: return "eq";
4097 case 03: return "ueq";
4098 case 04: return "olt";
4099 case 05: return "ult";
4100 case 06: return "ole";
4101 case 07: return "ule";
4102 case 010: return "sf";
4103 case 011: return "ngle";
4104 case 012: return "seq";
4105 case 013: return "ngl";
4106 case 014: return "lt";
4107 case 015: return "nge";
4108 case 016: return "le";
4109 case 017: return "ngt";
4110 default: return "?";
4115 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
4116 "abs.%s<FMT> f<FD>, f<FS>"
4117 *mipsI,mipsII,mipsIII,mipsIV:
4120 // start-sanitize-vr4320
4122 // end-sanitize-vr4320
4123 // start-sanitize-cygnus
4125 // end-sanitize-cygnus
4127 // start-sanitize-tx19
4129 // end-sanitize-tx19
4131 unsigned32 instruction = instruction_0;
4132 int destreg = ((instruction >> 6) & 0x0000001F);
4133 int fs = ((instruction >> 11) & 0x0000001F);
4134 int format = ((instruction >> 21) & 0x00000007);
4136 if ((format != fmt_single) && (format != fmt_double))
4137 SignalException(ReservedInstruction,instruction);
4139 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
4145 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
4146 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
4147 *mipsI,mipsII,mipsIII,mipsIV:
4150 // start-sanitize-vr4320
4152 // end-sanitize-vr4320
4153 // start-sanitize-cygnus
4155 // end-sanitize-cygnus
4157 // start-sanitize-tx19
4159 // end-sanitize-tx19
4161 unsigned32 instruction = instruction_0;
4162 int destreg = ((instruction >> 6) & 0x0000001F);
4163 int fs = ((instruction >> 11) & 0x0000001F);
4164 int ft = ((instruction >> 16) & 0x0000001F);
4165 int format = ((instruction >> 21) & 0x00000007);
4167 if ((format != fmt_single) && (format != fmt_double))
4168 SignalException(ReservedInstruction, instruction);
4170 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
4181 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
4182 "bc1%s<TF>%s<ND> <OFFSET>"
4183 *mipsI,mipsII,mipsIII:
4185 // start-sanitize-r5900
4187 // end-sanitize-r5900
4189 check_branch_bug ();
4190 TRACE_BRANCH_INPUT (PREVCOC1());
4191 if (PREVCOC1() == TF)
4193 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4194 TRACE_BRANCH_RESULT (dest);
4195 mark_branch_bug (dest);
4200 TRACE_BRANCH_RESULT (0);
4201 NULLIFY_NEXT_INSTRUCTION ();
4205 TRACE_BRANCH_RESULT (NIA);
4209 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
4210 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4211 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4214 // start-sanitize-vr4320
4216 // end-sanitize-vr4320
4217 // start-sanitize-cygnus
4219 // end-sanitize-cygnus
4221 // start-sanitize-tx19
4223 // end-sanitize-tx19
4225 check_branch_bug ();
4226 if (GETFCC(CC) == TF)
4228 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4229 mark_branch_bug (dest);
4234 NULLIFY_NEXT_INSTRUCTION ();
4247 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
4249 if ((fmt != fmt_single) && (fmt != fmt_double))
4250 SignalException (ReservedInstruction, insn);
4257 unsigned64 ofs = ValueFPR (fs, fmt);
4258 unsigned64 oft = ValueFPR (ft, fmt);
4259 if (NaN (ofs, fmt) || NaN (oft, fmt))
4261 if (FCSR & FP_ENABLE (IO))
4263 FCSR |= FP_CAUSE (IO);
4264 SignalExceptionFPE ();
4272 less = Less (ofs, oft, fmt);
4273 equal = Equal (ofs, oft, fmt);
4276 condition = (((cond & (1 << 2)) && less)
4277 || ((cond & (1 << 1)) && equal)
4278 || ((cond & (1 << 0)) && unordered));
4279 SETFCC (cc, condition);
4283 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
4284 *mipsI,mipsII,mipsIII:
4285 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4287 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4290 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
4291 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4292 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4296 // start-sanitize-vr4320
4298 // end-sanitize-vr4320
4299 // start-sanitize-cygnus
4301 // end-sanitize-cygnus
4303 // start-sanitize-tx19
4305 // end-sanitize-tx19
4307 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4311 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4312 "ceil.l.%s<FMT> f<FD>, f<FS>"
4317 // start-sanitize-vr4320
4319 // end-sanitize-vr4320
4320 // start-sanitize-cygnus
4322 // end-sanitize-cygnus
4323 // start-sanitize-r5900
4325 // end-sanitize-r5900
4327 // start-sanitize-tx19
4329 // end-sanitize-tx19
4331 unsigned32 instruction = instruction_0;
4332 int destreg = ((instruction >> 6) & 0x0000001F);
4333 int fs = ((instruction >> 11) & 0x0000001F);
4334 int format = ((instruction >> 21) & 0x00000007);
4336 if ((format != fmt_single) && (format != fmt_double))
4337 SignalException(ReservedInstruction,instruction);
4339 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4344 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4350 // start-sanitize-vr4320
4352 // end-sanitize-vr4320
4353 // start-sanitize-cygnus
4355 // end-sanitize-cygnus
4356 // start-sanitize-r5900
4358 // end-sanitize-r5900
4360 // start-sanitize-tx19
4362 // end-sanitize-tx19
4364 unsigned32 instruction = instruction_0;
4365 int destreg = ((instruction >> 6) & 0x0000001F);
4366 int fs = ((instruction >> 11) & 0x0000001F);
4367 int format = ((instruction >> 21) & 0x00000007);
4369 if ((format != fmt_single) && (format != fmt_double))
4370 SignalException(ReservedInstruction,instruction);
4372 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4379 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4380 "c%s<X>c1 r<RT>, f<FS>"
4388 PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4390 PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4392 PENDING_FILL(COCIDX,0); /* special case */
4395 { /* control from */
4397 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4399 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4403 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4404 "c%s<X>c1 r<RT>, f<FS>"
4408 // start-sanitize-vr4320
4410 // end-sanitize-vr4320
4411 // start-sanitize-cygnus
4413 // end-sanitize-cygnus
4415 // start-sanitize-tx19
4417 // end-sanitize-tx19
4422 TRACE_ALU_INPUT1 (GPR[RT]);
4425 FCR0 = VL4_8(GPR[RT]);
4426 TRACE_ALU_RESULT (FCR0);
4430 FCR31 = VL4_8(GPR[RT]);
4431 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4432 TRACE_ALU_RESULT (FCR31);
4436 TRACE_ALU_RESULT0 ();
4441 { /* control from */
4444 TRACE_ALU_INPUT1 (FCR0);
4445 GPR[RT] = SIGNEXTEND (FCR0, 32);
4449 TRACE_ALU_INPUT1 (FCR31);
4450 GPR[RT] = SIGNEXTEND (FCR31, 32);
4452 TRACE_ALU_RESULT (GPR[RT]);
4459 // FIXME: Does not correctly differentiate between mips*
4461 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4462 "cvt.d.%s<FMT> f<FD>, f<FS>"
4463 *mipsI,mipsII,mipsIII,mipsIV:
4466 // start-sanitize-vr4320
4468 // end-sanitize-vr4320
4469 // start-sanitize-cygnus
4471 // end-sanitize-cygnus
4473 // start-sanitize-tx19
4475 // end-sanitize-tx19
4477 unsigned32 instruction = instruction_0;
4478 int destreg = ((instruction >> 6) & 0x0000001F);
4479 int fs = ((instruction >> 11) & 0x0000001F);
4480 int format = ((instruction >> 21) & 0x00000007);
4482 if ((format == fmt_double) | 0)
4483 SignalException(ReservedInstruction,instruction);
4485 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4490 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4491 "cvt.l.%s<FMT> f<FD>, f<FS>"
4496 // start-sanitize-vr4320
4498 // end-sanitize-vr4320
4499 // start-sanitize-cygnus
4501 // end-sanitize-cygnus
4503 // start-sanitize-tx19
4505 // end-sanitize-tx19
4507 unsigned32 instruction = instruction_0;
4508 int destreg = ((instruction >> 6) & 0x0000001F);
4509 int fs = ((instruction >> 11) & 0x0000001F);
4510 int format = ((instruction >> 21) & 0x00000007);
4512 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4513 SignalException(ReservedInstruction,instruction);
4515 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4521 // FIXME: Does not correctly differentiate between mips*
4523 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4524 "cvt.s.%s<FMT> f<FD>, f<FS>"
4525 *mipsI,mipsII,mipsIII,mipsIV:
4528 // start-sanitize-vr4320
4530 // end-sanitize-vr4320
4531 // start-sanitize-cygnus
4533 // end-sanitize-cygnus
4535 // start-sanitize-tx19
4537 // end-sanitize-tx19
4539 unsigned32 instruction = instruction_0;
4540 int destreg = ((instruction >> 6) & 0x0000001F);
4541 int fs = ((instruction >> 11) & 0x0000001F);
4542 int format = ((instruction >> 21) & 0x00000007);
4544 if ((format == fmt_single) | 0)
4545 SignalException(ReservedInstruction,instruction);
4547 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4552 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4553 "cvt.w.%s<FMT> f<FD>, f<FS>"
4554 *mipsI,mipsII,mipsIII,mipsIV:
4557 // start-sanitize-vr4320
4559 // end-sanitize-vr4320
4560 // start-sanitize-cygnus
4562 // end-sanitize-cygnus
4564 // start-sanitize-tx19
4566 // end-sanitize-tx19
4568 unsigned32 instruction = instruction_0;
4569 int destreg = ((instruction >> 6) & 0x0000001F);
4570 int fs = ((instruction >> 11) & 0x0000001F);
4571 int format = ((instruction >> 21) & 0x00000007);
4573 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4574 SignalException(ReservedInstruction,instruction);
4576 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4581 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4582 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4583 *mipsI,mipsII,mipsIII,mipsIV:
4586 // start-sanitize-vr4320
4588 // end-sanitize-vr4320
4589 // start-sanitize-cygnus
4591 // end-sanitize-cygnus
4593 // start-sanitize-tx19
4595 // end-sanitize-tx19
4597 unsigned32 instruction = instruction_0;
4598 int destreg = ((instruction >> 6) & 0x0000001F);
4599 int fs = ((instruction >> 11) & 0x0000001F);
4600 int ft = ((instruction >> 16) & 0x0000001F);
4601 int format = ((instruction >> 21) & 0x00000007);
4603 if ((format != fmt_single) && (format != fmt_double))
4604 SignalException(ReservedInstruction,instruction);
4606 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4613 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4614 "dm%s<X>c1 r<RT>, f<FS>"
4619 if (SizeFGR() == 64)
4620 PENDING_FILL((FS + FGRIDX),GPR[RT]);
4621 else if ((FS & 0x1) == 0)
4623 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4624 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4629 if (SizeFGR() == 64)
4630 PENDING_FILL(RT,FGR[FS]);
4631 else if ((FS & 0x1) == 0)
4632 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4634 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4637 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4638 "dm%s<X>c1 r<RT>, f<FS>"
4642 // start-sanitize-vr4320
4644 // end-sanitize-vr4320
4645 // start-sanitize-cygnus
4647 // end-sanitize-cygnus
4648 // start-sanitize-r5900
4650 // end-sanitize-r5900
4652 // start-sanitize-tx19
4654 // end-sanitize-tx19
4658 if (SizeFGR() == 64)
4659 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4660 else if ((FS & 0x1) == 0)
4661 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4665 if (SizeFGR() == 64)
4667 else if ((FS & 0x1) == 0)
4668 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4670 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4675 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4676 "floor.l.%s<FMT> f<FD>, f<FS>"
4681 // start-sanitize-vr4320
4683 // end-sanitize-vr4320
4684 // start-sanitize-cygnus
4686 // end-sanitize-cygnus
4687 // start-sanitize-r5900
4689 // end-sanitize-r5900
4691 // start-sanitize-tx19
4693 // end-sanitize-tx19
4695 unsigned32 instruction = instruction_0;
4696 int destreg = ((instruction >> 6) & 0x0000001F);
4697 int fs = ((instruction >> 11) & 0x0000001F);
4698 int format = ((instruction >> 21) & 0x00000007);
4700 if ((format != fmt_single) && (format != fmt_double))
4701 SignalException(ReservedInstruction,instruction);
4703 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4708 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4709 "floor.w.%s<FMT> f<FD>, f<FS>"
4715 // start-sanitize-vr4320
4717 // end-sanitize-vr4320
4718 // start-sanitize-cygnus
4720 // end-sanitize-cygnus
4721 // start-sanitize-r5900
4723 // end-sanitize-r5900
4725 // start-sanitize-tx19
4727 // end-sanitize-tx19
4729 unsigned32 instruction = instruction_0;
4730 int destreg = ((instruction >> 6) & 0x0000001F);
4731 int fs = ((instruction >> 11) & 0x0000001F);
4732 int format = ((instruction >> 21) & 0x00000007);
4734 if ((format != fmt_single) && (format != fmt_double))
4735 SignalException(ReservedInstruction,instruction);
4737 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4742 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4743 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4749 // start-sanitize-vr4320
4751 // end-sanitize-vr4320
4752 // start-sanitize-cygnus
4754 // end-sanitize-cygnus
4756 // start-sanitize-tx19
4758 // end-sanitize-tx19
4760 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4764 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4765 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4768 // start-sanitize-vr4320
4770 // end-sanitize-vr4320
4771 // start-sanitize-cygnus
4773 // end-sanitize-cygnus
4775 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4780 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4781 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4782 *mipsI,mipsII,mipsIII,mipsIV:
4785 // start-sanitize-vr4320
4787 // end-sanitize-vr4320
4788 // start-sanitize-cygnus
4790 // end-sanitize-cygnus
4791 // start-sanitize-r5900
4793 // end-sanitize-r5900
4795 // start-sanitize-tx19
4797 // end-sanitize-tx19
4799 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4803 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4804 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4807 // start-sanitize-vr4320
4809 // end-sanitize-vr4320
4810 // start-sanitize-cygnus
4812 // end-sanitize-cygnus
4814 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4820 // FIXME: Not correct for mips*
4822 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4823 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4826 // start-sanitize-vr4320
4828 // end-sanitize-vr4320
4829 // start-sanitize-cygnus
4831 // end-sanitize-cygnus
4833 unsigned32 instruction = instruction_0;
4834 int destreg = ((instruction >> 6) & 0x0000001F);
4835 int fs = ((instruction >> 11) & 0x0000001F);
4836 int ft = ((instruction >> 16) & 0x0000001F);
4837 int fr = ((instruction >> 21) & 0x0000001F);
4839 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4844 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4845 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4848 // start-sanitize-vr4320
4850 // end-sanitize-vr4320
4851 // start-sanitize-cygnus
4853 // end-sanitize-cygnus
4855 unsigned32 instruction = instruction_0;
4856 int destreg = ((instruction >> 6) & 0x0000001F);
4857 int fs = ((instruction >> 11) & 0x0000001F);
4858 int ft = ((instruction >> 16) & 0x0000001F);
4859 int fr = ((instruction >> 21) & 0x0000001F);
4861 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4868 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4869 "m%s<X>c1 r<RT>, f<FS>"
4876 if (SizeFGR() == 64)
4877 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4879 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4882 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4884 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4885 "m%s<X>c1 r<RT>, f<FS>"
4889 // start-sanitize-vr4320
4891 // end-sanitize-vr4320
4892 // start-sanitize-cygnus
4894 // end-sanitize-cygnus
4896 // start-sanitize-tx19
4898 // end-sanitize-tx19
4902 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4904 GPR[RT] = SIGNEXTEND(FGR[FS],32);
4908 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4909 "mov.%s<FMT> f<FD>, f<FS>"
4910 *mipsI,mipsII,mipsIII,mipsIV:
4913 // start-sanitize-vr4320
4915 // end-sanitize-vr4320
4916 // start-sanitize-cygnus
4918 // end-sanitize-cygnus
4920 // start-sanitize-tx19
4922 // end-sanitize-tx19
4924 unsigned32 instruction = instruction_0;
4925 int destreg = ((instruction >> 6) & 0x0000001F);
4926 int fs = ((instruction >> 11) & 0x0000001F);
4927 int format = ((instruction >> 21) & 0x00000007);
4929 StoreFPR(destreg,format,ValueFPR(fs,format));
4935 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4936 "mov%s<TF> r<RD>, r<RS>, <CC>"
4939 // start-sanitize-vr4320
4941 // end-sanitize-vr4320
4942 // start-sanitize-cygnus
4944 // end-sanitize-cygnus
4945 // start-sanitize-r5900
4947 // end-sanitize-r5900
4949 if (GETFCC(CC) == TF)
4955 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4956 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4959 // start-sanitize-vr4320
4961 // end-sanitize-vr4320
4962 // start-sanitize-cygnus
4964 // end-sanitize-cygnus
4965 // start-sanitize-r5900
4967 // end-sanitize-r5900
4969 unsigned32 instruction = instruction_0;
4970 int format = ((instruction >> 21) & 0x00000007);
4972 if (GETFCC(CC) == TF)
4973 StoreFPR (FD, format, ValueFPR (FS, format));
4975 StoreFPR (FD, format, ValueFPR (FD, format));
4980 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4983 // start-sanitize-vr4320
4985 // end-sanitize-vr4320
4986 // start-sanitize-cygnus
4988 // end-sanitize-cygnus
4989 // start-sanitize-r5900
4991 // end-sanitize-r5900
4993 unsigned32 instruction = instruction_0;
4994 int destreg = ((instruction >> 6) & 0x0000001F);
4995 int fs = ((instruction >> 11) & 0x0000001F);
4996 int format = ((instruction >> 21) & 0x00000007);
4998 StoreFPR(destreg,format,ValueFPR(fs,format));
5006 // MOVT.fmt see MOVtf.fmt
5010 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
5011 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
5014 // start-sanitize-vr4320
5016 // end-sanitize-vr4320
5017 // start-sanitize-cygnus
5019 // end-sanitize-cygnus
5020 // start-sanitize-r5900
5022 // end-sanitize-r5900
5024 unsigned32 instruction = instruction_0;
5025 int destreg = ((instruction >> 6) & 0x0000001F);
5026 int fs = ((instruction >> 11) & 0x0000001F);
5027 int format = ((instruction >> 21) & 0x00000007);
5029 StoreFPR(destreg,format,ValueFPR(fs,format));
5035 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
5036 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
5039 // start-sanitize-vr4320
5041 // end-sanitize-vr4320
5042 // start-sanitize-cygnus
5044 // end-sanitize-cygnus
5045 // start-sanitize-r5900
5047 // end-sanitize-r5900
5049 unsigned32 instruction = instruction_0;
5050 int destreg = ((instruction >> 6) & 0x0000001F);
5051 int fs = ((instruction >> 11) & 0x0000001F);
5052 int ft = ((instruction >> 16) & 0x0000001F);
5053 int fr = ((instruction >> 21) & 0x0000001F);
5055 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
5061 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
5062 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
5065 // start-sanitize-vr4320
5067 // end-sanitize-vr4320
5068 // start-sanitize-cygnus
5070 // end-sanitize-cygnus
5071 // start-sanitize-r5900
5073 // end-sanitize-r5900
5075 unsigned32 instruction = instruction_0;
5076 int destreg = ((instruction >> 6) & 0x0000001F);
5077 int fs = ((instruction >> 11) & 0x0000001F);
5078 int ft = ((instruction >> 16) & 0x0000001F);
5079 int fr = ((instruction >> 21) & 0x0000001F);
5081 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
5089 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
5090 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
5091 *mipsI,mipsII,mipsIII,mipsIV:
5094 // start-sanitize-vr4320
5096 // end-sanitize-vr4320
5097 // start-sanitize-cygnus
5099 // end-sanitize-cygnus
5101 // start-sanitize-tx19
5103 // end-sanitize-tx19
5105 unsigned32 instruction = instruction_0;
5106 int destreg = ((instruction >> 6) & 0x0000001F);
5107 int fs = ((instruction >> 11) & 0x0000001F);
5108 int ft = ((instruction >> 16) & 0x0000001F);
5109 int format = ((instruction >> 21) & 0x00000007);
5111 if ((format != fmt_single) && (format != fmt_double))
5112 SignalException(ReservedInstruction,instruction);
5114 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
5119 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
5120 "neg.%s<FMT> f<FD>, f<FS>"
5121 *mipsI,mipsII,mipsIII,mipsIV:
5124 // start-sanitize-vr4320
5126 // end-sanitize-vr4320
5127 // start-sanitize-cygnus
5129 // end-sanitize-cygnus
5131 // start-sanitize-tx19
5133 // end-sanitize-tx19
5135 unsigned32 instruction = instruction_0;
5136 int destreg = ((instruction >> 6) & 0x0000001F);
5137 int fs = ((instruction >> 11) & 0x0000001F);
5138 int format = ((instruction >> 21) & 0x00000007);
5140 if ((format != fmt_single) && (format != fmt_double))
5141 SignalException(ReservedInstruction,instruction);
5143 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
5149 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
5150 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
5153 // start-sanitize-vr4320
5155 // end-sanitize-vr4320
5156 // start-sanitize-cygnus
5158 // end-sanitize-cygnus
5160 unsigned32 instruction = instruction_0;
5161 int destreg = ((instruction >> 6) & 0x0000001F);
5162 int fs = ((instruction >> 11) & 0x0000001F);
5163 int ft = ((instruction >> 16) & 0x0000001F);
5164 int fr = ((instruction >> 21) & 0x0000001F);
5166 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5172 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
5173 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
5176 // start-sanitize-vr4320
5178 // end-sanitize-vr4320
5179 // start-sanitize-cygnus
5181 // end-sanitize-cygnus
5183 unsigned32 instruction = instruction_0;
5184 int destreg = ((instruction >> 6) & 0x0000001F);
5185 int fs = ((instruction >> 11) & 0x0000001F);
5186 int ft = ((instruction >> 16) & 0x0000001F);
5187 int fr = ((instruction >> 21) & 0x0000001F);
5189 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5195 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
5196 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
5199 // start-sanitize-vr4320
5201 // end-sanitize-vr4320
5202 // start-sanitize-cygnus
5204 // end-sanitize-cygnus
5206 unsigned32 instruction = instruction_0;
5207 int destreg = ((instruction >> 6) & 0x0000001F);
5208 int fs = ((instruction >> 11) & 0x0000001F);
5209 int ft = ((instruction >> 16) & 0x0000001F);
5210 int fr = ((instruction >> 21) & 0x0000001F);
5212 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5218 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
5219 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
5222 // start-sanitize-vr4320
5224 // end-sanitize-vr4320
5225 // start-sanitize-cygnus
5227 // end-sanitize-cygnus
5229 unsigned32 instruction = instruction_0;
5230 int destreg = ((instruction >> 6) & 0x0000001F);
5231 int fs = ((instruction >> 11) & 0x0000001F);
5232 int ft = ((instruction >> 16) & 0x0000001F);
5233 int fr = ((instruction >> 21) & 0x0000001F);
5235 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5240 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
5241 "prefx <HINT>, r<INDEX>(r<BASE>)"
5244 // start-sanitize-vr4320
5246 // end-sanitize-vr4320
5247 // start-sanitize-cygnus
5249 // end-sanitize-cygnus
5251 unsigned32 instruction = instruction_0;
5252 int fs = ((instruction >> 11) & 0x0000001F);
5253 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5254 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5256 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
5259 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5260 Prefetch(uncached,paddr,vaddr,isDATA,fs);
5264 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
5266 "recip.%s<FMT> f<FD>, f<FS>"
5268 // start-sanitize-vr4320
5270 // end-sanitize-vr4320
5271 // start-sanitize-cygnus
5273 // end-sanitize-cygnus
5275 unsigned32 instruction = instruction_0;
5276 int destreg = ((instruction >> 6) & 0x0000001F);
5277 int fs = ((instruction >> 11) & 0x0000001F);
5278 int format = ((instruction >> 21) & 0x00000007);
5280 if ((format != fmt_single) && (format != fmt_double))
5281 SignalException(ReservedInstruction,instruction);
5283 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5288 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
5289 "round.l.%s<FMT> f<FD>, f<FS>"
5294 // start-sanitize-vr4320
5296 // end-sanitize-vr4320
5297 // start-sanitize-cygnus
5299 // end-sanitize-cygnus
5300 // start-sanitize-r5900
5302 // end-sanitize-r5900
5304 // start-sanitize-tx19
5306 // end-sanitize-tx19
5308 unsigned32 instruction = instruction_0;
5309 int destreg = ((instruction >> 6) & 0x0000001F);
5310 int fs = ((instruction >> 11) & 0x0000001F);
5311 int format = ((instruction >> 21) & 0x00000007);
5313 if ((format != fmt_single) && (format != fmt_double))
5314 SignalException(ReservedInstruction,instruction);
5316 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5321 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5322 "round.w.%s<FMT> f<FD>, f<FS>"
5328 // start-sanitize-vr4320
5330 // end-sanitize-vr4320
5331 // start-sanitize-cygnus
5333 // end-sanitize-cygnus
5334 // start-sanitize-r5900
5336 // end-sanitize-r5900
5338 // start-sanitize-tx19
5340 // end-sanitize-tx19
5342 unsigned32 instruction = instruction_0;
5343 int destreg = ((instruction >> 6) & 0x0000001F);
5344 int fs = ((instruction >> 11) & 0x0000001F);
5345 int format = ((instruction >> 21) & 0x00000007);
5347 if ((format != fmt_single) && (format != fmt_double))
5348 SignalException(ReservedInstruction,instruction);
5350 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5355 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5357 "rsqrt.%s<FMT> f<FD>, f<FS>"
5359 // start-sanitize-vr4320
5361 // end-sanitize-vr4320
5362 // start-sanitize-cygnus
5364 // end-sanitize-cygnus
5366 unsigned32 instruction = instruction_0;
5367 int destreg = ((instruction >> 6) & 0x0000001F);
5368 int fs = ((instruction >> 11) & 0x0000001F);
5369 int format = ((instruction >> 21) & 0x00000007);
5371 if ((format != fmt_single) && (format != fmt_double))
5372 SignalException(ReservedInstruction,instruction);
5374 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5379 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5380 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5386 // start-sanitize-vr4320
5388 // end-sanitize-vr4320
5389 // start-sanitize-cygnus
5391 // end-sanitize-cygnus
5393 // start-sanitize-tx19
5395 // end-sanitize-tx19
5397 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5401 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
5402 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
5405 // start-sanitize-vr4320
5407 // end-sanitize-vr4320
5408 // start-sanitize-cygnus
5410 // end-sanitize-cygnus
5412 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5416 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5417 "sqrt.%s<FMT> f<FD>, f<FS>"
5423 // start-sanitize-vr4320
5425 // end-sanitize-vr4320
5426 // start-sanitize-cygnus
5428 // end-sanitize-cygnus
5430 // start-sanitize-tx19
5432 // end-sanitize-tx19
5434 unsigned32 instruction = instruction_0;
5435 int destreg = ((instruction >> 6) & 0x0000001F);
5436 int fs = ((instruction >> 11) & 0x0000001F);
5437 int format = ((instruction >> 21) & 0x00000007);
5439 if ((format != fmt_single) && (format != fmt_double))
5440 SignalException(ReservedInstruction,instruction);
5442 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5447 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5448 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5449 *mipsI,mipsII,mipsIII,mipsIV:
5452 // start-sanitize-vr4320
5454 // end-sanitize-vr4320
5455 // start-sanitize-cygnus
5457 // end-sanitize-cygnus
5459 // start-sanitize-tx19
5461 // end-sanitize-tx19
5463 unsigned32 instruction = instruction_0;
5464 int destreg = ((instruction >> 6) & 0x0000001F);
5465 int fs = ((instruction >> 11) & 0x0000001F);
5466 int ft = ((instruction >> 16) & 0x0000001F);
5467 int format = ((instruction >> 21) & 0x00000007);
5469 if ((format != fmt_single) && (format != fmt_double))
5470 SignalException(ReservedInstruction,instruction);
5472 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5478 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5479 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5480 *mipsI,mipsII,mipsIII,mipsIV:
5483 // start-sanitize-vr4320
5485 // end-sanitize-vr4320
5486 // start-sanitize-cygnus
5488 // end-sanitize-cygnus
5489 // start-sanitize-r5900
5491 // end-sanitize-r5900
5493 // start-sanitize-tx19
5495 // end-sanitize-tx19
5497 unsigned32 instruction = instruction_0;
5498 signed_word offset = EXTEND16 (OFFSET);
5499 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5500 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5502 address_word vaddr = ((uword64)op1 + offset);
5505 if ((vaddr & 3) != 0)
5506 SignalExceptionAddressStore();
5509 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5512 uword64 memval1 = 0;
5513 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5514 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5515 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5517 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5518 byte = ((vaddr & mask) ^ bigendiancpu);
5519 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5520 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5527 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5528 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5531 // start-sanitize-vr4320
5533 // end-sanitize-vr4320
5534 // start-sanitize-cygnus
5536 // end-sanitize-cygnus
5538 unsigned32 instruction = instruction_0;
5539 int fs = ((instruction >> 11) & 0x0000001F);
5540 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5541 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5543 address_word vaddr = ((unsigned64)op1 + op2);
5546 if ((vaddr & 3) != 0)
5547 SignalExceptionAddressStore();
5550 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5552 unsigned64 memval = 0;
5553 unsigned64 memval1 = 0;
5554 unsigned64 mask = 0x7;
5556 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5557 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5558 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5560 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5568 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5569 "trunc.l.%s<FMT> f<FD>, f<FS>"
5574 // start-sanitize-vr4320
5576 // end-sanitize-vr4320
5577 // start-sanitize-cygnus
5579 // end-sanitize-cygnus
5580 // start-sanitize-r5900
5582 // end-sanitize-r5900
5584 // start-sanitize-tx19
5586 // end-sanitize-tx19
5588 unsigned32 instruction = instruction_0;
5589 int destreg = ((instruction >> 6) & 0x0000001F);
5590 int fs = ((instruction >> 11) & 0x0000001F);
5591 int format = ((instruction >> 21) & 0x00000007);
5593 if ((format != fmt_single) && (format != fmt_double))
5594 SignalException(ReservedInstruction,instruction);
5596 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5601 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5602 "trunc.w.%s<FMT> f<FD>, f<FS>"
5608 // start-sanitize-vr4320
5610 // end-sanitize-vr4320
5611 // start-sanitize-cygnus
5613 // end-sanitize-cygnus
5614 // start-sanitize-r5900
5616 // end-sanitize-r5900
5618 // start-sanitize-tx19
5620 // end-sanitize-tx19
5622 unsigned32 instruction = instruction_0;
5623 int destreg = ((instruction >> 6) & 0x0000001F);
5624 int fs = ((instruction >> 11) & 0x0000001F);
5625 int format = ((instruction >> 21) & 0x00000007);
5627 if ((format != fmt_single) && (format != fmt_double))
5628 SignalException(ReservedInstruction,instruction);
5630 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5636 // MIPS Architecture:
5638 // System Control Instruction Set (COP0)
5642 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5644 *mipsI,mipsII,mipsIII,mipsIV:
5647 // start-sanitize-vr4320
5649 // end-sanitize-vr4320
5650 // start-sanitize-cygnus
5652 // end-sanitize-cygnus
5655 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5657 *mipsI,mipsII,mipsIII,mipsIV:
5660 // start-sanitize-vr4320
5662 // end-sanitize-vr4320
5663 // start-sanitize-cygnus
5665 // end-sanitize-cygnus
5668 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5670 *mipsI,mipsII,mipsIII,mipsIV:
5674 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5676 *mipsI,mipsII,mipsIII,mipsIV:
5679 // start-sanitize-vr4320
5681 // end-sanitize-vr4320
5682 // start-sanitize-cygnus
5684 // end-sanitize-cygnus
5687 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5692 // start-sanitize-vr4320
5694 // end-sanitize-vr4320
5695 // start-sanitize-cygnus
5697 // end-sanitize-cygnus
5699 // start-sanitize-tx19
5701 // end-sanitize-tx19
5703 unsigned32 instruction = instruction_0;
5704 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5705 int hint = ((instruction >> 16) & 0x0000001F);
5706 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5708 address_word vaddr = (op1 + offset);
5711 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5712 CacheOp(hint,vaddr,paddr,instruction);
5717 010000,10000,000000000000000,111001:COP0:32::DI
5719 *mipsI,mipsII,mipsIII,mipsIV:
5722 // start-sanitize-vr4320
5724 // end-sanitize-vr4320
5725 // start-sanitize-cygnus
5727 // end-sanitize-cygnus
5730 010000,10000,000000000000000,111000:COP0:32::EI
5732 *mipsI,mipsII,mipsIII,mipsIV:
5735 // start-sanitize-vr4320
5737 // end-sanitize-vr4320
5738 // start-sanitize-cygnus
5740 // end-sanitize-cygnus
5743 010000,10000,000000000000000,011000:COP0:32::ERET
5749 // start-sanitize-vr4320
5751 // end-sanitize-vr4320
5752 // start-sanitize-cygnus
5754 // end-sanitize-cygnus
5755 // start-sanitize-r5900
5757 // end-sanitize-r5900
5759 if (SR & status_ERL)
5761 /* Oops, not yet available */
5762 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5774 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5775 "mfc0 r<RT>, r<RD> # <REGX>"
5776 *mipsI,mipsII,mipsIII,mipsIV:
5780 // start-sanitize-vr4320
5782 // end-sanitize-vr4320
5783 // start-sanitize-cygnus
5785 // end-sanitize-cygnus
5786 // start-sanitize-r5900
5788 // end-sanitize-r5900
5790 TRACE_ALU_INPUT0 ();
5791 DecodeCoproc (instruction_0);
5792 TRACE_ALU_RESULT (GPR[RT]);
5795 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5796 "mtc0 r<RT>, r<RD> # <REGX>"
5797 *mipsI,mipsII,mipsIII,mipsIV:
5798 // start-sanitize-tx19
5800 // end-sanitize-tx19
5803 // start-sanitize-vr4320
5805 // end-sanitize-vr4320
5807 // start-sanitize-cygnus
5809 // end-sanitize-cygnus
5810 // start-sanitize-r5900
5812 // end-sanitize-r5900
5814 DecodeCoproc (instruction_0);
5818 010000,10000,000000000000000,010000:COP0:32::RFE
5820 *mipsI,mipsII,mipsIII,mipsIV:
5821 // start-sanitize-tx19
5823 // end-sanitize-tx19
5826 // start-sanitize-vr4320
5828 // end-sanitize-vr4320
5830 // start-sanitize-cygnus
5832 // end-sanitize-cygnus
5833 // start-sanitize-r5900
5835 // end-sanitize-r5900
5837 DecodeCoproc (instruction_0);
5841 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5842 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5843 *mipsI,mipsII,mipsIII,mipsIV:
5845 // start-sanitize-r5900
5847 // end-sanitize-r5900
5849 // start-sanitize-tx19
5851 // end-sanitize-tx19
5853 DecodeCoproc (instruction_0);
5858 010000,10000,000000000000000,001000:COP0:32::TLBP
5860 *mipsI,mipsII,mipsIII,mipsIV:
5863 // start-sanitize-vr4320
5865 // end-sanitize-vr4320
5866 // start-sanitize-cygnus
5868 // end-sanitize-cygnus
5871 010000,10000,000000000000000,000001:COP0:32::TLBR
5873 *mipsI,mipsII,mipsIII,mipsIV:
5876 // start-sanitize-vr4320
5878 // end-sanitize-vr4320
5879 // start-sanitize-cygnus
5881 // end-sanitize-cygnus
5884 010000,10000,000000000000000,000010:COP0:32::TLBWI
5886 *mipsI,mipsII,mipsIII,mipsIV:
5889 // start-sanitize-vr4320
5891 // end-sanitize-vr4320
5892 // start-sanitize-cygnus
5894 // end-sanitize-cygnus
5897 010000,10000,000000000000000,000110:COP0:32::TLBWR
5899 *mipsI,mipsII,mipsIII,mipsIV:
5902 // start-sanitize-vr4320
5904 // end-sanitize-vr4320
5905 // start-sanitize-cygnus
5907 // end-sanitize-cygnus
5911 // start-sanitize-cygnus
5912 :include:64,f::mdmx.igen
5913 // end-sanitize-cygnus
5914 // start-sanitize-r5900
5915 :include::r5900:r5900.igen
5916 // end-sanitize-r5900
5920 // start-sanitize-cygnus-never
5922 // // FIXME FIXME FIXME What is this instruction?
5923 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5928 // // start-sanitize-r5900
5930 // // end-sanitize-r5900
5932 // // start-sanitize-tx19
5934 // // end-sanitize-tx19
5936 // unsigned32 instruction = instruction_0;
5937 // signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5938 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5939 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5941 // if (CoProcPresent(3))
5942 // SignalException(CoProcessorUnusable);
5944 // SignalException(ReservedInstruction,instruction);
5948 // end-sanitize-cygnus-never
5949 // start-sanitize-cygnus-never
5951 // // FIXME FIXME FIXME What is this?
5952 // 11100,******,00001:RR:16::SDBBP
5955 // unsigned32 instruction = instruction_0;
5956 // if (have_extendval)
5957 // SignalException (ReservedInstruction, instruction);
5959 // SignalException(DebugBreakPoint,instruction);
5963 // end-sanitize-cygnus-never
5964 // start-sanitize-cygnus-never
5966 // // FIXME FIXME FIXME What is this?
5967 // 000000,********************,001110:SPECIAL:32::SDBBP
5970 // unsigned32 instruction = instruction_0;
5972 // SignalException(DebugBreakPoint,instruction);
5976 // end-sanitize-cygnus-never